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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.21


Total test records in report: 1151
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T85 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2857885542 Jun 28 06:18:46 PM PDT 24 Jun 28 06:18:50 PM PDT 24 55435817 ps
T93 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2483713525 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:01 PM PDT 24 29424264 ps
T102 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4200077274 Jun 28 06:18:52 PM PDT 24 Jun 28 06:19:07 PM PDT 24 36894229 ps
T82 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.815468222 Jun 28 06:18:50 PM PDT 24 Jun 28 06:19:13 PM PDT 24 1118010443 ps
T1043 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3139175424 Jun 28 06:18:58 PM PDT 24 Jun 28 06:19:07 PM PDT 24 29241097 ps
T1044 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3653847179 Jun 28 06:19:05 PM PDT 24 Jun 28 06:19:11 PM PDT 24 14030521 ps
T1045 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3384986134 Jun 28 06:19:01 PM PDT 24 Jun 28 06:19:08 PM PDT 24 13417992 ps
T1046 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2590903156 Jun 28 06:19:01 PM PDT 24 Jun 28 06:19:08 PM PDT 24 48215867 ps
T1047 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3280755999 Jun 28 06:18:46 PM PDT 24 Jun 28 06:18:50 PM PDT 24 14073244 ps
T1048 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1476073009 Jun 28 06:18:56 PM PDT 24 Jun 28 06:19:05 PM PDT 24 13862025 ps
T95 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3616093204 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:18 PM PDT 24 918862242 ps
T88 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1809631768 Jun 28 06:18:55 PM PDT 24 Jun 28 06:19:07 PM PDT 24 334920147 ps
T1049 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1006388218 Jun 28 06:19:11 PM PDT 24 Jun 28 06:19:15 PM PDT 24 35556869 ps
T1050 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4044608914 Jun 28 06:18:54 PM PDT 24 Jun 28 06:19:03 PM PDT 24 20119453 ps
T1051 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1874796492 Jun 28 06:19:05 PM PDT 24 Jun 28 06:19:12 PM PDT 24 222965626 ps
T130 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2753921226 Jun 28 06:18:54 PM PDT 24 Jun 28 06:19:29 PM PDT 24 4379640177 ps
T149 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3318007792 Jun 28 06:18:46 PM PDT 24 Jun 28 06:19:06 PM PDT 24 1288993346 ps
T1052 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2030829370 Jun 28 06:19:10 PM PDT 24 Jun 28 06:19:14 PM PDT 24 16740583 ps
T131 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.649625953 Jun 28 06:18:48 PM PDT 24 Jun 28 06:19:16 PM PDT 24 4422298435 ps
T132 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2235849890 Jun 28 06:18:45 PM PDT 24 Jun 28 06:19:09 PM PDT 24 4292899528 ps
T1053 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.784639185 Jun 28 06:18:56 PM PDT 24 Jun 28 06:19:09 PM PDT 24 215991702 ps
T103 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3529138193 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:01 PM PDT 24 147343023 ps
T1054 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3741109136 Jun 28 06:19:08 PM PDT 24 Jun 28 06:19:13 PM PDT 24 14317115 ps
T104 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2401084466 Jun 28 06:19:06 PM PDT 24 Jun 28 06:19:11 PM PDT 24 128453326 ps
T1055 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1386983834 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:16 PM PDT 24 29528170 ps
T105 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3628193560 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:56 PM PDT 24 39978430 ps
T89 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1579285956 Jun 28 06:19:08 PM PDT 24 Jun 28 06:19:15 PM PDT 24 168229960 ps
T1056 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3197355597 Jun 28 06:18:55 PM PDT 24 Jun 28 06:19:05 PM PDT 24 64705507 ps
T1057 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1451751215 Jun 28 06:19:15 PM PDT 24 Jun 28 06:19:19 PM PDT 24 14243613 ps
T1058 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.298729527 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:16 PM PDT 24 35169971 ps
T153 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.361147651 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:38 PM PDT 24 4647608569 ps
T1059 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1663767736 Jun 28 06:19:08 PM PDT 24 Jun 28 06:19:15 PM PDT 24 155148844 ps
T106 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.337687431 Jun 28 06:18:45 PM PDT 24 Jun 28 06:19:08 PM PDT 24 1996868673 ps
T107 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.325223379 Jun 28 06:19:08 PM PDT 24 Jun 28 06:19:13 PM PDT 24 355350227 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1533665860 Jun 28 06:18:43 PM PDT 24 Jun 28 06:18:57 PM PDT 24 632815355 ps
T1061 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1730613053 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:19 PM PDT 24 37940551 ps
T108 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3583385179 Jun 28 06:18:42 PM PDT 24 Jun 28 06:18:59 PM PDT 24 1490406236 ps
T1062 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1768903246 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:19 PM PDT 24 126387594 ps
T110 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.577661035 Jun 28 06:18:50 PM PDT 24 Jun 28 06:19:00 PM PDT 24 20178648 ps
T109 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1842350269 Jun 28 06:18:49 PM PDT 24 Jun 28 06:18:58 PM PDT 24 116384544 ps
T1063 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2177743030 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:55 PM PDT 24 50470167 ps
T92 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.606073302 Jun 28 06:18:44 PM PDT 24 Jun 28 06:18:50 PM PDT 24 239307346 ps
T1064 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4041031613 Jun 28 06:18:53 PM PDT 24 Jun 28 06:19:05 PM PDT 24 243861016 ps
T133 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1210360850 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:37 PM PDT 24 946262675 ps
T1065 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2191977994 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:55 PM PDT 24 44755096 ps
T1066 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3810346092 Jun 28 06:19:08 PM PDT 24 Jun 28 06:19:13 PM PDT 24 66918994 ps
T1067 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3486979391 Jun 28 06:18:54 PM PDT 24 Jun 28 06:19:07 PM PDT 24 116555193 ps
T111 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1572110237 Jun 28 06:18:52 PM PDT 24 Jun 28 06:19:03 PM PDT 24 92108299 ps
T90 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1471970957 Jun 28 06:19:09 PM PDT 24 Jun 28 06:19:16 PM PDT 24 154135858 ps
T137 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3366223283 Jun 28 06:18:45 PM PDT 24 Jun 28 06:18:49 PM PDT 24 72981099 ps
T1068 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1579625647 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:04 PM PDT 24 1313857506 ps
T134 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1898336819 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:53 PM PDT 24 291616890 ps
T1069 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3872920234 Jun 28 06:18:56 PM PDT 24 Jun 28 06:19:06 PM PDT 24 248353905 ps
T1070 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.579321604 Jun 28 06:18:50 PM PDT 24 Jun 28 06:18:59 PM PDT 24 23063301 ps
T1071 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.752739874 Jun 28 06:18:49 PM PDT 24 Jun 28 06:18:58 PM PDT 24 154756518 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.882005471 Jun 28 06:18:43 PM PDT 24 Jun 28 06:18:45 PM PDT 24 40862918 ps
T86 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2110553341 Jun 28 06:18:50 PM PDT 24 Jun 28 06:19:04 PM PDT 24 76938153 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2107136232 Jun 28 06:18:57 PM PDT 24 Jun 28 06:19:12 PM PDT 24 108677109 ps
T1074 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2620151676 Jun 28 06:18:53 PM PDT 24 Jun 28 06:19:06 PM PDT 24 128805141 ps
T151 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1760335571 Jun 28 06:18:52 PM PDT 24 Jun 28 06:19:08 PM PDT 24 315174588 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3483993859 Jun 28 06:18:54 PM PDT 24 Jun 28 06:19:26 PM PDT 24 5746776841 ps
T1076 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2012779819 Jun 28 06:18:56 PM PDT 24 Jun 28 06:19:05 PM PDT 24 11376922 ps
T87 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2236466703 Jun 28 06:18:46 PM PDT 24 Jun 28 06:18:54 PM PDT 24 104200639 ps
T135 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.924078144 Jun 28 06:18:56 PM PDT 24 Jun 28 06:19:09 PM PDT 24 925534657 ps
T136 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.242366208 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:59 PM PDT 24 161029881 ps
T1077 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1425873231 Jun 28 06:19:02 PM PDT 24 Jun 28 06:19:11 PM PDT 24 207913739 ps
T1078 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1576105912 Jun 28 06:19:10 PM PDT 24 Jun 28 06:19:18 PM PDT 24 160353779 ps
T65 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.700443159 Jun 28 06:18:50 PM PDT 24 Jun 28 06:18:59 PM PDT 24 70336593 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.343185296 Jun 28 06:18:54 PM PDT 24 Jun 28 06:19:05 PM PDT 24 307282952 ps
T1080 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2237905624 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:56 PM PDT 24 502477823 ps
T1081 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4269018538 Jun 28 06:19:05 PM PDT 24 Jun 28 06:19:11 PM PDT 24 104342441 ps
T94 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.707987669 Jun 28 06:18:44 PM PDT 24 Jun 28 06:18:48 PM PDT 24 169019324 ps
T1082 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.28990389 Jun 28 06:18:48 PM PDT 24 Jun 28 06:19:20 PM PDT 24 2467185908 ps
T1083 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3067933489 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:55 PM PDT 24 51036657 ps
T1084 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1744166921 Jun 28 06:18:53 PM PDT 24 Jun 28 06:19:04 PM PDT 24 26905433 ps
T1085 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3312217695 Jun 28 06:18:48 PM PDT 24 Jun 28 06:19:01 PM PDT 24 36936742 ps
T1086 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3807304755 Jun 28 06:19:00 PM PDT 24 Jun 28 06:19:08 PM PDT 24 47956595 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3006510192 Jun 28 06:18:45 PM PDT 24 Jun 28 06:18:52 PM PDT 24 143916303 ps
T66 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3479508475 Jun 28 06:18:50 PM PDT 24 Jun 28 06:18:58 PM PDT 24 41700190 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2795422729 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:53 PM PDT 24 53489130 ps
T1089 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3135569329 Jun 28 06:19:08 PM PDT 24 Jun 28 06:19:13 PM PDT 24 112492766 ps
T1090 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.390676750 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:55 PM PDT 24 179336814 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3308876461 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:58 PM PDT 24 177375241 ps
T1092 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.721394222 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:55 PM PDT 24 101783882 ps
T1093 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2455782355 Jun 28 06:18:54 PM PDT 24 Jun 28 06:19:07 PM PDT 24 426261453 ps
T1094 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2121189640 Jun 28 06:18:49 PM PDT 24 Jun 28 06:18:57 PM PDT 24 18392721 ps
T154 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2585862529 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:40 PM PDT 24 1104106241 ps
T1095 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.48342575 Jun 28 06:18:56 PM PDT 24 Jun 28 06:19:13 PM PDT 24 349450013 ps
T1096 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1895944639 Jun 28 06:18:52 PM PDT 24 Jun 28 06:19:02 PM PDT 24 11643933 ps
T1097 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1141564866 Jun 28 06:19:07 PM PDT 24 Jun 28 06:19:14 PM PDT 24 287100301 ps
T1098 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3752904371 Jun 28 06:19:09 PM PDT 24 Jun 28 06:19:14 PM PDT 24 17088280 ps
T1099 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2522411936 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:19 PM PDT 24 186888707 ps
T1100 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3918436243 Jun 28 06:18:48 PM PDT 24 Jun 28 06:19:02 PM PDT 24 200059177 ps
T91 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1359720312 Jun 28 06:18:45 PM PDT 24 Jun 28 06:18:52 PM PDT 24 182337132 ps
T1101 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.529884471 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:16 PM PDT 24 14286281 ps
T1102 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1163421746 Jun 28 06:19:03 PM PDT 24 Jun 28 06:19:11 PM PDT 24 55690772 ps
T1103 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2268637707 Jun 28 06:19:16 PM PDT 24 Jun 28 06:19:20 PM PDT 24 12635210 ps
T1104 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.686305425 Jun 28 06:19:07 PM PDT 24 Jun 28 06:19:12 PM PDT 24 42913625 ps
T1105 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2273702563 Jun 28 06:19:01 PM PDT 24 Jun 28 06:19:09 PM PDT 24 102481039 ps
T1106 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4046744522 Jun 28 06:18:52 PM PDT 24 Jun 28 06:19:03 PM PDT 24 183652751 ps
T67 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3705154991 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:53 PM PDT 24 140532263 ps
T1107 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2138249655 Jun 28 06:18:58 PM PDT 24 Jun 28 06:19:07 PM PDT 24 39484515 ps
T1108 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2565179505 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:20 PM PDT 24 167666300 ps
T1109 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3727305207 Jun 28 06:19:11 PM PDT 24 Jun 28 06:19:17 PM PDT 24 47606188 ps
T1110 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3193089298 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:11 PM PDT 24 201831847 ps
T1111 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2922173660 Jun 28 06:19:04 PM PDT 24 Jun 28 06:19:12 PM PDT 24 173402351 ps
T1112 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1039544719 Jun 28 06:19:04 PM PDT 24 Jun 28 06:19:12 PM PDT 24 1294432060 ps
T1113 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1598521762 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:55 PM PDT 24 58096556 ps
T150 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4074443348 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:20 PM PDT 24 1046611908 ps
T1114 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1108309458 Jun 28 06:19:09 PM PDT 24 Jun 28 06:19:15 PM PDT 24 259045665 ps
T1115 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2379619603 Jun 28 06:19:02 PM PDT 24 Jun 28 06:19:09 PM PDT 24 83381471 ps
T1116 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2449869461 Jun 28 06:19:09 PM PDT 24 Jun 28 06:19:20 PM PDT 24 292269679 ps
T68 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1287816662 Jun 28 06:18:50 PM PDT 24 Jun 28 06:18:58 PM PDT 24 16743299 ps
T1117 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3859116305 Jun 28 06:18:54 PM PDT 24 Jun 28 06:19:28 PM PDT 24 5063220184 ps
T1118 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1403445169 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:04 PM PDT 24 167107089 ps
T1119 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1187966935 Jun 28 06:18:46 PM PDT 24 Jun 28 06:18:51 PM PDT 24 88860985 ps
T1120 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2785135390 Jun 28 06:19:01 PM PDT 24 Jun 28 06:19:15 PM PDT 24 1044925036 ps
T1121 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2125363020 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:17 PM PDT 24 13084384 ps
T152 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.11973353 Jun 28 06:19:06 PM PDT 24 Jun 28 06:19:28 PM PDT 24 782351546 ps
T1122 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.563338333 Jun 28 06:19:11 PM PDT 24 Jun 28 06:19:29 PM PDT 24 1120109480 ps
T148 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3631096620 Jun 28 06:19:09 PM PDT 24 Jun 28 06:19:20 PM PDT 24 1584614767 ps
T1123 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2078693877 Jun 28 06:19:11 PM PDT 24 Jun 28 06:19:15 PM PDT 24 12163400 ps
T1124 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2250225161 Jun 28 06:19:04 PM PDT 24 Jun 28 06:19:10 PM PDT 24 37672029 ps
T1125 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1080771752 Jun 28 06:19:11 PM PDT 24 Jun 28 06:19:18 PM PDT 24 121428138 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1094283600 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:00 PM PDT 24 12174859 ps
T1127 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3142172689 Jun 28 06:19:08 PM PDT 24 Jun 28 06:19:15 PM PDT 24 670894482 ps
T1128 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3206589291 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:20 PM PDT 24 286272654 ps
T1129 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2300194214 Jun 28 06:18:55 PM PDT 24 Jun 28 06:19:05 PM PDT 24 208788023 ps
T1130 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3784901761 Jun 28 06:18:55 PM PDT 24 Jun 28 06:19:11 PM PDT 24 300856115 ps
T1131 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2565281351 Jun 28 06:18:46 PM PDT 24 Jun 28 06:18:51 PM PDT 24 274028528 ps
T1132 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.757193126 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:03 PM PDT 24 103196691 ps
T1133 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2937299944 Jun 28 06:18:53 PM PDT 24 Jun 28 06:19:03 PM PDT 24 27952766 ps
T1134 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2448446332 Jun 28 06:19:09 PM PDT 24 Jun 28 06:19:16 PM PDT 24 478512509 ps
T1135 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3253033646 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:21 PM PDT 24 319032084 ps
T1136 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1000970058 Jun 28 06:19:09 PM PDT 24 Jun 28 06:19:15 PM PDT 24 368456432 ps
T1137 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2145020905 Jun 28 06:19:11 PM PDT 24 Jun 28 06:19:18 PM PDT 24 132333886 ps
T1138 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.600858490 Jun 28 06:19:05 PM PDT 24 Jun 28 06:19:10 PM PDT 24 13211153 ps
T1139 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3398882315 Jun 28 06:18:56 PM PDT 24 Jun 28 06:19:05 PM PDT 24 20143391 ps
T1140 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2528835383 Jun 28 06:19:11 PM PDT 24 Jun 28 06:19:18 PM PDT 24 140042545 ps
T1141 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.528593199 Jun 28 06:19:14 PM PDT 24 Jun 28 06:19:18 PM PDT 24 159315478 ps
T1142 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4039572952 Jun 28 06:19:00 PM PDT 24 Jun 28 06:19:08 PM PDT 24 12766193 ps
T1143 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4227477953 Jun 28 06:19:15 PM PDT 24 Jun 28 06:19:19 PM PDT 24 150388493 ps
T1144 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1448403726 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:03 PM PDT 24 1731911687 ps
T1145 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3461606409 Jun 28 06:19:12 PM PDT 24 Jun 28 06:19:17 PM PDT 24 105481176 ps
T1146 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1689819442 Jun 28 06:19:08 PM PDT 24 Jun 28 06:19:16 PM PDT 24 247807783 ps
T1147 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4105919691 Jun 28 06:19:09 PM PDT 24 Jun 28 06:19:15 PM PDT 24 141494700 ps
T1148 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1731430145 Jun 28 06:19:08 PM PDT 24 Jun 28 06:19:13 PM PDT 24 55913983 ps
T1149 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.213652919 Jun 28 06:19:03 PM PDT 24 Jun 28 06:19:10 PM PDT 24 45946448 ps
T1150 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3645174277 Jun 28 06:19:08 PM PDT 24 Jun 28 06:19:13 PM PDT 24 43094424 ps
T147 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2260874082 Jun 28 06:18:57 PM PDT 24 Jun 28 06:19:10 PM PDT 24 757194248 ps
T1151 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1285375400 Jun 28 06:19:03 PM PDT 24 Jun 28 06:19:10 PM PDT 24 73045210 ps

Test location /workspace/coverage/default/44.spi_device_stress_all.263935795
Short name T2
Test name
Test status
Simulation time 8798547204 ps
CPU time 57.14 seconds
Started Jun 28 06:34:01 PM PDT 24
Finished Jun 28 06:35:01 PM PDT 24
Peak memory 240388 kb
Host smart-36cd0cf6-d38d-4587-ad49-51be2e2bf3dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263935795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.263935795
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2461287533
Short name T37
Test name
Test status
Simulation time 8245409220 ps
CPU time 97.24 seconds
Started Jun 28 06:30:37 PM PDT 24
Finished Jun 28 06:32:16 PM PDT 24
Peak memory 273316 kb
Host smart-e765b11e-ec7c-4420-9e17-24e2e0ed1821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461287533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2461287533
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.852933075
Short name T167
Test name
Test status
Simulation time 144310728188 ps
CPU time 439.7 seconds
Started Jun 28 06:31:47 PM PDT 24
Finished Jun 28 06:39:09 PM PDT 24
Peak memory 265292 kb
Host smart-632f5e72-278e-4f09-98e4-78df44cec0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852933075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.852933075
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2753921226
Short name T130
Test name
Test status
Simulation time 4379640177 ps
CPU time 24.8 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:29 PM PDT 24
Peak memory 215952 kb
Host smart-7d64b42b-35d2-4a91-aec8-a9efaa522764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753921226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2753921226
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1770164159
Short name T17
Test name
Test status
Simulation time 47540257515 ps
CPU time 294.15 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:37:54 PM PDT 24
Peak memory 265520 kb
Host smart-4b789495-b910-4120-b4a4-8ae946b52fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770164159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1770164159
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2777211313
Short name T47
Test name
Test status
Simulation time 50556440 ps
CPU time 0.76 seconds
Started Jun 28 06:27:55 PM PDT 24
Finished Jun 28 06:27:58 PM PDT 24
Peak memory 216144 kb
Host smart-e3d18ca6-3973-4e09-90b3-4366a0244906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777211313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2777211313
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.100062392
Short name T22
Test name
Test status
Simulation time 173948754648 ps
CPU time 572.1 seconds
Started Jun 28 06:31:11 PM PDT 24
Finished Jun 28 06:40:44 PM PDT 24
Peak memory 284044 kb
Host smart-485a21f6-6552-4f7c-8489-703997de55cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100062392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.100062392
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4076428715
Short name T83
Test name
Test status
Simulation time 366785752 ps
CPU time 2.6 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 215596 kb
Host smart-c8a144dc-0ab4-4fe3-9d20-31804be0827b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076428715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
076428715
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2681905619
Short name T7
Test name
Test status
Simulation time 60018485777 ps
CPU time 403.27 seconds
Started Jun 28 06:30:38 PM PDT 24
Finished Jun 28 06:37:23 PM PDT 24
Peak memory 265048 kb
Host smart-b19504c8-60c3-49f2-a31b-e8fbfa229631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681905619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2681905619
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.358453589
Short name T146
Test name
Test status
Simulation time 31541535367 ps
CPU time 365.3 seconds
Started Jun 28 06:31:03 PM PDT 24
Finished Jun 28 06:37:10 PM PDT 24
Peak memory 290120 kb
Host smart-17f1f850-4be7-45de-9eda-2774e443b41d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358453589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.358453589
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4026432866
Short name T45
Test name
Test status
Simulation time 175354342104 ps
CPU time 874.45 seconds
Started Jun 28 06:32:09 PM PDT 24
Finished Jun 28 06:46:45 PM PDT 24
Peak memory 286600 kb
Host smart-5983b7e7-5050-436f-9980-dcd5b9770a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026432866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4026432866
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.824070095
Short name T21
Test name
Test status
Simulation time 252634890 ps
CPU time 1.2 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:24 PM PDT 24
Peak memory 235928 kb
Host smart-c9ddb80a-11b9-4e80-9245-c9c98208b96c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824070095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.824070095
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2928765189
Short name T35
Test name
Test status
Simulation time 7074201005 ps
CPU time 24.44 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:36 PM PDT 24
Peak memory 241008 kb
Host smart-ad566bc3-7817-47a1-8399-f10d3969928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928765189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2928765189
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2488065086
Short name T62
Test name
Test status
Simulation time 78859208701 ps
CPU time 670.03 seconds
Started Jun 28 06:30:38 PM PDT 24
Finished Jun 28 06:41:49 PM PDT 24
Peak memory 271180 kb
Host smart-1bdaf3f5-0075-4952-bbfc-8b1d3f0b2cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488065086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2488065086
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2187022626
Short name T28
Test name
Test status
Simulation time 686697945402 ps
CPU time 574.28 seconds
Started Jun 28 06:33:38 PM PDT 24
Finished Jun 28 06:43:14 PM PDT 24
Peak memory 272824 kb
Host smart-7106306f-427a-49df-8ab7-bc2e1bf1f665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187022626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2187022626
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2346630637
Short name T60
Test name
Test status
Simulation time 25307866403 ps
CPU time 212.01 seconds
Started Jun 28 06:33:18 PM PDT 24
Finished Jun 28 06:36:52 PM PDT 24
Peak memory 256040 kb
Host smart-7032ce9d-ddc2-4f4e-9912-36ef2e300202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346630637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2346630637
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3529138193
Short name T103
Test name
Test status
Simulation time 147343023 ps
CPU time 1.21 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:01 PM PDT 24
Peak memory 207208 kb
Host smart-946fd0fc-3b89-4dc7-ad14-add20957f6b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529138193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3529138193
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3355609653
Short name T117
Test name
Test status
Simulation time 26469785793 ps
CPU time 304.25 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:37:28 PM PDT 24
Peak memory 266500 kb
Host smart-a12b6fb8-2378-4b8e-b99f-66c17f2cba18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355609653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3355609653
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3308368833
Short name T177
Test name
Test status
Simulation time 16323513363 ps
CPU time 87.63 seconds
Started Jun 28 06:30:36 PM PDT 24
Finished Jun 28 06:32:04 PM PDT 24
Peak memory 270048 kb
Host smart-8b3fa13a-cc49-49c0-92b2-037199e8057a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308368833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3308368833
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3403771878
Short name T509
Test name
Test status
Simulation time 27828258 ps
CPU time 1.08 seconds
Started Jun 28 06:27:54 PM PDT 24
Finished Jun 28 06:27:58 PM PDT 24
Peak memory 216776 kb
Host smart-774f46e7-8f9b-4b70-84e2-7556fb84dfaa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403771878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3403771878
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3028424776
Short name T24
Test name
Test status
Simulation time 109196630956 ps
CPU time 413.38 seconds
Started Jun 28 06:32:58 PM PDT 24
Finished Jun 28 06:39:54 PM PDT 24
Peak memory 265388 kb
Host smart-baf51feb-da46-49b0-b8b1-290d5af2f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028424776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3028424776
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3411423022
Short name T139
Test name
Test status
Simulation time 20632346367 ps
CPU time 349.14 seconds
Started Jun 28 06:32:28 PM PDT 24
Finished Jun 28 06:38:18 PM PDT 24
Peak memory 283300 kb
Host smart-0b1e87b7-91aa-451c-ab59-51dcd8425e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411423022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3411423022
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.991581099
Short name T42
Test name
Test status
Simulation time 11379629662 ps
CPU time 128.12 seconds
Started Jun 28 06:28:29 PM PDT 24
Finished Jun 28 06:30:38 PM PDT 24
Peak memory 265600 kb
Host smart-1c618697-1270-4993-a99f-c7613eb08f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991581099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.991581099
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1102271607
Short name T188
Test name
Test status
Simulation time 44862143457 ps
CPU time 139.26 seconds
Started Jun 28 06:29:42 PM PDT 24
Finished Jun 28 06:32:03 PM PDT 24
Peak memory 270000 kb
Host smart-c6df4b72-445c-4d73-8d3c-49d703adcb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102271607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1102271607
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.802383900
Short name T156
Test name
Test status
Simulation time 14389951172 ps
CPU time 77.9 seconds
Started Jun 28 06:32:20 PM PDT 24
Finished Jun 28 06:33:39 PM PDT 24
Peak memory 256628 kb
Host smart-3aab8625-b4a6-4729-9fe2-ff894f7c3fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802383900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.802383900
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2530670451
Short name T5
Test name
Test status
Simulation time 43739820 ps
CPU time 0.74 seconds
Started Jun 28 06:28:07 PM PDT 24
Finished Jun 28 06:28:09 PM PDT 24
Peak memory 205388 kb
Host smart-106493b3-09a8-4595-a4e4-661b55927c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530670451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
530670451
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2756246995
Short name T243
Test name
Test status
Simulation time 10169952593 ps
CPU time 158.35 seconds
Started Jun 28 06:34:29 PM PDT 24
Finished Jun 28 06:37:09 PM PDT 24
Peak memory 263448 kb
Host smart-0c34fee8-c579-4d27-8df4-5678b831c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756246995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2756246995
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2110553341
Short name T86
Test name
Test status
Simulation time 76938153 ps
CPU time 4.78 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:19:04 PM PDT 24
Peak memory 215512 kb
Host smart-5642bf5c-fdd4-4c80-8319-af2f154ff48a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110553341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
110553341
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1210360850
Short name T133
Test name
Test status
Simulation time 946262675 ps
CPU time 21.33 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:37 PM PDT 24
Peak memory 216120 kb
Host smart-24b2b2b4-fd6c-4bda-ab86-cc8573ef4ec3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210360850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1210360850
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1325586951
Short name T257
Test name
Test status
Simulation time 68217968970 ps
CPU time 195.02 seconds
Started Jun 28 06:30:10 PM PDT 24
Finished Jun 28 06:33:26 PM PDT 24
Peak memory 273828 kb
Host smart-8bf688b1-d4f1-4c40-a166-e5cf3fcd6bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325586951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1325586951
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4160303306
Short name T76
Test name
Test status
Simulation time 6576588668 ps
CPU time 7.46 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:33:03 PM PDT 24
Peak memory 232788 kb
Host smart-ddac5894-531b-42cf-8449-6df6e7b1698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160303306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4160303306
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4155741265
Short name T185
Test name
Test status
Simulation time 1967316691 ps
CPU time 40.45 seconds
Started Jun 28 06:29:22 PM PDT 24
Finished Jun 28 06:30:03 PM PDT 24
Peak memory 250168 kb
Host smart-070c323a-1983-4534-8e97-f93674f9cc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155741265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4155741265
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1327836947
Short name T248
Test name
Test status
Simulation time 29485358774 ps
CPU time 106.48 seconds
Started Jun 28 06:29:53 PM PDT 24
Finished Jun 28 06:31:41 PM PDT 24
Peak memory 267816 kb
Host smart-da68494f-5e82-420d-a4dc-97d347b1f9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327836947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1327836947
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3803190399
Short name T231
Test name
Test status
Simulation time 8406047718 ps
CPU time 54.87 seconds
Started Jun 28 06:30:02 PM PDT 24
Finished Jun 28 06:30:58 PM PDT 24
Peak memory 249208 kb
Host smart-edab0fba-6c71-4983-901f-2d8a5bf5644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803190399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3803190399
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.619733476
Short name T267
Test name
Test status
Simulation time 9782646450 ps
CPU time 35.89 seconds
Started Jun 28 06:31:13 PM PDT 24
Finished Jun 28 06:31:50 PM PDT 24
Peak memory 232824 kb
Host smart-eb61d798-15ff-41ae-8bbe-2a048341a704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619733476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.619733476
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3318007792
Short name T149
Test name
Test status
Simulation time 1288993346 ps
CPU time 16.25 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:19:06 PM PDT 24
Peak memory 215676 kb
Host smart-9993e44b-2258-4fc8-92dc-8428a4f0ad2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318007792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3318007792
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2260874082
Short name T147
Test name
Test status
Simulation time 757194248 ps
CPU time 4.38 seconds
Started Jun 28 06:18:57 PM PDT 24
Finished Jun 28 06:19:10 PM PDT 24
Peak memory 215588 kb
Host smart-8b8cad23-b96f-42bf-806f-f8eb8ec8087c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260874082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
260874082
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3376112691
Short name T140
Test name
Test status
Simulation time 9520882241 ps
CPU time 134.79 seconds
Started Jun 28 06:29:22 PM PDT 24
Finished Jun 28 06:31:38 PM PDT 24
Peak memory 263936 kb
Host smart-7189bac0-1858-4804-9417-2459974660d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376112691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3376112691
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4248933666
Short name T70
Test name
Test status
Simulation time 839590594 ps
CPU time 5.56 seconds
Started Jun 28 06:29:45 PM PDT 24
Finished Jun 28 06:29:52 PM PDT 24
Peak memory 216132 kb
Host smart-e4edc976-6011-48be-b161-2324d6b37bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248933666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4248933666
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3531165791
Short name T266
Test name
Test status
Simulation time 151437763 ps
CPU time 7.24 seconds
Started Jun 28 06:30:13 PM PDT 24
Finished Jun 28 06:30:22 PM PDT 24
Peak memory 239948 kb
Host smart-f69f945e-85f2-4df1-8beb-d52180683e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531165791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3531165791
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3818479992
Short name T158
Test name
Test status
Simulation time 13243724587 ps
CPU time 84.79 seconds
Started Jun 28 06:30:27 PM PDT 24
Finished Jun 28 06:31:54 PM PDT 24
Peak memory 240776 kb
Host smart-357cc0d8-7c39-46e6-bd12-17ade0e6d833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818479992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3818479992
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.482214133
Short name T244
Test name
Test status
Simulation time 45018875683 ps
CPU time 302.38 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:35:31 PM PDT 24
Peak memory 257116 kb
Host smart-0d38acb7-9e71-47ab-9216-155fd571a60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482214133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.482214133
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1345553168
Short name T274
Test name
Test status
Simulation time 310894500 ps
CPU time 5.64 seconds
Started Jun 28 06:30:48 PM PDT 24
Finished Jun 28 06:30:57 PM PDT 24
Peak memory 238880 kb
Host smart-6db5d012-af8b-4f7a-92a8-9e0f536454a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345553168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1345553168
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.242884971
Short name T246
Test name
Test status
Simulation time 88879604039 ps
CPU time 126.62 seconds
Started Jun 28 06:31:40 PM PDT 24
Finished Jun 28 06:33:47 PM PDT 24
Peak memory 263676 kb
Host smart-ed61bedc-6729-42c4-b536-b201292089e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242884971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.242884971
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2747072215
Short name T251
Test name
Test status
Simulation time 21925618635 ps
CPU time 184.84 seconds
Started Jun 28 06:31:57 PM PDT 24
Finished Jun 28 06:35:04 PM PDT 24
Peak memory 265204 kb
Host smart-dd1dde43-499a-4cc6-ab22-6dee53b6c9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747072215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2747072215
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.970776408
Short name T249
Test name
Test status
Simulation time 38327567840 ps
CPU time 245.98 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:36:50 PM PDT 24
Peak memory 262968 kb
Host smart-a36f9184-d83c-4586-b7b6-6dcf594ac442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970776408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.970776408
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.213652919
Short name T1149
Test name
Test status
Simulation time 45946448 ps
CPU time 1.48 seconds
Started Jun 28 06:19:03 PM PDT 24
Finished Jun 28 06:19:10 PM PDT 24
Peak memory 217456 kb
Host smart-f78bbd92-9509-4440-ac8a-1d449302371e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213652919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.213652919
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1579285956
Short name T89
Test name
Test status
Simulation time 168229960 ps
CPU time 2.58 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:15 PM PDT 24
Peak memory 215624 kb
Host smart-792ba8a8-dc8f-4e2b-a3c4-0d04d20fd467
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579285956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1579285956
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3918436243
Short name T1100
Test name
Test status
Simulation time 200059177 ps
CPU time 7.85 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:19:02 PM PDT 24
Peak memory 207140 kb
Host smart-df6ee5dc-61f5-4e89-8290-667b77d075bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918436243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3918436243
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3193089298
Short name T1110
Test name
Test status
Simulation time 201831847 ps
CPU time 11.93 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:11 PM PDT 24
Peak memory 207096 kb
Host smart-11a2f2ee-4365-4b80-aebd-853cbeb5608a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193089298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3193089298
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.242366208
Short name T136
Test name
Test status
Simulation time 161029881 ps
CPU time 3.8 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:59 PM PDT 24
Peak memory 218232 kb
Host smart-165adac5-e237-4513-b042-e51f03737994
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242366208 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.242366208
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1898336819
Short name T134
Test name
Test status
Simulation time 291616890 ps
CPU time 2 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:53 PM PDT 24
Peak memory 215408 kb
Host smart-32fb1cc3-99f7-4c0d-8497-a99098ce8e29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898336819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
898336819
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4269018538
Short name T1081
Test name
Test status
Simulation time 104342441 ps
CPU time 0.78 seconds
Started Jun 28 06:19:05 PM PDT 24
Finished Jun 28 06:19:11 PM PDT 24
Peak memory 203868 kb
Host smart-21c2cf1c-f90f-487c-aaf6-df1a7dd92182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269018538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
269018538
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1163421746
Short name T1102
Test name
Test status
Simulation time 55690772 ps
CPU time 2.17 seconds
Started Jun 28 06:19:03 PM PDT 24
Finished Jun 28 06:19:11 PM PDT 24
Peak memory 215440 kb
Host smart-47848c10-b38d-434f-bc9d-4013440188b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163421746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1163421746
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2915770375
Short name T1034
Test name
Test status
Simulation time 13174133 ps
CPU time 0.74 seconds
Started Jun 28 06:19:00 PM PDT 24
Finished Jun 28 06:19:08 PM PDT 24
Peak memory 203708 kb
Host smart-e5082424-ae2b-46e2-8b93-88b195d09071
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915770375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2915770375
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1579625647
Short name T1068
Test name
Test status
Simulation time 1313857506 ps
CPU time 4.57 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:04 PM PDT 24
Peak memory 215468 kb
Host smart-209dc9bf-9055-4cfc-9b05-fea57ded8450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579625647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1579625647
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3583385179
Short name T108
Test name
Test status
Simulation time 1490406236 ps
CPU time 15.98 seconds
Started Jun 28 06:18:42 PM PDT 24
Finished Jun 28 06:18:59 PM PDT 24
Peak memory 215408 kb
Host smart-dbee4988-606c-4339-a8c4-25891b7f3e51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583385179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3583385179
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3483993859
Short name T1075
Test name
Test status
Simulation time 5746776841 ps
CPU time 23.18 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:26 PM PDT 24
Peak memory 207216 kb
Host smart-21d99ced-2ab0-41c8-83d0-d39b7c0ad52e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483993859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3483993859
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3479508475
Short name T66
Test name
Test status
Simulation time 41700190 ps
CPU time 1.35 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:58 PM PDT 24
Peak memory 215248 kb
Host smart-47572094-fcf2-4268-bfff-b19d2a686bc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479508475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3479508475
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3308876461
Short name T1091
Test name
Test status
Simulation time 177375241 ps
CPU time 3.53 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:58 PM PDT 24
Peak memory 217112 kb
Host smart-32d7ee4a-bbc1-4d7d-813a-db2bcbd59b76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308876461 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3308876461
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1744166921
Short name T1084
Test name
Test status
Simulation time 26905433 ps
CPU time 1.79 seconds
Started Jun 28 06:18:53 PM PDT 24
Finished Jun 28 06:19:04 PM PDT 24
Peak memory 215320 kb
Host smart-4dce73bb-1d89-4246-acd0-8b4136556ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744166921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
744166921
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3312217695
Short name T1085
Test name
Test status
Simulation time 36936742 ps
CPU time 0.73 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:19:01 PM PDT 24
Peak memory 203828 kb
Host smart-ee95c398-da70-462c-b5be-03748e06bf40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312217695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
312217695
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3628193560
Short name T105
Test name
Test status
Simulation time 39978430 ps
CPU time 1.54 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:56 PM PDT 24
Peak memory 215464 kb
Host smart-5209e5a1-aa0e-4c12-8217-3a3107711eff
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628193560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3628193560
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3280755999
Short name T1047
Test name
Test status
Simulation time 14073244 ps
CPU time 0.67 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:50 PM PDT 24
Peak memory 203692 kb
Host smart-44795351-dce9-4413-aef0-ee34f5a1905e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280755999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3280755999
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.721394222
Short name T1092
Test name
Test status
Simulation time 101783882 ps
CPU time 1.72 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 215468 kb
Host smart-f010e663-7033-4b38-84ef-4d10184ffe5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721394222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.721394222
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1359720312
Short name T91
Test name
Test status
Simulation time 182337132 ps
CPU time 4.19 seconds
Started Jun 28 06:18:45 PM PDT 24
Finished Jun 28 06:18:52 PM PDT 24
Peak memory 215800 kb
Host smart-d1117f0f-c1d5-440b-8a51-a814d0b85ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359720312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
359720312
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1760335571
Short name T151
Test name
Test status
Simulation time 315174588 ps
CPU time 6.88 seconds
Started Jun 28 06:18:52 PM PDT 24
Finished Jun 28 06:19:08 PM PDT 24
Peak memory 215492 kb
Host smart-56911766-dea7-4838-a18a-4c3642bb8b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760335571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1760335571
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1874796492
Short name T1051
Test name
Test status
Simulation time 222965626 ps
CPU time 2.47 seconds
Started Jun 28 06:19:05 PM PDT 24
Finished Jun 28 06:19:12 PM PDT 24
Peak memory 217432 kb
Host smart-194fd3f6-c6a2-45c4-be28-5cbe635f248a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874796492 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1874796492
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2125363020
Short name T1121
Test name
Test status
Simulation time 13084384 ps
CPU time 0.76 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:17 PM PDT 24
Peak memory 203856 kb
Host smart-bedfb1a8-74f8-475a-be9b-9b588d7741c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125363020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2125363020
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2455782355
Short name T1093
Test name
Test status
Simulation time 426261453 ps
CPU time 3.15 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:07 PM PDT 24
Peak memory 215396 kb
Host smart-b4d6f1c5-144f-4992-955a-d870e45e58ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455782355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2455782355
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2300194214
Short name T1129
Test name
Test status
Simulation time 208788023 ps
CPU time 1.58 seconds
Started Jun 28 06:18:55 PM PDT 24
Finished Jun 28 06:19:05 PM PDT 24
Peak memory 215708 kb
Host smart-4568a192-348d-40a0-a86f-bd05554bb604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300194214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2300194214
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2449869461
Short name T1116
Test name
Test status
Simulation time 292269679 ps
CPU time 8.18 seconds
Started Jun 28 06:19:09 PM PDT 24
Finished Jun 28 06:19:20 PM PDT 24
Peak memory 215608 kb
Host smart-3acd7aaa-bb7b-4c50-852a-b9db746bdb59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449869461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2449869461
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1730613053
Short name T1061
Test name
Test status
Simulation time 37940551 ps
CPU time 2.77 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:19 PM PDT 24
Peak memory 218048 kb
Host smart-8d9dfe97-7452-4f89-ad69-ab5a2906508a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730613053 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1730613053
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1285375400
Short name T1151
Test name
Test status
Simulation time 73045210 ps
CPU time 1.32 seconds
Started Jun 28 06:19:03 PM PDT 24
Finished Jun 28 06:19:10 PM PDT 24
Peak memory 207140 kb
Host smart-2e479224-3841-476d-a523-39fff02dafec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285375400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1285375400
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4044608914
Short name T1050
Test name
Test status
Simulation time 20119453 ps
CPU time 0.7 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 204136 kb
Host smart-e65cf06d-7cb0-4362-99ce-9f6ee9ab11ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044608914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4044608914
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1425873231
Short name T1077
Test name
Test status
Simulation time 207913739 ps
CPU time 2.89 seconds
Started Jun 28 06:19:02 PM PDT 24
Finished Jun 28 06:19:11 PM PDT 24
Peak memory 215400 kb
Host smart-2da03818-38d2-4619-9179-0b2e4f183d1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425873231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1425873231
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1809631768
Short name T88
Test name
Test status
Simulation time 334920147 ps
CPU time 3.14 seconds
Started Jun 28 06:18:55 PM PDT 24
Finished Jun 28 06:19:07 PM PDT 24
Peak memory 215632 kb
Host smart-84024f76-e05d-4b1e-9df7-b856d6b1ceca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809631768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1809631768
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2107136232
Short name T1073
Test name
Test status
Simulation time 108677109 ps
CPU time 6.47 seconds
Started Jun 28 06:18:57 PM PDT 24
Finished Jun 28 06:19:12 PM PDT 24
Peak memory 215512 kb
Host smart-542284b5-d2ae-4e6e-9325-662e1350a065
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107136232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2107136232
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2522411936
Short name T1099
Test name
Test status
Simulation time 186888707 ps
CPU time 2.84 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:19 PM PDT 24
Peak memory 216556 kb
Host smart-c8c6173a-f060-4fad-a20e-6d8ab8796737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522411936 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2522411936
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.343185296
Short name T1079
Test name
Test status
Simulation time 307282952 ps
CPU time 1.36 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:05 PM PDT 24
Peak memory 207228 kb
Host smart-dc2318f7-c3c2-46d2-8ba0-ed7423027566
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343185296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.343185296
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1668224151
Short name T1040
Test name
Test status
Simulation time 37790715 ps
CPU time 0.72 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:17 PM PDT 24
Peak memory 203688 kb
Host smart-febbaa06-9668-484e-ac26-03b2df924bb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668224151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1668224151
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.924078144
Short name T135
Test name
Test status
Simulation time 925534657 ps
CPU time 4.19 seconds
Started Jun 28 06:18:56 PM PDT 24
Finished Jun 28 06:19:09 PM PDT 24
Peak memory 207268 kb
Host smart-1e0f5f86-6b28-424b-a707-8a59a49761d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924078144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.924078144
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2145020905
Short name T1137
Test name
Test status
Simulation time 132333886 ps
CPU time 3.55 seconds
Started Jun 28 06:19:11 PM PDT 24
Finished Jun 28 06:19:18 PM PDT 24
Peak memory 217600 kb
Host smart-7965ca25-2591-42cb-8e2b-e7b84105ba7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145020905 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2145020905
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4200077274
Short name T102
Test name
Test status
Simulation time 36894229 ps
CPU time 2.37 seconds
Started Jun 28 06:18:52 PM PDT 24
Finished Jun 28 06:19:07 PM PDT 24
Peak memory 207208 kb
Host smart-e2474c6f-feb4-48a4-b39c-f183a1879302
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200077274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
4200077274
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.686305425
Short name T1104
Test name
Test status
Simulation time 42913625 ps
CPU time 0.69 seconds
Started Jun 28 06:19:07 PM PDT 24
Finished Jun 28 06:19:12 PM PDT 24
Peak memory 204148 kb
Host smart-9e964db6-ba82-43b6-9836-539101d72299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686305425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.686305425
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3727305207
Short name T1109
Test name
Test status
Simulation time 47606188 ps
CPU time 1.71 seconds
Started Jun 28 06:19:11 PM PDT 24
Finished Jun 28 06:19:17 PM PDT 24
Peak memory 215384 kb
Host smart-99dd8f43-d101-4e4b-9d95-9f6df482718e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727305207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3727305207
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2565179505
Short name T1108
Test name
Test status
Simulation time 167666300 ps
CPU time 4.44 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:20 PM PDT 24
Peak memory 215072 kb
Host smart-6d0c2f1c-1cb9-414b-a2ac-bc157fa8b4fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565179505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2565179505
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2492636263
Short name T78
Test name
Test status
Simulation time 2742094489 ps
CPU time 19.23 seconds
Started Jun 28 06:19:11 PM PDT 24
Finished Jun 28 06:19:34 PM PDT 24
Peak memory 223676 kb
Host smart-d3cb71dc-a222-4828-b180-417f05f4acbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492636263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2492636263
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3142172689
Short name T1127
Test name
Test status
Simulation time 670894482 ps
CPU time 2.54 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:15 PM PDT 24
Peak memory 216536 kb
Host smart-a401598c-2225-43f1-aedb-6d49593e47d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142172689 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3142172689
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1108309458
Short name T1114
Test name
Test status
Simulation time 259045665 ps
CPU time 1.98 seconds
Started Jun 28 06:19:09 PM PDT 24
Finished Jun 28 06:19:15 PM PDT 24
Peak memory 215352 kb
Host smart-e59b70db-a6d8-4fb8-b6a4-d206b1bf9fa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108309458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1108309458
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2250225161
Short name T1124
Test name
Test status
Simulation time 37672029 ps
CPU time 0.69 seconds
Started Jun 28 06:19:04 PM PDT 24
Finished Jun 28 06:19:10 PM PDT 24
Peak memory 204108 kb
Host smart-63874c48-de5e-40ce-8ee1-df3b59fc220f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250225161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2250225161
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.784639185
Short name T1053
Test name
Test status
Simulation time 215991702 ps
CPU time 3.92 seconds
Started Jun 28 06:18:56 PM PDT 24
Finished Jun 28 06:19:09 PM PDT 24
Peak memory 215476 kb
Host smart-50628e41-1569-44b2-a05a-d275b42df07f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784639185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.784639185
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1080771752
Short name T1125
Test name
Test status
Simulation time 121428138 ps
CPU time 3.2 seconds
Started Jun 28 06:19:11 PM PDT 24
Finished Jun 28 06:19:18 PM PDT 24
Peak memory 215596 kb
Host smart-6928c82c-fe6c-4c2f-bd70-384b05630142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080771752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1080771752
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2785135390
Short name T1120
Test name
Test status
Simulation time 1044925036 ps
CPU time 7.14 seconds
Started Jun 28 06:19:01 PM PDT 24
Finished Jun 28 06:19:15 PM PDT 24
Peak memory 215860 kb
Host smart-c62fc175-7e10-4296-8f63-02706424b138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785135390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2785135390
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1000970058
Short name T1136
Test name
Test status
Simulation time 368456432 ps
CPU time 2.89 seconds
Started Jun 28 06:19:09 PM PDT 24
Finished Jun 28 06:19:15 PM PDT 24
Peak memory 217488 kb
Host smart-a98d8765-907e-42c1-b004-9c99cc510512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000970058 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1000970058
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3559321318
Short name T99
Test name
Test status
Simulation time 28527317 ps
CPU time 1.91 seconds
Started Jun 28 06:19:09 PM PDT 24
Finished Jun 28 06:19:14 PM PDT 24
Peak memory 207176 kb
Host smart-12e9952e-5888-4f62-8b85-f0a5fe86dd4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559321318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3559321318
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1731430145
Short name T1148
Test name
Test status
Simulation time 55913983 ps
CPU time 0.73 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:13 PM PDT 24
Peak memory 203868 kb
Host smart-53a2bede-33dc-47ed-ae51-4c79eca6a5f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731430145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1731430145
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2275971477
Short name T123
Test name
Test status
Simulation time 767511847 ps
CPU time 4.05 seconds
Started Jun 28 06:19:13 PM PDT 24
Finished Jun 28 06:19:20 PM PDT 24
Peak memory 215336 kb
Host smart-8f94a22c-556a-4975-b993-99df94a2f77d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275971477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2275971477
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2459264424
Short name T84
Test name
Test status
Simulation time 154018625 ps
CPU time 1.8 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:14 PM PDT 24
Peak memory 215704 kb
Host smart-d85654dd-3691-497f-b879-b4c0ed1213fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459264424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2459264424
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2585862529
Short name T154
Test name
Test status
Simulation time 1104106241 ps
CPU time 23.83 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:40 PM PDT 24
Peak memory 215708 kb
Host smart-228a9b6d-42d5-409b-b86f-2a2b38cbe845
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585862529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2585862529
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1663767736
Short name T1059
Test name
Test status
Simulation time 155148844 ps
CPU time 2.95 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:15 PM PDT 24
Peak memory 217952 kb
Host smart-319f70f2-4afd-4cbe-b46f-b4aac1469304
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663767736 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1663767736
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2401084466
Short name T104
Test name
Test status
Simulation time 128453326 ps
CPU time 1.34 seconds
Started Jun 28 06:19:06 PM PDT 24
Finished Jun 28 06:19:11 PM PDT 24
Peak memory 207148 kb
Host smart-03c7f9ef-31e9-435e-a1fc-1d8eceaf962a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401084466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2401084466
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.298729527
Short name T1058
Test name
Test status
Simulation time 35169971 ps
CPU time 0.75 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:16 PM PDT 24
Peak memory 204132 kb
Host smart-9fbf8487-3afc-4ec9-a099-76a9b1d2d91c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298729527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.298729527
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.757193126
Short name T1132
Test name
Test status
Simulation time 103196691 ps
CPU time 3.93 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 215364 kb
Host smart-9e6eedb7-456a-46cf-b538-2bf5f59d0102
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757193126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.757193126
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2448446332
Short name T1134
Test name
Test status
Simulation time 478512509 ps
CPU time 2.65 seconds
Started Jun 28 06:19:09 PM PDT 24
Finished Jun 28 06:19:16 PM PDT 24
Peak memory 215568 kb
Host smart-2798ba00-3058-43fe-b95e-359ae7c7e70c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448446332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2448446332
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.48342575
Short name T1095
Test name
Test status
Simulation time 349450013 ps
CPU time 8.11 seconds
Started Jun 28 06:18:56 PM PDT 24
Finished Jun 28 06:19:13 PM PDT 24
Peak memory 215436 kb
Host smart-f1481176-ae07-4f61-ad12-c955aec200de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48342575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_
tl_intg_err.48342575
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3616093204
Short name T95
Test name
Test status
Simulation time 918862242 ps
CPU time 2.76 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:18 PM PDT 24
Peak memory 216100 kb
Host smart-52225d76-ff70-417e-a12c-6761b3b4c6f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616093204 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3616093204
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.325223379
Short name T107
Test name
Test status
Simulation time 355350227 ps
CPU time 1.26 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:13 PM PDT 24
Peak memory 215324 kb
Host smart-684da5ed-992e-46ce-b7d2-7e83eb709b25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325223379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.325223379
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1006388218
Short name T1049
Test name
Test status
Simulation time 35556869 ps
CPU time 0.7 seconds
Started Jun 28 06:19:11 PM PDT 24
Finished Jun 28 06:19:15 PM PDT 24
Peak memory 203772 kb
Host smart-03286110-74ef-42bf-9647-6239e27bd8a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006388218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1006388218
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2528835383
Short name T1140
Test name
Test status
Simulation time 140042545 ps
CPU time 3.22 seconds
Started Jun 28 06:19:11 PM PDT 24
Finished Jun 28 06:19:18 PM PDT 24
Peak memory 215448 kb
Host smart-43afa310-fd39-4535-a3a4-e02d60248af0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528835383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2528835383
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4034131296
Short name T81
Test name
Test status
Simulation time 388914092 ps
CPU time 2.83 seconds
Started Jun 28 06:19:09 PM PDT 24
Finished Jun 28 06:19:15 PM PDT 24
Peak memory 215536 kb
Host smart-7e2a8a90-f479-47e4-8678-de4292588191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034131296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4034131296
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3631096620
Short name T148
Test name
Test status
Simulation time 1584614767 ps
CPU time 7.97 seconds
Started Jun 28 06:19:09 PM PDT 24
Finished Jun 28 06:19:20 PM PDT 24
Peak memory 215564 kb
Host smart-18dad46c-1376-47bc-b6d9-f477e048fe6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631096620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3631096620
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2182604726
Short name T80
Test name
Test status
Simulation time 258795448 ps
CPU time 3.7 seconds
Started Jun 28 06:19:07 PM PDT 24
Finished Jun 28 06:19:20 PM PDT 24
Peak memory 217400 kb
Host smart-3116595d-23a6-47b2-bfad-aa5b22bd94c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182604726 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2182604726
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1039544719
Short name T1112
Test name
Test status
Simulation time 1294432060 ps
CPU time 2.81 seconds
Started Jun 28 06:19:04 PM PDT 24
Finished Jun 28 06:19:12 PM PDT 24
Peak memory 215408 kb
Host smart-312e6f86-92c0-4282-9c4e-f58ae94368e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039544719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1039544719
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.841843515
Short name T1033
Test name
Test status
Simulation time 51631296 ps
CPU time 0.71 seconds
Started Jun 28 06:19:07 PM PDT 24
Finished Jun 28 06:19:12 PM PDT 24
Peak memory 203876 kb
Host smart-4e655d2d-d300-4701-ae1f-48fd16a6c093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841843515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.841843515
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1768903246
Short name T1062
Test name
Test status
Simulation time 126387594 ps
CPU time 3.28 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:19 PM PDT 24
Peak memory 215104 kb
Host smart-a072344e-0fa0-4c84-8720-58758f9d7c02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768903246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1768903246
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1689819442
Short name T1146
Test name
Test status
Simulation time 247807783 ps
CPU time 4.3 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:16 PM PDT 24
Peak memory 215624 kb
Host smart-6b5fe348-ceb3-47e4-a261-4ceba14f6b20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689819442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1689819442
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.361147651
Short name T153
Test name
Test status
Simulation time 4647608569 ps
CPU time 22.37 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:38 PM PDT 24
Peak memory 215536 kb
Host smart-47a4b327-21aa-414f-bc32-009186c820ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361147651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.361147651
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2922173660
Short name T1111
Test name
Test status
Simulation time 173402351 ps
CPU time 3.59 seconds
Started Jun 28 06:19:04 PM PDT 24
Finished Jun 28 06:19:12 PM PDT 24
Peak memory 218036 kb
Host smart-4426b5d6-8d35-4a53-8a77-d8ff6ee8738f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922173660 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2922173660
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1057304394
Short name T101
Test name
Test status
Simulation time 191044382 ps
CPU time 2.49 seconds
Started Jun 28 06:19:03 PM PDT 24
Finished Jun 28 06:19:11 PM PDT 24
Peak memory 215248 kb
Host smart-23f62ba1-804c-4d56-b21c-b53cb3bf1d81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057304394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1057304394
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1476073009
Short name T1048
Test name
Test status
Simulation time 13862025 ps
CPU time 0.79 seconds
Started Jun 28 06:18:56 PM PDT 24
Finished Jun 28 06:19:05 PM PDT 24
Peak memory 203872 kb
Host smart-c033fc5e-6ea3-4087-abbc-e91228c08e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476073009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1476073009
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1576105912
Short name T1078
Test name
Test status
Simulation time 160353779 ps
CPU time 4.49 seconds
Started Jun 28 06:19:10 PM PDT 24
Finished Jun 28 06:19:18 PM PDT 24
Peak memory 215416 kb
Host smart-daa025cc-4274-444e-a28e-fe4a3cc65522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576105912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1576105912
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4105919691
Short name T1147
Test name
Test status
Simulation time 141494700 ps
CPU time 2.36 seconds
Started Jun 28 06:19:09 PM PDT 24
Finished Jun 28 06:19:15 PM PDT 24
Peak memory 215624 kb
Host smart-872e33c9-2b05-4238-9413-c8ba081837c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105919691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4105919691
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.563338333
Short name T1122
Test name
Test status
Simulation time 1120109480 ps
CPU time 14.32 seconds
Started Jun 28 06:19:11 PM PDT 24
Finished Jun 28 06:19:29 PM PDT 24
Peak memory 215472 kb
Host smart-63399065-d4f3-4193-a5fc-67e758ab4ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563338333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.563338333
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.337687431
Short name T106
Test name
Test status
Simulation time 1996868673 ps
CPU time 20.16 seconds
Started Jun 28 06:18:45 PM PDT 24
Finished Jun 28 06:19:08 PM PDT 24
Peak memory 215352 kb
Host smart-d9d5e772-ddea-4188-947d-4fc1dfd4466e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337687431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.337687431
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.28990389
Short name T1082
Test name
Test status
Simulation time 2467185908 ps
CPU time 26.07 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:19:20 PM PDT 24
Peak memory 215440 kb
Host smart-6e12fb79-0773-4d28-acb0-877997a6d35e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28990389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
bit_bash.28990389
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.700443159
Short name T65
Test name
Test status
Simulation time 70336593 ps
CPU time 1.04 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:59 PM PDT 24
Peak memory 206944 kb
Host smart-326ead04-2054-4d98-b910-e23c3d0e8edc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700443159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.700443159
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2273702563
Short name T1105
Test name
Test status
Simulation time 102481039 ps
CPU time 1.8 seconds
Started Jun 28 06:19:01 PM PDT 24
Finished Jun 28 06:19:09 PM PDT 24
Peak memory 215552 kb
Host smart-216e16c8-812f-4dd4-b26d-325837d2036a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273702563 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2273702563
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.752739874
Short name T1071
Test name
Test status
Simulation time 154756518 ps
CPU time 1.81 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:58 PM PDT 24
Peak memory 215408 kb
Host smart-084aaea0-ddc3-4d70-8d83-5a3e0d57db42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752739874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.752739874
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.882005471
Short name T1072
Test name
Test status
Simulation time 40862918 ps
CPU time 0.74 seconds
Started Jun 28 06:18:43 PM PDT 24
Finished Jun 28 06:18:45 PM PDT 24
Peak memory 203796 kb
Host smart-add12822-c30d-4c5a-b492-d0e55a00dbb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882005471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.882005471
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2795422729
Short name T1088
Test name
Test status
Simulation time 53489130 ps
CPU time 1.26 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:53 PM PDT 24
Peak memory 215412 kb
Host smart-0591206d-9212-487d-a008-4591a9e3e017
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795422729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2795422729
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1781227438
Short name T1039
Test name
Test status
Simulation time 52523757 ps
CPU time 0.66 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:57 PM PDT 24
Peak memory 204044 kb
Host smart-3536d4c4-fb35-4263-aea8-de66747b80f2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781227438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1781227438
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3006510192
Short name T1087
Test name
Test status
Simulation time 143916303 ps
CPU time 3.91 seconds
Started Jun 28 06:18:45 PM PDT 24
Finished Jun 28 06:18:52 PM PDT 24
Peak memory 215448 kb
Host smart-8796f361-52e6-44ea-9b18-469da7c2d0ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006510192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3006510192
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2857885542
Short name T85
Test name
Test status
Simulation time 55435817 ps
CPU time 1.94 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:50 PM PDT 24
Peak memory 215628 kb
Host smart-621a07e1-c5e0-47cb-b185-f7b8adab32d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857885542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
857885542
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.123736064
Short name T77
Test name
Test status
Simulation time 592008523 ps
CPU time 15.7 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:19:05 PM PDT 24
Peak memory 215708 kb
Host smart-964ff834-d135-4bea-8135-d811340926f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123736064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.123736064
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.600858490
Short name T1138
Test name
Test status
Simulation time 13211153 ps
CPU time 0.73 seconds
Started Jun 28 06:19:05 PM PDT 24
Finished Jun 28 06:19:10 PM PDT 24
Peak memory 203868 kb
Host smart-83b8ef75-6dc2-40f7-9cd7-cf766bff4ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600858490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.600858490
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1386983834
Short name T1055
Test name
Test status
Simulation time 29528170 ps
CPU time 0.77 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:16 PM PDT 24
Peak memory 203880 kb
Host smart-b34e5fe4-ce1f-4464-a33c-a6b48f52cf3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386983834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1386983834
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2012779819
Short name T1076
Test name
Test status
Simulation time 11376922 ps
CPU time 0.75 seconds
Started Jun 28 06:18:56 PM PDT 24
Finished Jun 28 06:19:05 PM PDT 24
Peak memory 203848 kb
Host smart-dc99cc0f-db71-47b9-902a-49b55d826e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012779819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2012779819
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3342925949
Short name T1037
Test name
Test status
Simulation time 16333326 ps
CPU time 0.78 seconds
Started Jun 28 06:18:55 PM PDT 24
Finished Jun 28 06:19:05 PM PDT 24
Peak memory 204112 kb
Host smart-30239755-6695-435e-a18f-3a1e875b8992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342925949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3342925949
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1895944639
Short name T1096
Test name
Test status
Simulation time 11643933 ps
CPU time 0.73 seconds
Started Jun 28 06:18:52 PM PDT 24
Finished Jun 28 06:19:02 PM PDT 24
Peak memory 203860 kb
Host smart-e4109c1b-2464-4b8f-b70d-482fb19baa8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895944639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1895944639
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2078693877
Short name T1123
Test name
Test status
Simulation time 12163400 ps
CPU time 0.75 seconds
Started Jun 28 06:19:11 PM PDT 24
Finished Jun 28 06:19:15 PM PDT 24
Peak memory 204136 kb
Host smart-947aa9e0-b621-4a6d-8741-0d4914e3aef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078693877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2078693877
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3653847179
Short name T1044
Test name
Test status
Simulation time 14030521 ps
CPU time 0.73 seconds
Started Jun 28 06:19:05 PM PDT 24
Finished Jun 28 06:19:11 PM PDT 24
Peak memory 203844 kb
Host smart-b0282c28-f3d8-4f82-adf3-d3411af66d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653847179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3653847179
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4039572952
Short name T1142
Test name
Test status
Simulation time 12766193 ps
CPU time 0.85 seconds
Started Jun 28 06:19:00 PM PDT 24
Finished Jun 28 06:19:08 PM PDT 24
Peak memory 203836 kb
Host smart-467fb8b5-b8ce-40af-81be-01948c76db39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039572952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4039572952
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3135569329
Short name T1089
Test name
Test status
Simulation time 112492766 ps
CPU time 0.77 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:13 PM PDT 24
Peak memory 203888 kb
Host smart-68ca23d8-e092-4cb6-bedc-4d243046796a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135569329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3135569329
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2590903156
Short name T1046
Test name
Test status
Simulation time 48215867 ps
CPU time 0.76 seconds
Started Jun 28 06:19:01 PM PDT 24
Finished Jun 28 06:19:08 PM PDT 24
Peak memory 203864 kb
Host smart-83ded184-d251-4423-8bb8-df9ebc8ec592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590903156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2590903156
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3718553052
Short name T100
Test name
Test status
Simulation time 455914406 ps
CPU time 8.58 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 207116 kb
Host smart-8f49a1b9-84fb-402c-ac6c-7e7822fe6941
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718553052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3718553052
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1533665860
Short name T1060
Test name
Test status
Simulation time 632815355 ps
CPU time 12.93 seconds
Started Jun 28 06:18:43 PM PDT 24
Finished Jun 28 06:18:57 PM PDT 24
Peak memory 207152 kb
Host smart-fc901555-351a-42b8-b622-3003896f370f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533665860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1533665860
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3705154991
Short name T67
Test name
Test status
Simulation time 140532263 ps
CPU time 1.15 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:53 PM PDT 24
Peak memory 216408 kb
Host smart-81b96b78-733b-4b13-9d14-57a7255d37fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705154991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3705154991
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1448403726
Short name T1144
Test name
Test status
Simulation time 1731911687 ps
CPU time 3.87 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 218220 kb
Host smart-08ba2d8f-c919-49e5-bd32-cd2289c51525
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448403726 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1448403726
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3366223283
Short name T137
Test name
Test status
Simulation time 72981099 ps
CPU time 1.29 seconds
Started Jun 28 06:18:45 PM PDT 24
Finished Jun 28 06:18:49 PM PDT 24
Peak memory 207112 kb
Host smart-65a49dc8-4b58-4980-ad98-5e4d920b5404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366223283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
366223283
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1094283600
Short name T1126
Test name
Test status
Simulation time 12174859 ps
CPU time 0.77 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:00 PM PDT 24
Peak memory 203848 kb
Host smart-8807cae8-d413-4af4-b1e2-b360994de77a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094283600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
094283600
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2191977994
Short name T1065
Test name
Test status
Simulation time 44755096 ps
CPU time 1.8 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 215484 kb
Host smart-16e588a7-8d13-4b46-aa4d-c3aad659fc31
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191977994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2191977994
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3205782389
Short name T1038
Test name
Test status
Simulation time 16214816 ps
CPU time 0.65 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:51 PM PDT 24
Peak memory 203708 kb
Host smart-b749b3e0-85aa-4eb7-ba12-45b74042e6b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205782389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3205782389
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3627648880
Short name T121
Test name
Test status
Simulation time 122159817 ps
CPU time 3.99 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:19:00 PM PDT 24
Peak memory 215400 kb
Host smart-e2f470e0-f82f-439f-aa31-7237c74643c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627648880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3627648880
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2235849890
Short name T132
Test name
Test status
Simulation time 4292899528 ps
CPU time 14.76 seconds
Started Jun 28 06:18:45 PM PDT 24
Finished Jun 28 06:19:09 PM PDT 24
Peak memory 215932 kb
Host smart-a85d67cc-649c-40a1-a14b-1e83f579146c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235849890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2235849890
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3360154827
Short name T1032
Test name
Test status
Simulation time 35849343 ps
CPU time 0.72 seconds
Started Jun 28 06:18:55 PM PDT 24
Finished Jun 28 06:19:04 PM PDT 24
Peak memory 203796 kb
Host smart-27139b6d-253a-4664-81eb-5747616a96d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360154827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3360154827
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3017390158
Short name T1036
Test name
Test status
Simulation time 14764253 ps
CPU time 0.75 seconds
Started Jun 28 06:18:56 PM PDT 24
Finished Jun 28 06:19:05 PM PDT 24
Peak memory 203868 kb
Host smart-2d3e9183-5a62-45a6-800f-77db98e7de8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017390158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3017390158
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3741109136
Short name T1054
Test name
Test status
Simulation time 14317115 ps
CPU time 0.71 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:13 PM PDT 24
Peak memory 204140 kb
Host smart-3a8bb7ab-133c-478b-9570-38c2f7948ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741109136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3741109136
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3752904371
Short name T1098
Test name
Test status
Simulation time 17088280 ps
CPU time 0.79 seconds
Started Jun 28 06:19:09 PM PDT 24
Finished Jun 28 06:19:14 PM PDT 24
Peak memory 203824 kb
Host smart-4c30f586-98ce-4556-8482-a9d6df63c18e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752904371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3752904371
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3645174277
Short name T1150
Test name
Test status
Simulation time 43094424 ps
CPU time 0.82 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:13 PM PDT 24
Peak memory 203868 kb
Host smart-357f7132-713c-4e8a-95db-4714c8927d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645174277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3645174277
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2138249655
Short name T1107
Test name
Test status
Simulation time 39484515 ps
CPU time 0.7 seconds
Started Jun 28 06:18:58 PM PDT 24
Finished Jun 28 06:19:07 PM PDT 24
Peak memory 203764 kb
Host smart-90ffa3a9-db9d-4f37-a1a9-29fc416fcb15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138249655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2138249655
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3872920234
Short name T1069
Test name
Test status
Simulation time 248353905 ps
CPU time 0.79 seconds
Started Jun 28 06:18:56 PM PDT 24
Finished Jun 28 06:19:06 PM PDT 24
Peak memory 203800 kb
Host smart-3702f6e1-6fe8-41f2-82d2-04e6e4de5214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872920234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3872920234
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2379619603
Short name T1115
Test name
Test status
Simulation time 83381471 ps
CPU time 0.7 seconds
Started Jun 28 06:19:02 PM PDT 24
Finished Jun 28 06:19:09 PM PDT 24
Peak memory 203800 kb
Host smart-8ad8b93e-a4c3-4cea-bb1c-0c8ec88d2ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379619603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2379619603
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3139175424
Short name T1043
Test name
Test status
Simulation time 29241097 ps
CPU time 0.77 seconds
Started Jun 28 06:18:58 PM PDT 24
Finished Jun 28 06:19:07 PM PDT 24
Peak memory 203872 kb
Host smart-b99e435f-8038-4f41-bc14-5df8bc744aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139175424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3139175424
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.528593199
Short name T1141
Test name
Test status
Simulation time 159315478 ps
CPU time 0.74 seconds
Started Jun 28 06:19:14 PM PDT 24
Finished Jun 28 06:19:18 PM PDT 24
Peak memory 203868 kb
Host smart-45d7efb2-1228-421c-ad08-2dc4db109b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528593199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.528593199
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3253033646
Short name T1135
Test name
Test status
Simulation time 319032084 ps
CPU time 20.5 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:21 PM PDT 24
Peak memory 215376 kb
Host smart-eefedd6c-7cb4-49b7-a796-355ebcfb92c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253033646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3253033646
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3859116305
Short name T1117
Test name
Test status
Simulation time 5063220184 ps
CPU time 25 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:28 PM PDT 24
Peak memory 207260 kb
Host smart-e304bd4e-28f7-48c5-b858-8a76b6aa2abe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859116305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3859116305
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1287816662
Short name T68
Test name
Test status
Simulation time 16743299 ps
CPU time 0.93 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:58 PM PDT 24
Peak memory 206860 kb
Host smart-cf67c94b-221c-4afe-8914-6779013bf454
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287816662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1287816662
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1598521762
Short name T1113
Test name
Test status
Simulation time 58096556 ps
CPU time 4.25 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 219208 kb
Host smart-82e07faf-4297-4ebd-92e4-3ae2f16b1d7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598521762 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1598521762
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.390676750
Short name T1090
Test name
Test status
Simulation time 179336814 ps
CPU time 1.34 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 207212 kb
Host smart-b5fac9a3-d1e2-4fcf-8705-4c15dae48151
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390676750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.390676750
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1187966935
Short name T1119
Test name
Test status
Simulation time 88860985 ps
CPU time 0.76 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:51 PM PDT 24
Peak memory 203872 kb
Host smart-0451df64-fbfe-4b82-afe3-43bc89347dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187966935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
187966935
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.577661035
Short name T110
Test name
Test status
Simulation time 20178648 ps
CPU time 1.25 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:19:00 PM PDT 24
Peak memory 215492 kb
Host smart-57a10b1c-e8ad-421e-b55e-f646df3a3377
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577661035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.577661035
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2177743030
Short name T1063
Test name
Test status
Simulation time 50470167 ps
CPU time 0.64 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 203856 kb
Host smart-56c9aca0-2e3b-4d8e-966d-bb6669b4c117
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177743030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2177743030
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2565281351
Short name T1131
Test name
Test status
Simulation time 274028528 ps
CPU time 1.9 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:51 PM PDT 24
Peak memory 215392 kb
Host smart-849151a9-6c32-4180-b604-cb5bea005eb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565281351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2565281351
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.707987669
Short name T94
Test name
Test status
Simulation time 169019324 ps
CPU time 2.01 seconds
Started Jun 28 06:18:44 PM PDT 24
Finished Jun 28 06:18:48 PM PDT 24
Peak memory 215660 kb
Host smart-5037d841-be7d-4bc7-a824-bc883cde9b59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707987669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.707987669
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4074443348
Short name T150
Test name
Test status
Simulation time 1046611908 ps
CPU time 21.08 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:20 PM PDT 24
Peak memory 215424 kb
Host smart-a3b8d78b-99d4-43a6-a42a-df446dcb4e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074443348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4074443348
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2030829370
Short name T1052
Test name
Test status
Simulation time 16740583 ps
CPU time 0.73 seconds
Started Jun 28 06:19:10 PM PDT 24
Finished Jun 28 06:19:14 PM PDT 24
Peak memory 203828 kb
Host smart-c1a2f8ef-ffb5-4c7b-8d08-6938e801126b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030829370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2030829370
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.529884471
Short name T1101
Test name
Test status
Simulation time 14286281 ps
CPU time 0.72 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:16 PM PDT 24
Peak memory 203824 kb
Host smart-4ba25332-8732-472c-87f3-f46385316ae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529884471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.529884471
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3384986134
Short name T1045
Test name
Test status
Simulation time 13417992 ps
CPU time 0.75 seconds
Started Jun 28 06:19:01 PM PDT 24
Finished Jun 28 06:19:08 PM PDT 24
Peak memory 203744 kb
Host smart-280fb9b3-0f91-4770-8e7d-3bf0f050536a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384986134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3384986134
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4067357423
Short name T1035
Test name
Test status
Simulation time 40386403 ps
CPU time 0.78 seconds
Started Jun 28 06:19:01 PM PDT 24
Finished Jun 28 06:19:08 PM PDT 24
Peak memory 203864 kb
Host smart-e0f2eab0-42aa-421c-8b4e-d7f212019627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067357423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4067357423
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3398882315
Short name T1139
Test name
Test status
Simulation time 20143391 ps
CPU time 0.83 seconds
Started Jun 28 06:18:56 PM PDT 24
Finished Jun 28 06:19:05 PM PDT 24
Peak memory 203876 kb
Host smart-d9807149-11b5-4712-801a-1ee18aa59bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398882315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3398882315
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4227477953
Short name T1143
Test name
Test status
Simulation time 150388493 ps
CPU time 0.75 seconds
Started Jun 28 06:19:15 PM PDT 24
Finished Jun 28 06:19:19 PM PDT 24
Peak memory 203816 kb
Host smart-af158f0a-fa18-418c-a891-9841c6030af3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227477953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4227477953
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1451751215
Short name T1057
Test name
Test status
Simulation time 14243613 ps
CPU time 0.71 seconds
Started Jun 28 06:19:15 PM PDT 24
Finished Jun 28 06:19:19 PM PDT 24
Peak memory 204144 kb
Host smart-6d24a795-0f7d-492f-b4b5-43a8002c23bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451751215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1451751215
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3461606409
Short name T1145
Test name
Test status
Simulation time 105481176 ps
CPU time 0.73 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:17 PM PDT 24
Peak memory 204136 kb
Host smart-3fe53a9e-21c0-41a7-9190-272d2a033d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461606409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3461606409
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1686690179
Short name T1041
Test name
Test status
Simulation time 36920362 ps
CPU time 0.73 seconds
Started Jun 28 06:19:27 PM PDT 24
Finished Jun 28 06:19:30 PM PDT 24
Peak memory 203836 kb
Host smart-04b24490-1603-4f2d-ac49-3c3cf90d30d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686690179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1686690179
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2268637707
Short name T1103
Test name
Test status
Simulation time 12635210 ps
CPU time 0.7 seconds
Started Jun 28 06:19:16 PM PDT 24
Finished Jun 28 06:19:20 PM PDT 24
Peak memory 203820 kb
Host smart-53a6f38e-c3e3-4a55-bc78-6d1a45809207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268637707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2268637707
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2483713525
Short name T93
Test name
Test status
Simulation time 29424264 ps
CPU time 2.04 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:01 PM PDT 24
Peak memory 216464 kb
Host smart-1b819d90-2d53-4762-8723-1c2826043fa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483713525 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2483713525
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2237905624
Short name T1080
Test name
Test status
Simulation time 502477823 ps
CPU time 2.45 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:56 PM PDT 24
Peak memory 215328 kb
Host smart-8b7dea42-7124-429d-b697-2cbbc7e79b0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237905624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
237905624
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2121189640
Short name T1094
Test name
Test status
Simulation time 18392721 ps
CPU time 0.76 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:57 PM PDT 24
Peak memory 204144 kb
Host smart-43977ba8-2a76-4765-b1b0-42e3e83205d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121189640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
121189640
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1403445169
Short name T1118
Test name
Test status
Simulation time 167107089 ps
CPU time 4.14 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:04 PM PDT 24
Peak memory 215476 kb
Host smart-56b8565c-2e41-43e6-bd39-9de66e3dc307
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403445169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1403445169
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.606073302
Short name T92
Test name
Test status
Simulation time 239307346 ps
CPU time 4.87 seconds
Started Jun 28 06:18:44 PM PDT 24
Finished Jun 28 06:18:50 PM PDT 24
Peak memory 215588 kb
Host smart-c352aa8f-a476-4277-827a-395c920dcbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606073302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.606073302
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.649625953
Short name T131
Test name
Test status
Simulation time 4422298435 ps
CPU time 21.61 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:19:16 PM PDT 24
Peak memory 215540 kb
Host smart-8bd1523b-9a63-4049-bd5a-5e35cb9d657d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649625953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.649625953
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2786077102
Short name T79
Test name
Test status
Simulation time 104545651 ps
CPU time 1.77 seconds
Started Jun 28 06:18:52 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 216484 kb
Host smart-0622cb93-9e08-4943-ae81-72a8fd785cf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786077102 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2786077102
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1842350269
Short name T109
Test name
Test status
Simulation time 116384544 ps
CPU time 1.92 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:58 PM PDT 24
Peak memory 215408 kb
Host smart-a802d2e8-2f1a-465d-9ad1-4ba7b8e7a2fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842350269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
842350269
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3675391456
Short name T1042
Test name
Test status
Simulation time 18212765 ps
CPU time 0.78 seconds
Started Jun 28 06:19:03 PM PDT 24
Finished Jun 28 06:19:09 PM PDT 24
Peak memory 203856 kb
Host smart-193b6d5f-8b2a-4d11-9b1d-6fea0692ab29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675391456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
675391456
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3398674722
Short name T122
Test name
Test status
Simulation time 654354668 ps
CPU time 3.98 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:19:00 PM PDT 24
Peak memory 215468 kb
Host smart-9a532459-9384-4c51-996c-59fb34e1fa68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398674722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3398674722
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2236466703
Short name T87
Test name
Test status
Simulation time 104200639 ps
CPU time 3.62 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 215728 kb
Host smart-6a1ca1ce-ed6b-4dab-9beb-e6c8178aba75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236466703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
236466703
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.815468222
Short name T82
Test name
Test status
Simulation time 1118010443 ps
CPU time 14.41 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:19:13 PM PDT 24
Peak memory 215552 kb
Host smart-73b0212f-4a8e-4628-b0fa-e1a854012999
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815468222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.815468222
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2620151676
Short name T1074
Test name
Test status
Simulation time 128805141 ps
CPU time 3.86 seconds
Started Jun 28 06:18:53 PM PDT 24
Finished Jun 28 06:19:06 PM PDT 24
Peak memory 217340 kb
Host smart-5373f54a-b374-4950-9f86-38819fb0d154
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620151676 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2620151676
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1572110237
Short name T111
Test name
Test status
Simulation time 92108299 ps
CPU time 2.57 seconds
Started Jun 28 06:18:52 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 215348 kb
Host smart-d0b2a2d6-cb21-4187-b3d8-ac767cbc9410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572110237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
572110237
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.579321604
Short name T1070
Test name
Test status
Simulation time 23063301 ps
CPU time 0.68 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:59 PM PDT 24
Peak memory 203756 kb
Host smart-e7b01470-0881-4431-a0b4-16841bffa252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579321604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.579321604
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3486979391
Short name T1067
Test name
Test status
Simulation time 116555193 ps
CPU time 4.11 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:07 PM PDT 24
Peak memory 215564 kb
Host smart-b71bde1e-5b78-476d-b40a-3b5ddb7bf320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486979391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3486979391
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3067933489
Short name T1083
Test name
Test status
Simulation time 51036657 ps
CPU time 3.32 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 215568 kb
Host smart-669174f5-f81c-438b-a4d8-386ee8d5fb79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067933489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
067933489
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3784901761
Short name T1130
Test name
Test status
Simulation time 300856115 ps
CPU time 7.19 seconds
Started Jun 28 06:18:55 PM PDT 24
Finished Jun 28 06:19:11 PM PDT 24
Peak memory 215412 kb
Host smart-d8eefab9-842c-4d9e-832d-1a8169a6d7ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784901761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3784901761
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1471970957
Short name T90
Test name
Test status
Simulation time 154135858 ps
CPU time 3.58 seconds
Started Jun 28 06:19:09 PM PDT 24
Finished Jun 28 06:19:16 PM PDT 24
Peak memory 216692 kb
Host smart-571a2c5d-da6b-4b1a-a927-acb65e33d255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471970957 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1471970957
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3810346092
Short name T1066
Test name
Test status
Simulation time 66918994 ps
CPU time 1.18 seconds
Started Jun 28 06:19:08 PM PDT 24
Finished Jun 28 06:19:13 PM PDT 24
Peak memory 215400 kb
Host smart-63132ead-4892-48b5-92e4-10507ebf564e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810346092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
810346092
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2937299944
Short name T1133
Test name
Test status
Simulation time 27952766 ps
CPU time 0.81 seconds
Started Jun 28 06:18:53 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 203876 kb
Host smart-f0f6e6b1-0226-47d5-971c-e2f52d894d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937299944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
937299944
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1141564866
Short name T1097
Test name
Test status
Simulation time 287100301 ps
CPU time 3.27 seconds
Started Jun 28 06:19:07 PM PDT 24
Finished Jun 28 06:19:14 PM PDT 24
Peak memory 215408 kb
Host smart-5725e844-aa14-4e1d-9e4e-60d8a5530463
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141564866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1141564866
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4046744522
Short name T1106
Test name
Test status
Simulation time 183652751 ps
CPU time 1.86 seconds
Started Jun 28 06:18:52 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 215532 kb
Host smart-255b0de9-ab53-4936-86c9-e6cd985d68c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046744522 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.4046744522
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3807304755
Short name T1086
Test name
Test status
Simulation time 47956595 ps
CPU time 1.52 seconds
Started Jun 28 06:19:00 PM PDT 24
Finished Jun 28 06:19:08 PM PDT 24
Peak memory 215352 kb
Host smart-ac41e56a-e97d-40da-9bb0-e7c1d7174e5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807304755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
807304755
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3197355597
Short name T1056
Test name
Test status
Simulation time 64705507 ps
CPU time 0.74 seconds
Started Jun 28 06:18:55 PM PDT 24
Finished Jun 28 06:19:05 PM PDT 24
Peak memory 203772 kb
Host smart-050a5e3c-0dd2-41df-a7ef-1daff2874a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197355597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
197355597
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4041031613
Short name T1064
Test name
Test status
Simulation time 243861016 ps
CPU time 3.95 seconds
Started Jun 28 06:18:53 PM PDT 24
Finished Jun 28 06:19:05 PM PDT 24
Peak memory 215476 kb
Host smart-b3b323b8-2045-48ec-8630-7b0210b80051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041031613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4041031613
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3206589291
Short name T1128
Test name
Test status
Simulation time 286272654 ps
CPU time 3.95 seconds
Started Jun 28 06:19:12 PM PDT 24
Finished Jun 28 06:19:20 PM PDT 24
Peak memory 216588 kb
Host smart-26fb02b2-d704-431a-9d32-84d1dbfb531c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206589291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
206589291
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.11973353
Short name T152
Test name
Test status
Simulation time 782351546 ps
CPU time 17.52 seconds
Started Jun 28 06:19:06 PM PDT 24
Finished Jun 28 06:19:28 PM PDT 24
Peak memory 215876 kb
Host smart-3c735ca9-b909-4381-8491-85defab68cbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11973353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_t
l_intg_err.11973353
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.566750163
Short name T564
Test name
Test status
Simulation time 15323019 ps
CPU time 0.73 seconds
Started Jun 28 06:28:10 PM PDT 24
Finished Jun 28 06:28:12 PM PDT 24
Peak memory 204828 kb
Host smart-5ffca0d1-d8e8-408e-8baa-337bb9c47caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566750163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.566750163
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1472099397
Short name T212
Test name
Test status
Simulation time 810973163 ps
CPU time 12.24 seconds
Started Jun 28 06:27:52 PM PDT 24
Finished Jun 28 06:28:05 PM PDT 24
Peak memory 224448 kb
Host smart-34dad0f3-f2db-4eb5-9f32-8e1a90514561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472099397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1472099397
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.195419104
Short name T566
Test name
Test status
Simulation time 13579098 ps
CPU time 0.81 seconds
Started Jun 28 06:27:52 PM PDT 24
Finished Jun 28 06:27:55 PM PDT 24
Peak memory 206548 kb
Host smart-056cbe3b-03a9-456e-850d-428fcdd5f6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195419104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.195419104
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1564499469
Short name T362
Test name
Test status
Simulation time 21479736195 ps
CPU time 148.04 seconds
Started Jun 28 06:27:53 PM PDT 24
Finished Jun 28 06:30:24 PM PDT 24
Peak memory 256780 kb
Host smart-ba80f393-0def-4ad0-a81e-d4ba52a20cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564499469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1564499469
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3358876525
Short name T323
Test name
Test status
Simulation time 1869586072 ps
CPU time 6.28 seconds
Started Jun 28 06:27:55 PM PDT 24
Finished Jun 28 06:28:03 PM PDT 24
Peak memory 217500 kb
Host smart-3e8f3485-239b-4a4a-8a70-a7ee4ead3039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358876525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3358876525
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3328190258
Short name T930
Test name
Test status
Simulation time 7831935430 ps
CPU time 55.63 seconds
Started Jun 28 06:27:56 PM PDT 24
Finished Jun 28 06:28:53 PM PDT 24
Peak memory 224556 kb
Host smart-3a7c7a02-a3fe-4dc4-90fd-12e5f7b431d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328190258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3328190258
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1943967178
Short name T395
Test name
Test status
Simulation time 978648900 ps
CPU time 5.29 seconds
Started Jun 28 06:27:52 PM PDT 24
Finished Jun 28 06:27:59 PM PDT 24
Peak memory 232680 kb
Host smart-04737c6e-8db1-4beb-9cd3-3f8ddc77e86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943967178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1943967178
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3537706898
Short name T973
Test name
Test status
Simulation time 24101454183 ps
CPU time 105.4 seconds
Started Jun 28 06:27:53 PM PDT 24
Finished Jun 28 06:29:41 PM PDT 24
Peak memory 240436 kb
Host smart-46242893-6a4e-4d0d-9e58-7204c5d66dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537706898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3537706898
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1841814970
Short name T633
Test name
Test status
Simulation time 1092119992 ps
CPU time 3.69 seconds
Started Jun 28 06:27:56 PM PDT 24
Finished Jun 28 06:28:01 PM PDT 24
Peak memory 224412 kb
Host smart-ec037666-0f0f-4f0c-ad5e-9430851d9ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841814970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1841814970
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4126835207
Short name T840
Test name
Test status
Simulation time 30603073101 ps
CPU time 81.75 seconds
Started Jun 28 06:27:54 PM PDT 24
Finished Jun 28 06:29:18 PM PDT 24
Peak memory 240624 kb
Host smart-24941a61-c545-4561-9e02-7cab6cb23a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126835207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4126835207
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2740415028
Short name T228
Test name
Test status
Simulation time 80851861757 ps
CPU time 19.33 seconds
Started Jun 28 06:27:52 PM PDT 24
Finished Jun 28 06:28:13 PM PDT 24
Peak memory 232764 kb
Host smart-299d433a-914c-4841-aeff-a297fc2d1ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740415028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2740415028
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1800687240
Short name T467
Test name
Test status
Simulation time 61099345 ps
CPU time 2.32 seconds
Started Jun 28 06:27:52 PM PDT 24
Finished Jun 28 06:27:56 PM PDT 24
Peak memory 232384 kb
Host smart-eeb98200-5205-413a-89af-f45cdefc066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800687240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1800687240
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1325277639
Short name T906
Test name
Test status
Simulation time 85898124 ps
CPU time 3.92 seconds
Started Jun 28 06:27:53 PM PDT 24
Finished Jun 28 06:28:00 PM PDT 24
Peak memory 222408 kb
Host smart-a02c4faa-e2aa-4ff9-9cea-0405c02a7a84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1325277639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1325277639
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2717163782
Short name T49
Test name
Test status
Simulation time 270014379 ps
CPU time 1.15 seconds
Started Jun 28 06:28:07 PM PDT 24
Finished Jun 28 06:28:09 PM PDT 24
Peak memory 235544 kb
Host smart-f450fbdc-93a1-45ea-9409-196402ab75ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717163782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2717163782
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.945990540
Short name T965
Test name
Test status
Simulation time 6171466329 ps
CPU time 160.91 seconds
Started Jun 28 06:28:11 PM PDT 24
Finished Jun 28 06:30:53 PM PDT 24
Peak memory 271240 kb
Host smart-62280cd9-9dc1-4b97-8408-9dca717b2b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945990540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.945990540
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2002455130
Short name T787
Test name
Test status
Simulation time 586510632 ps
CPU time 3.78 seconds
Started Jun 28 06:27:52 PM PDT 24
Finished Jun 28 06:27:59 PM PDT 24
Peak memory 216280 kb
Host smart-4737ed36-02a9-4bb8-b59b-070bae4e9fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002455130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2002455130
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1540464116
Short name T807
Test name
Test status
Simulation time 1056711083 ps
CPU time 5.74 seconds
Started Jun 28 06:27:53 PM PDT 24
Finished Jun 28 06:28:02 PM PDT 24
Peak memory 216188 kb
Host smart-fa02649b-44ff-4493-9569-804fab587678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540464116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1540464116
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1140385936
Short name T978
Test name
Test status
Simulation time 1094677915 ps
CPU time 1.85 seconds
Started Jun 28 06:27:53 PM PDT 24
Finished Jun 28 06:27:58 PM PDT 24
Peak memory 216212 kb
Host smart-936ff205-c1c5-46f3-ace2-89a1a6c56f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140385936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1140385936
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1511177314
Short name T448
Test name
Test status
Simulation time 17342393 ps
CPU time 0.72 seconds
Started Jun 28 06:27:53 PM PDT 24
Finished Jun 28 06:27:57 PM PDT 24
Peak memory 205896 kb
Host smart-3d35f626-4984-4fc2-9236-69972cd1efe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511177314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1511177314
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.929525425
Short name T662
Test name
Test status
Simulation time 59393882 ps
CPU time 2.37 seconds
Started Jun 28 06:27:54 PM PDT 24
Finished Jun 28 06:27:59 PM PDT 24
Peak memory 232372 kb
Host smart-3414e477-91de-471c-8bb1-12ffd66cc4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929525425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.929525425
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.218076448
Short name T548
Test name
Test status
Simulation time 247677094 ps
CPU time 2.89 seconds
Started Jun 28 06:28:09 PM PDT 24
Finished Jun 28 06:28:14 PM PDT 24
Peak memory 224452 kb
Host smart-785a25ae-9abb-4acb-a78a-eb631377d772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218076448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.218076448
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2775018892
Short name T449
Test name
Test status
Simulation time 14326884 ps
CPU time 0.82 seconds
Started Jun 28 06:28:08 PM PDT 24
Finished Jun 28 06:28:10 PM PDT 24
Peak memory 206888 kb
Host smart-62e25734-a8e3-4236-a38b-265181e44de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775018892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2775018892
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1833599173
Short name T805
Test name
Test status
Simulation time 198100483917 ps
CPU time 275.26 seconds
Started Jun 28 06:28:09 PM PDT 24
Finished Jun 28 06:32:46 PM PDT 24
Peak memory 267096 kb
Host smart-771671b6-8c51-4fda-b354-39e1ebe653ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833599173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1833599173
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2956108062
Short name T1030
Test name
Test status
Simulation time 49739467551 ps
CPU time 39.64 seconds
Started Jun 28 06:28:09 PM PDT 24
Finished Jun 28 06:28:50 PM PDT 24
Peak memory 240972 kb
Host smart-144d7e62-bdae-490d-ad43-71a5788263cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956108062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2956108062
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3653473051
Short name T196
Test name
Test status
Simulation time 139210231259 ps
CPU time 226.05 seconds
Started Jun 28 06:28:07 PM PDT 24
Finished Jun 28 06:31:55 PM PDT 24
Peak memory 249256 kb
Host smart-6a1fb93f-e54a-457e-9aca-46eaa167e9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653473051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3653473051
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4202150915
Short name T762
Test name
Test status
Simulation time 1102092144 ps
CPU time 5.75 seconds
Started Jun 28 06:28:08 PM PDT 24
Finished Jun 28 06:28:16 PM PDT 24
Peak memory 232672 kb
Host smart-993a9435-f223-4f61-86ef-cf2ef488f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202150915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4202150915
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2626298578
Short name T813
Test name
Test status
Simulation time 98472083981 ps
CPU time 177.89 seconds
Started Jun 28 06:28:11 PM PDT 24
Finished Jun 28 06:31:10 PM PDT 24
Peak memory 257216 kb
Host smart-43ee9718-9770-45a1-9934-960cb4484c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626298578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2626298578
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3940952295
Short name T848
Test name
Test status
Simulation time 703279787 ps
CPU time 4.53 seconds
Started Jun 28 06:28:11 PM PDT 24
Finished Jun 28 06:28:17 PM PDT 24
Peak memory 232660 kb
Host smart-fe2c0080-4af6-4711-add0-83605cad5120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940952295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3940952295
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.226479689
Short name T713
Test name
Test status
Simulation time 1649771723 ps
CPU time 9.79 seconds
Started Jun 28 06:28:09 PM PDT 24
Finished Jun 28 06:28:21 PM PDT 24
Peak memory 224436 kb
Host smart-02c701b6-6f3e-4784-b467-fc75ef637e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226479689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.226479689
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1359664073
Short name T809
Test name
Test status
Simulation time 23807082 ps
CPU time 1.08 seconds
Started Jun 28 06:28:11 PM PDT 24
Finished Jun 28 06:28:13 PM PDT 24
Peak memory 216768 kb
Host smart-9f4b0b0e-e42d-4c6f-93ef-421db65d8c52
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359664073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1359664073
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1363556564
Short name T977
Test name
Test status
Simulation time 3528486287 ps
CPU time 11.4 seconds
Started Jun 28 06:28:08 PM PDT 24
Finished Jun 28 06:28:21 PM PDT 24
Peak memory 224544 kb
Host smart-756ddf20-52cd-4b46-974f-6daf64511529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363556564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1363556564
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.201413328
Short name T900
Test name
Test status
Simulation time 9348868026 ps
CPU time 27.7 seconds
Started Jun 28 06:28:08 PM PDT 24
Finished Jun 28 06:28:37 PM PDT 24
Peak memory 248856 kb
Host smart-a09a0563-78b1-4d7e-b272-ee6e92861831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201413328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.201413328
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.29845163
Short name T660
Test name
Test status
Simulation time 1581939696 ps
CPU time 6.71 seconds
Started Jun 28 06:28:08 PM PDT 24
Finished Jun 28 06:28:17 PM PDT 24
Peak memory 222260 kb
Host smart-193367ec-fde6-475b-9717-32f0422cbf1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=29845163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct
.29845163
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2201628083
Short name T50
Test name
Test status
Simulation time 177412949 ps
CPU time 1.18 seconds
Started Jun 28 06:28:06 PM PDT 24
Finished Jun 28 06:28:08 PM PDT 24
Peak memory 237008 kb
Host smart-ab3b18ad-cbca-4064-8916-76b409510c46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201628083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2201628083
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2215287273
Short name T707
Test name
Test status
Simulation time 44924358569 ps
CPU time 200.71 seconds
Started Jun 28 06:28:08 PM PDT 24
Finished Jun 28 06:31:30 PM PDT 24
Peak memory 264704 kb
Host smart-31acd51e-15a3-460c-908b-e39fd6b55393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215287273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2215287273
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3318881977
Short name T280
Test name
Test status
Simulation time 7372744307 ps
CPU time 19.6 seconds
Started Jun 28 06:28:09 PM PDT 24
Finished Jun 28 06:28:30 PM PDT 24
Peak memory 216444 kb
Host smart-a152d34a-25a0-43a9-b145-fe511dc58681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318881977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3318881977
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2592389322
Short name T383
Test name
Test status
Simulation time 1354099665 ps
CPU time 6.19 seconds
Started Jun 28 06:28:08 PM PDT 24
Finished Jun 28 06:28:15 PM PDT 24
Peak memory 216200 kb
Host smart-20443f02-d760-4476-89ca-5a2e6cba91ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592389322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2592389322
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.762283242
Short name T484
Test name
Test status
Simulation time 86482130 ps
CPU time 1.43 seconds
Started Jun 28 06:28:11 PM PDT 24
Finished Jun 28 06:28:14 PM PDT 24
Peak memory 215984 kb
Host smart-74529c17-19fa-4461-b5db-07fa3ecfd95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762283242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.762283242
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1680987295
Short name T116
Test name
Test status
Simulation time 13189448 ps
CPU time 0.73 seconds
Started Jun 28 06:28:08 PM PDT 24
Finished Jun 28 06:28:11 PM PDT 24
Peak memory 205868 kb
Host smart-26d7dd33-14ab-44ec-b682-6886a0be6181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680987295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1680987295
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.477626661
Short name T994
Test name
Test status
Simulation time 693823723 ps
CPU time 2.35 seconds
Started Jun 28 06:28:09 PM PDT 24
Finished Jun 28 06:28:13 PM PDT 24
Peak memory 224136 kb
Host smart-cc670728-d5a8-472c-923f-ecef97feda3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477626661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.477626661
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2900658955
Short name T708
Test name
Test status
Simulation time 14445865 ps
CPU time 0.73 seconds
Started Jun 28 06:29:22 PM PDT 24
Finished Jun 28 06:29:24 PM PDT 24
Peak memory 205444 kb
Host smart-18fdd795-f5ff-4f48-a506-0c4f307c22df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900658955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2900658955
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2030645205
Short name T465
Test name
Test status
Simulation time 142781839 ps
CPU time 2.93 seconds
Started Jun 28 06:29:12 PM PDT 24
Finished Jun 28 06:29:16 PM PDT 24
Peak memory 232680 kb
Host smart-fc4d0292-6d4c-40c3-9321-2c6b81e7aa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030645205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2030645205
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3050405829
Short name T553
Test name
Test status
Simulation time 47731050 ps
CPU time 0.74 seconds
Started Jun 28 06:29:11 PM PDT 24
Finished Jun 28 06:29:14 PM PDT 24
Peak memory 205424 kb
Host smart-15967e79-0833-4724-a035-e35ceca642f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050405829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3050405829
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1998757
Short name T875
Test name
Test status
Simulation time 2355269278 ps
CPU time 50.82 seconds
Started Jun 28 06:29:19 PM PDT 24
Finished Jun 28 06:30:12 PM PDT 24
Peak memory 253252 kb
Host smart-1aec6a68-b4eb-43c2-91c9-65aa170a49ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1998757
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1827424896
Short name T433
Test name
Test status
Simulation time 1432360134 ps
CPU time 4.54 seconds
Started Jun 28 06:29:20 PM PDT 24
Finished Jun 28 06:29:26 PM PDT 24
Peak memory 217212 kb
Host smart-acc2e46d-0661-4cd7-b028-6dee780491d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827424896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1827424896
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1941282669
Short name T169
Test name
Test status
Simulation time 3063709952 ps
CPU time 42.88 seconds
Started Jun 28 06:29:22 PM PDT 24
Finished Jun 28 06:30:06 PM PDT 24
Peak memory 237652 kb
Host smart-455588c8-e7b2-4101-b18e-5ba7c2b92b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941282669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1941282669
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3989741180
Short name T779
Test name
Test status
Simulation time 45094570 ps
CPU time 0.77 seconds
Started Jun 28 06:29:20 PM PDT 24
Finished Jun 28 06:29:22 PM PDT 24
Peak memory 215792 kb
Host smart-924d7c65-d70a-4256-b35e-139809f81564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989741180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3989741180
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.697757646
Short name T997
Test name
Test status
Simulation time 2903938369 ps
CPU time 8.33 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:19 PM PDT 24
Peak memory 232800 kb
Host smart-d641396e-3e18-490e-a763-c00154e4c420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697757646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.697757646
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4054484917
Short name T693
Test name
Test status
Simulation time 592618329 ps
CPU time 14.43 seconds
Started Jun 28 06:29:10 PM PDT 24
Finished Jun 28 06:29:26 PM PDT 24
Peak memory 240856 kb
Host smart-0f805565-bcec-49d5-86c4-84a57427fa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054484917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4054484917
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3802395068
Short name T947
Test name
Test status
Simulation time 14487292 ps
CPU time 1 seconds
Started Jun 28 06:29:10 PM PDT 24
Finished Jun 28 06:29:13 PM PDT 24
Peak memory 218080 kb
Host smart-f8a1d63f-bfaa-4224-8563-2bb932eead0d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802395068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3802395068
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1152799677
Short name T1016
Test name
Test status
Simulation time 15593903266 ps
CPU time 12.24 seconds
Started Jun 28 06:29:11 PM PDT 24
Finished Jun 28 06:29:25 PM PDT 24
Peak memory 224592 kb
Host smart-47be831a-112b-44ad-919a-44599ad7c821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152799677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1152799677
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3247870336
Short name T201
Test name
Test status
Simulation time 23373904139 ps
CPU time 31.2 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:42 PM PDT 24
Peak memory 232752 kb
Host smart-6b161d2f-701d-4eca-974f-3fcedd0ca615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247870336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3247870336
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2976656335
Short name T1013
Test name
Test status
Simulation time 14567404055 ps
CPU time 8.77 seconds
Started Jun 28 06:29:17 PM PDT 24
Finished Jun 28 06:29:27 PM PDT 24
Peak memory 223156 kb
Host smart-45690e1c-ad0f-4472-abc7-c8f436ceb7f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2976656335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2976656335
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2774486393
Short name T4
Test name
Test status
Simulation time 21036896372 ps
CPU time 29.01 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:40 PM PDT 24
Peak memory 216340 kb
Host smart-167a529a-e909-4dee-b39b-018d6400bd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774486393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2774486393
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.477170384
Short name T835
Test name
Test status
Simulation time 4279559310 ps
CPU time 6.24 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:17 PM PDT 24
Peak memory 216336 kb
Host smart-10278b16-2187-4716-b0b7-915c01508336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477170384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.477170384
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3986673733
Short name T650
Test name
Test status
Simulation time 354770818 ps
CPU time 7.34 seconds
Started Jun 28 06:29:18 PM PDT 24
Finished Jun 28 06:29:27 PM PDT 24
Peak memory 216368 kb
Host smart-82abbd1c-ba00-4742-b7f7-1687c42e758d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986673733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3986673733
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3606669032
Short name T951
Test name
Test status
Simulation time 139269244 ps
CPU time 0.79 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:12 PM PDT 24
Peak memory 205892 kb
Host smart-f70417c5-073f-4de7-a766-b69df2160e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606669032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3606669032
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3021839664
Short name T382
Test name
Test status
Simulation time 6025933431 ps
CPU time 18.16 seconds
Started Jun 28 06:29:12 PM PDT 24
Finished Jun 28 06:29:31 PM PDT 24
Peak memory 232760 kb
Host smart-24fc99bb-739f-49cf-8104-7b8071cf9fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021839664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3021839664
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.592928728
Short name T366
Test name
Test status
Simulation time 14618548 ps
CPU time 0.7 seconds
Started Jun 28 06:29:30 PM PDT 24
Finished Jun 28 06:29:31 PM PDT 24
Peak memory 205424 kb
Host smart-5c46112e-dd8f-419a-9f1a-c9a5e0101f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592928728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.592928728
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2455316548
Short name T73
Test name
Test status
Simulation time 265666005 ps
CPU time 4.91 seconds
Started Jun 28 06:29:20 PM PDT 24
Finished Jun 28 06:29:26 PM PDT 24
Peak memory 224444 kb
Host smart-18c562c8-cfff-4ade-b3ec-9389ecc9e2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455316548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2455316548
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.271796736
Short name T974
Test name
Test status
Simulation time 112593647 ps
CPU time 0.81 seconds
Started Jun 28 06:29:20 PM PDT 24
Finished Jun 28 06:29:22 PM PDT 24
Peak memory 206876 kb
Host smart-041716c8-5e8f-4497-8ec7-4801b16cc88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271796736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.271796736
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.696601264
Short name T700
Test name
Test status
Simulation time 4353971620 ps
CPU time 15.67 seconds
Started Jun 28 06:29:22 PM PDT 24
Finished Jun 28 06:29:39 PM PDT 24
Peak memory 235588 kb
Host smart-a384c25d-14b6-4d2c-8b8f-f4ec4cdf9671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696601264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.696601264
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2858644065
Short name T205
Test name
Test status
Simulation time 9450145714 ps
CPU time 92.22 seconds
Started Jun 28 06:29:17 PM PDT 24
Finished Jun 28 06:30:50 PM PDT 24
Peak memory 252776 kb
Host smart-cffd9dd8-b631-4861-a713-122714a5854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858644065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2858644065
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.27952221
Short name T686
Test name
Test status
Simulation time 234000078 ps
CPU time 5.27 seconds
Started Jun 28 06:29:20 PM PDT 24
Finished Jun 28 06:29:27 PM PDT 24
Peak memory 232680 kb
Host smart-819627c2-7416-4689-b5ea-b1732ee13e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27952221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.27952221
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1137313490
Short name T175
Test name
Test status
Simulation time 188090486719 ps
CPU time 345.08 seconds
Started Jun 28 06:29:22 PM PDT 24
Finished Jun 28 06:35:08 PM PDT 24
Peak memory 257384 kb
Host smart-02080850-d2a4-449b-915b-b4ea95513500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137313490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1137313490
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.7886195
Short name T215
Test name
Test status
Simulation time 2330701739 ps
CPU time 7.5 seconds
Started Jun 28 06:29:19 PM PDT 24
Finished Jun 28 06:29:28 PM PDT 24
Peak memory 232744 kb
Host smart-86686301-c2f2-4879-ba88-b5be9b1ba8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7886195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.7886195
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2904648824
Short name T623
Test name
Test status
Simulation time 14587112049 ps
CPU time 139.79 seconds
Started Jun 28 06:29:20 PM PDT 24
Finished Jun 28 06:31:41 PM PDT 24
Peak memory 232760 kb
Host smart-1ee66542-6f31-4bc1-81ec-41ea73afd8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904648824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2904648824
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1187098688
Short name T695
Test name
Test status
Simulation time 14274481 ps
CPU time 1 seconds
Started Jun 28 06:29:21 PM PDT 24
Finished Jun 28 06:29:24 PM PDT 24
Peak memory 218012 kb
Host smart-e027ccd5-ee4a-49c7-80f9-d84a2924b724
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187098688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1187098688
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.474391458
Short name T872
Test name
Test status
Simulation time 9809749469 ps
CPU time 15.53 seconds
Started Jun 28 06:29:22 PM PDT 24
Finished Jun 28 06:29:39 PM PDT 24
Peak memory 232760 kb
Host smart-2a82f187-4e8e-4c42-8efc-2b6cbf39ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474391458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.474391458
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1682537367
Short name T224
Test name
Test status
Simulation time 1838837716 ps
CPU time 5.12 seconds
Started Jun 28 06:29:22 PM PDT 24
Finished Jun 28 06:29:29 PM PDT 24
Peak memory 224460 kb
Host smart-2d383e6e-6a70-4b7b-8286-0f78b55ff658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682537367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1682537367
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.710928113
Short name T52
Test name
Test status
Simulation time 535987260 ps
CPU time 8.4 seconds
Started Jun 28 06:29:19 PM PDT 24
Finished Jun 28 06:29:29 PM PDT 24
Peak memory 221892 kb
Host smart-6132af8e-85ec-4f42-a52e-7e7f0259f9fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=710928113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.710928113
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1444292714
Short name T20
Test name
Test status
Simulation time 43909051513 ps
CPU time 401.43 seconds
Started Jun 28 06:29:31 PM PDT 24
Finished Jun 28 06:36:14 PM PDT 24
Peak memory 264752 kb
Host smart-9390ed1f-802f-4b62-9e8c-12e1a4f585c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444292714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1444292714
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2093310947
Short name T679
Test name
Test status
Simulation time 1163036989 ps
CPU time 3.23 seconds
Started Jun 28 06:29:21 PM PDT 24
Finished Jun 28 06:29:26 PM PDT 24
Peak memory 216664 kb
Host smart-6971f082-f084-48d2-9aea-454afa114705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093310947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2093310947
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.349275599
Short name T899
Test name
Test status
Simulation time 1606252866 ps
CPU time 2.52 seconds
Started Jun 28 06:29:22 PM PDT 24
Finished Jun 28 06:29:26 PM PDT 24
Peak memory 216108 kb
Host smart-0dfb04b3-1446-45a7-8a5b-351cb65f0219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349275599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.349275599
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1192541018
Short name T649
Test name
Test status
Simulation time 486093338 ps
CPU time 4.17 seconds
Started Jun 28 06:29:21 PM PDT 24
Finished Jun 28 06:29:27 PM PDT 24
Peak memory 216284 kb
Host smart-6decb0c5-1d08-42b5-8b20-76190127dc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192541018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1192541018
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2724313495
Short name T456
Test name
Test status
Simulation time 22390072 ps
CPU time 0.79 seconds
Started Jun 28 06:29:20 PM PDT 24
Finished Jun 28 06:29:22 PM PDT 24
Peak memory 205880 kb
Host smart-83de838a-dff2-4342-aec1-2d18bc819089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724313495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2724313495
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1276978517
Short name T454
Test name
Test status
Simulation time 2616798469 ps
CPU time 4.03 seconds
Started Jun 28 06:29:20 PM PDT 24
Finished Jun 28 06:29:25 PM PDT 24
Peak memory 224556 kb
Host smart-0e02e42f-34de-4a45-9c87-121f08d80716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276978517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1276978517
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.39588140
Short name T893
Test name
Test status
Simulation time 14501398 ps
CPU time 0.73 seconds
Started Jun 28 06:29:32 PM PDT 24
Finished Jun 28 06:29:35 PM PDT 24
Peak memory 204832 kb
Host smart-d30e706d-5ec6-4016-95a2-552b87aec8cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39588140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.39588140
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.660108360
Short name T661
Test name
Test status
Simulation time 696773893 ps
CPU time 3.03 seconds
Started Jun 28 06:29:32 PM PDT 24
Finished Jun 28 06:29:37 PM PDT 24
Peak memory 224408 kb
Host smart-63e0546b-2874-450d-b4eb-08405e8b359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660108360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.660108360
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2845929409
Short name T726
Test name
Test status
Simulation time 40512272 ps
CPU time 0.83 seconds
Started Jun 28 06:29:30 PM PDT 24
Finished Jun 28 06:29:32 PM PDT 24
Peak memory 206884 kb
Host smart-36252e35-26ac-4fb6-ba97-3ae6c6f2364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845929409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2845929409
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.335952638
Short name T789
Test name
Test status
Simulation time 7504232589 ps
CPU time 19.84 seconds
Started Jun 28 06:29:33 PM PDT 24
Finished Jun 28 06:29:54 PM PDT 24
Peak memory 224588 kb
Host smart-0d5dbe0e-4055-4217-aaf9-032899cbb697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335952638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.335952638
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3562603574
Short name T1012
Test name
Test status
Simulation time 3443585156 ps
CPU time 50.21 seconds
Started Jun 28 06:29:34 PM PDT 24
Finished Jun 28 06:30:25 PM PDT 24
Peak memory 249792 kb
Host smart-36856fdf-52ed-4bfb-8bc9-e8873e709baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562603574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3562603574
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2936445957
Short name T888
Test name
Test status
Simulation time 21068224420 ps
CPU time 268.98 seconds
Started Jun 28 06:29:32 PM PDT 24
Finished Jun 28 06:34:02 PM PDT 24
Peak memory 265648 kb
Host smart-63cdfe8c-b164-4888-8321-9278b582ba43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936445957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2936445957
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2885898468
Short name T429
Test name
Test status
Simulation time 961949323 ps
CPU time 8.82 seconds
Started Jun 28 06:29:31 PM PDT 24
Finished Jun 28 06:29:40 PM PDT 24
Peak memory 237120 kb
Host smart-9846a1af-978c-4a48-a7d8-14dff26b2af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885898468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2885898468
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3320969754
Short name T186
Test name
Test status
Simulation time 17412974367 ps
CPU time 97.37 seconds
Started Jun 28 06:29:32 PM PDT 24
Finished Jun 28 06:31:10 PM PDT 24
Peak memory 265532 kb
Host smart-f6421ce7-c6e2-48d4-8bff-69274745e4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320969754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3320969754
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2082237605
Short name T823
Test name
Test status
Simulation time 1073996540 ps
CPU time 7.34 seconds
Started Jun 28 06:29:32 PM PDT 24
Finished Jun 28 06:29:41 PM PDT 24
Peak memory 224440 kb
Host smart-6c05091e-45ed-4558-9f6a-79f2721a1574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082237605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2082237605
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3281843987
Short name T534
Test name
Test status
Simulation time 5609578078 ps
CPU time 20.99 seconds
Started Jun 28 06:29:31 PM PDT 24
Finished Jun 28 06:29:53 PM PDT 24
Peak memory 232824 kb
Host smart-fce73915-f45e-4062-8d52-4d0cf6790d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281843987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3281843987
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2352653078
Short name T709
Test name
Test status
Simulation time 48188878 ps
CPU time 1.06 seconds
Started Jun 28 06:29:31 PM PDT 24
Finished Jun 28 06:29:32 PM PDT 24
Peak memory 216776 kb
Host smart-5dcdba63-f994-47b6-a797-c60f8b801ff1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352653078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2352653078
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1904067393
Short name T659
Test name
Test status
Simulation time 534423068 ps
CPU time 6.1 seconds
Started Jun 28 06:29:31 PM PDT 24
Finished Jun 28 06:29:37 PM PDT 24
Peak memory 240672 kb
Host smart-482290be-b7e8-44d2-9eab-23746a3bc178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904067393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1904067393
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.746832305
Short name T634
Test name
Test status
Simulation time 22740074221 ps
CPU time 19.85 seconds
Started Jun 28 06:29:33 PM PDT 24
Finished Jun 28 06:29:54 PM PDT 24
Peak memory 232720 kb
Host smart-dadd448d-d010-403d-a565-2309edd110a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746832305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.746832305
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.885874507
Short name T428
Test name
Test status
Simulation time 419882017 ps
CPU time 4.11 seconds
Started Jun 28 06:29:33 PM PDT 24
Finished Jun 28 06:29:39 PM PDT 24
Peak memory 220632 kb
Host smart-102bcc32-292f-4a8c-8d78-63c3ef6c8634
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=885874507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.885874507
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.383001309
Short name T549
Test name
Test status
Simulation time 7869834956 ps
CPU time 143.82 seconds
Started Jun 28 06:29:31 PM PDT 24
Finished Jun 28 06:31:56 PM PDT 24
Peak memory 256608 kb
Host smart-f73626f5-aada-4481-988d-2401c560f5bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383001309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.383001309
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1361364414
Short name T751
Test name
Test status
Simulation time 4541930511 ps
CPU time 23.86 seconds
Started Jun 28 06:29:32 PM PDT 24
Finished Jun 28 06:29:57 PM PDT 24
Peak memory 216312 kb
Host smart-68d05ea7-9f36-4d5d-aa7e-94f9ea9efbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361364414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1361364414
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2193545533
Short name T882
Test name
Test status
Simulation time 97186266771 ps
CPU time 15.7 seconds
Started Jun 28 06:29:33 PM PDT 24
Finished Jun 28 06:29:50 PM PDT 24
Peak memory 217600 kb
Host smart-48493901-5f74-4571-9dc1-b34d131ac6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193545533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2193545533
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.749998703
Short name T319
Test name
Test status
Simulation time 239031994 ps
CPU time 4.25 seconds
Started Jun 28 06:29:30 PM PDT 24
Finished Jun 28 06:29:35 PM PDT 24
Peak memory 216220 kb
Host smart-e11dfb19-38ed-45f7-94c9-9cbb6842dbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749998703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.749998703
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.816906660
Short name T320
Test name
Test status
Simulation time 33346650 ps
CPU time 0.72 seconds
Started Jun 28 06:29:31 PM PDT 24
Finished Jun 28 06:29:33 PM PDT 24
Peak memory 205584 kb
Host smart-126aefba-d548-4b09-94cf-3c65fd283710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816906660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.816906660
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.370732275
Short name T417
Test name
Test status
Simulation time 2530633580 ps
CPU time 10.28 seconds
Started Jun 28 06:29:30 PM PDT 24
Finished Jun 28 06:29:41 PM PDT 24
Peak memory 232752 kb
Host smart-61a0f2c7-4366-47bc-b500-e56d6a8ed61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370732275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.370732275
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.582013897
Short name T1014
Test name
Test status
Simulation time 62757580 ps
CPU time 0.74 seconds
Started Jun 28 06:29:42 PM PDT 24
Finished Jun 28 06:29:44 PM PDT 24
Peak memory 204832 kb
Host smart-6a6cdf5d-017e-4adc-9eb9-a6bb4ca339c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582013897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.582013897
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3722972348
Short name T915
Test name
Test status
Simulation time 506499285 ps
CPU time 4.31 seconds
Started Jun 28 06:29:42 PM PDT 24
Finished Jun 28 06:29:48 PM PDT 24
Peak memory 224436 kb
Host smart-fb3465f9-0bbf-49a7-9684-a092f82d7375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722972348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3722972348
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3236440277
Short name T714
Test name
Test status
Simulation time 145466383 ps
CPU time 0.77 seconds
Started Jun 28 06:29:33 PM PDT 24
Finished Jun 28 06:29:35 PM PDT 24
Peak memory 206496 kb
Host smart-ad3f7f3d-43ec-4639-9d5b-f1c3fca18b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236440277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3236440277
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.13751787
Short name T532
Test name
Test status
Simulation time 39886884353 ps
CPU time 79.29 seconds
Started Jun 28 06:29:40 PM PDT 24
Finished Jun 28 06:31:00 PM PDT 24
Peak memory 249220 kb
Host smart-3856bcca-2eb4-4e07-854f-25bfca7de418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13751787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.13751787
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4110363751
Short name T967
Test name
Test status
Simulation time 3888278182 ps
CPU time 73.3 seconds
Started Jun 28 06:29:42 PM PDT 24
Finished Jun 28 06:30:56 PM PDT 24
Peak memory 265308 kb
Host smart-488ae6ca-e208-4f1c-8451-abe24e04b36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110363751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4110363751
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1162118291
Short name T1004
Test name
Test status
Simulation time 216905422 ps
CPU time 7.55 seconds
Started Jun 28 06:29:41 PM PDT 24
Finished Jun 28 06:29:50 PM PDT 24
Peak memory 240068 kb
Host smart-0602f6e0-9459-48a9-9e12-9b870e018a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162118291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1162118291
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1189267918
Short name T983
Test name
Test status
Simulation time 2877718132 ps
CPU time 19.1 seconds
Started Jun 28 06:29:40 PM PDT 24
Finished Jun 28 06:30:00 PM PDT 24
Peak memory 241004 kb
Host smart-acfe84df-d9fb-476c-97b8-b0c0e00b91a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189267918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1189267918
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4012155683
Short name T825
Test name
Test status
Simulation time 132109071 ps
CPU time 3.86 seconds
Started Jun 28 06:29:41 PM PDT 24
Finished Jun 28 06:29:46 PM PDT 24
Peak memory 224436 kb
Host smart-2d9c005f-0061-465e-ac14-5c5ae61cbed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012155683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4012155683
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1472012228
Short name T444
Test name
Test status
Simulation time 159380876 ps
CPU time 4.75 seconds
Started Jun 28 06:29:40 PM PDT 24
Finished Jun 28 06:29:46 PM PDT 24
Peak memory 234264 kb
Host smart-60eb5f4c-dcc0-4aa6-b276-a225290eb92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472012228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1472012228
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2881998920
Short name T31
Test name
Test status
Simulation time 176670197 ps
CPU time 1.08 seconds
Started Jun 28 06:29:32 PM PDT 24
Finished Jun 28 06:29:34 PM PDT 24
Peak memory 218004 kb
Host smart-e57f2cd8-0d7d-4afa-b8d6-7a538af530ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881998920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2881998920
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3349094771
Short name T259
Test name
Test status
Simulation time 2514898918 ps
CPU time 4.36 seconds
Started Jun 28 06:29:42 PM PDT 24
Finished Jun 28 06:29:47 PM PDT 24
Peak memory 224524 kb
Host smart-4971a025-2618-4e25-85ac-17979c76cb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349094771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3349094771
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.656025513
Short name T861
Test name
Test status
Simulation time 801527199 ps
CPU time 10.74 seconds
Started Jun 28 06:29:43 PM PDT 24
Finished Jun 28 06:29:55 PM PDT 24
Peak memory 248508 kb
Host smart-331295e0-7298-4f19-84e9-661901a2b5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656025513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.656025513
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2584071825
Short name T504
Test name
Test status
Simulation time 1700932042 ps
CPU time 6.38 seconds
Started Jun 28 06:29:45 PM PDT 24
Finished Jun 28 06:29:52 PM PDT 24
Peak memory 220576 kb
Host smart-2838ec7d-fd84-45a7-96cd-d9808fe52882
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2584071825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2584071825
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2969999314
Short name T576
Test name
Test status
Simulation time 82869343847 ps
CPU time 206.18 seconds
Started Jun 28 06:29:45 PM PDT 24
Finished Jun 28 06:33:12 PM PDT 24
Peak memory 257452 kb
Host smart-ce94281b-c5bf-4908-adb2-e681977e1897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969999314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2969999314
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.71108859
Short name T289
Test name
Test status
Simulation time 2907803852 ps
CPU time 16.22 seconds
Started Jun 28 06:29:42 PM PDT 24
Finished Jun 28 06:29:59 PM PDT 24
Peak memory 219268 kb
Host smart-f186ff73-1c2c-465f-b2b2-3b428f132d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71108859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.71108859
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4271604731
Short name T557
Test name
Test status
Simulation time 25186442 ps
CPU time 0.72 seconds
Started Jun 28 06:29:33 PM PDT 24
Finished Jun 28 06:29:35 PM PDT 24
Peak memory 205656 kb
Host smart-ca8c2245-8097-482d-bdcb-c4d294035278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271604731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4271604731
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2167854065
Short name T531
Test name
Test status
Simulation time 159848206 ps
CPU time 1.42 seconds
Started Jun 28 06:29:43 PM PDT 24
Finished Jun 28 06:29:45 PM PDT 24
Peak memory 216156 kb
Host smart-6eabf58b-9086-44e0-bf18-c9c0feca5bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167854065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2167854065
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1206718279
Short name T1005
Test name
Test status
Simulation time 347564407 ps
CPU time 0.92 seconds
Started Jun 28 06:29:41 PM PDT 24
Finished Jun 28 06:29:43 PM PDT 24
Peak memory 206300 kb
Host smart-5566144d-0ff2-4060-9019-7fac20f18ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206718279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1206718279
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4033006220
Short name T461
Test name
Test status
Simulation time 1323256381 ps
CPU time 5.38 seconds
Started Jun 28 06:29:42 PM PDT 24
Finished Jun 28 06:29:48 PM PDT 24
Peak memory 232644 kb
Host smart-85a46268-31d3-4284-869a-7b488bd4b670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033006220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4033006220
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.214374484
Short name T528
Test name
Test status
Simulation time 15137454 ps
CPU time 0.73 seconds
Started Jun 28 06:29:53 PM PDT 24
Finished Jun 28 06:29:55 PM PDT 24
Peak memory 204832 kb
Host smart-8f0cafbb-aa75-4241-a423-57922a5b8880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214374484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.214374484
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1544984125
Short name T409
Test name
Test status
Simulation time 35126711 ps
CPU time 2.56 seconds
Started Jun 28 06:29:55 PM PDT 24
Finished Jun 28 06:29:59 PM PDT 24
Peak memory 232380 kb
Host smart-af4e15c3-0117-4a5c-8b3e-c631381c922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544984125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1544984125
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2078544251
Short name T612
Test name
Test status
Simulation time 45635090 ps
CPU time 0.83 seconds
Started Jun 28 06:29:43 PM PDT 24
Finished Jun 28 06:29:45 PM PDT 24
Peak memory 206556 kb
Host smart-e90f94be-2285-407e-9e40-c0f7789f175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078544251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2078544251
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2054473927
Short name T119
Test name
Test status
Simulation time 3772635294 ps
CPU time 81.14 seconds
Started Jun 28 06:29:52 PM PDT 24
Finished Jun 28 06:31:15 PM PDT 24
Peak memory 254580 kb
Host smart-dcc20941-5641-44ec-9707-75f64cdd2ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054473927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2054473927
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3311579842
Short name T166
Test name
Test status
Simulation time 259169091697 ps
CPU time 635.34 seconds
Started Jun 28 06:29:53 PM PDT 24
Finished Jun 28 06:40:30 PM PDT 24
Peak memory 269616 kb
Host smart-44461042-6602-4c4b-ab71-b35637d7d61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311579842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3311579842
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1765717414
Short name T939
Test name
Test status
Simulation time 4203130350 ps
CPU time 24.9 seconds
Started Jun 28 06:29:50 PM PDT 24
Finished Jun 28 06:30:16 PM PDT 24
Peak memory 232672 kb
Host smart-af8243c7-37fd-4322-a5fc-b3af41869cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765717414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1765717414
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1173641170
Short name T677
Test name
Test status
Simulation time 2244577758 ps
CPU time 32.21 seconds
Started Jun 28 06:29:52 PM PDT 24
Finished Jun 28 06:30:26 PM PDT 24
Peak memory 249100 kb
Host smart-82578e32-8f02-4e70-8f89-f4051ad69f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173641170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1173641170
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1927093043
Short name T936
Test name
Test status
Simulation time 1870633088 ps
CPU time 17.65 seconds
Started Jun 28 06:29:55 PM PDT 24
Finished Jun 28 06:30:14 PM PDT 24
Peak memory 224420 kb
Host smart-e8bce3c2-3689-45bd-b6f0-b25c6df3cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927093043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1927093043
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1344781016
Short name T841
Test name
Test status
Simulation time 522576790 ps
CPU time 9.95 seconds
Started Jun 28 06:29:52 PM PDT 24
Finished Jun 28 06:30:03 PM PDT 24
Peak memory 232644 kb
Host smart-476b27d6-1434-4d73-a215-bf8c54dd53a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344781016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1344781016
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.199945885
Short name T30
Test name
Test status
Simulation time 15097666 ps
CPU time 1.04 seconds
Started Jun 28 06:29:41 PM PDT 24
Finished Jun 28 06:29:43 PM PDT 24
Peak memory 216760 kb
Host smart-163a4c7a-725b-4a9b-a29c-d474d8a279e9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199945885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.199945885
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.498149157
Short name T56
Test name
Test status
Simulation time 1817177369 ps
CPU time 3.89 seconds
Started Jun 28 06:29:50 PM PDT 24
Finished Jun 28 06:29:54 PM PDT 24
Peak memory 224464 kb
Host smart-fb09983a-6a7e-47a4-b3c2-4afd8159e0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498149157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.498149157
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3315228344
Short name T913
Test name
Test status
Simulation time 2799523673 ps
CPU time 8.55 seconds
Started Jun 28 06:29:41 PM PDT 24
Finished Jun 28 06:29:51 PM PDT 24
Peak memory 224524 kb
Host smart-19803392-d729-4850-91dc-f72205c9ab14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315228344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3315228344
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1992397103
Short name T482
Test name
Test status
Simulation time 5464238699 ps
CPU time 12.93 seconds
Started Jun 28 06:29:50 PM PDT 24
Finished Jun 28 06:30:04 PM PDT 24
Peak memory 222980 kb
Host smart-785aeb87-e530-4f1d-9fba-67ae5ff173c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1992397103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1992397103
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1766938472
Short name T143
Test name
Test status
Simulation time 115327520294 ps
CPU time 372.44 seconds
Started Jun 28 06:29:54 PM PDT 24
Finished Jun 28 06:36:08 PM PDT 24
Peak memory 265976 kb
Host smart-0c064989-0a30-40f0-8a9b-4973ea05b12c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766938472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1766938472
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4243652849
Short name T113
Test name
Test status
Simulation time 13210682 ps
CPU time 0.74 seconds
Started Jun 28 06:29:46 PM PDT 24
Finished Jun 28 06:29:47 PM PDT 24
Peak memory 205184 kb
Host smart-3be61f6f-f2fc-44db-926e-dba151dff1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243652849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4243652849
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4081781550
Short name T742
Test name
Test status
Simulation time 29680066 ps
CPU time 1.15 seconds
Started Jun 28 06:29:46 PM PDT 24
Finished Jun 28 06:29:48 PM PDT 24
Peak memory 206776 kb
Host smart-b4ede0a1-fc66-4cbf-9c79-487ea2738a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081781550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4081781550
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3942784292
Short name T871
Test name
Test status
Simulation time 100168178 ps
CPU time 0.82 seconds
Started Jun 28 06:29:45 PM PDT 24
Finished Jun 28 06:29:47 PM PDT 24
Peak memory 205848 kb
Host smart-2cb01e2f-6885-41a1-88df-dc6bc8360130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942784292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3942784292
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1015782011
Short name T388
Test name
Test status
Simulation time 130864485 ps
CPU time 2.98 seconds
Started Jun 28 06:29:50 PM PDT 24
Finished Jun 28 06:29:54 PM PDT 24
Peak memory 232620 kb
Host smart-a293235a-eedb-4d55-92b8-4c72410aefd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015782011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1015782011
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1784759785
Short name T386
Test name
Test status
Simulation time 14727883 ps
CPU time 0.73 seconds
Started Jun 28 06:30:05 PM PDT 24
Finished Jun 28 06:30:07 PM PDT 24
Peak memory 205748 kb
Host smart-ead0b316-179d-48a4-a6b3-fb500c08d2a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784759785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1784759785
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.667035618
Short name T72
Test name
Test status
Simulation time 2394182323 ps
CPU time 6.95 seconds
Started Jun 28 06:30:00 PM PDT 24
Finished Jun 28 06:30:09 PM PDT 24
Peak memory 232828 kb
Host smart-ec898403-2029-4dd0-84ef-98f2eea9597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667035618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.667035618
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3758596264
Short name T333
Test name
Test status
Simulation time 40410519 ps
CPU time 0.78 seconds
Started Jun 28 06:29:51 PM PDT 24
Finished Jun 28 06:29:53 PM PDT 24
Peak memory 206544 kb
Host smart-ff5964ec-3899-41a4-a956-551e73a39043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758596264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3758596264
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4155573778
Short name T486
Test name
Test status
Simulation time 24445914314 ps
CPU time 39.92 seconds
Started Jun 28 06:30:01 PM PDT 24
Finished Jun 28 06:30:42 PM PDT 24
Peak memory 236360 kb
Host smart-09d18856-bc11-49cf-8140-ba0ac8f3fd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155573778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4155573778
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2232623784
Short name T385
Test name
Test status
Simulation time 45075323457 ps
CPU time 56.02 seconds
Started Jun 28 06:29:59 PM PDT 24
Finished Jun 28 06:30:57 PM PDT 24
Peak memory 234496 kb
Host smart-4942dd0b-1b6e-4793-8f78-48cc9376dff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232623784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2232623784
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.378529647
Short name T620
Test name
Test status
Simulation time 167922974363 ps
CPU time 279.4 seconds
Started Jun 28 06:30:00 PM PDT 24
Finished Jun 28 06:34:41 PM PDT 24
Peak memory 240956 kb
Host smart-397bf91a-5669-473d-a4fe-210644cf8bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378529647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.378529647
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3008880368
Short name T345
Test name
Test status
Simulation time 5316840183 ps
CPU time 21.64 seconds
Started Jun 28 06:30:07 PM PDT 24
Finished Jun 28 06:30:29 PM PDT 24
Peak memory 239016 kb
Host smart-7e16a7b7-3ac3-4c2e-81d1-9eaad1164811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008880368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3008880368
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.841391976
Short name T583
Test name
Test status
Simulation time 52431564219 ps
CPU time 92.25 seconds
Started Jun 28 06:29:59 PM PDT 24
Finished Jun 28 06:31:33 PM PDT 24
Peak memory 249172 kb
Host smart-58a0138b-2cc5-4372-b837-a95f18f3b278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841391976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.841391976
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3580001651
Short name T744
Test name
Test status
Simulation time 7294837265 ps
CPU time 6.79 seconds
Started Jun 28 06:30:00 PM PDT 24
Finished Jun 28 06:30:08 PM PDT 24
Peak memory 224592 kb
Host smart-efa4c13f-58db-40fe-8095-3f03ee0fa5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580001651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3580001651
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.274085635
Short name T217
Test name
Test status
Simulation time 830755365 ps
CPU time 4.58 seconds
Started Jun 28 06:30:05 PM PDT 24
Finished Jun 28 06:30:11 PM PDT 24
Peak memory 232620 kb
Host smart-2f485a25-015f-4207-8f60-76bcef8bc4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274085635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.274085635
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2054818026
Short name T982
Test name
Test status
Simulation time 16616485 ps
CPU time 1 seconds
Started Jun 28 06:29:52 PM PDT 24
Finished Jun 28 06:29:55 PM PDT 24
Peak memory 218080 kb
Host smart-4a277d4c-c90b-4ec0-9c0b-6d14c5ff08b3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054818026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2054818026
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.8232606
Short name T560
Test name
Test status
Simulation time 9379297492 ps
CPU time 9.9 seconds
Started Jun 28 06:29:49 PM PDT 24
Finished Jun 28 06:30:00 PM PDT 24
Peak memory 224552 kb
Host smart-14017d57-27b1-4471-9b66-9962f94914f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8232606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.8232606
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3068825472
Short name T827
Test name
Test status
Simulation time 556031279 ps
CPU time 2.86 seconds
Started Jun 28 06:29:52 PM PDT 24
Finished Jun 28 06:29:56 PM PDT 24
Peak memory 232612 kb
Host smart-64217738-9ee8-4988-bc88-65a3d94eea0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068825472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3068825472
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3517392276
Short name T471
Test name
Test status
Simulation time 938347778 ps
CPU time 13.85 seconds
Started Jun 28 06:29:58 PM PDT 24
Finished Jun 28 06:30:13 PM PDT 24
Peak memory 222320 kb
Host smart-d319c5af-fd26-47ac-99e6-3d25e278cee8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3517392276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3517392276
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2800021998
Short name T138
Test name
Test status
Simulation time 133253607439 ps
CPU time 334.64 seconds
Started Jun 28 06:30:01 PM PDT 24
Finished Jun 28 06:35:37 PM PDT 24
Peak memory 254948 kb
Host smart-b7126d84-edaf-4886-8073-75a09ac8c2f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800021998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2800021998
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.697143848
Short name T781
Test name
Test status
Simulation time 623482973 ps
CPU time 9.62 seconds
Started Jun 28 06:29:52 PM PDT 24
Finished Jun 28 06:30:03 PM PDT 24
Peak memory 216512 kb
Host smart-92ec988f-8464-4f83-8a7e-6cba3b9e8756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697143848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.697143848
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3629850847
Short name T380
Test name
Test status
Simulation time 11630200537 ps
CPU time 33.18 seconds
Started Jun 28 06:29:53 PM PDT 24
Finished Jun 28 06:30:28 PM PDT 24
Peak memory 216276 kb
Host smart-388e669a-8cf6-4d47-a89b-bd914e9783f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629850847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3629850847
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1214421211
Short name T351
Test name
Test status
Simulation time 80513866 ps
CPU time 1.5 seconds
Started Jun 28 06:29:49 PM PDT 24
Finished Jun 28 06:29:52 PM PDT 24
Peak memory 216232 kb
Host smart-a307c965-67aa-47d3-9cf0-0a53cf4b40ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214421211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1214421211
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1456167197
Short name T1009
Test name
Test status
Simulation time 118753892 ps
CPU time 1.1 seconds
Started Jun 28 06:29:51 PM PDT 24
Finished Jun 28 06:29:53 PM PDT 24
Peak memory 206860 kb
Host smart-68a6767e-1316-4bc6-84c3-e3247f48c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456167197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1456167197
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2762253271
Short name T13
Test name
Test status
Simulation time 283465702 ps
CPU time 3.3 seconds
Started Jun 28 06:30:00 PM PDT 24
Finished Jun 28 06:30:05 PM PDT 24
Peak memory 224432 kb
Host smart-a32a1d4b-1ed2-4421-996e-b0233e97f282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762253271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2762253271
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4000066703
Short name T822
Test name
Test status
Simulation time 47327725 ps
CPU time 0.76 seconds
Started Jun 28 06:30:13 PM PDT 24
Finished Jun 28 06:30:15 PM PDT 24
Peak memory 205700 kb
Host smart-cbd50037-bba4-4d70-95d5-d19f3c8fe56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000066703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4000066703
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.618474603
Short name T412
Test name
Test status
Simulation time 5481061017 ps
CPU time 18.04 seconds
Started Jun 28 06:30:01 PM PDT 24
Finished Jun 28 06:30:20 PM PDT 24
Peak memory 224592 kb
Host smart-c0582837-cbc6-44c6-95f3-8edcb524c13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618474603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.618474603
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3508296570
Short name T434
Test name
Test status
Simulation time 14656576 ps
CPU time 0.78 seconds
Started Jun 28 06:30:07 PM PDT 24
Finished Jun 28 06:30:08 PM PDT 24
Peak memory 206872 kb
Host smart-44a4dfa5-7930-405a-b92e-c07e0dd843d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508296570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3508296570
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1731734203
Short name T298
Test name
Test status
Simulation time 27355527 ps
CPU time 0.88 seconds
Started Jun 28 06:30:12 PM PDT 24
Finished Jun 28 06:30:15 PM PDT 24
Peak memory 215844 kb
Host smart-07c94324-2e7f-40d5-8799-36e391a68291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731734203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1731734203
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2378919353
Short name T931
Test name
Test status
Simulation time 12124515115 ps
CPU time 83.49 seconds
Started Jun 28 06:30:12 PM PDT 24
Finished Jun 28 06:31:37 PM PDT 24
Peak memory 232796 kb
Host smart-7524e6ee-310d-4e9e-b10f-a72a173c9350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378919353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2378919353
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2480581464
Short name T440
Test name
Test status
Simulation time 445178302 ps
CPU time 6.88 seconds
Started Jun 28 06:30:13 PM PDT 24
Finished Jun 28 06:30:22 PM PDT 24
Peak memory 217268 kb
Host smart-6649ce2b-fb3b-4f97-b70d-3aca753455c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480581464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2480581464
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1007967623
Short name T907
Test name
Test status
Simulation time 303599967 ps
CPU time 7.03 seconds
Started Jun 28 06:30:00 PM PDT 24
Finished Jun 28 06:30:08 PM PDT 24
Peak memory 232684 kb
Host smart-83a751d0-9913-4c7e-b517-556ff42b313b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007967623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1007967623
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2008923345
Short name T197
Test name
Test status
Simulation time 28412613502 ps
CPU time 14.74 seconds
Started Jun 28 06:30:00 PM PDT 24
Finished Jun 28 06:30:17 PM PDT 24
Peak memory 224556 kb
Host smart-964600f2-07d4-40d4-8172-887d769e8f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008923345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2008923345
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4210405320
Short name T563
Test name
Test status
Simulation time 25108192283 ps
CPU time 76.23 seconds
Started Jun 28 06:30:01 PM PDT 24
Finished Jun 28 06:31:19 PM PDT 24
Peak memory 224556 kb
Host smart-8d1ff172-58dd-4a15-835b-1fcc7b5db73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210405320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4210405320
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3871485251
Short name T473
Test name
Test status
Simulation time 52759759 ps
CPU time 1.1 seconds
Started Jun 28 06:30:01 PM PDT 24
Finished Jun 28 06:30:03 PM PDT 24
Peak memory 216772 kb
Host smart-50486df8-4d5b-4875-8433-a2458c702038
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871485251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3871485251
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3874356113
Short name T942
Test name
Test status
Simulation time 406044322 ps
CPU time 5.84 seconds
Started Jun 28 06:30:01 PM PDT 24
Finished Jun 28 06:30:09 PM PDT 24
Peak memory 232628 kb
Host smart-3f310c0e-0f9b-4382-9b4b-88b4e9d94bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874356113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3874356113
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3178458324
Short name T500
Test name
Test status
Simulation time 25963322127 ps
CPU time 10.24 seconds
Started Jun 28 06:30:00 PM PDT 24
Finished Jun 28 06:30:11 PM PDT 24
Peak memory 232736 kb
Host smart-31b7030f-500e-446e-8768-3531eae4bc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178458324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3178458324
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1453248232
Short name T463
Test name
Test status
Simulation time 3983594709 ps
CPU time 9.51 seconds
Started Jun 28 06:30:11 PM PDT 24
Finished Jun 28 06:30:22 PM PDT 24
Peak memory 222236 kb
Host smart-814dda66-ea0c-45b9-bdf2-f519e87b3ce2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1453248232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1453248232
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3409324554
Short name T606
Test name
Test status
Simulation time 89718640 ps
CPU time 1.06 seconds
Started Jun 28 06:30:12 PM PDT 24
Finished Jun 28 06:30:15 PM PDT 24
Peak memory 206704 kb
Host smart-4a13e091-7b21-45ee-9142-361d8db9ba09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409324554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3409324554
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1333536694
Short name T468
Test name
Test status
Simulation time 309945847 ps
CPU time 2.32 seconds
Started Jun 28 06:29:59 PM PDT 24
Finished Jun 28 06:30:03 PM PDT 24
Peak memory 217924 kb
Host smart-6c757382-4b1f-4b19-878e-9386e95d4406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333536694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1333536694
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3935996820
Short name T69
Test name
Test status
Simulation time 6065870588 ps
CPU time 18.04 seconds
Started Jun 28 06:30:00 PM PDT 24
Finished Jun 28 06:30:20 PM PDT 24
Peak memory 216328 kb
Host smart-ccdc3bb3-20b9-42e1-a0f9-29248a988203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935996820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3935996820
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1845105026
Short name T674
Test name
Test status
Simulation time 821743274 ps
CPU time 1.25 seconds
Started Jun 28 06:30:00 PM PDT 24
Finished Jun 28 06:30:03 PM PDT 24
Peak memory 216236 kb
Host smart-e220d1aa-eea6-4a98-8f5b-bba99bc74dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845105026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1845105026
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3554123161
Short name T6
Test name
Test status
Simulation time 58400125 ps
CPU time 0.91 seconds
Started Jun 28 06:30:00 PM PDT 24
Finished Jun 28 06:30:03 PM PDT 24
Peak memory 205912 kb
Host smart-aa623f1e-a82e-4c0b-920f-88acd3a3b12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554123161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3554123161
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3782855602
Short name T494
Test name
Test status
Simulation time 1464956589 ps
CPU time 5.41 seconds
Started Jun 28 06:30:02 PM PDT 24
Finished Jun 28 06:30:09 PM PDT 24
Peak memory 232668 kb
Host smart-31e629bc-008e-4379-935d-204326f517e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782855602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3782855602
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3056528013
Short name T683
Test name
Test status
Simulation time 15337814 ps
CPU time 0.73 seconds
Started Jun 28 06:30:12 PM PDT 24
Finished Jun 28 06:30:14 PM PDT 24
Peak memory 205744 kb
Host smart-da00765d-1f17-40cd-b4a9-7b1e9e70ba05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056528013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3056528013
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2946395201
Short name T754
Test name
Test status
Simulation time 244683750 ps
CPU time 5.07 seconds
Started Jun 28 06:30:10 PM PDT 24
Finished Jun 28 06:30:15 PM PDT 24
Peak memory 232656 kb
Host smart-49fe5000-ad0a-4015-8bab-1366e4e35777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946395201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2946395201
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.96796151
Short name T296
Test name
Test status
Simulation time 52929689 ps
CPU time 0.77 seconds
Started Jun 28 06:30:11 PM PDT 24
Finished Jun 28 06:30:13 PM PDT 24
Peak memory 205524 kb
Host smart-412bde5e-87b6-4147-bfc0-1ff0aa410b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96796151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.96796151
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3042160508
Short name T63
Test name
Test status
Simulation time 20526279976 ps
CPU time 172.66 seconds
Started Jun 28 06:30:12 PM PDT 24
Finished Jun 28 06:33:07 PM PDT 24
Peak memory 240984 kb
Host smart-523e7de9-817c-4cda-acb2-8dacb509466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042160508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3042160508
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1218453673
Short name T574
Test name
Test status
Simulation time 23893874079 ps
CPU time 49.28 seconds
Started Jun 28 06:30:11 PM PDT 24
Finished Jun 28 06:31:02 PM PDT 24
Peak memory 232820 kb
Host smart-55272607-55f5-42ce-a890-2af60059de82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218453673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1218453673
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1486667297
Short name T958
Test name
Test status
Simulation time 2947794502 ps
CPU time 35.11 seconds
Started Jun 28 06:30:12 PM PDT 24
Finished Jun 28 06:30:49 PM PDT 24
Peak memory 249232 kb
Host smart-670356ec-0d65-4dfe-a45c-c926e00976fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486667297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1486667297
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1358802971
Short name T163
Test name
Test status
Simulation time 13353523915 ps
CPU time 85.48 seconds
Started Jun 28 06:30:13 PM PDT 24
Finished Jun 28 06:31:40 PM PDT 24
Peak memory 252992 kb
Host smart-99a70d42-9ddf-431f-bb42-7ed9408197cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358802971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1358802971
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4224907924
Short name T181
Test name
Test status
Simulation time 2686438898 ps
CPU time 13.01 seconds
Started Jun 28 06:30:11 PM PDT 24
Finished Jun 28 06:30:25 PM PDT 24
Peak memory 224556 kb
Host smart-11f406f4-5546-47cf-a211-3c320edf229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224907924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4224907924
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.884464807
Short name T957
Test name
Test status
Simulation time 14850963046 ps
CPU time 35.05 seconds
Started Jun 28 06:30:12 PM PDT 24
Finished Jun 28 06:30:48 PM PDT 24
Peak memory 240788 kb
Host smart-35bc6e1c-aaf5-4dc7-9665-c6c5936fa85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884464807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.884464807
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3924245452
Short name T943
Test name
Test status
Simulation time 188862782 ps
CPU time 1.1 seconds
Started Jun 28 06:30:13 PM PDT 24
Finished Jun 28 06:30:16 PM PDT 24
Peak memory 216780 kb
Host smart-001addfd-23a0-44c6-9f06-5fafe422aa58
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924245452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3924245452
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1846827314
Short name T937
Test name
Test status
Simulation time 5370236943 ps
CPU time 10.16 seconds
Started Jun 28 06:30:12 PM PDT 24
Finished Jun 28 06:30:23 PM PDT 24
Peak memory 224492 kb
Host smart-243ec270-93f4-433a-9296-2fb539ac2fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846827314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1846827314
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3111270462
Short name T797
Test name
Test status
Simulation time 303727748 ps
CPU time 5.25 seconds
Started Jun 28 06:30:13 PM PDT 24
Finished Jun 28 06:30:20 PM PDT 24
Peak memory 236632 kb
Host smart-e9dd1ce9-641e-4794-b6a5-af4d5bf6a0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111270462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3111270462
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1656009288
Short name T732
Test name
Test status
Simulation time 1646787676 ps
CPU time 11.99 seconds
Started Jun 28 06:30:12 PM PDT 24
Finished Jun 28 06:30:26 PM PDT 24
Peak memory 220284 kb
Host smart-8b643f57-add2-4f39-bf8e-c86e8c70ace2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1656009288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1656009288
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.384131022
Short name T543
Test name
Test status
Simulation time 32131615201 ps
CPU time 46.66 seconds
Started Jun 28 06:30:11 PM PDT 24
Finished Jun 28 06:30:59 PM PDT 24
Peak memory 216292 kb
Host smart-830ffe24-436d-49b3-bdaf-f16f85f0d087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384131022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.384131022
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3545786639
Short name T346
Test name
Test status
Simulation time 3374366484 ps
CPU time 3.44 seconds
Started Jun 28 06:30:11 PM PDT 24
Finished Jun 28 06:30:15 PM PDT 24
Peak memory 216340 kb
Host smart-f3840ca5-4718-40ca-ae69-d16c6b7d74b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545786639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3545786639
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3017827401
Short name T836
Test name
Test status
Simulation time 996846130 ps
CPU time 5.6 seconds
Started Jun 28 06:30:11 PM PDT 24
Finished Jun 28 06:30:18 PM PDT 24
Peak memory 216080 kb
Host smart-539d157f-568e-4f7b-86de-8b2f558bd457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017827401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3017827401
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2027252887
Short name T316
Test name
Test status
Simulation time 49977726 ps
CPU time 0.87 seconds
Started Jun 28 06:30:15 PM PDT 24
Finished Jun 28 06:30:17 PM PDT 24
Peak memory 205872 kb
Host smart-46690859-35df-46a4-b34a-2136b55702fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027252887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2027252887
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.284016355
Short name T647
Test name
Test status
Simulation time 3195306498 ps
CPU time 6.44 seconds
Started Jun 28 06:30:10 PM PDT 24
Finished Jun 28 06:30:18 PM PDT 24
Peak memory 232824 kb
Host smart-8b4907e8-ff7f-467e-bceb-c1a82224f2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284016355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.284016355
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.226301631
Short name T57
Test name
Test status
Simulation time 14502382 ps
CPU time 0.74 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:28 PM PDT 24
Peak memory 204840 kb
Host smart-537727db-de3f-4dac-b381-a32f53a03961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226301631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.226301631
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3321798249
Short name T870
Test name
Test status
Simulation time 305059531 ps
CPU time 3.61 seconds
Started Jun 28 06:30:25 PM PDT 24
Finished Jun 28 06:30:30 PM PDT 24
Peak memory 232704 kb
Host smart-3c4cc682-19ad-47c2-89a8-7ff735e63163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321798249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3321798249
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1287764845
Short name T524
Test name
Test status
Simulation time 46793641 ps
CPU time 0.87 seconds
Started Jun 28 06:30:11 PM PDT 24
Finished Jun 28 06:30:14 PM PDT 24
Peak memory 205524 kb
Host smart-37a2d1af-f171-4cea-8e79-cd7e92df6294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287764845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1287764845
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.309103956
Short name T648
Test name
Test status
Simulation time 3289473612 ps
CPU time 16.69 seconds
Started Jun 28 06:30:25 PM PDT 24
Finished Jun 28 06:30:43 PM PDT 24
Peak memory 239692 kb
Host smart-b98a45da-4e81-4230-9ed7-2bc5f310c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309103956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.309103956
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.225218412
Short name T522
Test name
Test status
Simulation time 1876612940 ps
CPU time 30.17 seconds
Started Jun 28 06:30:25 PM PDT 24
Finished Jun 28 06:30:56 PM PDT 24
Peak memory 224548 kb
Host smart-785a0620-a0ae-4bbc-96ee-e15f965b55b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225218412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.225218412
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3780443264
Short name T793
Test name
Test status
Simulation time 1032340746 ps
CPU time 4.56 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:33 PM PDT 24
Peak memory 224424 kb
Host smart-7a5efd30-23d7-467c-8ac8-3d17b47ad4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780443264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3780443264
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1488116355
Short name T725
Test name
Test status
Simulation time 1071447759 ps
CPU time 10.01 seconds
Started Jun 28 06:30:27 PM PDT 24
Finished Jun 28 06:30:39 PM PDT 24
Peak memory 224388 kb
Host smart-9d13eb7b-b140-4c98-9d18-dbc4c6275aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488116355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1488116355
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2932675105
Short name T171
Test name
Test status
Simulation time 37206099659 ps
CPU time 56.32 seconds
Started Jun 28 06:30:25 PM PDT 24
Finished Jun 28 06:31:23 PM PDT 24
Peak memory 232736 kb
Host smart-7505db60-e759-4667-88ad-e43c030979ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932675105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2932675105
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2662235777
Short name T565
Test name
Test status
Simulation time 111039229 ps
CPU time 1.1 seconds
Started Jun 28 06:30:12 PM PDT 24
Finished Jun 28 06:30:15 PM PDT 24
Peak memory 216772 kb
Host smart-04ea6925-25ff-4b65-aab1-dccec6c4c4d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662235777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2662235777
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1650919623
Short name T415
Test name
Test status
Simulation time 22662490796 ps
CPU time 16.22 seconds
Started Jun 28 06:30:25 PM PDT 24
Finished Jun 28 06:30:42 PM PDT 24
Peak memory 224528 kb
Host smart-bc74a00a-c3e6-4511-9c73-401ec998a027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650919623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1650919623
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1842991983
Short name T455
Test name
Test status
Simulation time 268183492 ps
CPU time 2.26 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:31 PM PDT 24
Peak memory 224124 kb
Host smart-5e8e810c-97cc-4512-84b7-f5f725abb29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842991983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1842991983
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.44706001
Short name T759
Test name
Test status
Simulation time 210926417 ps
CPU time 4.68 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:33 PM PDT 24
Peak memory 220688 kb
Host smart-1e2fb6bb-021c-45e8-8cdc-97952544774d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=44706001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direc
t.44706001
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.564604099
Short name T396
Test name
Test status
Simulation time 6496458446 ps
CPU time 75.94 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:31:45 PM PDT 24
Peak memory 252392 kb
Host smart-adf46410-c4c4-49c8-8cc4-b084317d62dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564604099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.564604099
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3612063302
Short name T580
Test name
Test status
Simulation time 3770307538 ps
CPU time 26.24 seconds
Started Jun 28 06:30:11 PM PDT 24
Finished Jun 28 06:30:38 PM PDT 24
Peak memory 216576 kb
Host smart-1d64bcdc-cace-40c0-bcd5-13db2fcf8885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612063302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3612063302
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.58250698
Short name T525
Test name
Test status
Simulation time 879634124 ps
CPU time 3.6 seconds
Started Jun 28 06:30:11 PM PDT 24
Finished Jun 28 06:30:16 PM PDT 24
Peak memory 216152 kb
Host smart-5648aa0b-dd0a-469f-ae73-083bd478d3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58250698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.58250698
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1228628594
Short name T290
Test name
Test status
Simulation time 56360403 ps
CPU time 1.61 seconds
Started Jun 28 06:30:25 PM PDT 24
Finished Jun 28 06:30:28 PM PDT 24
Peak memory 216268 kb
Host smart-05f0f93a-5aae-4608-ad53-15cce50dcd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228628594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1228628594
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.369145687
Short name T466
Test name
Test status
Simulation time 166837326 ps
CPU time 0.9 seconds
Started Jun 28 06:30:25 PM PDT 24
Finished Jun 28 06:30:27 PM PDT 24
Peak memory 205860 kb
Host smart-b79c6fc2-0213-46df-b8b2-62db3fc6fe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369145687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.369145687
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1624071821
Short name T698
Test name
Test status
Simulation time 4307504559 ps
CPU time 18.85 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:48 PM PDT 24
Peak memory 240740 kb
Host smart-b7351ccf-63ad-4c66-94bc-5ffd5f8f7c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624071821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1624071821
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3348565633
Short name T405
Test name
Test status
Simulation time 16272127 ps
CPU time 0.72 seconds
Started Jun 28 06:30:37 PM PDT 24
Finished Jun 28 06:30:39 PM PDT 24
Peak memory 204836 kb
Host smart-09454529-8bf3-4736-8d52-ab61743da50c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348565633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3348565633
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.542844505
Short name T867
Test name
Test status
Simulation time 5665654648 ps
CPU time 5.48 seconds
Started Jun 28 06:30:25 PM PDT 24
Finished Jun 28 06:30:31 PM PDT 24
Peak memory 224492 kb
Host smart-b01cb800-b324-426e-abc4-e31e937c7d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542844505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.542844505
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3774049749
Short name T112
Test name
Test status
Simulation time 60469161 ps
CPU time 0.77 seconds
Started Jun 28 06:30:27 PM PDT 24
Finished Jun 28 06:30:30 PM PDT 24
Peak memory 206568 kb
Host smart-4b52a3cb-2dca-49d1-a27b-e844e49d8bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774049749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3774049749
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3998469520
Short name T178
Test name
Test status
Simulation time 280527814722 ps
CPU time 416.36 seconds
Started Jun 28 06:30:37 PM PDT 24
Finished Jun 28 06:37:34 PM PDT 24
Peak memory 256492 kb
Host smart-d52a9ebf-79f5-49b9-9af2-f346261cd546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998469520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3998469520
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.785121023
Short name T256
Test name
Test status
Simulation time 41233499916 ps
CPU time 335.87 seconds
Started Jun 28 06:30:36 PM PDT 24
Finished Jun 28 06:36:13 PM PDT 24
Peak memory 263532 kb
Host smart-2d9feec2-6c62-400a-ac24-dc2a72a425eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785121023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.785121023
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1513391002
Short name T360
Test name
Test status
Simulation time 300313161 ps
CPU time 5.1 seconds
Started Jun 28 06:30:27 PM PDT 24
Finished Jun 28 06:30:34 PM PDT 24
Peak memory 232712 kb
Host smart-aa3555ce-9eea-4870-b264-7eb27f470a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513391002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1513391002
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3371923862
Short name T925
Test name
Test status
Simulation time 4343498299 ps
CPU time 12.67 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:41 PM PDT 24
Peak memory 232764 kb
Host smart-1b255544-6c46-47a1-9588-5974b76c5ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371923862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3371923862
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2238819439
Short name T972
Test name
Test status
Simulation time 2891083749 ps
CPU time 19.22 seconds
Started Jun 28 06:30:27 PM PDT 24
Finished Jun 28 06:30:48 PM PDT 24
Peak memory 249024 kb
Host smart-2419b2c0-6a6c-4bc6-bae5-272952332c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238819439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2238819439
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2867051275
Short name T370
Test name
Test status
Simulation time 27948534 ps
CPU time 1.06 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:29 PM PDT 24
Peak memory 216712 kb
Host smart-d0581e39-8745-4c40-b40f-ae74d4f1691a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867051275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2867051275
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2590129
Short name T54
Test name
Test status
Simulation time 32269149 ps
CPU time 2.41 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:30 PM PDT 24
Peak memory 232352 kb
Host smart-833690bd-9a3b-4dbd-a86d-4214bd33a651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.2590129
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.718452679
Short name T663
Test name
Test status
Simulation time 4755296614 ps
CPU time 12.29 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:41 PM PDT 24
Peak memory 240488 kb
Host smart-fa682500-3293-433a-8f42-71d80bb5a9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718452679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.718452679
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4287853305
Short name T125
Test name
Test status
Simulation time 511863692 ps
CPU time 3.22 seconds
Started Jun 28 06:30:38 PM PDT 24
Finished Jun 28 06:30:43 PM PDT 24
Peak memory 218672 kb
Host smart-8cb352c7-abad-42c8-aeb3-2a304509d0af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4287853305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4287853305
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2253523097
Short name T144
Test name
Test status
Simulation time 46947484785 ps
CPU time 479.1 seconds
Started Jun 28 06:30:40 PM PDT 24
Finished Jun 28 06:38:41 PM PDT 24
Peak memory 265588 kb
Host smart-aa804e3c-c8e5-4786-b2ad-685449a03495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253523097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2253523097
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.966373892
Short name T371
Test name
Test status
Simulation time 10705008108 ps
CPU time 27.03 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:55 PM PDT 24
Peak memory 216412 kb
Host smart-4263cdb4-3548-4ba5-9102-4f9f12761cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966373892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.966373892
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.7473700
Short name T1010
Test name
Test status
Simulation time 2151296290 ps
CPU time 2.29 seconds
Started Jun 28 06:30:27 PM PDT 24
Finished Jun 28 06:30:31 PM PDT 24
Peak memory 207032 kb
Host smart-ec554ce7-f262-4ca5-b663-ce8cddb8fdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7473700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.7473700
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1148885917
Short name T624
Test name
Test status
Simulation time 25644974 ps
CPU time 0.76 seconds
Started Jun 28 06:30:25 PM PDT 24
Finished Jun 28 06:30:28 PM PDT 24
Peak memory 205888 kb
Host smart-93beaf98-2679-4f3a-8e0a-70eaae1be753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148885917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1148885917
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4201690791
Short name T544
Test name
Test status
Simulation time 71876708 ps
CPU time 0.96 seconds
Started Jun 28 06:30:25 PM PDT 24
Finished Jun 28 06:30:28 PM PDT 24
Peak memory 205888 kb
Host smart-245bacbf-d971-4b04-93e2-64aadd52747d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201690791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4201690791
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2103099917
Short name T14
Test name
Test status
Simulation time 5506166910 ps
CPU time 9.66 seconds
Started Jun 28 06:30:26 PM PDT 24
Finished Jun 28 06:30:38 PM PDT 24
Peak memory 224528 kb
Host smart-67bf196c-e616-4e62-bec6-0a43fd17803b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103099917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2103099917
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3336664201
Short name T609
Test name
Test status
Simulation time 53740077 ps
CPU time 0.77 seconds
Started Jun 28 06:28:18 PM PDT 24
Finished Jun 28 06:28:21 PM PDT 24
Peak memory 204836 kb
Host smart-ec4ba337-9df8-4b42-9dbe-d93c855dacb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336664201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
336664201
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3771992039
Short name T927
Test name
Test status
Simulation time 973643976 ps
CPU time 5.9 seconds
Started Jun 28 06:28:19 PM PDT 24
Finished Jun 28 06:28:26 PM PDT 24
Peak memory 232668 kb
Host smart-2a1ee3f1-8eb8-4857-9661-046166353c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771992039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3771992039
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3823707431
Short name T373
Test name
Test status
Simulation time 19311522 ps
CPU time 0.75 seconds
Started Jun 28 06:28:08 PM PDT 24
Finished Jun 28 06:28:10 PM PDT 24
Peak memory 205540 kb
Host smart-81758d95-0e21-434b-810d-82b12c07e33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823707431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3823707431
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.361552788
Short name T193
Test name
Test status
Simulation time 6200523322 ps
CPU time 48.38 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:29:12 PM PDT 24
Peak memory 241208 kb
Host smart-31a24c7c-c98a-406d-8311-c2538b937a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361552788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.361552788
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1119878187
Short name T630
Test name
Test status
Simulation time 4473954032 ps
CPU time 29.78 seconds
Started Jun 28 06:28:19 PM PDT 24
Finished Jun 28 06:28:51 PM PDT 24
Peak memory 217636 kb
Host smart-05890572-6343-4ac2-90a9-85427665372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119878187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1119878187
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.109286994
Short name T96
Test name
Test status
Simulation time 4982925642 ps
CPU time 30.03 seconds
Started Jun 28 06:28:18 PM PDT 24
Finished Jun 28 06:28:50 PM PDT 24
Peak memory 249308 kb
Host smart-14f5bdf9-0091-497c-8ee5-ad1395c46d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109286994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
109286994
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.24654979
Short name T34
Test name
Test status
Simulation time 2065462380 ps
CPU time 29.53 seconds
Started Jun 28 06:28:19 PM PDT 24
Finished Jun 28 06:28:50 PM PDT 24
Peak memory 240824 kb
Host smart-d449d154-43fb-4826-ad92-015ae547f52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24654979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.24654979
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3920745557
Short name T608
Test name
Test status
Simulation time 21474354195 ps
CPU time 162.7 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:31:07 PM PDT 24
Peak memory 255936 kb
Host smart-edd2ed3f-f307-4343-b964-f56d1e706fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920745557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3920745557
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.488048854
Short name T184
Test name
Test status
Simulation time 163398982 ps
CPU time 4.45 seconds
Started Jun 28 06:28:22 PM PDT 24
Finished Jun 28 06:28:29 PM PDT 24
Peak memory 224440 kb
Host smart-37b030c2-2407-4cf0-837b-6b6b6553d17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488048854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.488048854
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3041303188
Short name T168
Test name
Test status
Simulation time 2367970794 ps
CPU time 10.3 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:32 PM PDT 24
Peak memory 232700 kb
Host smart-6fc9dc97-fb2a-4e56-b0e1-66c9cdd0407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041303188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3041303188
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3028490024
Short name T790
Test name
Test status
Simulation time 129578852 ps
CPU time 1.09 seconds
Started Jun 28 06:28:09 PM PDT 24
Finished Jun 28 06:28:12 PM PDT 24
Peak memory 216776 kb
Host smart-8f71afd4-35cb-4f26-9316-21da129fd348
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028490024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3028490024
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1338681939
Short name T658
Test name
Test status
Simulation time 6046736958 ps
CPU time 5.7 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:28 PM PDT 24
Peak memory 232912 kb
Host smart-86977c08-661d-46d6-88be-ae1e86c04df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338681939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1338681939
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3299749685
Short name T584
Test name
Test status
Simulation time 31758879 ps
CPU time 2.63 seconds
Started Jun 28 06:28:19 PM PDT 24
Finished Jun 28 06:28:23 PM PDT 24
Peak memory 232368 kb
Host smart-09252dd6-c84f-4d99-a1af-a7c6bff65642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299749685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3299749685
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3995641521
Short name T318
Test name
Test status
Simulation time 8000288219 ps
CPU time 20.33 seconds
Started Jun 28 06:28:23 PM PDT 24
Finished Jun 28 06:28:45 PM PDT 24
Peak memory 221648 kb
Host smart-c1716a27-00df-4ce1-bd50-ffe9fb5c9554
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3995641521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3995641521
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2864362490
Short name T470
Test name
Test status
Simulation time 122324078291 ps
CPU time 47.53 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:29:11 PM PDT 24
Peak memory 223880 kb
Host smart-ecda18b4-9f28-4025-9520-ad31b39817b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864362490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2864362490
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2604225283
Short name T740
Test name
Test status
Simulation time 6840147114 ps
CPU time 8.16 seconds
Started Jun 28 06:28:10 PM PDT 24
Finished Jun 28 06:28:20 PM PDT 24
Peak memory 216344 kb
Host smart-914f8ca1-c3ef-4938-b01b-0b3f794c824d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604225283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2604225283
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2607940822
Short name T291
Test name
Test status
Simulation time 2118525197 ps
CPU time 6.28 seconds
Started Jun 28 06:28:08 PM PDT 24
Finished Jun 28 06:28:16 PM PDT 24
Peak memory 216196 kb
Host smart-854ae146-3e44-4180-b3e5-7613fb9aa260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607940822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2607940822
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1362069826
Short name T381
Test name
Test status
Simulation time 1414609915 ps
CPU time 3.62 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:26 PM PDT 24
Peak memory 216256 kb
Host smart-9d9fa162-1a2a-45dd-8454-d9fdd4134808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362069826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1362069826
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3219965121
Short name T917
Test name
Test status
Simulation time 67317623 ps
CPU time 0.79 seconds
Started Jun 28 06:28:10 PM PDT 24
Finished Jun 28 06:28:12 PM PDT 24
Peak memory 205888 kb
Host smart-3b3d9e5b-cf13-43ca-80c3-57dc50526518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219965121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3219965121
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.791662235
Short name T979
Test name
Test status
Simulation time 270452165 ps
CPU time 2.42 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:24 PM PDT 24
Peak memory 224460 kb
Host smart-b4c8daeb-330b-4331-8c83-bd2c6ab90872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791662235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.791662235
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3632783051
Short name T407
Test name
Test status
Simulation time 12443899 ps
CPU time 0.71 seconds
Started Jun 28 06:30:37 PM PDT 24
Finished Jun 28 06:30:39 PM PDT 24
Peak memory 205736 kb
Host smart-e603ec68-fb41-4cd8-8a1b-2d4c8a73db5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632783051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3632783051
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3482855938
Short name T404
Test name
Test status
Simulation time 325228687 ps
CPU time 4.62 seconds
Started Jun 28 06:30:39 PM PDT 24
Finished Jun 28 06:30:46 PM PDT 24
Peak memory 232620 kb
Host smart-7f75214b-3bb1-46d6-a6fb-a0744b0f6504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482855938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3482855938
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1721080
Short name T292
Test name
Test status
Simulation time 14863164 ps
CPU time 0.77 seconds
Started Jun 28 06:30:38 PM PDT 24
Finished Jun 28 06:30:40 PM PDT 24
Peak memory 206528 kb
Host smart-973fd1d6-c2d4-49cb-81df-b6993881c2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1721080
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.253953948
Short name T810
Test name
Test status
Simulation time 55150374642 ps
CPU time 235.07 seconds
Started Jun 28 06:30:39 PM PDT 24
Finished Jun 28 06:34:36 PM PDT 24
Peak memory 261740 kb
Host smart-f28abcc3-f27f-4db9-ad6a-ef28b538807e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253953948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.253953948
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2120121011
Short name T182
Test name
Test status
Simulation time 256967816220 ps
CPU time 650.88 seconds
Started Jun 28 06:30:40 PM PDT 24
Finished Jun 28 06:41:33 PM PDT 24
Peak memory 267108 kb
Host smart-9b8377cf-4b59-4732-9c70-bd685cb7e31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120121011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2120121011
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2025752489
Short name T812
Test name
Test status
Simulation time 3512605381 ps
CPU time 23.59 seconds
Started Jun 28 06:30:39 PM PDT 24
Finished Jun 28 06:31:05 PM PDT 24
Peak memory 217480 kb
Host smart-8058a71b-25fe-4b96-82b7-50515f71c452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025752489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2025752489
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1071023581
Short name T886
Test name
Test status
Simulation time 290521672 ps
CPU time 6.47 seconds
Started Jun 28 06:30:39 PM PDT 24
Finished Jun 28 06:30:47 PM PDT 24
Peak memory 231656 kb
Host smart-9dd95738-046f-435b-8153-295284490a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071023581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1071023581
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.132196877
Short name T476
Test name
Test status
Simulation time 1425637869 ps
CPU time 9.04 seconds
Started Jun 28 06:30:39 PM PDT 24
Finished Jun 28 06:30:50 PM PDT 24
Peak memory 224428 kb
Host smart-909b5ff0-72ef-44bc-8ca9-87778d0ca261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132196877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.132196877
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1997240087
Short name T952
Test name
Test status
Simulation time 40419518377 ps
CPU time 71.27 seconds
Started Jun 28 06:30:37 PM PDT 24
Finished Jun 28 06:31:49 PM PDT 24
Peak memory 240580 kb
Host smart-c16889a2-74cb-4208-8bea-8d6e916bcd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997240087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1997240087
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2867725171
Short name T238
Test name
Test status
Simulation time 3042200822 ps
CPU time 7.14 seconds
Started Jun 28 06:30:38 PM PDT 24
Finished Jun 28 06:30:47 PM PDT 24
Peak memory 224552 kb
Host smart-5cc44a41-5c7b-4174-8d08-ce061eae2d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867725171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2867725171
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.331483888
Short name T240
Test name
Test status
Simulation time 343526127 ps
CPU time 6.42 seconds
Started Jun 28 06:30:40 PM PDT 24
Finished Jun 28 06:30:48 PM PDT 24
Peak memory 232612 kb
Host smart-4140c6be-ddfc-4508-9b77-36f630e9a297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331483888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.331483888
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1462762533
Short name T995
Test name
Test status
Simulation time 1338945724 ps
CPU time 14.07 seconds
Started Jun 28 06:30:38 PM PDT 24
Finished Jun 28 06:30:54 PM PDT 24
Peak memory 221984 kb
Host smart-02b2c43c-4ba8-42ee-9aee-b48f93b408a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1462762533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1462762533
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2956165790
Short name T959
Test name
Test status
Simulation time 4110128571 ps
CPU time 21.31 seconds
Started Jun 28 06:30:40 PM PDT 24
Finished Jun 28 06:31:03 PM PDT 24
Peak memory 216600 kb
Host smart-a3edc203-f535-4b55-998f-95ed280d5f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956165790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2956165790
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1481887249
Short name T741
Test name
Test status
Simulation time 1342426077 ps
CPU time 5.39 seconds
Started Jun 28 06:30:37 PM PDT 24
Finished Jun 28 06:30:44 PM PDT 24
Peak memory 216164 kb
Host smart-54d72579-1652-40f6-b4f7-1deb39cdbb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481887249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1481887249
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.157990326
Short name T981
Test name
Test status
Simulation time 162407023 ps
CPU time 1.33 seconds
Started Jun 28 06:30:38 PM PDT 24
Finished Jun 28 06:30:41 PM PDT 24
Peak memory 216148 kb
Host smart-db8d401f-3c65-4997-b837-43b434870e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157990326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.157990326
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1686525918
Short name T359
Test name
Test status
Simulation time 34779330 ps
CPU time 0.88 seconds
Started Jun 28 06:30:41 PM PDT 24
Finished Jun 28 06:30:43 PM PDT 24
Peak memory 206064 kb
Host smart-4fffcc82-b93f-4931-b488-fafd71281d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686525918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1686525918
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1529471350
Short name T876
Test name
Test status
Simulation time 1786522492 ps
CPU time 12.92 seconds
Started Jun 28 06:30:39 PM PDT 24
Finished Jun 28 06:30:54 PM PDT 24
Peak memory 224408 kb
Host smart-7798d0ba-9ee4-431d-abd0-b2f9d8c995be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529471350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1529471350
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2629222431
Short name T622
Test name
Test status
Simulation time 38461977 ps
CPU time 0.77 seconds
Started Jun 28 06:30:53 PM PDT 24
Finished Jun 28 06:30:56 PM PDT 24
Peak memory 205928 kb
Host smart-67e67eb2-b305-41b7-b694-0bb5dbc4aa54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629222431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2629222431
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4044282757
Short name T478
Test name
Test status
Simulation time 331721485 ps
CPU time 3.66 seconds
Started Jun 28 06:30:46 PM PDT 24
Finished Jun 28 06:30:51 PM PDT 24
Peak memory 224432 kb
Host smart-fadf0746-ebb8-46e0-8334-56149320340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044282757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4044282757
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2628994849
Short name T295
Test name
Test status
Simulation time 20872038 ps
CPU time 0.75 seconds
Started Jun 28 06:30:40 PM PDT 24
Finished Jun 28 06:30:43 PM PDT 24
Peak memory 205516 kb
Host smart-79a8a3f9-761a-414a-b46d-4f7299645a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628994849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2628994849
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3982605743
Short name T254
Test name
Test status
Simulation time 60462952430 ps
CPU time 230.9 seconds
Started Jun 28 06:30:53 PM PDT 24
Finished Jun 28 06:34:46 PM PDT 24
Peak memory 257348 kb
Host smart-18acba49-c09d-4a5a-a11e-426702765fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982605743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3982605743
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3538095388
Short name T335
Test name
Test status
Simulation time 167835949825 ps
CPU time 356.1 seconds
Started Jun 28 06:30:47 PM PDT 24
Finished Jun 28 06:36:46 PM PDT 24
Peak memory 255396 kb
Host smart-e1dd8874-946a-4d54-bf5e-9e8864c954a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538095388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3538095388
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3856701814
Short name T114
Test name
Test status
Simulation time 1169848382 ps
CPU time 2.58 seconds
Started Jun 28 06:30:48 PM PDT 24
Finished Jun 28 06:30:53 PM PDT 24
Peak memory 217640 kb
Host smart-570f302e-3fdd-43b9-83f4-016af06c7304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856701814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3856701814
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.4266668110
Short name T804
Test name
Test status
Simulation time 230516733239 ps
CPU time 153.13 seconds
Started Jun 28 06:30:51 PM PDT 24
Finished Jun 28 06:33:27 PM PDT 24
Peak memory 261128 kb
Host smart-fa089336-675a-4917-8a7d-8c82b128abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266668110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.4266668110
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.39699709
Short name T653
Test name
Test status
Simulation time 2585590954 ps
CPU time 5.86 seconds
Started Jun 28 06:30:41 PM PDT 24
Finished Jun 28 06:30:48 PM PDT 24
Peak memory 224552 kb
Host smart-dfa06ac9-4e66-4535-9b42-649e19a67df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39699709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.39699709
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3446624200
Short name T935
Test name
Test status
Simulation time 1201141960 ps
CPU time 12.5 seconds
Started Jun 28 06:30:48 PM PDT 24
Finished Jun 28 06:31:03 PM PDT 24
Peak memory 232672 kb
Host smart-174c32ad-0ecd-4d3e-bb6e-b219c2eec27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446624200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3446624200
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2053007628
Short name T379
Test name
Test status
Simulation time 230498480 ps
CPU time 5.28 seconds
Started Jun 28 06:30:36 PM PDT 24
Finished Jun 28 06:30:43 PM PDT 24
Peak memory 232664 kb
Host smart-36b36b30-4f4e-4318-8d13-55bd4fee46f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053007628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2053007628
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3837909626
Short name T643
Test name
Test status
Simulation time 52520309 ps
CPU time 2.2 seconds
Started Jun 28 06:30:37 PM PDT 24
Finished Jun 28 06:30:40 PM PDT 24
Peak memory 222988 kb
Host smart-7fd0bc80-182a-41d0-aa97-7714a7f5a055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837909626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3837909626
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3627052154
Short name T601
Test name
Test status
Simulation time 319383273 ps
CPU time 4.97 seconds
Started Jun 28 06:30:52 PM PDT 24
Finished Jun 28 06:31:00 PM PDT 24
Peak memory 219928 kb
Host smart-b2980805-51ca-47fe-a7af-d685ddd16845
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3627052154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3627052154
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.336854101
Short name T458
Test name
Test status
Simulation time 29726157605 ps
CPU time 277.99 seconds
Started Jun 28 06:30:47 PM PDT 24
Finished Jun 28 06:35:28 PM PDT 24
Peak memory 272464 kb
Host smart-7cb2469b-a063-40a6-b379-0faf068f06a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336854101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.336854101
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1298090716
Short name T516
Test name
Test status
Simulation time 483257226 ps
CPU time 4.91 seconds
Started Jun 28 06:30:38 PM PDT 24
Finished Jun 28 06:30:45 PM PDT 24
Peak memory 216376 kb
Host smart-50c98b2a-ef35-4b8a-be64-d99be3f363be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298090716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1298090716
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1896037727
Short name T357
Test name
Test status
Simulation time 2092844698 ps
CPU time 4.93 seconds
Started Jun 28 06:30:38 PM PDT 24
Finished Jun 28 06:30:44 PM PDT 24
Peak memory 216216 kb
Host smart-da79a5b5-1fb9-4916-8ba5-f826a89d8488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896037727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1896037727
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3113942086
Short name T1000
Test name
Test status
Simulation time 190386789 ps
CPU time 1.17 seconds
Started Jun 28 06:30:40 PM PDT 24
Finished Jun 28 06:30:43 PM PDT 24
Peak memory 216120 kb
Host smart-4e04260f-11cf-4ca5-bf21-1ea6eb941d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113942086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3113942086
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2257846970
Short name T668
Test name
Test status
Simulation time 58922681 ps
CPU time 0.93 seconds
Started Jun 28 06:30:37 PM PDT 24
Finished Jun 28 06:30:39 PM PDT 24
Peak memory 206904 kb
Host smart-79e95a82-a7db-468a-97f8-67f172dd635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257846970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2257846970
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1645506124
Short name T697
Test name
Test status
Simulation time 152222452 ps
CPU time 3.62 seconds
Started Jun 28 06:30:47 PM PDT 24
Finished Jun 28 06:30:54 PM PDT 24
Peak memory 232656 kb
Host smart-a17aa4fa-9190-4e0b-9c61-c470291ac329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645506124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1645506124
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.330580648
Short name T411
Test name
Test status
Simulation time 24801055 ps
CPU time 0.75 seconds
Started Jun 28 06:30:59 PM PDT 24
Finished Jun 28 06:31:02 PM PDT 24
Peak memory 205404 kb
Host smart-177e44ed-f495-4c41-9623-f334ec9be164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330580648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.330580648
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3124601719
Short name T856
Test name
Test status
Simulation time 44012365 ps
CPU time 2.42 seconds
Started Jun 28 06:30:53 PM PDT 24
Finished Jun 28 06:30:58 PM PDT 24
Peak memory 232860 kb
Host smart-64ab5e2b-3377-4527-aa04-591248b00818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124601719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3124601719
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3908472465
Short name T308
Test name
Test status
Simulation time 32571532 ps
CPU time 0.79 seconds
Started Jun 28 06:30:49 PM PDT 24
Finished Jun 28 06:30:52 PM PDT 24
Peak memory 206560 kb
Host smart-611a7c2d-d23d-4e53-988f-8aa11a233f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908472465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3908472465
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.992649705
Short name T313
Test name
Test status
Simulation time 1975586743 ps
CPU time 15.59 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:31:19 PM PDT 24
Peak memory 236960 kb
Host smart-d35e4028-6298-4b8d-a1e9-3fcabd946751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992649705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.992649705
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.579795514
Short name T38
Test name
Test status
Simulation time 10322029877 ps
CPU time 71.2 seconds
Started Jun 28 06:31:01 PM PDT 24
Finished Jun 28 06:32:15 PM PDT 24
Peak memory 264760 kb
Host smart-2a291799-dac1-4a7d-b722-6eafde2ea3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579795514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.579795514
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.574452425
Short name T253
Test name
Test status
Simulation time 314526260946 ps
CPU time 745.64 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:43:29 PM PDT 24
Peak memory 265752 kb
Host smart-6fb5ab56-4428-4dd4-a548-90dfb08cdcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574452425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.574452425
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1702763862
Short name T273
Test name
Test status
Simulation time 1066920594 ps
CPU time 23.92 seconds
Started Jun 28 06:31:01 PM PDT 24
Finished Jun 28 06:31:27 PM PDT 24
Peak memory 232588 kb
Host smart-74ac8d82-ffd5-4114-8db0-1ce845dfc569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702763862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1702763862
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3115140858
Short name T61
Test name
Test status
Simulation time 24501341302 ps
CPU time 133.62 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:33:16 PM PDT 24
Peak memory 249140 kb
Host smart-27a1d999-4025-4c98-9054-2a67a740bd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115140858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3115140858
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1364203415
Short name T811
Test name
Test status
Simulation time 628618926 ps
CPU time 3.28 seconds
Started Jun 28 06:30:46 PM PDT 24
Finished Jun 28 06:30:50 PM PDT 24
Peak memory 224436 kb
Host smart-78a0ae21-55cf-429b-9d8f-0fefb2f4edd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364203415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1364203415
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1531238340
Short name T339
Test name
Test status
Simulation time 41899610 ps
CPU time 2.58 seconds
Started Jun 28 06:30:49 PM PDT 24
Finished Jun 28 06:30:54 PM PDT 24
Peak memory 232412 kb
Host smart-d233fbfc-9b15-454b-bb4d-7683ee18e66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531238340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1531238340
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2428227221
Short name T230
Test name
Test status
Simulation time 37386319149 ps
CPU time 23.34 seconds
Started Jun 28 06:30:48 PM PDT 24
Finished Jun 28 06:31:14 PM PDT 24
Peak memory 232744 kb
Host smart-dfe676f2-4e96-4ebb-96ab-2e0dc4588cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428227221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2428227221
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.504198650
Short name T443
Test name
Test status
Simulation time 781214989 ps
CPU time 4.21 seconds
Started Jun 28 06:30:48 PM PDT 24
Finished Jun 28 06:30:55 PM PDT 24
Peak memory 224472 kb
Host smart-a1a42907-b1a4-45c0-bf44-ffe5c1ee7a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504198650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.504198650
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2837065081
Short name T423
Test name
Test status
Simulation time 4544210937 ps
CPU time 8.2 seconds
Started Jun 28 06:31:02 PM PDT 24
Finished Jun 28 06:31:12 PM PDT 24
Peak memory 222500 kb
Host smart-7c84e8aa-d02c-48b0-8295-ef93358156b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2837065081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2837065081
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.295793620
Short name T19
Test name
Test status
Simulation time 53334211 ps
CPU time 1.09 seconds
Started Jun 28 06:31:02 PM PDT 24
Finished Jun 28 06:31:05 PM PDT 24
Peak memory 206732 kb
Host smart-24da979c-93ca-42c9-b5c5-bf4b23501f4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295793620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.295793620
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2052252412
Short name T776
Test name
Test status
Simulation time 406971984 ps
CPU time 7.09 seconds
Started Jun 28 06:30:47 PM PDT 24
Finished Jun 28 06:30:55 PM PDT 24
Peak memory 218176 kb
Host smart-c6a33014-fb49-4f32-bfa7-922f3073bbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052252412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2052252412
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4092530366
Short name T390
Test name
Test status
Simulation time 1333926917 ps
CPU time 2.58 seconds
Started Jun 28 06:30:49 PM PDT 24
Finished Jun 28 06:30:54 PM PDT 24
Peak memory 207744 kb
Host smart-12633218-a527-4467-97df-ee32b7caf29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092530366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4092530366
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1209491226
Short name T554
Test name
Test status
Simulation time 157645401 ps
CPU time 1.07 seconds
Started Jun 28 06:30:51 PM PDT 24
Finished Jun 28 06:30:55 PM PDT 24
Peak memory 206924 kb
Host smart-2a170fc0-5c26-449c-b17b-9d7039e13927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209491226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1209491226
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.898155316
Short name T829
Test name
Test status
Simulation time 29208432 ps
CPU time 0.86 seconds
Started Jun 28 06:30:48 PM PDT 24
Finished Jun 28 06:30:52 PM PDT 24
Peak memory 206092 kb
Host smart-09137d86-e010-481b-a7b3-4f53f881b791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898155316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.898155316
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2717924216
Short name T1028
Test name
Test status
Simulation time 1336409672 ps
CPU time 2.41 seconds
Started Jun 28 06:30:48 PM PDT 24
Finished Jun 28 06:30:53 PM PDT 24
Peak memory 223064 kb
Host smart-8bc5d552-60d2-426f-afb4-509d6dc1f5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717924216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2717924216
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4045320198
Short name T311
Test name
Test status
Simulation time 31764323 ps
CPU time 0.74 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:31:03 PM PDT 24
Peak memory 204784 kb
Host smart-108b1759-981f-4d33-b644-d7dc9e10019b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045320198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4045320198
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.854933898
Short name T160
Test name
Test status
Simulation time 86865269 ps
CPU time 2.97 seconds
Started Jun 28 06:30:59 PM PDT 24
Finished Jun 28 06:31:03 PM PDT 24
Peak memory 224444 kb
Host smart-c7319e8a-c6cf-4884-8b12-bd607ecf2b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854933898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.854933898
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3288915539
Short name T420
Test name
Test status
Simulation time 22209186 ps
CPU time 0.85 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:31:04 PM PDT 24
Peak memory 206548 kb
Host smart-0371aa0f-8c27-42d7-882d-17dfc0cd95aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288915539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3288915539
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1615811063
Short name T209
Test name
Test status
Simulation time 3691743720 ps
CPU time 63.22 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:32:05 PM PDT 24
Peak memory 266568 kb
Host smart-e2b26099-d573-4262-ad74-a7c138e9db8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615811063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1615811063
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3888968310
Short name T687
Test name
Test status
Simulation time 23528388455 ps
CPU time 262.93 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:35:25 PM PDT 24
Peak memory 249200 kb
Host smart-d24f5439-4cf0-41cd-9be2-2375e12f2a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888968310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3888968310
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3866220058
Short name T616
Test name
Test status
Simulation time 287082475686 ps
CPU time 216.41 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:34:39 PM PDT 24
Peak memory 253668 kb
Host smart-4907706e-87a3-4e1e-8949-ed03503de05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866220058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3866220058
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3618765614
Short name T795
Test name
Test status
Simulation time 4508072837 ps
CPU time 18.15 seconds
Started Jun 28 06:31:01 PM PDT 24
Finished Jun 28 06:31:21 PM PDT 24
Peak memory 224604 kb
Host smart-be649719-9be1-448c-9a50-e12053b26475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618765614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3618765614
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3532649347
Short name T165
Test name
Test status
Simulation time 47638423731 ps
CPU time 80.29 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:32:23 PM PDT 24
Peak memory 232712 kb
Host smart-5302619b-e394-463c-9288-9afd2559bef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532649347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3532649347
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.363929371
Short name T340
Test name
Test status
Simulation time 696794006 ps
CPU time 8.96 seconds
Started Jun 28 06:30:59 PM PDT 24
Finished Jun 28 06:31:10 PM PDT 24
Peak memory 232616 kb
Host smart-9152cb46-4430-4802-a918-549f4bc75018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363929371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.363929371
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.746893637
Short name T343
Test name
Test status
Simulation time 37762832 ps
CPU time 2.31 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:31:05 PM PDT 24
Peak memory 224472 kb
Host smart-4f634437-4843-40c5-8787-95b1eee86473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746893637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.746893637
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1821993848
Short name T784
Test name
Test status
Simulation time 862295500 ps
CPU time 3.83 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:31:06 PM PDT 24
Peak memory 224468 kb
Host smart-baa05f8e-e06f-4bc2-9041-06062aafe4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821993848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1821993848
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1326208622
Short name T397
Test name
Test status
Simulation time 11808247207 ps
CPU time 19.88 seconds
Started Jun 28 06:31:01 PM PDT 24
Finished Jun 28 06:31:23 PM PDT 24
Peak memory 240956 kb
Host smart-8478af38-bae2-438e-b0d0-1bc55b7ca86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326208622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1326208622
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.888007619
Short name T314
Test name
Test status
Simulation time 1099262185 ps
CPU time 10.17 seconds
Started Jun 28 06:30:59 PM PDT 24
Finished Jun 28 06:31:11 PM PDT 24
Peak memory 222300 kb
Host smart-f2efd0df-b5bc-44a7-ac84-8a0674c89f60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=888007619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.888007619
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.501630615
Short name T418
Test name
Test status
Simulation time 1692011884 ps
CPU time 27.34 seconds
Started Jun 28 06:30:59 PM PDT 24
Finished Jun 28 06:31:29 PM PDT 24
Peak memory 216144 kb
Host smart-6977093d-3c7a-44c9-a441-fa53ec13cf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501630615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.501630615
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1962187221
Short name T451
Test name
Test status
Simulation time 6335295507 ps
CPU time 20.74 seconds
Started Jun 28 06:31:01 PM PDT 24
Finished Jun 28 06:31:24 PM PDT 24
Peak memory 216300 kb
Host smart-c9e2c6bd-c72c-4752-9af3-99ce3bd4a614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962187221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1962187221
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1478259701
Short name T830
Test name
Test status
Simulation time 400897032 ps
CPU time 4.8 seconds
Started Jun 28 06:30:59 PM PDT 24
Finished Jun 28 06:31:06 PM PDT 24
Peak memory 216240 kb
Host smart-b50fc422-9314-42f5-97d2-93b4f867fb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478259701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1478259701
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1509228614
Short name T389
Test name
Test status
Simulation time 14846489 ps
CPU time 0.83 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:31:03 PM PDT 24
Peak memory 205864 kb
Host smart-174a8f07-0993-469b-96f4-26e0734f223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509228614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1509228614
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1381017033
Short name T838
Test name
Test status
Simulation time 156329361 ps
CPU time 2.43 seconds
Started Jun 28 06:31:00 PM PDT 24
Finished Jun 28 06:31:05 PM PDT 24
Peak memory 224460 kb
Host smart-12cde499-1dac-458f-94fe-04a3d537df2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381017033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1381017033
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.460117260
Short name T998
Test name
Test status
Simulation time 13293617 ps
CPU time 0.73 seconds
Started Jun 28 06:31:13 PM PDT 24
Finished Jun 28 06:31:15 PM PDT 24
Peak memory 204844 kb
Host smart-0cecffe6-6603-4b7f-9448-0a0928d38a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460117260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.460117260
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3716484792
Short name T854
Test name
Test status
Simulation time 241667527 ps
CPU time 2.69 seconds
Started Jun 28 06:31:12 PM PDT 24
Finished Jun 28 06:31:16 PM PDT 24
Peak memory 224408 kb
Host smart-adceae62-91a2-42ea-b295-3515836e91db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716484792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3716484792
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1626001163
Short name T474
Test name
Test status
Simulation time 41350513 ps
CPU time 0.75 seconds
Started Jun 28 06:31:01 PM PDT 24
Finished Jun 28 06:31:04 PM PDT 24
Peak memory 205756 kb
Host smart-80ef0420-1f4c-4ed8-87db-a9804cb63175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626001163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1626001163
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.536555126
Short name T641
Test name
Test status
Simulation time 6286972287 ps
CPU time 13.28 seconds
Started Jun 28 06:31:13 PM PDT 24
Finished Jun 28 06:31:28 PM PDT 24
Peak memory 236348 kb
Host smart-218e11de-3a38-4f14-a465-10c3a116a52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536555126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.536555126
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4149568161
Short name T235
Test name
Test status
Simulation time 93879510431 ps
CPU time 276.15 seconds
Started Jun 28 06:31:12 PM PDT 24
Finished Jun 28 06:35:50 PM PDT 24
Peak memory 251992 kb
Host smart-a0f4e1bf-b76f-46c3-8e48-c308b8b05458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149568161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4149568161
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2971808786
Short name T718
Test name
Test status
Simulation time 15012284614 ps
CPU time 60.85 seconds
Started Jun 28 06:31:15 PM PDT 24
Finished Jun 28 06:32:17 PM PDT 24
Peak memory 253528 kb
Host smart-f9449238-15dd-4ab5-8e8f-17b3d95570f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971808786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2971808786
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2761360262
Short name T198
Test name
Test status
Simulation time 1265866498 ps
CPU time 15.58 seconds
Started Jun 28 06:31:13 PM PDT 24
Finished Jun 28 06:31:31 PM PDT 24
Peak memory 240852 kb
Host smart-3f01ade4-d6da-447a-a6f2-18b0a6a2adeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761360262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2761360262
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2098217505
Short name T515
Test name
Test status
Simulation time 451474969 ps
CPU time 7.43 seconds
Started Jun 28 06:31:12 PM PDT 24
Finished Jun 28 06:31:21 PM PDT 24
Peak memory 229332 kb
Host smart-5e3f258b-6d50-42ba-b938-f82af0ea765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098217505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2098217505
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.966872419
Short name T640
Test name
Test status
Simulation time 3483582507 ps
CPU time 32.04 seconds
Started Jun 28 06:31:13 PM PDT 24
Finished Jun 28 06:31:46 PM PDT 24
Peak memory 240780 kb
Host smart-f5cc9913-8a68-4bc0-b036-3cc8fcd976bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966872419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.966872419
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2412437692
Short name T562
Test name
Test status
Simulation time 4466639746 ps
CPU time 9.87 seconds
Started Jun 28 06:31:14 PM PDT 24
Finished Jun 28 06:31:25 PM PDT 24
Peak memory 240488 kb
Host smart-0db3acb8-6808-4c02-9b13-b15e555336a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412437692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2412437692
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4230743486
Short name T814
Test name
Test status
Simulation time 13428713389 ps
CPU time 37.66 seconds
Started Jun 28 06:31:12 PM PDT 24
Finished Jun 28 06:31:50 PM PDT 24
Peak memory 240872 kb
Host smart-0f8f54ac-2b82-4a14-80b7-0a8152fd3e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230743486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4230743486
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1743636243
Short name T866
Test name
Test status
Simulation time 1481801110 ps
CPU time 5.31 seconds
Started Jun 28 06:31:12 PM PDT 24
Finished Jun 28 06:31:19 PM PDT 24
Peak memory 222520 kb
Host smart-80619b15-7ca1-474a-8adb-f76d5ab86b9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1743636243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1743636243
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4122926023
Short name T367
Test name
Test status
Simulation time 11340407934 ps
CPU time 16.08 seconds
Started Jun 28 06:31:12 PM PDT 24
Finished Jun 28 06:31:29 PM PDT 24
Peak memory 220108 kb
Host smart-56ea3d85-36af-47c0-bcb7-2296b6d4ab97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122926023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4122926023
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1207947518
Short name T774
Test name
Test status
Simulation time 11467460786 ps
CPU time 16.03 seconds
Started Jun 28 06:31:01 PM PDT 24
Finished Jun 28 06:31:19 PM PDT 24
Peak memory 216344 kb
Host smart-8dd20aac-874c-497f-8f1b-255aed65d11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207947518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1207947518
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3819690234
Short name T896
Test name
Test status
Simulation time 126084780 ps
CPU time 1.97 seconds
Started Jun 28 06:31:13 PM PDT 24
Finished Jun 28 06:31:17 PM PDT 24
Peak memory 216148 kb
Host smart-00c84c3b-1dad-48ce-99f4-76e7076c6e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819690234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3819690234
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1919109346
Short name T312
Test name
Test status
Simulation time 26661530 ps
CPU time 0.7 seconds
Started Jun 28 06:31:13 PM PDT 24
Finished Jun 28 06:31:15 PM PDT 24
Peak memory 205880 kb
Host smart-7c20424a-0ae4-48b2-bcbc-4e23edaebf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919109346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1919109346
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1395773037
Short name T179
Test name
Test status
Simulation time 4164944078 ps
CPU time 21.6 seconds
Started Jun 28 06:31:13 PM PDT 24
Finished Jun 28 06:31:36 PM PDT 24
Peak memory 235792 kb
Host smart-9eb8a903-49ab-4572-9f6a-48f436c2fdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395773037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1395773037
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3910164336
Short name T26
Test name
Test status
Simulation time 59543690 ps
CPU time 0.73 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:31:26 PM PDT 24
Peak memory 205704 kb
Host smart-29bd3373-f9f9-4b35-aafa-92dab420aee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910164336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3910164336
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2663264834
Short name T374
Test name
Test status
Simulation time 704296214 ps
CPU time 3.27 seconds
Started Jun 28 06:31:26 PM PDT 24
Finished Jun 28 06:31:31 PM PDT 24
Peak memory 224472 kb
Host smart-f739c2b8-a7a6-4a1b-845b-30d78b043efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663264834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2663264834
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3786707435
Short name T755
Test name
Test status
Simulation time 51848530 ps
CPU time 0.75 seconds
Started Jun 28 06:31:13 PM PDT 24
Finished Jun 28 06:31:15 PM PDT 24
Peak memory 205528 kb
Host smart-031e4cad-a028-4863-b8ae-a6769ba684df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786707435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3786707435
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3867387547
Short name T961
Test name
Test status
Simulation time 36038591666 ps
CPU time 70.85 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:32:36 PM PDT 24
Peak memory 250460 kb
Host smart-a407aee2-9ad9-42db-a4d3-628695e2a250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867387547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3867387547
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1615571608
Short name T349
Test name
Test status
Simulation time 22382534 ps
CPU time 0.83 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:31:27 PM PDT 24
Peak memory 216928 kb
Host smart-70b1c27c-cdc0-484d-8f43-17eadb721bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615571608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1615571608
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1316137574
Short name T408
Test name
Test status
Simulation time 35955953331 ps
CPU time 307.15 seconds
Started Jun 28 06:31:25 PM PDT 24
Finished Jun 28 06:36:33 PM PDT 24
Peak memory 256792 kb
Host smart-ea64077a-469f-449e-82d5-af62601d65a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316137574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1316137574
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.304692669
Short name T736
Test name
Test status
Simulation time 312849064 ps
CPU time 4.86 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:31:30 PM PDT 24
Peak memory 232672 kb
Host smart-c796a64f-5f51-40b2-9c54-0c0e78872eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304692669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.304692669
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2269206897
Short name T628
Test name
Test status
Simulation time 248249667 ps
CPU time 0.9 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:31:27 PM PDT 24
Peak memory 215932 kb
Host smart-634db5a6-5ec9-4412-a917-f427c15f2dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269206897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2269206897
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3399661479
Short name T589
Test name
Test status
Simulation time 3464669128 ps
CPU time 12.43 seconds
Started Jun 28 06:31:28 PM PDT 24
Finished Jun 28 06:31:41 PM PDT 24
Peak memory 224612 kb
Host smart-6b65ae3f-0850-426d-b97f-d9d831ff7c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399661479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3399661479
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.809023482
Short name T58
Test name
Test status
Simulation time 1512856301 ps
CPU time 21.97 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:31:47 PM PDT 24
Peak memory 236796 kb
Host smart-d6888c18-b80a-49fb-8690-e4eb7ae67c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809023482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.809023482
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3960524220
Short name T172
Test name
Test status
Simulation time 668779115 ps
CPU time 5.57 seconds
Started Jun 28 06:31:23 PM PDT 24
Finished Jun 28 06:31:30 PM PDT 24
Peak memory 232632 kb
Host smart-b6d2fd1c-505b-41e9-8808-3a49702741a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960524220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3960524220
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3796355841
Short name T241
Test name
Test status
Simulation time 1298995653 ps
CPU time 10.94 seconds
Started Jun 28 06:31:15 PM PDT 24
Finished Jun 28 06:31:27 PM PDT 24
Peak memory 249056 kb
Host smart-c585d850-6643-4a3d-b573-c4c0d73dbdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796355841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3796355841
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3598272935
Short name T8
Test name
Test status
Simulation time 167438650 ps
CPU time 3.9 seconds
Started Jun 28 06:31:27 PM PDT 24
Finished Jun 28 06:31:32 PM PDT 24
Peak memory 218560 kb
Host smart-0499bbe2-9415-4e99-a734-a56e88606a9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3598272935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3598272935
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1263162884
Short name T16
Test name
Test status
Simulation time 109629830 ps
CPU time 1.1 seconds
Started Jun 28 06:31:23 PM PDT 24
Finished Jun 28 06:31:26 PM PDT 24
Peak memory 206920 kb
Host smart-916d7472-78a4-4f14-a2bf-98edbc609bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263162884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1263162884
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.669336400
Short name T782
Test name
Test status
Simulation time 5505242245 ps
CPU time 20.86 seconds
Started Jun 28 06:31:13 PM PDT 24
Finished Jun 28 06:31:36 PM PDT 24
Peak memory 216340 kb
Host smart-a28698e8-90d5-4535-a853-6c240a43cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669336400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.669336400
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1657909958
Short name T523
Test name
Test status
Simulation time 12681837 ps
CPU time 0.72 seconds
Started Jun 28 06:31:12 PM PDT 24
Finished Jun 28 06:31:15 PM PDT 24
Peak memory 205620 kb
Host smart-afca6f1f-4bb4-428e-b0dc-8d6c19b04c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657909958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1657909958
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1346258498
Short name T980
Test name
Test status
Simulation time 83270376 ps
CPU time 0.95 seconds
Started Jun 28 06:31:12 PM PDT 24
Finished Jun 28 06:31:14 PM PDT 24
Peak memory 207248 kb
Host smart-bbc453cf-51e0-48ab-b7b0-4f9ddbad5fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346258498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1346258498
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.42017411
Short name T808
Test name
Test status
Simulation time 20826833 ps
CPU time 0.75 seconds
Started Jun 28 06:31:12 PM PDT 24
Finished Jun 28 06:31:14 PM PDT 24
Peak memory 205892 kb
Host smart-8b8d98ec-2577-4937-acda-c0dcc47238dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42017411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.42017411
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2055732295
Short name T627
Test name
Test status
Simulation time 18708043210 ps
CPU time 20.05 seconds
Started Jun 28 06:31:25 PM PDT 24
Finished Jun 28 06:31:47 PM PDT 24
Peak memory 232824 kb
Host smart-4cb18d60-da28-41ee-b244-2b058f074a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055732295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2055732295
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3851596801
Short name T863
Test name
Test status
Simulation time 18151520 ps
CPU time 0.7 seconds
Started Jun 28 06:31:25 PM PDT 24
Finished Jun 28 06:31:27 PM PDT 24
Peak memory 205388 kb
Host smart-50860f6f-ca97-429b-8a3a-8bc5a94bcc39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851596801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3851596801
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4172904845
Short name T599
Test name
Test status
Simulation time 896394885 ps
CPU time 4.12 seconds
Started Jun 28 06:31:26 PM PDT 24
Finished Jun 28 06:31:32 PM PDT 24
Peak memory 224416 kb
Host smart-5261ca0f-24c3-4adb-89a7-476bd9341af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172904845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4172904845
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.671719504
Short name T394
Test name
Test status
Simulation time 31762839 ps
CPU time 0.74 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:31:26 PM PDT 24
Peak memory 206880 kb
Host smart-e0029921-91c6-45cf-b739-d2cc314c6bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671719504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.671719504
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3149211795
Short name T9
Test name
Test status
Simulation time 81472256047 ps
CPU time 134.17 seconds
Started Jun 28 06:31:26 PM PDT 24
Finished Jun 28 06:33:41 PM PDT 24
Peak memory 249148 kb
Host smart-dea51448-caec-4df7-b240-13e1a1de011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149211795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3149211795
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1399162346
Short name T720
Test name
Test status
Simulation time 9973728560 ps
CPU time 81.89 seconds
Started Jun 28 06:31:25 PM PDT 24
Finished Jun 28 06:32:48 PM PDT 24
Peak memory 238496 kb
Host smart-09d0d573-cc84-4fb7-a593-a1b28f6e8461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399162346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1399162346
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1314970844
Short name T887
Test name
Test status
Simulation time 5794346959 ps
CPU time 87.97 seconds
Started Jun 28 06:31:25 PM PDT 24
Finished Jun 28 06:32:54 PM PDT 24
Peak memory 254708 kb
Host smart-fb1fea8a-3e9a-4bb9-bcaa-bd2dbaac6aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314970844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1314970844
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2554329575
Short name T894
Test name
Test status
Simulation time 819327489 ps
CPU time 5.52 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:31:31 PM PDT 24
Peak memory 232708 kb
Host smart-76a1304d-b1a7-4573-8f4b-d79726572fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554329575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2554329575
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.4033843748
Short name T39
Test name
Test status
Simulation time 74480335681 ps
CPU time 271.89 seconds
Started Jun 28 06:31:23 PM PDT 24
Finished Jun 28 06:35:56 PM PDT 24
Peak memory 256696 kb
Host smart-a54272a8-dc81-4401-a975-97bdd8526023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033843748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.4033843748
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1198076433
Short name T734
Test name
Test status
Simulation time 178629675 ps
CPU time 4.83 seconds
Started Jun 28 06:31:27 PM PDT 24
Finished Jun 28 06:31:33 PM PDT 24
Peak memory 224424 kb
Host smart-a4c35402-05ec-41fb-86f8-ad8b602725cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198076433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1198076433
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4141182377
Short name T775
Test name
Test status
Simulation time 34894623123 ps
CPU time 117.04 seconds
Started Jun 28 06:31:26 PM PDT 24
Finished Jun 28 06:33:25 PM PDT 24
Peak memory 232796 kb
Host smart-38637e44-b0f8-49a8-ad8f-30c7c54484a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141182377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4141182377
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3736291430
Short name T898
Test name
Test status
Simulation time 1587437741 ps
CPU time 3.81 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:31:29 PM PDT 24
Peak memory 233680 kb
Host smart-67ff1784-f877-4354-ab89-0879fed293eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736291430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3736291430
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2538090968
Short name T763
Test name
Test status
Simulation time 6521648767 ps
CPU time 18.8 seconds
Started Jun 28 06:31:23 PM PDT 24
Finished Jun 28 06:31:44 PM PDT 24
Peak memory 240552 kb
Host smart-5085cd76-4ba3-422d-a482-0364c03df1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538090968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2538090968
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.127620325
Short name T445
Test name
Test status
Simulation time 1650883562 ps
CPU time 8.1 seconds
Started Jun 28 06:31:23 PM PDT 24
Finished Jun 28 06:31:32 PM PDT 24
Peak memory 218428 kb
Host smart-b7c5ca23-0712-41f3-8b0f-4eaddd9fb365
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=127620325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.127620325
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2465709705
Short name T18
Test name
Test status
Simulation time 19804063799 ps
CPU time 22.71 seconds
Started Jun 28 06:31:25 PM PDT 24
Finished Jun 28 06:31:49 PM PDT 24
Peak memory 241024 kb
Host smart-5c1bc669-3d27-4a35-b412-74b76c350737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465709705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2465709705
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3083384858
Short name T97
Test name
Test status
Simulation time 28669679667 ps
CPU time 32.1 seconds
Started Jun 28 06:31:25 PM PDT 24
Finished Jun 28 06:31:58 PM PDT 24
Peak memory 216348 kb
Host smart-83ec3117-d24f-4a7f-bedf-f05af8c70393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083384858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3083384858
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1069281054
Short name T438
Test name
Test status
Simulation time 23249126 ps
CPU time 0.7 seconds
Started Jun 28 06:31:25 PM PDT 24
Finished Jun 28 06:31:27 PM PDT 24
Peak memory 205652 kb
Host smart-636921df-3ac7-4e05-aa0e-2d38f4a6d55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069281054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1069281054
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.130078459
Short name T302
Test name
Test status
Simulation time 491637427 ps
CPU time 2.57 seconds
Started Jun 28 06:31:25 PM PDT 24
Finished Jun 28 06:31:30 PM PDT 24
Peak memory 216120 kb
Host smart-eadb5fcd-e953-4038-820b-bc87efdd69c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130078459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.130078459
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1209758874
Short name T400
Test name
Test status
Simulation time 217573596 ps
CPU time 0.89 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:31:26 PM PDT 24
Peak memory 205860 kb
Host smart-ed1ce531-42fe-4369-ab33-d5acd1791408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209758874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1209758874
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1042451887
Short name T469
Test name
Test status
Simulation time 2304533952 ps
CPU time 5.82 seconds
Started Jun 28 06:31:24 PM PDT 24
Finished Jun 28 06:31:31 PM PDT 24
Peak memory 239112 kb
Host smart-00e57cee-7ff6-478d-b2c7-ed1d543cdf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042451887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1042451887
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4210657595
Short name T729
Test name
Test status
Simulation time 33492920 ps
CPU time 0.74 seconds
Started Jun 28 06:31:35 PM PDT 24
Finished Jun 28 06:31:37 PM PDT 24
Peak memory 204840 kb
Host smart-69547a4b-f7c5-4e2b-9f6e-6e2b4d7d8595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210657595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4210657595
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.339877656
Short name T15
Test name
Test status
Simulation time 1117954762 ps
CPU time 6.67 seconds
Started Jun 28 06:31:37 PM PDT 24
Finished Jun 28 06:31:45 PM PDT 24
Peak memory 232612 kb
Host smart-8def7568-a55c-47d4-8c6f-5d31b57f0c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339877656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.339877656
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3615288940
Short name T424
Test name
Test status
Simulation time 18076629 ps
CPU time 0.77 seconds
Started Jun 28 06:31:22 PM PDT 24
Finished Jun 28 06:31:23 PM PDT 24
Peak memory 206884 kb
Host smart-7e1b381b-ffe8-4261-b034-33142680534c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615288940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3615288940
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1316372859
Short name T27
Test name
Test status
Simulation time 4117224067 ps
CPU time 55.22 seconds
Started Jun 28 06:31:38 PM PDT 24
Finished Jun 28 06:32:34 PM PDT 24
Peak memory 249240 kb
Host smart-3e9a0fca-98be-41cb-ba57-cdcb65b3a016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316372859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1316372859
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3858929666
Short name T194
Test name
Test status
Simulation time 18011610493 ps
CPU time 93 seconds
Started Jun 28 06:31:36 PM PDT 24
Finished Jun 28 06:33:10 PM PDT 24
Peak memory 249464 kb
Host smart-3dbea780-5e8e-4158-9904-73a35c5a427e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858929666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3858929666
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3328791725
Short name T355
Test name
Test status
Simulation time 266487544 ps
CPU time 7.25 seconds
Started Jun 28 06:31:36 PM PDT 24
Finished Jun 28 06:31:45 PM PDT 24
Peak memory 232532 kb
Host smart-55addcdd-adb6-4d82-bb22-b2b2ad819aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328791725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3328791725
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3856890868
Short name T632
Test name
Test status
Simulation time 76291474008 ps
CPU time 295.23 seconds
Started Jun 28 06:31:36 PM PDT 24
Finished Jun 28 06:36:32 PM PDT 24
Peak memory 252528 kb
Host smart-2b582a01-a466-4e48-8176-a47b5c0ba7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856890868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3856890868
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2371585707
Short name T590
Test name
Test status
Simulation time 982490790 ps
CPU time 6.63 seconds
Started Jun 28 06:31:35 PM PDT 24
Finished Jun 28 06:31:43 PM PDT 24
Peak memory 232604 kb
Host smart-0efd8ce7-9550-4332-b556-c8b92581a862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371585707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2371585707
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1762309111
Short name T202
Test name
Test status
Simulation time 1680576577 ps
CPU time 3.65 seconds
Started Jun 28 06:31:36 PM PDT 24
Finished Jun 28 06:31:41 PM PDT 24
Peak memory 224428 kb
Host smart-f3248830-e1d4-4b25-8d3f-7258c59c0ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762309111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1762309111
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2295175840
Short name T737
Test name
Test status
Simulation time 3461310173 ps
CPU time 3.28 seconds
Started Jun 28 06:31:34 PM PDT 24
Finished Jun 28 06:31:38 PM PDT 24
Peak memory 224496 kb
Host smart-00783d58-02b9-444b-91cd-30bcc47a2a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295175840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2295175840
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1124114499
Short name T354
Test name
Test status
Simulation time 15837159461 ps
CPU time 15.78 seconds
Started Jun 28 06:31:35 PM PDT 24
Finished Jun 28 06:31:52 PM PDT 24
Peak memory 224604 kb
Host smart-ca0670e5-523e-42c1-ab03-eefba679d332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124114499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1124114499
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1295350518
Short name T510
Test name
Test status
Simulation time 699976842 ps
CPU time 13 seconds
Started Jun 28 06:31:35 PM PDT 24
Finished Jun 28 06:31:49 PM PDT 24
Peak memory 220372 kb
Host smart-506b1cd2-07c9-41bc-8e9f-60db7a4f272a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1295350518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1295350518
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3470845444
Short name T1020
Test name
Test status
Simulation time 50921973868 ps
CPU time 112.34 seconds
Started Jun 28 06:31:36 PM PDT 24
Finished Jun 28 06:33:29 PM PDT 24
Peak memory 249844 kb
Host smart-f43cc2eb-6e4c-44c9-a04c-915ef5dd7990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470845444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3470845444
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1321876116
Short name T321
Test name
Test status
Simulation time 3482908913 ps
CPU time 19.01 seconds
Started Jun 28 06:31:39 PM PDT 24
Finished Jun 28 06:31:59 PM PDT 24
Peak memory 216536 kb
Host smart-bc55b661-2cde-41a7-b3a3-4cdb8aa45ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321876116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1321876116
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2559466887
Short name T336
Test name
Test status
Simulation time 4800896733 ps
CPU time 16.51 seconds
Started Jun 28 06:31:35 PM PDT 24
Finished Jun 28 06:31:52 PM PDT 24
Peak memory 216332 kb
Host smart-ba35169e-202e-48ac-9202-1b27bea84a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559466887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2559466887
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2906268995
Short name T996
Test name
Test status
Simulation time 125123551 ps
CPU time 1.14 seconds
Started Jun 28 06:31:37 PM PDT 24
Finished Jun 28 06:31:39 PM PDT 24
Peak memory 207848 kb
Host smart-4c16cc2c-836e-4832-96fb-24e77ebea4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906268995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2906268995
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4291632018
Short name T689
Test name
Test status
Simulation time 55303578 ps
CPU time 0.77 seconds
Started Jun 28 06:31:40 PM PDT 24
Finished Jun 28 06:31:42 PM PDT 24
Peak memory 205496 kb
Host smart-e8627a78-628e-4ba2-bfc3-c47ec9bdfd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291632018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4291632018
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1470477171
Short name T976
Test name
Test status
Simulation time 3334903789 ps
CPU time 13.37 seconds
Started Jun 28 06:31:34 PM PDT 24
Finished Jun 28 06:31:49 PM PDT 24
Peak memory 250140 kb
Host smart-516ac6eb-a94e-4e6c-9aa8-63e659d035db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470477171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1470477171
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2214006282
Short name T817
Test name
Test status
Simulation time 26781095 ps
CPU time 0.75 seconds
Started Jun 28 06:31:45 PM PDT 24
Finished Jun 28 06:31:47 PM PDT 24
Peak memory 205412 kb
Host smart-a7a38db6-5023-4204-b8f8-9868d3fb73d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214006282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2214006282
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1503052581
Short name T820
Test name
Test status
Simulation time 666839612 ps
CPU time 8.82 seconds
Started Jun 28 06:31:45 PM PDT 24
Finished Jun 28 06:31:55 PM PDT 24
Peak memory 232648 kb
Host smart-f769ea46-245b-4cfd-9774-0dcbc2e91f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503052581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1503052581
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1987692169
Short name T446
Test name
Test status
Simulation time 42645745 ps
CPU time 0.76 seconds
Started Jun 28 06:31:37 PM PDT 24
Finished Jun 28 06:31:39 PM PDT 24
Peak memory 205812 kb
Host smart-2d9b3ab0-ce67-4bc7-8dc8-1b914fa3ea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987692169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1987692169
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1318456013
Short name T170
Test name
Test status
Simulation time 9368844095 ps
CPU time 89.64 seconds
Started Jun 28 06:31:46 PM PDT 24
Finished Jun 28 06:33:18 PM PDT 24
Peak memory 269496 kb
Host smart-9b154e34-e9ba-42e4-8c28-b105071ecb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318456013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1318456013
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2909613661
Short name T233
Test name
Test status
Simulation time 1136602766 ps
CPU time 28.96 seconds
Started Jun 28 06:31:50 PM PDT 24
Finished Jun 28 06:32:21 PM PDT 24
Peak memory 255820 kb
Host smart-0be31854-8239-4531-95fd-e5e5f49c7ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909613661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2909613661
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4106500773
Short name T392
Test name
Test status
Simulation time 379178057 ps
CPU time 5.82 seconds
Started Jun 28 06:31:46 PM PDT 24
Finished Jun 28 06:31:53 PM PDT 24
Peak memory 233068 kb
Host smart-91a50037-ed9d-4065-943c-9fbc11facd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106500773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4106500773
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2762105017
Short name T987
Test name
Test status
Simulation time 9911268130 ps
CPU time 132.93 seconds
Started Jun 28 06:31:51 PM PDT 24
Finished Jun 28 06:34:06 PM PDT 24
Peak memory 269492 kb
Host smart-bf162f20-cbb0-4625-bae9-eea0079191c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762105017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2762105017
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2459567793
Short name T692
Test name
Test status
Simulation time 722435632 ps
CPU time 4.19 seconds
Started Jun 28 06:31:36 PM PDT 24
Finished Jun 28 06:31:41 PM PDT 24
Peak memory 232636 kb
Host smart-c7b8e3bf-df4d-4475-bbbd-23222879f337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459567793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2459567793
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3430749317
Short name T596
Test name
Test status
Simulation time 10693749714 ps
CPU time 33.28 seconds
Started Jun 28 06:31:34 PM PDT 24
Finished Jun 28 06:32:08 PM PDT 24
Peak memory 224516 kb
Host smart-940f6a28-7bfb-48af-b089-27bcac361da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430749317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3430749317
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2590062162
Short name T600
Test name
Test status
Simulation time 432079135 ps
CPU time 4.26 seconds
Started Jun 28 06:31:38 PM PDT 24
Finished Jun 28 06:31:43 PM PDT 24
Peak memory 232600 kb
Host smart-e113d7ea-c786-4c72-ac68-54b487158045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590062162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2590062162
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.408788809
Short name T604
Test name
Test status
Simulation time 2983658076 ps
CPU time 7.48 seconds
Started Jun 28 06:31:35 PM PDT 24
Finished Jun 28 06:31:44 PM PDT 24
Peak memory 232760 kb
Host smart-534ca972-283c-4da9-9a54-f0725d6f9a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408788809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.408788809
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4215581650
Short name T595
Test name
Test status
Simulation time 1818780917 ps
CPU time 15.71 seconds
Started Jun 28 06:31:45 PM PDT 24
Finished Jun 28 06:32:02 PM PDT 24
Peak memory 219204 kb
Host smart-05ac0ddc-2978-4e38-a857-e1180ec242ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4215581650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4215581650
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3001940238
Short name T142
Test name
Test status
Simulation time 15577908110 ps
CPU time 52.75 seconds
Started Jun 28 06:31:45 PM PDT 24
Finished Jun 28 06:32:40 PM PDT 24
Peak memory 232792 kb
Host smart-848b5360-9202-4d6c-a313-02a869c6eed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001940238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3001940238
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4118569194
Short name T711
Test name
Test status
Simulation time 784957394 ps
CPU time 2.39 seconds
Started Jun 28 06:31:36 PM PDT 24
Finished Jun 28 06:31:40 PM PDT 24
Peak memory 216188 kb
Host smart-456a48ee-1fe7-455c-811f-aa8be4bbf14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118569194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4118569194
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2176084684
Short name T963
Test name
Test status
Simulation time 5277737284 ps
CPU time 6.69 seconds
Started Jun 28 06:31:35 PM PDT 24
Finished Jun 28 06:31:43 PM PDT 24
Peak memory 216316 kb
Host smart-747d074d-78ee-4735-8276-bb18a4cdb93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176084684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2176084684
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2682279001
Short name T885
Test name
Test status
Simulation time 123528273 ps
CPU time 2.05 seconds
Started Jun 28 06:31:37 PM PDT 24
Finished Jun 28 06:31:40 PM PDT 24
Peak memory 216216 kb
Host smart-4f6d3bc8-6e16-4418-8dd5-753d1ee47bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682279001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2682279001
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1367101177
Short name T71
Test name
Test status
Simulation time 109362562 ps
CPU time 0.79 seconds
Started Jun 28 06:31:34 PM PDT 24
Finished Jun 28 06:31:36 PM PDT 24
Peak memory 205892 kb
Host smart-cbfdb555-2c3f-4357-871d-ebc99e2c4245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367101177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1367101177
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.743702530
Short name T945
Test name
Test status
Simulation time 148481109 ps
CPU time 2.52 seconds
Started Jun 28 06:31:37 PM PDT 24
Finished Jun 28 06:31:41 PM PDT 24
Peak memory 232384 kb
Host smart-7a6b8030-b56e-4d66-8cff-9ab87aa42af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743702530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.743702530
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3138348123
Short name T721
Test name
Test status
Simulation time 17454222 ps
CPU time 0.66 seconds
Started Jun 28 06:31:50 PM PDT 24
Finished Jun 28 06:31:52 PM PDT 24
Peak memory 205736 kb
Host smart-89927aa3-89a3-4d82-b48e-91e9b21bdb6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138348123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3138348123
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1210673463
Short name T502
Test name
Test status
Simulation time 3623089074 ps
CPU time 15.37 seconds
Started Jun 28 06:31:46 PM PDT 24
Finished Jun 28 06:32:03 PM PDT 24
Peak memory 224564 kb
Host smart-9803c770-9a22-4a1f-ae86-299e6906213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210673463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1210673463
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.991035384
Short name T678
Test name
Test status
Simulation time 21192207 ps
CPU time 0.83 seconds
Started Jun 28 06:31:46 PM PDT 24
Finished Jun 28 06:31:48 PM PDT 24
Peak memory 206548 kb
Host smart-dfacc6b9-eb6c-474e-844d-da8bc08d51f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991035384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.991035384
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.992144548
Short name T916
Test name
Test status
Simulation time 42144154935 ps
CPU time 184.67 seconds
Started Jun 28 06:31:51 PM PDT 24
Finished Jun 28 06:34:57 PM PDT 24
Peak memory 261884 kb
Host smart-00d3a340-a3d6-4c68-b675-aef066c4fbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992144548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.992144548
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1535879277
Short name T684
Test name
Test status
Simulation time 7441419784 ps
CPU time 9.06 seconds
Started Jun 28 06:31:52 PM PDT 24
Finished Jun 28 06:32:03 PM PDT 24
Peak memory 217576 kb
Host smart-a8caebc8-9268-4ee0-8e30-ddb59ba52db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535879277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1535879277
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.728895889
Short name T884
Test name
Test status
Simulation time 8798947195 ps
CPU time 114.54 seconds
Started Jun 28 06:31:47 PM PDT 24
Finished Jun 28 06:33:43 PM PDT 24
Peak memory 255272 kb
Host smart-fde1dd1f-cdc6-441a-a2a5-55f30d238f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728895889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.728895889
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.183209274
Short name T521
Test name
Test status
Simulation time 273640275 ps
CPU time 2.54 seconds
Started Jun 28 06:31:46 PM PDT 24
Finished Jun 28 06:31:50 PM PDT 24
Peak memory 232668 kb
Host smart-68f83af0-0fb1-4a2e-987e-7b613e25139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183209274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.183209274
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3937802138
Short name T575
Test name
Test status
Simulation time 15751190 ps
CPU time 0.78 seconds
Started Jun 28 06:31:44 PM PDT 24
Finished Jun 28 06:31:45 PM PDT 24
Peak memory 215820 kb
Host smart-6ddecc18-18a6-456d-85a2-0aa8fcf2aba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937802138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3937802138
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.107554916
Short name T1026
Test name
Test status
Simulation time 1181102356 ps
CPU time 14.13 seconds
Started Jun 28 06:31:47 PM PDT 24
Finished Jun 28 06:32:02 PM PDT 24
Peak memory 232636 kb
Host smart-50e5d40a-3daf-4757-8e75-1e74b41cb246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107554916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.107554916
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2807057728
Short name T1029
Test name
Test status
Simulation time 25410220266 ps
CPU time 57.04 seconds
Started Jun 28 06:31:45 PM PDT 24
Finished Jun 28 06:32:44 PM PDT 24
Peak memory 224524 kb
Host smart-5ac4d88f-fa0a-4be7-b1ee-24188d0c4792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807057728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2807057728
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1271466842
Short name T258
Test name
Test status
Simulation time 913303174 ps
CPU time 2.71 seconds
Started Jun 28 06:31:48 PM PDT 24
Finished Jun 28 06:31:52 PM PDT 24
Peak memory 232640 kb
Host smart-436bcaa4-1e92-48ff-b214-c8cef443b5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271466842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1271466842
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3149977442
Short name T874
Test name
Test status
Simulation time 3441671037 ps
CPU time 10.17 seconds
Started Jun 28 06:31:45 PM PDT 24
Finished Jun 28 06:31:57 PM PDT 24
Peak memory 224560 kb
Host smart-2ad3a65d-499a-4797-a9ae-e3362c734d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149977442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3149977442
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2113622494
Short name T507
Test name
Test status
Simulation time 457452587 ps
CPU time 6.63 seconds
Started Jun 28 06:31:49 PM PDT 24
Finished Jun 28 06:31:57 PM PDT 24
Peak memory 223060 kb
Host smart-bae0d07d-1226-4cf5-99f1-2fe516bc3e80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2113622494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2113622494
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2974971708
Short name T245
Test name
Test status
Simulation time 66488947383 ps
CPU time 601.98 seconds
Started Jun 28 06:31:48 PM PDT 24
Finished Jun 28 06:41:52 PM PDT 24
Peak memory 272904 kb
Host smart-23a57698-30d0-4f76-a594-d429b9ca58fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974971708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2974971708
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4143850916
Short name T764
Test name
Test status
Simulation time 4427080962 ps
CPU time 13.15 seconds
Started Jun 28 06:31:48 PM PDT 24
Finished Jun 28 06:32:03 PM PDT 24
Peak memory 216228 kb
Host smart-468aa61c-0e44-4c80-a9cd-5ddb69f8022c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143850916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4143850916
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.370980512
Short name T309
Test name
Test status
Simulation time 4574474584 ps
CPU time 7.27 seconds
Started Jun 28 06:31:45 PM PDT 24
Finished Jun 28 06:31:54 PM PDT 24
Peak memory 216300 kb
Host smart-05e8be3f-b9d3-4379-81e8-0cf7693f6a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370980512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.370980512
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2967128517
Short name T801
Test name
Test status
Simulation time 258471852 ps
CPU time 1.42 seconds
Started Jun 28 06:31:46 PM PDT 24
Finished Jun 28 06:31:49 PM PDT 24
Peak memory 216204 kb
Host smart-c8701c4b-9df7-4316-b254-470f08f02f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967128517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2967128517
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.419897627
Short name T904
Test name
Test status
Simulation time 108127266 ps
CPU time 0.85 seconds
Started Jun 28 06:31:46 PM PDT 24
Finished Jun 28 06:31:49 PM PDT 24
Peak memory 205888 kb
Host smart-e71d5e6a-b0ed-4345-8c15-01c746f2eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419897627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.419897627
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4240526965
Short name T344
Test name
Test status
Simulation time 1865535259 ps
CPU time 7.76 seconds
Started Jun 28 06:31:45 PM PDT 24
Finished Jun 28 06:31:55 PM PDT 24
Peak memory 224476 kb
Host smart-e2d5f865-b206-4419-aded-936182388b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240526965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4240526965
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.458682493
Short name T493
Test name
Test status
Simulation time 15202587 ps
CPU time 0.76 seconds
Started Jun 28 06:28:23 PM PDT 24
Finished Jun 28 06:28:25 PM PDT 24
Peak memory 204836 kb
Host smart-d57c5fad-8f35-420e-96f9-b9bbed84a371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458682493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.458682493
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.4001628612
Short name T472
Test name
Test status
Simulation time 16992778689 ps
CPU time 15.92 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:39 PM PDT 24
Peak memory 232756 kb
Host smart-0e74bec5-f2d1-4145-b8aa-51771e1ddaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001628612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4001628612
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2537232252
Short name T765
Test name
Test status
Simulation time 50035070 ps
CPU time 0.77 seconds
Started Jun 28 06:28:18 PM PDT 24
Finished Jun 28 06:28:21 PM PDT 24
Peak memory 205828 kb
Host smart-773f44d6-a2bf-44b8-8606-0d5e4c39fc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537232252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2537232252
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1933146250
Short name T933
Test name
Test status
Simulation time 13577512 ps
CPU time 0.77 seconds
Started Jun 28 06:28:22 PM PDT 24
Finished Jun 28 06:28:25 PM PDT 24
Peak memory 215848 kb
Host smart-b4e0566a-af3c-411c-b9be-07ce47e44141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933146250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1933146250
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2535055092
Short name T1001
Test name
Test status
Simulation time 6732973249 ps
CPU time 37.8 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:29:00 PM PDT 24
Peak memory 250468 kb
Host smart-bc88a8fd-037b-43b2-b630-0ca61ab3d413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535055092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2535055092
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3664151095
Short name T1017
Test name
Test status
Simulation time 3057673334 ps
CPU time 35.04 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:57 PM PDT 24
Peak memory 240992 kb
Host smart-7552eae3-f20c-45ea-9fa4-722585edc6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664151095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3664151095
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4134659814
Short name T506
Test name
Test status
Simulation time 462330949 ps
CPU time 4.26 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:28:28 PM PDT 24
Peak memory 240896 kb
Host smart-09369647-19d5-4b6c-89d9-335f3ce53931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134659814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4134659814
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.731495321
Short name T722
Test name
Test status
Simulation time 9148222636 ps
CPU time 22.92 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:28:46 PM PDT 24
Peak memory 224568 kb
Host smart-5a1cff93-a723-41a0-a0d2-cd5ff26c392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731495321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
731495321
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3307147531
Short name T862
Test name
Test status
Simulation time 5281002493 ps
CPU time 8.4 seconds
Started Jun 28 06:28:19 PM PDT 24
Finished Jun 28 06:28:29 PM PDT 24
Peak memory 224592 kb
Host smart-ad40ba79-4942-41a5-b3df-6907faccb432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307147531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3307147531
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3868096779
Short name T206
Test name
Test status
Simulation time 357224311 ps
CPU time 2.41 seconds
Started Jun 28 06:28:24 PM PDT 24
Finished Jun 28 06:28:28 PM PDT 24
Peak memory 224396 kb
Host smart-24a67328-e424-4f00-9803-ec2ebcea8a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868096779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3868096779
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.916727595
Short name T513
Test name
Test status
Simulation time 26422319 ps
CPU time 1.14 seconds
Started Jun 28 06:28:18 PM PDT 24
Finished Jun 28 06:28:21 PM PDT 24
Peak memory 216784 kb
Host smart-95315e7c-068e-420b-8df0-483e2cd60653
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916727595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.916727595
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2624820839
Short name T226
Test name
Test status
Simulation time 29575513518 ps
CPU time 22.94 seconds
Started Jun 28 06:28:19 PM PDT 24
Finished Jun 28 06:28:45 PM PDT 24
Peak memory 232756 kb
Host smart-a9bc84ad-91a9-460b-9192-48034dffcf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624820839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2624820839
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3936693457
Short name T769
Test name
Test status
Simulation time 91337675 ps
CPU time 3.43 seconds
Started Jun 28 06:28:19 PM PDT 24
Finished Jun 28 06:28:24 PM PDT 24
Peak memory 240476 kb
Host smart-97befb2b-c7a2-4c67-9d61-4b74f09cd558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936693457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3936693457
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2403458581
Short name T605
Test name
Test status
Simulation time 93023317 ps
CPU time 4.51 seconds
Started Jun 28 06:28:19 PM PDT 24
Finished Jun 28 06:28:25 PM PDT 24
Peak memory 222756 kb
Host smart-470ef8da-fd7a-427d-92ab-41745fe08871
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2403458581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2403458581
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1369394004
Short name T51
Test name
Test status
Simulation time 327127097 ps
CPU time 1.14 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:28:24 PM PDT 24
Peak memory 235552 kb
Host smart-19172220-db11-4ddf-8728-5f4acc88dd7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369394004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1369394004
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4216180124
Short name T682
Test name
Test status
Simulation time 71888169 ps
CPU time 0.87 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:24 PM PDT 24
Peak memory 205884 kb
Host smart-058c86b3-2bef-4a45-babc-c2eca5fca2ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216180124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4216180124
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.470630600
Short name T570
Test name
Test status
Simulation time 6864376905 ps
CPU time 36.86 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:29:00 PM PDT 24
Peak memory 216280 kb
Host smart-6f3edae7-c2f3-4a9a-9146-55b5ead68151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470630600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.470630600
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3638989007
Short name T847
Test name
Test status
Simulation time 23718997363 ps
CPU time 15.17 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:28:39 PM PDT 24
Peak memory 216384 kb
Host smart-f0160b15-1308-49f0-be05-1f508ae9c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638989007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3638989007
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.4154665712
Short name T637
Test name
Test status
Simulation time 174062780 ps
CPU time 1.41 seconds
Started Jun 28 06:28:18 PM PDT 24
Finished Jun 28 06:28:21 PM PDT 24
Peak memory 216184 kb
Host smart-f91265ae-6fb9-406f-80b9-fcee3821b936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154665712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4154665712
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1306065137
Short name T585
Test name
Test status
Simulation time 59696166 ps
CPU time 0.76 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:24 PM PDT 24
Peak memory 205880 kb
Host smart-824d9f69-3f37-40b0-9b85-633dbd60572e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306065137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1306065137
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.750046049
Short name T749
Test name
Test status
Simulation time 11251115362 ps
CPU time 13.04 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:28:37 PM PDT 24
Peak memory 232764 kb
Host smart-8f0c04e8-f2bb-4328-888e-c5a2fd93c138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750046049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.750046049
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3640113329
Short name T432
Test name
Test status
Simulation time 13039353 ps
CPU time 0.73 seconds
Started Jun 28 06:31:58 PM PDT 24
Finished Jun 28 06:32:00 PM PDT 24
Peak memory 204800 kb
Host smart-2dcb3081-b39b-4bfc-a1d6-8ae456959ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640113329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3640113329
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2863968026
Short name T798
Test name
Test status
Simulation time 1774221979 ps
CPU time 5.54 seconds
Started Jun 28 06:32:00 PM PDT 24
Finished Jun 28 06:32:07 PM PDT 24
Peak memory 224508 kb
Host smart-a840fd71-94e9-45ff-af0e-5f7b06b0bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863968026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2863968026
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3417838784
Short name T849
Test name
Test status
Simulation time 19652024 ps
CPU time 0.85 seconds
Started Jun 28 06:31:46 PM PDT 24
Finished Jun 28 06:31:49 PM PDT 24
Peak memory 206568 kb
Host smart-ac86b409-14b8-434b-93d8-f51aa51d018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417838784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3417838784
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.55467359
Short name T384
Test name
Test status
Simulation time 5498117119 ps
CPU time 73.92 seconds
Started Jun 28 06:31:58 PM PDT 24
Finished Jun 28 06:33:14 PM PDT 24
Peak memory 249184 kb
Host smart-fd92f906-0f6e-4bde-8965-f89ed4cf1e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55467359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.55467359
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1099134484
Short name T489
Test name
Test status
Simulation time 17311360605 ps
CPU time 37.09 seconds
Started Jun 28 06:32:00 PM PDT 24
Finished Jun 28 06:32:38 PM PDT 24
Peak memory 249152 kb
Host smart-085681ec-718e-4181-8ede-9177f7faf58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099134484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1099134484
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1849457450
Short name T901
Test name
Test status
Simulation time 494133918 ps
CPU time 6.43 seconds
Started Jun 28 06:31:58 PM PDT 24
Finished Jun 28 06:32:06 PM PDT 24
Peak memory 237280 kb
Host smart-c8d9d288-0956-4930-8306-313f3d87a72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849457450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1849457450
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1419364635
Short name T173
Test name
Test status
Simulation time 15917717892 ps
CPU time 103.31 seconds
Started Jun 28 06:31:58 PM PDT 24
Finished Jun 28 06:33:43 PM PDT 24
Peak memory 240972 kb
Host smart-635b5b06-5149-4f2e-a527-01838aecff87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419364635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1419364635
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.739596855
Short name T986
Test name
Test status
Simulation time 544088274 ps
CPU time 3.85 seconds
Started Jun 28 06:32:00 PM PDT 24
Finished Jun 28 06:32:05 PM PDT 24
Peak memory 232564 kb
Host smart-04623830-1f18-4d54-a3a0-c9ada2707b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739596855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.739596855
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.149256553
Short name T477
Test name
Test status
Simulation time 34209710291 ps
CPU time 59.03 seconds
Started Jun 28 06:31:57 PM PDT 24
Finished Jun 28 06:32:57 PM PDT 24
Peak memory 232760 kb
Host smart-2c6928af-9e00-4520-ac56-378531b12625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149256553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.149256553
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2052797084
Short name T992
Test name
Test status
Simulation time 12347317025 ps
CPU time 5.51 seconds
Started Jun 28 06:31:59 PM PDT 24
Finished Jun 28 06:32:06 PM PDT 24
Peak memory 224532 kb
Host smart-7cd24343-522a-4f8d-97c5-a0e142a3dc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052797084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2052797084
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2304530591
Short name T499
Test name
Test status
Simulation time 44601427764 ps
CPU time 25.98 seconds
Started Jun 28 06:31:58 PM PDT 24
Finished Jun 28 06:32:26 PM PDT 24
Peak memory 240972 kb
Host smart-fa5ebe30-be55-4f0d-a33c-67e12c60f899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304530591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2304530591
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.930999216
Short name T655
Test name
Test status
Simulation time 2132998047 ps
CPU time 7.62 seconds
Started Jun 28 06:31:59 PM PDT 24
Finished Jun 28 06:32:08 PM PDT 24
Peak memory 222888 kb
Host smart-dd833d00-3a92-4ec3-b63e-c1fa9190d4cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=930999216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.930999216
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.403244206
Short name T227
Test name
Test status
Simulation time 306895567498 ps
CPU time 299.71 seconds
Started Jun 28 06:31:59 PM PDT 24
Finished Jun 28 06:37:00 PM PDT 24
Peak memory 257208 kb
Host smart-80fb7dff-847d-41a1-9f07-998de63657ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403244206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.403244206
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1862116668
Short name T1025
Test name
Test status
Simulation time 12626860052 ps
CPU time 21.11 seconds
Started Jun 28 06:31:50 PM PDT 24
Finished Jun 28 06:32:13 PM PDT 24
Peak memory 216256 kb
Host smart-e72e0b49-2ab9-4056-a85f-8160081a8212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862116668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1862116668
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3749904537
Short name T572
Test name
Test status
Simulation time 5160532422 ps
CPU time 14.74 seconds
Started Jun 28 06:31:46 PM PDT 24
Finished Jun 28 06:32:02 PM PDT 24
Peak memory 216332 kb
Host smart-7a9e4731-7818-4757-b27a-2b54cc65ea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749904537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3749904537
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2194573853
Short name T427
Test name
Test status
Simulation time 796371343 ps
CPU time 4.19 seconds
Started Jun 28 06:31:50 PM PDT 24
Finished Jun 28 06:31:56 PM PDT 24
Peak memory 216160 kb
Host smart-f1598c43-d310-4a3a-85a5-41cb518b51f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194573853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2194573853
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2192252449
Short name T705
Test name
Test status
Simulation time 12546790 ps
CPU time 0.68 seconds
Started Jun 28 06:31:47 PM PDT 24
Finished Jun 28 06:31:49 PM PDT 24
Peak memory 205588 kb
Host smart-3c2ddb8e-8879-4fcb-96f2-72051cbbfe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192252449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2192252449
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4142872878
Short name T617
Test name
Test status
Simulation time 1061764144 ps
CPU time 5.7 seconds
Started Jun 28 06:31:56 PM PDT 24
Finished Jun 28 06:32:03 PM PDT 24
Peak memory 232632 kb
Host smart-dd628f83-7794-4272-930a-2eb40401cdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142872878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4142872878
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.522683282
Short name T934
Test name
Test status
Simulation time 23290619 ps
CPU time 0.77 seconds
Started Jun 28 06:32:11 PM PDT 24
Finished Jun 28 06:32:15 PM PDT 24
Peak memory 205332 kb
Host smart-c97d25b8-91c2-4a45-a974-824f19ae2d85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522683282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.522683282
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3955850822
Short name T579
Test name
Test status
Simulation time 1380676116 ps
CPU time 18.8 seconds
Started Jun 28 06:32:09 PM PDT 24
Finished Jun 28 06:32:29 PM PDT 24
Peak memory 224444 kb
Host smart-20867c75-412f-426d-87c7-8a05d92cba39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955850822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3955850822
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1430723374
Short name T946
Test name
Test status
Simulation time 42155702 ps
CPU time 0.78 seconds
Started Jun 28 06:31:58 PM PDT 24
Finished Jun 28 06:32:00 PM PDT 24
Peak memory 205532 kb
Host smart-7e9b0a59-7383-48c7-9a01-49976994d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430723374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1430723374
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3576141398
Short name T1003
Test name
Test status
Simulation time 3838837139 ps
CPU time 49.83 seconds
Started Jun 28 06:32:11 PM PDT 24
Finished Jun 28 06:33:04 PM PDT 24
Peak memory 249176 kb
Host smart-3c86327a-3b51-4257-85f8-56de6b09085f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576141398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3576141398
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.401533340
Short name T421
Test name
Test status
Simulation time 5688581615 ps
CPU time 80.1 seconds
Started Jun 28 06:32:10 PM PDT 24
Finished Jun 28 06:33:33 PM PDT 24
Peak memory 265664 kb
Host smart-e5ae97a4-446e-42fe-951e-cdbb68d7cefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401533340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.401533340
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2383475859
Short name T607
Test name
Test status
Simulation time 12884737566 ps
CPU time 177.7 seconds
Started Jun 28 06:32:11 PM PDT 24
Finished Jun 28 06:35:12 PM PDT 24
Peak memory 253792 kb
Host smart-12e6bc64-1efe-4299-b94a-5cbe40b61933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383475859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2383475859
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3825637109
Short name T593
Test name
Test status
Simulation time 60594328 ps
CPU time 2.58 seconds
Started Jun 28 06:32:10 PM PDT 24
Finished Jun 28 06:32:15 PM PDT 24
Peak memory 224472 kb
Host smart-310b3826-3986-4aac-8d1f-f09ae539f67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825637109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3825637109
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2655273499
Short name T74
Test name
Test status
Simulation time 2267872330 ps
CPU time 54.34 seconds
Started Jun 28 06:32:09 PM PDT 24
Finished Jun 28 06:33:04 PM PDT 24
Peak memory 250864 kb
Host smart-7a5509d0-9e56-4dcd-8496-6e210402efc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655273499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2655273499
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3390396299
Short name T512
Test name
Test status
Simulation time 132432868 ps
CPU time 3.31 seconds
Started Jun 28 06:32:10 PM PDT 24
Finished Jun 28 06:32:16 PM PDT 24
Peak memory 224416 kb
Host smart-f33b3499-3b30-46e9-898c-d3b66d99a05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390396299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3390396299
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3012570760
Short name T710
Test name
Test status
Simulation time 253177869 ps
CPU time 7.09 seconds
Started Jun 28 06:32:08 PM PDT 24
Finished Jun 28 06:32:17 PM PDT 24
Peak memory 224476 kb
Host smart-ee393e42-324f-4dbf-b853-8f2440e15922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012570760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3012570760
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.371240331
Short name T748
Test name
Test status
Simulation time 1342596415 ps
CPU time 11.86 seconds
Started Jun 28 06:32:11 PM PDT 24
Finished Jun 28 06:32:26 PM PDT 24
Peak memory 248976 kb
Host smart-6d30c818-2c9f-4c82-9af8-5c683a594402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371240331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.371240331
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.870186004
Short name T843
Test name
Test status
Simulation time 2673169578 ps
CPU time 4.74 seconds
Started Jun 28 06:32:10 PM PDT 24
Finished Jun 28 06:32:16 PM PDT 24
Peak memory 224560 kb
Host smart-634935ff-f711-4a3f-999c-b2a7b8a5b089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870186004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.870186004
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1213883112
Short name T36
Test name
Test status
Simulation time 2000186877 ps
CPU time 21 seconds
Started Jun 28 06:32:10 PM PDT 24
Finished Jun 28 06:32:34 PM PDT 24
Peak memory 219880 kb
Host smart-492bdb19-3869-4423-b73d-fad2fa3ae0e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1213883112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1213883112
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.715666357
Short name T277
Test name
Test status
Simulation time 1931989208 ps
CPU time 11.77 seconds
Started Jun 28 06:31:58 PM PDT 24
Finished Jun 28 06:32:11 PM PDT 24
Peak memory 216344 kb
Host smart-6ce5f889-9967-4a8b-966b-4c755fac53c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715666357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.715666357
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1317863469
Short name T771
Test name
Test status
Simulation time 1602859638 ps
CPU time 4.97 seconds
Started Jun 28 06:31:59 PM PDT 24
Finished Jun 28 06:32:06 PM PDT 24
Peak memory 216208 kb
Host smart-156e9952-e7ae-4f56-9b22-6d921e761337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317863469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1317863469
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1343648036
Short name T567
Test name
Test status
Simulation time 28058638 ps
CPU time 1.11 seconds
Started Jun 28 06:32:09 PM PDT 24
Finished Jun 28 06:32:11 PM PDT 24
Peak memory 207580 kb
Host smart-13ece529-8dcc-415c-93aa-8aa7f2f3e8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343648036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1343648036
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1833335675
Short name T618
Test name
Test status
Simulation time 202622021 ps
CPU time 1.02 seconds
Started Jun 28 06:32:09 PM PDT 24
Finished Jun 28 06:32:11 PM PDT 24
Peak memory 205892 kb
Host smart-ebf30b19-acde-4e6e-8322-5526e8dba69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833335675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1833335675
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.75964192
Short name T568
Test name
Test status
Simulation time 328562690 ps
CPU time 4.77 seconds
Started Jun 28 06:32:11 PM PDT 24
Finished Jun 28 06:32:19 PM PDT 24
Peak memory 232656 kb
Host smart-772659fc-b579-4c8e-ad3b-b64179520c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75964192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.75964192
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2418574776
Short name T850
Test name
Test status
Simulation time 15623247 ps
CPU time 0.72 seconds
Started Jun 28 06:32:21 PM PDT 24
Finished Jun 28 06:32:23 PM PDT 24
Peak memory 204836 kb
Host smart-7ac37b1b-52b8-4176-8d68-9371c6e3b79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418574776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2418574776
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1484844573
Short name T985
Test name
Test status
Simulation time 2893688400 ps
CPU time 17.98 seconds
Started Jun 28 06:32:21 PM PDT 24
Finished Jun 28 06:32:41 PM PDT 24
Peak memory 224596 kb
Host smart-134f2ce5-5679-4dc1-8b7c-fc083016f479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484844573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1484844573
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1917425172
Short name T294
Test name
Test status
Simulation time 34482789 ps
CPU time 0.79 seconds
Started Jun 28 06:32:10 PM PDT 24
Finished Jun 28 06:32:14 PM PDT 24
Peak memory 206884 kb
Host smart-7876272e-b14c-45b5-8481-45dd75fb38eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917425172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1917425172
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.261073394
Short name T334
Test name
Test status
Simulation time 22288540838 ps
CPU time 56.35 seconds
Started Jun 28 06:32:21 PM PDT 24
Finished Jun 28 06:33:19 PM PDT 24
Peak memory 252016 kb
Host smart-cdf554eb-c993-4058-9b77-89d8407e09a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261073394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.261073394
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.639006237
Short name T287
Test name
Test status
Simulation time 5584604228 ps
CPU time 12 seconds
Started Jun 28 06:32:23 PM PDT 24
Finished Jun 28 06:32:37 PM PDT 24
Peak memory 217424 kb
Host smart-291738cc-3af6-4458-a935-339e1b6e06ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639006237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.639006237
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3875128571
Short name T271
Test name
Test status
Simulation time 1063195506 ps
CPU time 9.3 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:32:33 PM PDT 24
Peak memory 240896 kb
Host smart-ce5dec38-9c8d-4301-afac-7f44ab2b10bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875128571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3875128571
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.86907449
Short name T329
Test name
Test status
Simulation time 301642442 ps
CPU time 3.58 seconds
Started Jun 28 06:32:10 PM PDT 24
Finished Jun 28 06:32:15 PM PDT 24
Peak memory 232664 kb
Host smart-f2a0e04e-885a-42f6-8f9a-32788dfeea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86907449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.86907449
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2603317467
Short name T327
Test name
Test status
Simulation time 6535768695 ps
CPU time 23.44 seconds
Started Jun 28 06:32:11 PM PDT 24
Finished Jun 28 06:32:38 PM PDT 24
Peak memory 251820 kb
Host smart-92a724e0-cd18-449f-b1f2-c71f067512df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603317467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2603317467
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1469041207
Short name T519
Test name
Test status
Simulation time 956338640 ps
CPU time 7.9 seconds
Started Jun 28 06:32:10 PM PDT 24
Finished Jun 28 06:32:21 PM PDT 24
Peak memory 232572 kb
Host smart-1f07fe72-db24-4678-9404-15dc64ae4997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469041207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1469041207
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2906759537
Short name T569
Test name
Test status
Simulation time 3985055066 ps
CPU time 13.39 seconds
Started Jun 28 06:32:10 PM PDT 24
Finished Jun 28 06:32:26 PM PDT 24
Peak memory 240332 kb
Host smart-7d5a9d57-f626-43a0-be60-3848e1e6fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906759537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2906759537
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2576878894
Short name T126
Test name
Test status
Simulation time 259541047 ps
CPU time 3.39 seconds
Started Jun 28 06:32:24 PM PDT 24
Finished Jun 28 06:32:29 PM PDT 24
Peak memory 219356 kb
Host smart-fd47b25f-b0c8-4ddc-a1a7-c8b965991e18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2576878894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2576878894
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3062228095
Short name T908
Test name
Test status
Simulation time 14963351 ps
CPU time 0.74 seconds
Started Jun 28 06:32:11 PM PDT 24
Finished Jun 28 06:32:15 PM PDT 24
Peak memory 205664 kb
Host smart-6e7ef6cc-97c9-4e26-ad20-0489762662a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062228095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3062228095
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1913083433
Short name T701
Test name
Test status
Simulation time 19239361048 ps
CPU time 14.65 seconds
Started Jun 28 06:32:11 PM PDT 24
Finished Jun 28 06:32:29 PM PDT 24
Peak memory 217596 kb
Host smart-05a8776b-47ce-4bc8-9b83-dd2474485b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913083433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1913083433
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1441191942
Short name T860
Test name
Test status
Simulation time 163004500 ps
CPU time 4.24 seconds
Started Jun 28 06:32:11 PM PDT 24
Finished Jun 28 06:32:18 PM PDT 24
Peak memory 216252 kb
Host smart-303768de-2495-445f-8bda-d0ffcd5f1d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441191942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1441191942
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2008430623
Short name T845
Test name
Test status
Simulation time 262766888 ps
CPU time 0.94 seconds
Started Jun 28 06:32:09 PM PDT 24
Finished Jun 28 06:32:11 PM PDT 24
Peak memory 205892 kb
Host smart-56687a61-f738-4b15-abfc-80d89bf96554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008430623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2008430623
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1258487665
Short name T953
Test name
Test status
Simulation time 682067030 ps
CPU time 7.2 seconds
Started Jun 28 06:32:11 PM PDT 24
Finished Jun 28 06:32:21 PM PDT 24
Peak memory 232676 kb
Host smart-b0bb2678-5b70-4a72-88e4-34b830ef96e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258487665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1258487665
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1600787515
Short name T300
Test name
Test status
Simulation time 35193616 ps
CPU time 0.71 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:32:25 PM PDT 24
Peak memory 205340 kb
Host smart-fdba66c9-44e2-443b-96e5-4550979f67cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600787515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1600787515
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1840194208
Short name T824
Test name
Test status
Simulation time 626242826 ps
CPU time 3.9 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:32:28 PM PDT 24
Peak memory 232656 kb
Host smart-158c91ab-33f8-4aa5-ac3c-72771ec84dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840194208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1840194208
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.355298221
Short name T897
Test name
Test status
Simulation time 31230185 ps
CPU time 0.77 seconds
Started Jun 28 06:32:23 PM PDT 24
Finished Jun 28 06:32:25 PM PDT 24
Peak memory 205528 kb
Host smart-b2743f93-2781-41d4-aadf-8692b2074b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355298221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.355298221
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1990090281
Short name T587
Test name
Test status
Simulation time 17937610 ps
CPU time 0.78 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:32:24 PM PDT 24
Peak memory 215840 kb
Host smart-bc5ca22a-9bf4-4c4a-8968-f57c8b4adc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990090281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1990090281
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1024368209
Short name T237
Test name
Test status
Simulation time 2612880982 ps
CPU time 57.51 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:33:21 PM PDT 24
Peak memory 253624 kb
Host smart-0b7ff0a5-ea21-4ffd-b6e6-c66c3630896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024368209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1024368209
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3565839595
Short name T262
Test name
Test status
Simulation time 75970437419 ps
CPU time 178.71 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:35:23 PM PDT 24
Peak memory 249204 kb
Host smart-a796505f-0edc-41b9-9539-921613841c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565839595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3565839595
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3665037500
Short name T270
Test name
Test status
Simulation time 2172671137 ps
CPU time 9.69 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:32:34 PM PDT 24
Peak memory 232768 kb
Host smart-7c626d66-b232-4b22-be65-0718469a8942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665037500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3665037500
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3608740367
Short name T918
Test name
Test status
Simulation time 18156234715 ps
CPU time 127.44 seconds
Started Jun 28 06:32:21 PM PDT 24
Finished Jun 28 06:34:29 PM PDT 24
Peak memory 250572 kb
Host smart-bb4f217b-1c17-4303-a4fe-01859813911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608740367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3608740367
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.501961216
Short name T459
Test name
Test status
Simulation time 116932630 ps
CPU time 3.18 seconds
Started Jun 28 06:32:20 PM PDT 24
Finished Jun 28 06:32:24 PM PDT 24
Peak memory 227788 kb
Host smart-4c329ef2-ca91-41ce-aa81-5126bc39619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501961216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.501961216
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2983809095
Short name T969
Test name
Test status
Simulation time 1051993200 ps
CPU time 4.26 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:32:28 PM PDT 24
Peak memory 232660 kb
Host smart-a55ac6a6-48f8-4a58-b5b8-58ceb46debf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983809095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2983809095
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3418841118
Short name T883
Test name
Test status
Simulation time 2519761197 ps
CPU time 5 seconds
Started Jun 28 06:32:21 PM PDT 24
Finished Jun 28 06:32:27 PM PDT 24
Peak memory 232732 kb
Host smart-f690eff1-fe11-41ae-930f-1a17a0df6a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418841118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3418841118
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.872097848
Short name T326
Test name
Test status
Simulation time 206935472 ps
CPU time 3.26 seconds
Started Jun 28 06:32:23 PM PDT 24
Finished Jun 28 06:32:28 PM PDT 24
Peak memory 224456 kb
Host smart-2a1b4705-afc0-4343-8efd-ebd73a379688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872097848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.872097848
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.642631767
Short name T124
Test name
Test status
Simulation time 947431343 ps
CPU time 3.69 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:32:28 PM PDT 24
Peak memory 222528 kb
Host smart-9a0e964e-5905-4131-aac2-04eaad0abcec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=642631767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.642631767
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1874772903
Short name T819
Test name
Test status
Simulation time 125546299 ps
CPU time 1.1 seconds
Started Jun 28 06:32:20 PM PDT 24
Finished Jun 28 06:32:22 PM PDT 24
Peak memory 207008 kb
Host smart-03da1865-b3d4-473e-8a7a-9cf83f6b4c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874772903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1874772903
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2739242500
Short name T416
Test name
Test status
Simulation time 7479579801 ps
CPU time 10.93 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:32:34 PM PDT 24
Peak memory 216332 kb
Host smart-6743b718-2cbd-4b46-84e2-d4970a576bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739242500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2739242500
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2721235379
Short name T556
Test name
Test status
Simulation time 757415946 ps
CPU time 3.92 seconds
Started Jun 28 06:32:21 PM PDT 24
Finished Jun 28 06:32:27 PM PDT 24
Peak memory 216144 kb
Host smart-05c68a4b-5bc1-44f9-8f5c-f45a85bef3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721235379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2721235379
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4039827283
Short name T909
Test name
Test status
Simulation time 51215979 ps
CPU time 0.95 seconds
Started Jun 28 06:32:24 PM PDT 24
Finished Jun 28 06:32:26 PM PDT 24
Peak memory 207032 kb
Host smart-358be6a5-c214-4e79-99ee-0ca111528e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039827283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4039827283
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3669755118
Short name T558
Test name
Test status
Simulation time 61125938 ps
CPU time 0.84 seconds
Started Jun 28 06:32:20 PM PDT 24
Finished Jun 28 06:32:22 PM PDT 24
Peak memory 205848 kb
Host smart-3a1bd6de-7627-420f-911b-3a2c4931228e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669755118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3669755118
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2222388339
Short name T53
Test name
Test status
Simulation time 269959303 ps
CPU time 4.33 seconds
Started Jun 28 06:32:21 PM PDT 24
Finished Jun 28 06:32:27 PM PDT 24
Peak memory 224428 kb
Host smart-fda239b6-46d7-4b9b-9fe1-ef4ba8506d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222388339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2222388339
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3224302864
Short name T920
Test name
Test status
Simulation time 30624016 ps
CPU time 0.68 seconds
Started Jun 28 06:32:42 PM PDT 24
Finished Jun 28 06:32:45 PM PDT 24
Peak memory 205392 kb
Host smart-95f3d86d-882c-4efd-a875-229ba1e7219a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224302864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3224302864
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.748272261
Short name T216
Test name
Test status
Simulation time 1072694846 ps
CPU time 11.68 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:56 PM PDT 24
Peak memory 232700 kb
Host smart-5d4e0de5-87b5-402c-b859-1c739799e1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748272261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.748272261
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.212887491
Short name T399
Test name
Test status
Simulation time 63856646 ps
CPU time 0.76 seconds
Started Jun 28 06:32:23 PM PDT 24
Finished Jun 28 06:32:25 PM PDT 24
Peak memory 205508 kb
Host smart-343190c4-191d-49ff-b360-4ee5a530b3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212887491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.212887491
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2606225135
Short name T731
Test name
Test status
Simulation time 51135085912 ps
CPU time 160.17 seconds
Started Jun 28 06:32:39 PM PDT 24
Finished Jun 28 06:35:20 PM PDT 24
Peak memory 240984 kb
Host smart-a1b14daf-dd87-4f28-a250-a428aa21d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606225135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2606225135
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3746056726
Short name T191
Test name
Test status
Simulation time 6840899688 ps
CPU time 52.77 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:33:37 PM PDT 24
Peak memory 249276 kb
Host smart-71858c9f-00c0-428f-98f0-7fa18539c82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746056726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3746056726
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.65196655
Short name T864
Test name
Test status
Simulation time 29150552802 ps
CPU time 167.89 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:35:32 PM PDT 24
Peak memory 257392 kb
Host smart-9f0eb44a-1959-4731-9ff6-2e27da1aa0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65196655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.65196655
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2596454227
Short name T272
Test name
Test status
Simulation time 680385814 ps
CPU time 13.26 seconds
Started Jun 28 06:32:40 PM PDT 24
Finished Jun 28 06:32:55 PM PDT 24
Peak memory 232676 kb
Host smart-e75563f4-4653-4b4c-a431-5d115c1ad17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596454227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2596454227
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3218111579
Short name T174
Test name
Test status
Simulation time 1483914730 ps
CPU time 17.19 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:33:02 PM PDT 24
Peak memory 232560 kb
Host smart-d65b7892-a24c-4ae6-a572-aa4a9abf39cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218111579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3218111579
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3356949897
Short name T447
Test name
Test status
Simulation time 3360186389 ps
CPU time 23.17 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:33:07 PM PDT 24
Peak memory 232764 kb
Host smart-a0b4d262-bc35-4617-8f0e-cc13cfcaafe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356949897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3356949897
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1734609530
Short name T538
Test name
Test status
Simulation time 260358765 ps
CPU time 3.64 seconds
Started Jun 28 06:32:42 PM PDT 24
Finished Jun 28 06:32:48 PM PDT 24
Peak memory 232664 kb
Host smart-2e43eab5-28e6-4bce-95ed-4e3c01bdf086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734609530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1734609530
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.830899777
Short name T450
Test name
Test status
Simulation time 35601903549 ps
CPU time 13.61 seconds
Started Jun 28 06:32:42 PM PDT 24
Finished Jun 28 06:32:59 PM PDT 24
Peak memory 224528 kb
Host smart-425c2611-93e5-43bf-99d6-571ad441a7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830899777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.830899777
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.710390860
Short name T128
Test name
Test status
Simulation time 401739106 ps
CPU time 3.74 seconds
Started Jun 28 06:32:40 PM PDT 24
Finished Jun 28 06:32:47 PM PDT 24
Peak memory 222920 kb
Host smart-2b437e73-4c33-45c5-9d12-05b860e0efcd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=710390860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.710390860
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1528942286
Short name T401
Test name
Test status
Simulation time 61715644597 ps
CPU time 255.71 seconds
Started Jun 28 06:32:40 PM PDT 24
Finished Jun 28 06:36:59 PM PDT 24
Peak memory 253788 kb
Host smart-7cd8a3fb-b4a4-4af0-b038-b170137c29cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528942286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1528942286
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.330584160
Short name T495
Test name
Test status
Simulation time 926887838 ps
CPU time 3.29 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:47 PM PDT 24
Peak memory 216252 kb
Host smart-ca676de2-d4a4-4065-9527-f9becfa8a496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330584160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.330584160
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1087792857
Short name T347
Test name
Test status
Simulation time 5859028074 ps
CPU time 8.24 seconds
Started Jun 28 06:32:22 PM PDT 24
Finished Jun 28 06:32:32 PM PDT 24
Peak memory 216344 kb
Host smart-4c6d1961-bfaf-4269-83b1-426707a68850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087792857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1087792857
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3734298998
Short name T644
Test name
Test status
Simulation time 55505474 ps
CPU time 0.96 seconds
Started Jun 28 06:32:40 PM PDT 24
Finished Jun 28 06:32:44 PM PDT 24
Peak memory 206980 kb
Host smart-e534e6be-b1b5-4f34-8a19-313b44e12475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734298998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3734298998
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.399466549
Short name T23
Test name
Test status
Simulation time 18003898 ps
CPU time 0.72 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:45 PM PDT 24
Peak memory 205884 kb
Host smart-b6aef6a1-805f-45f4-bb48-a2623c62b8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399466549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.399466549
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2434786276
Short name T1019
Test name
Test status
Simulation time 3902400451 ps
CPU time 14.26 seconds
Started Jun 28 06:32:43 PM PDT 24
Finished Jun 28 06:33:00 PM PDT 24
Peak memory 232796 kb
Host smart-be53ef59-36cc-42be-a74a-2d26e64db325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434786276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2434786276
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.737935914
Short name T858
Test name
Test status
Simulation time 34687064 ps
CPU time 0.71 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:32:59 PM PDT 24
Peak memory 205372 kb
Host smart-b557c2f1-faa8-4ca4-9456-ae587f86d730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737935914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.737935914
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2759233352
Short name T806
Test name
Test status
Simulation time 356756462 ps
CPU time 5.51 seconds
Started Jun 28 06:32:39 PM PDT 24
Finished Jun 28 06:32:46 PM PDT 24
Peak memory 224380 kb
Host smart-460b496e-cf46-43fb-a928-825c78000916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759233352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2759233352
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.638990123
Short name T869
Test name
Test status
Simulation time 255747413 ps
CPU time 0.78 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:45 PM PDT 24
Peak memory 205504 kb
Host smart-0797e74a-96fb-4a13-881e-105fa76c0113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638990123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.638990123
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.36828683
Short name T64
Test name
Test status
Simulation time 162714394165 ps
CPU time 289.82 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:37:35 PM PDT 24
Peak memory 264684 kb
Host smart-d3178817-4ec5-4021-b1e2-f2ced2fc56a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36828683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.36828683
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1027730652
Short name T673
Test name
Test status
Simulation time 6936250869 ps
CPU time 44.31 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:33:39 PM PDT 24
Peak memory 257376 kb
Host smart-74b36458-f519-4215-a6f3-39ae29af2886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027730652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1027730652
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.357427367
Short name T786
Test name
Test status
Simulation time 143177741 ps
CPU time 2.33 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:46 PM PDT 24
Peak memory 224428 kb
Host smart-dfe9d6f1-ee8b-48d7-bf67-3356fc349abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357427367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.357427367
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2762444543
Short name T966
Test name
Test status
Simulation time 26710787813 ps
CPU time 69.36 seconds
Started Jun 28 06:32:40 PM PDT 24
Finished Jun 28 06:33:52 PM PDT 24
Peak memory 255128 kb
Host smart-a3fe6be0-1769-4be5-be59-0f39f792a0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762444543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2762444543
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4152581345
Short name T183
Test name
Test status
Simulation time 8910968176 ps
CPU time 23.55 seconds
Started Jun 28 06:32:42 PM PDT 24
Finished Jun 28 06:33:09 PM PDT 24
Peak memory 224524 kb
Host smart-62b43cb1-9932-4093-b710-e79c913ee1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152581345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4152581345
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3327913891
Short name T621
Test name
Test status
Simulation time 13347379484 ps
CPU time 28.34 seconds
Started Jun 28 06:32:40 PM PDT 24
Finished Jun 28 06:33:12 PM PDT 24
Peak memory 232832 kb
Host smart-54d042ae-510a-421c-a82b-d6e1cd6e31a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327913891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3327913891
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1225601264
Short name T681
Test name
Test status
Simulation time 47520236 ps
CPU time 2.51 seconds
Started Jun 28 06:32:40 PM PDT 24
Finished Jun 28 06:32:46 PM PDT 24
Peak memory 232604 kb
Host smart-4fd49f14-e92e-4e97-9d79-c13e373f4fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225601264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1225601264
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.542221942
Short name T514
Test name
Test status
Simulation time 4724978925 ps
CPU time 8.26 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:53 PM PDT 24
Peak memory 224568 kb
Host smart-47e346fd-65f9-49ed-b001-bf4166ecec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542221942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.542221942
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2833649710
Short name T826
Test name
Test status
Simulation time 702516845 ps
CPU time 6.28 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:50 PM PDT 24
Peak memory 221900 kb
Host smart-f0cce91e-cf08-47a7-935d-0fc6d61f6380
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2833649710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2833649710
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1647790026
Short name T496
Test name
Test status
Simulation time 458497935 ps
CPU time 6.11 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:49 PM PDT 24
Peak memory 216244 kb
Host smart-5d9dd130-d19f-471f-87f4-248469f59a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647790026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1647790026
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2848842343
Short name T685
Test name
Test status
Simulation time 3985701836 ps
CPU time 7.76 seconds
Started Jun 28 06:32:40 PM PDT 24
Finished Jun 28 06:32:51 PM PDT 24
Peak memory 216312 kb
Host smart-a090ccc4-c02c-453a-8503-36975ab5a824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848842343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2848842343
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3157079490
Short name T941
Test name
Test status
Simulation time 1012917836 ps
CPU time 9.4 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:53 PM PDT 24
Peak memory 216244 kb
Host smart-08e140d4-ac53-446f-b958-46eff8eccd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157079490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3157079490
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1853346270
Short name T11
Test name
Test status
Simulation time 90613444 ps
CPU time 0.86 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:45 PM PDT 24
Peak memory 205888 kb
Host smart-2dd1f608-d91e-4330-a40f-13fc641e63e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853346270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1853346270
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2034829573
Short name T491
Test name
Test status
Simulation time 686665040 ps
CPU time 4.12 seconds
Started Jun 28 06:32:41 PM PDT 24
Finished Jun 28 06:32:48 PM PDT 24
Peak memory 232620 kb
Host smart-beec9699-5a62-4cbd-9057-895c85ab5ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034829573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2034829573
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1854853554
Short name T331
Test name
Test status
Simulation time 12804700 ps
CPU time 0.72 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:32:59 PM PDT 24
Peak memory 205404 kb
Host smart-c37b096f-8096-45c9-ae16-ea3c95d2567a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854853554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1854853554
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1788674313
Short name T436
Test name
Test status
Simulation time 1077101434 ps
CPU time 12.02 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:33:07 PM PDT 24
Peak memory 224472 kb
Host smart-707a12b3-db8d-4f27-a567-836b1413516f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788674313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1788674313
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3118692136
Short name T1008
Test name
Test status
Simulation time 15352440 ps
CPU time 0.79 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:32:57 PM PDT 24
Peak memory 206448 kb
Host smart-30391aa9-c6a9-49b7-8dd1-fe9beb48da24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118692136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3118692136
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4013210406
Short name T410
Test name
Test status
Simulation time 30957960680 ps
CPU time 104.97 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:34:44 PM PDT 24
Peak memory 249872 kb
Host smart-be3894bc-ba18-4795-b539-0675bad87ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013210406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4013210406
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.797322033
Short name T242
Test name
Test status
Simulation time 62421199830 ps
CPU time 109.94 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:34:47 PM PDT 24
Peak memory 249224 kb
Host smart-37ccab08-718a-4647-be25-0f9b96696ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797322033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.797322033
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2369746899
Short name T503
Test name
Test status
Simulation time 8887709078 ps
CPU time 102.41 seconds
Started Jun 28 06:33:03 PM PDT 24
Finished Jun 28 06:34:50 PM PDT 24
Peak memory 249176 kb
Host smart-8d59f697-fc49-42a0-82c2-a8a1ead4deaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369746899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2369746899
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.176113337
Short name T799
Test name
Test status
Simulation time 940956128 ps
CPU time 6.12 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:33:01 PM PDT 24
Peak memory 232640 kb
Host smart-654663a0-b06a-492a-8e60-5e4718c4f43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176113337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.176113337
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1746768060
Short name T195
Test name
Test status
Simulation time 23469228803 ps
CPU time 82.33 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:34:19 PM PDT 24
Peak memory 237408 kb
Host smart-fd63f071-1b71-4102-a9fd-e815a81fc7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746768060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1746768060
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1544115640
Short name T597
Test name
Test status
Simulation time 11705021762 ps
CPU time 18.52 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:33:18 PM PDT 24
Peak memory 232716 kb
Host smart-a24a8134-69f5-4330-97a7-92d7c09ebc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544115640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1544115640
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1380277609
Short name T666
Test name
Test status
Simulation time 16555299760 ps
CPU time 14.32 seconds
Started Jun 28 06:32:53 PM PDT 24
Finished Jun 28 06:33:08 PM PDT 24
Peak memory 249008 kb
Host smart-b88811bb-b6f7-4589-a841-88a399a5ac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380277609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1380277609
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.957552300
Short name T492
Test name
Test status
Simulation time 60374446832 ps
CPU time 17.63 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:33:13 PM PDT 24
Peak memory 237108 kb
Host smart-e3ee3878-4c12-483d-b00c-05fb6a1bacc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957552300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.957552300
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2770217429
Short name T413
Test name
Test status
Simulation time 697686122 ps
CPU time 10.22 seconds
Started Jun 28 06:33:03 PM PDT 24
Finished Jun 28 06:33:18 PM PDT 24
Peak memory 220012 kb
Host smart-d5e95e9c-3395-41ae-aada-856672fef80e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2770217429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2770217429
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.878229261
Short name T12
Test name
Test status
Simulation time 39456658939 ps
CPU time 66.41 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:34:05 PM PDT 24
Peak memory 250208 kb
Host smart-84510e91-2aa6-44d2-866b-c3b9a8bc79da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878229261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.878229261
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.334717841
Short name T283
Test name
Test status
Simulation time 2633126833 ps
CPU time 5.29 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:33:01 PM PDT 24
Peak memory 216340 kb
Host smart-47cb1233-5ad2-42a5-8d00-0e61db2458d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334717841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.334717841
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1031412027
Short name T672
Test name
Test status
Simulation time 1943430803 ps
CPU time 4.73 seconds
Started Jun 28 06:32:53 PM PDT 24
Finished Jun 28 06:32:58 PM PDT 24
Peak memory 216144 kb
Host smart-37e9a9f8-00e6-45b4-a3f2-98611bbfc039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031412027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1031412027
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1333963281
Short name T435
Test name
Test status
Simulation time 61672820 ps
CPU time 0.97 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:32:56 PM PDT 24
Peak memory 206524 kb
Host smart-191909ec-251d-4ca7-824f-80f261b7f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333963281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1333963281
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1494901088
Short name T868
Test name
Test status
Simulation time 46925071 ps
CPU time 0.81 seconds
Started Jun 28 06:32:58 PM PDT 24
Finished Jun 28 06:33:01 PM PDT 24
Peak memory 205656 kb
Host smart-8759a099-b563-49a6-8b7f-392bf72461f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494901088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1494901088
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2718218222
Short name T431
Test name
Test status
Simulation time 663963244 ps
CPU time 2.76 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:33:00 PM PDT 24
Peak memory 224496 kb
Host smart-de3da46f-1ebc-4da3-81da-f8dc9eecfea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718218222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2718218222
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1141720787
Short name T926
Test name
Test status
Simulation time 27346460 ps
CPU time 0.74 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:32:58 PM PDT 24
Peak memory 205352 kb
Host smart-c19aad1c-5b7d-4cc4-ad96-22ac97a2d7c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141720787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1141720787
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.435142012
Short name T889
Test name
Test status
Simulation time 256936160 ps
CPU time 3.31 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:33:03 PM PDT 24
Peak memory 224392 kb
Host smart-5cb97cd2-fe2a-43ce-baee-872c5a2b608b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435142012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.435142012
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2801858809
Short name T940
Test name
Test status
Simulation time 18813900 ps
CPU time 0.73 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:32:55 PM PDT 24
Peak memory 206564 kb
Host smart-f2a598e9-215a-4144-a206-b48c6f384093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801858809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2801858809
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1856852231
Short name T651
Test name
Test status
Simulation time 10859253542 ps
CPU time 37.35 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:33:36 PM PDT 24
Peak memory 249136 kb
Host smart-e42fdf43-fa85-445e-a804-5e4b0daf8e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856852231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1856852231
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.65155650
Short name T792
Test name
Test status
Simulation time 38139167378 ps
CPU time 259.62 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:37:18 PM PDT 24
Peak memory 264644 kb
Host smart-2d45c6fb-96c2-4348-ac89-70ad5183e8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65155650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.65155650
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2150657936
Short name T252
Test name
Test status
Simulation time 2442542767 ps
CPU time 65.85 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:34:02 PM PDT 24
Peak memory 254660 kb
Host smart-287db170-ea8e-4ddf-a7ed-d0b3fd81d2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150657936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2150657936
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1662835810
Short name T317
Test name
Test status
Simulation time 13213662148 ps
CPU time 53.2 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:33:53 PM PDT 24
Peak memory 240132 kb
Host smart-ceffd4d0-47f1-4ee7-933b-2ae4e7dead8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662835810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1662835810
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1432103936
Short name T968
Test name
Test status
Simulation time 2625481002 ps
CPU time 51.26 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:33:51 PM PDT 24
Peak memory 256392 kb
Host smart-84084748-4af0-487c-8543-c583ad215670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432103936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1432103936
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2824148808
Short name T865
Test name
Test status
Simulation time 4250818430 ps
CPU time 8.56 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:33:05 PM PDT 24
Peak memory 232788 kb
Host smart-d99051d2-4f53-43d9-bd72-2ebee2d676c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824148808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2824148808
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1914926573
Short name T954
Test name
Test status
Simulation time 534441883 ps
CPU time 10.92 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:33:10 PM PDT 24
Peak memory 232636 kb
Host smart-4e3a6e96-7dc5-4330-add4-9e2ae474cd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914926573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1914926573
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3946035560
Short name T225
Test name
Test status
Simulation time 249075358 ps
CPU time 4.15 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:33:03 PM PDT 24
Peak memory 224432 kb
Host smart-3229efe1-69df-425a-9181-92cee9888d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946035560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3946035560
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.748085602
Short name T236
Test name
Test status
Simulation time 183732468 ps
CPU time 2.41 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:32:57 PM PDT 24
Peak memory 224432 kb
Host smart-2371890a-c09f-4392-990a-7b108bcd03e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748085602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.748085602
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.324486295
Short name T391
Test name
Test status
Simulation time 5432048769 ps
CPU time 7.82 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:33:05 PM PDT 24
Peak memory 223308 kb
Host smart-d6358839-b18a-456a-8a38-513b10c28c84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=324486295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.324486295
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.629346406
Short name T517
Test name
Test status
Simulation time 8642437935 ps
CPU time 63.56 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:34:03 PM PDT 24
Peak memory 238044 kb
Host smart-4cb68461-56bc-4504-99b7-5205691fc5e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629346406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.629346406
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1465989404
Short name T880
Test name
Test status
Simulation time 2213293620 ps
CPU time 21.43 seconds
Started Jun 28 06:32:53 PM PDT 24
Finished Jun 28 06:33:16 PM PDT 24
Peak memory 216548 kb
Host smart-53bf0ced-e83d-48fd-8879-96f5cb4a9fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465989404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1465989404
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3803897794
Short name T733
Test name
Test status
Simulation time 2852979846 ps
CPU time 3.03 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:33:02 PM PDT 24
Peak memory 216256 kb
Host smart-f56ce928-2f86-4cb7-969e-8a2500be0303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803897794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3803897794
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2357796874
Short name T891
Test name
Test status
Simulation time 29498163 ps
CPU time 1.51 seconds
Started Jun 28 06:32:55 PM PDT 24
Finished Jun 28 06:33:00 PM PDT 24
Peak memory 216384 kb
Host smart-ae1b2904-a81d-49d4-871c-46481cb0a81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357796874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2357796874
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2037419297
Short name T724
Test name
Test status
Simulation time 87851202 ps
CPU time 0.76 seconds
Started Jun 28 06:32:56 PM PDT 24
Finished Jun 28 06:33:01 PM PDT 24
Peak memory 205852 kb
Host smart-a2a73cc9-8f2f-4592-bed5-08acff255906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037419297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2037419297
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.12181492
Short name T911
Test name
Test status
Simulation time 551040510 ps
CPU time 4.07 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:32:59 PM PDT 24
Peak memory 232684 kb
Host smart-0b97c0de-788f-4dba-ad0e-1e674e118829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12181492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.12181492
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4230038349
Short name T301
Test name
Test status
Simulation time 13008330 ps
CPU time 0.74 seconds
Started Jun 28 06:33:08 PM PDT 24
Finished Jun 28 06:33:13 PM PDT 24
Peak memory 205396 kb
Host smart-c7dc357f-29f7-4aea-9184-fd3caf44fc20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230038349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4230038349
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1832585241
Short name T905
Test name
Test status
Simulation time 472656460 ps
CPU time 5.68 seconds
Started Jun 28 06:33:09 PM PDT 24
Finished Jun 28 06:33:21 PM PDT 24
Peak memory 232652 kb
Host smart-b575017c-86ab-4ab9-be92-2334a8367eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832585241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1832585241
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.42616037
Short name T591
Test name
Test status
Simulation time 27879262 ps
CPU time 0.75 seconds
Started Jun 28 06:32:54 PM PDT 24
Finished Jun 28 06:32:57 PM PDT 24
Peak memory 205556 kb
Host smart-72b2c1f3-bffe-4484-8865-41dc952b9e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42616037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.42616037
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2950007222
Short name T341
Test name
Test status
Simulation time 40517674809 ps
CPU time 89.91 seconds
Started Jun 28 06:33:06 PM PDT 24
Finished Jun 28 06:34:40 PM PDT 24
Peak memory 252108 kb
Host smart-7331f927-ffa7-45ff-b2bf-564f5c4e4237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950007222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2950007222
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1692322689
Short name T29
Test name
Test status
Simulation time 100304951110 ps
CPU time 416 seconds
Started Jun 28 06:33:07 PM PDT 24
Finished Jun 28 06:40:08 PM PDT 24
Peak memory 255316 kb
Host smart-ec8a8bf1-77f2-4570-97be-63a01a1ce8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692322689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1692322689
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2638550153
Short name T873
Test name
Test status
Simulation time 27503706496 ps
CPU time 148.47 seconds
Started Jun 28 06:33:09 PM PDT 24
Finished Jun 28 06:35:43 PM PDT 24
Peak memory 241060 kb
Host smart-ecbe07dc-c8cf-4d5d-afce-b9cb6dda36f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638550153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2638550153
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1851791032
Short name T964
Test name
Test status
Simulation time 55748600 ps
CPU time 4.22 seconds
Started Jun 28 06:33:08 PM PDT 24
Finished Jun 28 06:33:17 PM PDT 24
Peak memory 232608 kb
Host smart-1cd1d09e-2771-4b73-adb8-9151cb3b60a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851791032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1851791032
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1911696521
Short name T837
Test name
Test status
Simulation time 7570981551 ps
CPU time 60.42 seconds
Started Jun 28 06:33:08 PM PDT 24
Finished Jun 28 06:34:14 PM PDT 24
Peak memory 255072 kb
Host smart-5252e167-4c3f-4bdb-9ba9-fe68b9abcb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911696521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1911696521
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1423674577
Short name T853
Test name
Test status
Simulation time 806822153 ps
CPU time 4.4 seconds
Started Jun 28 06:33:09 PM PDT 24
Finished Jun 28 06:33:18 PM PDT 24
Peak memory 232604 kb
Host smart-2812141d-034b-4918-8e29-a9019b490ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423674577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1423674577
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2362322439
Short name T990
Test name
Test status
Simulation time 7874422481 ps
CPU time 70.87 seconds
Started Jun 28 06:33:09 PM PDT 24
Finished Jun 28 06:34:25 PM PDT 24
Peak memory 239612 kb
Host smart-292d275f-1f5c-4355-b751-9b28596b519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362322439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2362322439
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3271429589
Short name T903
Test name
Test status
Simulation time 9730183737 ps
CPU time 12.58 seconds
Started Jun 28 06:33:09 PM PDT 24
Finished Jun 28 06:33:28 PM PDT 24
Peak memory 224620 kb
Host smart-68f8d897-199d-4ba3-b4cf-fdb946b2c0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271429589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3271429589
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2481269801
Short name T949
Test name
Test status
Simulation time 1263097068 ps
CPU time 2.33 seconds
Started Jun 28 06:33:06 PM PDT 24
Finished Jun 28 06:33:13 PM PDT 24
Peak memory 224284 kb
Host smart-416e4ba3-e060-4a2f-bf6f-2d219e2c24b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481269801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2481269801
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3777794415
Short name T690
Test name
Test status
Simulation time 878334474 ps
CPU time 3.95 seconds
Started Jun 28 06:33:06 PM PDT 24
Finished Jun 28 06:33:14 PM PDT 24
Peak memory 219712 kb
Host smart-cbf5bfa2-c7d3-42d6-844f-6e1a482bb1d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3777794415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3777794415
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1983238591
Short name T688
Test name
Test status
Simulation time 749995262845 ps
CPU time 578.54 seconds
Started Jun 28 06:33:08 PM PDT 24
Finished Jun 28 06:42:51 PM PDT 24
Peak memory 267724 kb
Host smart-96d379ad-75ce-4931-ad4a-0b29fb256be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983238591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1983238591
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2932391936
Short name T1031
Test name
Test status
Simulation time 6118418724 ps
CPU time 8.5 seconds
Started Jun 28 06:33:08 PM PDT 24
Finished Jun 28 06:33:23 PM PDT 24
Peak memory 216328 kb
Host smart-c29e274d-5334-44ad-88a4-8e214f5a1339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932391936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2932391936
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4275516786
Short name T561
Test name
Test status
Simulation time 2724645312 ps
CPU time 10.63 seconds
Started Jun 28 06:33:09 PM PDT 24
Finished Jun 28 06:33:25 PM PDT 24
Peak memory 216308 kb
Host smart-95587b50-4858-4120-b73c-d603424fadfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275516786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4275516786
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.958793130
Short name T422
Test name
Test status
Simulation time 185098778 ps
CPU time 1.37 seconds
Started Jun 28 06:33:07 PM PDT 24
Finished Jun 28 06:33:14 PM PDT 24
Peak memory 216196 kb
Host smart-6c5019f4-9c12-42a8-b221-016d6d73ba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958793130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.958793130
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4117502967
Short name T508
Test name
Test status
Simulation time 39457806 ps
CPU time 0.73 seconds
Started Jun 28 06:33:05 PM PDT 24
Finished Jun 28 06:33:10 PM PDT 24
Peak memory 205588 kb
Host smart-0b74b19c-8919-4edb-90b9-76fbe472e80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117502967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4117502967
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1369665866
Short name T498
Test name
Test status
Simulation time 447407653 ps
CPU time 9.1 seconds
Started Jun 28 06:33:07 PM PDT 24
Finished Jun 28 06:33:21 PM PDT 24
Peak memory 249056 kb
Host smart-1eb5ebf6-e190-41e6-aa79-23b5a81d2891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369665866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1369665866
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2618675904
Short name T960
Test name
Test status
Simulation time 102512002 ps
CPU time 0.72 seconds
Started Jun 28 06:33:19 PM PDT 24
Finished Jun 28 06:33:21 PM PDT 24
Peak memory 205716 kb
Host smart-9feba8c8-4f0f-4cdb-9e38-13085573e7f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618675904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2618675904
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3821577996
Short name T1023
Test name
Test status
Simulation time 771361813 ps
CPU time 6.39 seconds
Started Jun 28 06:33:18 PM PDT 24
Finished Jun 28 06:33:27 PM PDT 24
Peak memory 232624 kb
Host smart-3fab3f82-a954-46bb-80ae-35fdbfb699ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821577996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3821577996
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1529043293
Short name T646
Test name
Test status
Simulation time 53797982 ps
CPU time 0.76 seconds
Started Jun 28 06:33:09 PM PDT 24
Finished Jun 28 06:33:15 PM PDT 24
Peak memory 205536 kb
Host smart-66756506-9895-4f4b-b053-04bafddf2b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529043293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1529043293
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1889698677
Short name T480
Test name
Test status
Simulation time 27622990874 ps
CPU time 65.79 seconds
Started Jun 28 06:33:19 PM PDT 24
Finished Jun 28 06:34:27 PM PDT 24
Peak memory 232820 kb
Host smart-e74eecdb-6a6a-450b-b922-af8ed9d7718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889698677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1889698677
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1759871201
Short name T577
Test name
Test status
Simulation time 112163027960 ps
CPU time 239.41 seconds
Started Jun 28 06:33:20 PM PDT 24
Finished Jun 28 06:37:22 PM PDT 24
Peak memory 249260 kb
Host smart-9e00ca87-9925-4f74-84b7-28e13722095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759871201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1759871201
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3428342892
Short name T552
Test name
Test status
Simulation time 1053110061 ps
CPU time 9.29 seconds
Started Jun 28 06:33:20 PM PDT 24
Finished Jun 28 06:33:31 PM PDT 24
Peak memory 238452 kb
Host smart-0d288ba7-b595-49db-82cc-8084cda8e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428342892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3428342892
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1180792240
Short name T462
Test name
Test status
Simulation time 25047955056 ps
CPU time 36.48 seconds
Started Jun 28 06:33:18 PM PDT 24
Finished Jun 28 06:33:57 PM PDT 24
Peak memory 249200 kb
Host smart-2a6ae0be-aec3-4c7c-85bd-6ce0bae3ee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180792240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1180792240
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1487705314
Short name T211
Test name
Test status
Simulation time 157242805 ps
CPU time 2.88 seconds
Started Jun 28 06:33:08 PM PDT 24
Finished Jun 28 06:33:17 PM PDT 24
Peak memory 224436 kb
Host smart-16f66833-06df-4494-b504-e7df1ec4569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487705314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1487705314
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.488778978
Short name T834
Test name
Test status
Simulation time 221014007 ps
CPU time 4.14 seconds
Started Jun 28 06:33:07 PM PDT 24
Finished Jun 28 06:33:16 PM PDT 24
Peak memory 224428 kb
Host smart-9e34845a-7c57-4682-b226-6d2119baf298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488778978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.488778978
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1558667864
Short name T746
Test name
Test status
Simulation time 1119167945 ps
CPU time 4.01 seconds
Started Jun 28 06:33:10 PM PDT 24
Finished Jun 28 06:33:19 PM PDT 24
Peak memory 224388 kb
Host smart-ccdd336a-5ccc-4119-85f0-ea7600113397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558667864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1558667864
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2107566049
Short name T706
Test name
Test status
Simulation time 251660333 ps
CPU time 4.72 seconds
Started Jun 28 06:33:08 PM PDT 24
Finished Jun 28 06:33:18 PM PDT 24
Peak memory 224408 kb
Host smart-4ce2d7c2-cc61-4f52-a991-cdd66d04cd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107566049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2107566049
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1237025712
Short name T439
Test name
Test status
Simulation time 6872270480 ps
CPU time 14.43 seconds
Started Jun 28 06:33:19 PM PDT 24
Finished Jun 28 06:33:35 PM PDT 24
Peak memory 220312 kb
Host smart-557c1d6f-73d8-45b1-828b-fb483b90774c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1237025712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1237025712
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1778713017
Short name T852
Test name
Test status
Simulation time 103625940337 ps
CPU time 246.46 seconds
Started Jun 28 06:33:21 PM PDT 24
Finished Jun 28 06:37:29 PM PDT 24
Peak memory 265664 kb
Host smart-4c0b6fe1-e94f-46a9-8010-d1a94fe6cf82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778713017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1778713017
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.172220448
Short name T533
Test name
Test status
Simulation time 5447760430 ps
CPU time 26.05 seconds
Started Jun 28 06:33:07 PM PDT 24
Finished Jun 28 06:33:38 PM PDT 24
Peak memory 216308 kb
Host smart-af3de906-17b5-4d83-bab9-52702015c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172220448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.172220448
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.48823155
Short name T975
Test name
Test status
Simulation time 3668191337 ps
CPU time 6.29 seconds
Started Jun 28 06:33:06 PM PDT 24
Finished Jun 28 06:33:17 PM PDT 24
Peak memory 216328 kb
Host smart-78f053bb-4822-4256-a7ab-bd15583042aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48823155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.48823155
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1914597415
Short name T877
Test name
Test status
Simulation time 128063764 ps
CPU time 1.06 seconds
Started Jun 28 06:33:06 PM PDT 24
Finished Jun 28 06:33:12 PM PDT 24
Peak memory 207092 kb
Host smart-7042032e-c47a-4a77-88e2-b48e6c584ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914597415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1914597415
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3647873996
Short name T501
Test name
Test status
Simulation time 102049725 ps
CPU time 1.09 seconds
Started Jun 28 06:33:07 PM PDT 24
Finished Jun 28 06:33:13 PM PDT 24
Peak memory 206884 kb
Host smart-d55ecac7-40e8-4794-a0d6-0942fa3e7e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647873996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3647873996
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3032041506
Short name T929
Test name
Test status
Simulation time 15696520505 ps
CPU time 15.91 seconds
Started Jun 28 06:33:21 PM PDT 24
Finished Jun 28 06:33:38 PM PDT 24
Peak memory 240864 kb
Host smart-972579bb-e3a9-401c-ae3f-fbc6624fe2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032041506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3032041506
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1940000283
Short name T638
Test name
Test status
Simulation time 15771929 ps
CPU time 0.75 seconds
Started Jun 28 06:28:28 PM PDT 24
Finished Jun 28 06:28:30 PM PDT 24
Peak memory 204800 kb
Host smart-20a57123-50fb-4e0b-aa21-ee240151f883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940000283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
940000283
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3327042373
Short name T1027
Test name
Test status
Simulation time 2018609438 ps
CPU time 15.75 seconds
Started Jun 28 06:28:28 PM PDT 24
Finished Jun 28 06:28:45 PM PDT 24
Peak memory 224488 kb
Host smart-2aa81823-eafc-4a32-b7b1-eb1adea6c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327042373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3327042373
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3198683963
Short name T304
Test name
Test status
Simulation time 20301207 ps
CPU time 0.84 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:23 PM PDT 24
Peak memory 205864 kb
Host smart-b16be1aa-6ca4-4ba9-9c7a-8a57f4d168e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198683963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3198683963
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.478094579
Short name T363
Test name
Test status
Simulation time 36271603 ps
CPU time 0.76 seconds
Started Jun 28 06:28:28 PM PDT 24
Finished Jun 28 06:28:30 PM PDT 24
Peak memory 215848 kb
Host smart-29c1c422-34e8-4051-b8aa-5423494e774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478094579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.478094579
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.37607902
Short name T635
Test name
Test status
Simulation time 6377716332 ps
CPU time 24.85 seconds
Started Jun 28 06:28:26 PM PDT 24
Finished Jun 28 06:28:52 PM PDT 24
Peak memory 217460 kb
Host smart-5f14d98b-2e9d-4562-8463-b44b8272e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37607902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.37607902
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2221005474
Short name T738
Test name
Test status
Simulation time 105076890 ps
CPU time 3.1 seconds
Started Jun 28 06:28:33 PM PDT 24
Finished Jun 28 06:28:36 PM PDT 24
Peak memory 224468 kb
Host smart-0deac3d8-cb29-4816-adc7-9ada1a41665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221005474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2221005474
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.444272939
Short name T375
Test name
Test status
Simulation time 8540315055 ps
CPU time 89.13 seconds
Started Jun 28 06:28:28 PM PDT 24
Finished Jun 28 06:29:58 PM PDT 24
Peak memory 251924 kb
Host smart-f28eac04-2b9e-4bac-9347-c74a4caeb566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444272939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
444272939
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3719000978
Short name T203
Test name
Test status
Simulation time 3143058359 ps
CPU time 29.36 seconds
Started Jun 28 06:28:29 PM PDT 24
Finished Jun 28 06:29:00 PM PDT 24
Peak memory 224564 kb
Host smart-7e5c46ea-8362-417a-8814-6332a8bca599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719000978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3719000978
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.321710833
Short name T479
Test name
Test status
Simulation time 773294935 ps
CPU time 16.15 seconds
Started Jun 28 06:28:28 PM PDT 24
Finished Jun 28 06:28:45 PM PDT 24
Peak memory 224496 kb
Host smart-ba53e639-507b-4121-b8f6-c736245461e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321710833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.321710833
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1102390835
Short name T610
Test name
Test status
Simulation time 16012653 ps
CPU time 1.1 seconds
Started Jun 28 06:28:19 PM PDT 24
Finished Jun 28 06:28:23 PM PDT 24
Peak memory 218084 kb
Host smart-1081ee48-d8d8-40ce-a450-c8ee62c044ed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102390835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1102390835
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3900658788
Short name T356
Test name
Test status
Simulation time 672735548 ps
CPU time 8.34 seconds
Started Jun 28 06:28:32 PM PDT 24
Finished Jun 28 06:28:41 PM PDT 24
Peak memory 237424 kb
Host smart-54f8a8fd-e0a6-4c0c-bc77-bf4374896227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900658788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3900658788
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3921104496
Short name T452
Test name
Test status
Simulation time 5064386714 ps
CPU time 7.02 seconds
Started Jun 28 06:28:28 PM PDT 24
Finished Jun 28 06:28:36 PM PDT 24
Peak memory 232724 kb
Host smart-af14324f-9b3c-43e7-ada9-3f6261944bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921104496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3921104496
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.192531552
Short name T350
Test name
Test status
Simulation time 1372912766 ps
CPU time 5.51 seconds
Started Jun 28 06:28:26 PM PDT 24
Finished Jun 28 06:28:32 PM PDT 24
Peak memory 220180 kb
Host smart-b5b62b35-ebd9-403a-9260-ae63d534b850
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=192531552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.192531552
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.901870159
Short name T48
Test name
Test status
Simulation time 49907175 ps
CPU time 0.99 seconds
Started Jun 28 06:28:29 PM PDT 24
Finished Jun 28 06:28:31 PM PDT 24
Peak memory 235700 kb
Host smart-4e1883c9-517f-4786-ac98-7e97751cfcda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901870159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.901870159
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2015399830
Short name T598
Test name
Test status
Simulation time 29202384245 ps
CPU time 124.44 seconds
Started Jun 28 06:28:28 PM PDT 24
Finished Jun 28 06:30:33 PM PDT 24
Peak memory 261108 kb
Host smart-80aa22eb-e2fe-4174-b812-783b685b958b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015399830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2015399830
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3357593028
Short name T588
Test name
Test status
Simulation time 22624059851 ps
CPU time 25.35 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:28:48 PM PDT 24
Peak memory 216528 kb
Host smart-44a0712b-fc42-4951-a543-34798489347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357593028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3357593028
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1142106879
Short name T636
Test name
Test status
Simulation time 12169560 ps
CPU time 0.75 seconds
Started Jun 28 06:28:21 PM PDT 24
Finished Jun 28 06:28:24 PM PDT 24
Peak memory 205668 kb
Host smart-02f0673b-b797-4267-928e-eaaee7570ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142106879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1142106879
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1263567335
Short name T1007
Test name
Test status
Simulation time 458302935 ps
CPU time 2.4 seconds
Started Jun 28 06:28:20 PM PDT 24
Finished Jun 28 06:28:25 PM PDT 24
Peak memory 216404 kb
Host smart-38dfe0fc-8393-4231-b107-b4e40c3d9050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263567335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1263567335
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.946077170
Short name T25
Test name
Test status
Simulation time 559137006 ps
CPU time 1.05 seconds
Started Jun 28 06:28:23 PM PDT 24
Finished Jun 28 06:28:26 PM PDT 24
Peak memory 205888 kb
Host smart-d375262a-9bcd-4d21-941b-384c390c0fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946077170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.946077170
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1207290064
Short name T44
Test name
Test status
Simulation time 375405470 ps
CPU time 7.21 seconds
Started Jun 28 06:28:27 PM PDT 24
Finished Jun 28 06:28:35 PM PDT 24
Peak memory 232700 kb
Host smart-bbf32643-f583-4636-8283-509a054bf86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207290064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1207290064
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2373383523
Short name T728
Test name
Test status
Simulation time 78031123 ps
CPU time 0.72 seconds
Started Jun 28 06:33:19 PM PDT 24
Finished Jun 28 06:33:22 PM PDT 24
Peak memory 205428 kb
Host smart-eb5828aa-fd06-4f2d-8e75-51782af65470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373383523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2373383523
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.512585259
Short name T631
Test name
Test status
Simulation time 3277810541 ps
CPU time 25.33 seconds
Started Jun 28 06:33:30 PM PDT 24
Finished Jun 28 06:33:57 PM PDT 24
Peak memory 224552 kb
Host smart-1b172c5d-fdcf-4a49-81e4-876a6ecdcb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512585259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.512585259
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.839270325
Short name T594
Test name
Test status
Simulation time 49057181 ps
CPU time 0.79 seconds
Started Jun 28 06:33:19 PM PDT 24
Finished Jun 28 06:33:22 PM PDT 24
Peak memory 206548 kb
Host smart-cad9b32b-014f-442a-920e-2e7363e51edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839270325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.839270325
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1377487266
Short name T895
Test name
Test status
Simulation time 1878646119 ps
CPU time 21.41 seconds
Started Jun 28 06:33:17 PM PDT 24
Finished Jun 28 06:33:41 PM PDT 24
Peak memory 238984 kb
Host smart-b795fa2a-6455-4a5a-a8ca-a4bfe36cabed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377487266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1377487266
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2596652906
Short name T551
Test name
Test status
Simulation time 5944085822 ps
CPU time 52.75 seconds
Started Jun 28 06:33:29 PM PDT 24
Finished Jun 28 06:34:24 PM PDT 24
Peak memory 253108 kb
Host smart-72d2af4d-7259-4cfa-ba5e-992a85337e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596652906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2596652906
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1596318924
Short name T971
Test name
Test status
Simulation time 41107159136 ps
CPU time 103.44 seconds
Started Jun 28 06:33:18 PM PDT 24
Finished Jun 28 06:35:04 PM PDT 24
Peak memory 249812 kb
Host smart-a0aea741-fd57-46c0-9cea-852e759cb334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596318924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1596318924
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.772384695
Short name T269
Test name
Test status
Simulation time 1093384143 ps
CPU time 14.8 seconds
Started Jun 28 06:33:17 PM PDT 24
Finished Jun 28 06:33:34 PM PDT 24
Peak memory 224508 kb
Host smart-85ac2d22-b1bf-4ce0-a51d-a6149fe896ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772384695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.772384695
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3528056267
Short name T767
Test name
Test status
Simulation time 21849971518 ps
CPU time 162.54 seconds
Started Jun 28 06:33:19 PM PDT 24
Finished Jun 28 06:36:04 PM PDT 24
Peak memory 250284 kb
Host smart-ddb2b5da-3135-4459-a3a4-60edb6fcf171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528056267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3528056267
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1412697129
Short name T437
Test name
Test status
Simulation time 113420379 ps
CPU time 3.41 seconds
Started Jun 28 06:33:29 PM PDT 24
Finished Jun 28 06:33:35 PM PDT 24
Peak memory 232640 kb
Host smart-a71331a1-cab0-4afc-9334-0c1f30b96b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412697129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1412697129
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2567114181
Short name T234
Test name
Test status
Simulation time 571986064 ps
CPU time 4.15 seconds
Started Jun 28 06:33:19 PM PDT 24
Finished Jun 28 06:33:25 PM PDT 24
Peak memory 224388 kb
Host smart-a7b3c4df-803a-4c4e-939f-fd9637433356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567114181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2567114181
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3996143447
Short name T425
Test name
Test status
Simulation time 32278631 ps
CPU time 2.5 seconds
Started Jun 28 06:33:21 PM PDT 24
Finished Jun 28 06:33:25 PM PDT 24
Peak memory 232404 kb
Host smart-a251a223-ad46-4acf-b53b-76d1006169af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996143447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3996143447
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3750612641
Short name T426
Test name
Test status
Simulation time 13753931221 ps
CPU time 10.31 seconds
Started Jun 28 06:33:20 PM PDT 24
Finished Jun 28 06:33:33 PM PDT 24
Peak memory 232820 kb
Host smart-83c58b4d-d00f-41f0-bbc1-f1727b1534f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750612641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3750612641
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1763264381
Short name T664
Test name
Test status
Simulation time 1623030283 ps
CPU time 5.66 seconds
Started Jun 28 06:33:30 PM PDT 24
Finished Jun 28 06:33:37 PM PDT 24
Peak memory 222796 kb
Host smart-9844f92a-f518-4e6a-b3df-e4f65adc57f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1763264381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1763264381
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3464269943
Short name T141
Test name
Test status
Simulation time 46445121224 ps
CPU time 171.01 seconds
Started Jun 28 06:33:30 PM PDT 24
Finished Jun 28 06:36:23 PM PDT 24
Peak memory 256072 kb
Host smart-6548c489-61c9-4bde-bb40-9f5c178c1403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464269943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3464269943
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3124852867
Short name T98
Test name
Test status
Simulation time 2245646433 ps
CPU time 27.91 seconds
Started Jun 28 06:33:21 PM PDT 24
Finished Jun 28 06:33:50 PM PDT 24
Peak memory 216364 kb
Host smart-a3971b33-343b-4082-85a1-e1a0b485e0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124852867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3124852867
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.602774043
Short name T442
Test name
Test status
Simulation time 2137815175 ps
CPU time 8.62 seconds
Started Jun 28 06:33:30 PM PDT 24
Finished Jun 28 06:33:40 PM PDT 24
Peak memory 216112 kb
Host smart-6d19422a-8609-4245-a696-cf65f27a5cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602774043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.602774043
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.246929007
Short name T530
Test name
Test status
Simulation time 62136994 ps
CPU time 1.06 seconds
Started Jun 28 06:33:20 PM PDT 24
Finished Jun 28 06:33:23 PM PDT 24
Peak memory 207932 kb
Host smart-cc5c6059-9c68-467f-ad1f-4f9b7053d984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246929007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.246929007
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.649015328
Short name T723
Test name
Test status
Simulation time 102970135 ps
CPU time 0.96 seconds
Started Jun 28 06:33:20 PM PDT 24
Finished Jun 28 06:33:23 PM PDT 24
Peak memory 206904 kb
Host smart-aaa6281f-b06e-4aa3-b6f4-6035c396c102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649015328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.649015328
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.191066569
Short name T639
Test name
Test status
Simulation time 4033970387 ps
CPU time 9.45 seconds
Started Jun 28 06:33:20 PM PDT 24
Finished Jun 28 06:33:31 PM PDT 24
Peak memory 232796 kb
Host smart-2e871068-6ce8-4f78-a641-e06526684f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191066569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.191066569
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4094531041
Short name T923
Test name
Test status
Simulation time 22304324 ps
CPU time 0.69 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:33:29 PM PDT 24
Peak memory 205416 kb
Host smart-4cf1391c-c844-4630-933a-3f452eb1004c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094531041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4094531041
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2630955283
Short name T161
Test name
Test status
Simulation time 716428401 ps
CPU time 3.85 seconds
Started Jun 28 06:33:26 PM PDT 24
Finished Jun 28 06:33:32 PM PDT 24
Peak memory 224464 kb
Host smart-d9dae298-d359-4651-9a66-86c2a8978914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630955283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2630955283
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.335034664
Short name T297
Test name
Test status
Simulation time 33759715 ps
CPU time 0.77 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:33:31 PM PDT 24
Peak memory 206556 kb
Host smart-690c27e4-6357-4f1b-b2fc-4e7551cd4c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335034664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.335034664
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.453440501
Short name T187
Test name
Test status
Simulation time 31928989031 ps
CPU time 154.19 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:36:04 PM PDT 24
Peak memory 268440 kb
Host smart-6b9b7482-7951-4964-aff0-78e896aec5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453440501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.453440501
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1535417126
Short name T546
Test name
Test status
Simulation time 2583750496 ps
CPU time 16.65 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:33:46 PM PDT 24
Peak memory 219548 kb
Host smart-3c35807d-88c6-4c26-afbd-92ee1a7e0cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535417126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1535417126
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.4068691565
Short name T944
Test name
Test status
Simulation time 23784366512 ps
CPU time 325.75 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:38:55 PM PDT 24
Peak memory 273800 kb
Host smart-401231aa-b798-429f-8f42-baa6b66e063a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068691565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.4068691565
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3326869402
Short name T264
Test name
Test status
Simulation time 1497883431 ps
CPU time 26.24 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:33:55 PM PDT 24
Peak memory 232640 kb
Host smart-9d79cb3d-2f58-4419-9bd7-46378581fea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326869402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3326869402
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1250672292
Short name T844
Test name
Test status
Simulation time 20737033600 ps
CPU time 74.72 seconds
Started Jun 28 06:33:30 PM PDT 24
Finished Jun 28 06:34:46 PM PDT 24
Peak memory 255988 kb
Host smart-9edca82d-741f-4b71-9135-74ec78b2c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250672292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1250672292
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3548545368
Short name T338
Test name
Test status
Simulation time 217581417 ps
CPU time 2.93 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:33:31 PM PDT 24
Peak memory 232612 kb
Host smart-7fb6e211-44f7-409c-a55b-e694a1967eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548545368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3548545368
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.284298520
Short name T199
Test name
Test status
Simulation time 2288940238 ps
CPU time 12.93 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:33:42 PM PDT 24
Peak memory 224488 kb
Host smart-ea22e533-49ae-491c-a2f2-97962a6b5bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284298520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.284298520
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3304012877
Short name T481
Test name
Test status
Simulation time 1860815350 ps
CPU time 3.17 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:33:31 PM PDT 24
Peak memory 232580 kb
Host smart-f7fa0f9b-28f3-4db9-979d-1cf9302a5707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304012877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3304012877
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1847889101
Short name T505
Test name
Test status
Simulation time 6013509415 ps
CPU time 13.38 seconds
Started Jun 28 06:33:28 PM PDT 24
Finished Jun 28 06:33:44 PM PDT 24
Peak memory 240564 kb
Host smart-8793e109-7edc-47f8-a64c-4d1e4f8165d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847889101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1847889101
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2910374147
Short name T542
Test name
Test status
Simulation time 438154198 ps
CPU time 6.27 seconds
Started Jun 28 06:33:28 PM PDT 24
Finished Jun 28 06:33:37 PM PDT 24
Peak memory 223040 kb
Host smart-72f45ee3-2124-4030-ab18-da959a1221b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2910374147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2910374147
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3469838084
Short name T766
Test name
Test status
Simulation time 78789134993 ps
CPU time 235.41 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:37:25 PM PDT 24
Peak memory 267336 kb
Host smart-f18b8a04-dfa3-4c39-b4b4-2d19c5b76f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469838084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3469838084
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1143905370
Short name T286
Test name
Test status
Simulation time 1673344325 ps
CPU time 8.86 seconds
Started Jun 28 06:33:26 PM PDT 24
Finished Jun 28 06:33:37 PM PDT 24
Peak memory 216224 kb
Host smart-1dccd652-a3a6-4c74-8002-8d77a6b61d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143905370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1143905370
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2014879960
Short name T540
Test name
Test status
Simulation time 3405629904 ps
CPU time 5.56 seconds
Started Jun 28 06:33:26 PM PDT 24
Finished Jun 28 06:33:32 PM PDT 24
Peak memory 216300 kb
Host smart-71854d80-8f47-4b70-a643-b0a8f5c90e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014879960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2014879960
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.65748214
Short name T332
Test name
Test status
Simulation time 212745015 ps
CPU time 2.61 seconds
Started Jun 28 06:33:28 PM PDT 24
Finished Jun 28 06:33:33 PM PDT 24
Peak memory 216148 kb
Host smart-bd3485b0-a425-4bf4-ae50-ffc7c07ddc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65748214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.65748214
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.185622838
Short name T704
Test name
Test status
Simulation time 21180374 ps
CPU time 0.81 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:33:30 PM PDT 24
Peak memory 205888 kb
Host smart-c450689b-f460-4faf-a2b1-ddeba9409f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185622838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.185622838
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4174000615
Short name T1011
Test name
Test status
Simulation time 120569023 ps
CPU time 2.34 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:33:32 PM PDT 24
Peak memory 224428 kb
Host smart-b7cc5f06-46a8-4d95-87a1-0abdd2b646f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174000615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4174000615
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1143047884
Short name T716
Test name
Test status
Simulation time 15379534 ps
CPU time 0.71 seconds
Started Jun 28 06:33:38 PM PDT 24
Finished Jun 28 06:33:40 PM PDT 24
Peak memory 205380 kb
Host smart-8abf4551-65c7-4c9f-8b17-e65a0aa25c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143047884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1143047884
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4194180744
Short name T208
Test name
Test status
Simulation time 147348773 ps
CPU time 2.58 seconds
Started Jun 28 06:33:38 PM PDT 24
Finished Jun 28 06:33:42 PM PDT 24
Peak memory 232640 kb
Host smart-17d11727-5fe1-413b-b1e2-73f04723e1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194180744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4194180744
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.894974488
Short name T667
Test name
Test status
Simulation time 120889779 ps
CPU time 0.77 seconds
Started Jun 28 06:33:28 PM PDT 24
Finished Jun 28 06:33:31 PM PDT 24
Peak memory 205520 kb
Host smart-dd416f2b-384f-42ba-b4be-db2212d67457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894974488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.894974488
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2937301506
Short name T950
Test name
Test status
Simulation time 50551441354 ps
CPU time 158.94 seconds
Started Jun 28 06:33:38 PM PDT 24
Finished Jun 28 06:36:19 PM PDT 24
Peak memory 264852 kb
Host smart-da830921-5f6a-41a0-a3c1-17f846c4a4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937301506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2937301506
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2796977226
Short name T536
Test name
Test status
Simulation time 625525364 ps
CPU time 4.49 seconds
Started Jun 28 06:33:39 PM PDT 24
Finished Jun 28 06:33:45 PM PDT 24
Peak memory 217416 kb
Host smart-48623b9c-884e-46c3-9649-693b6ce34c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796977226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2796977226
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2527595787
Short name T488
Test name
Test status
Simulation time 328230072 ps
CPU time 7.8 seconds
Started Jun 28 06:33:42 PM PDT 24
Finished Jun 28 06:33:50 PM PDT 24
Peak memory 224508 kb
Host smart-566df68f-a3b8-4e8b-9566-79ce15ad3e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527595787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2527595787
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.4253534855
Short name T671
Test name
Test status
Simulation time 1871058526 ps
CPU time 8.9 seconds
Started Jun 28 06:33:39 PM PDT 24
Finished Jun 28 06:33:50 PM PDT 24
Peak memory 236944 kb
Host smart-aaaccc20-3679-4153-bba5-eac5cc3879ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253534855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.4253534855
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1911708921
Short name T293
Test name
Test status
Simulation time 107334900 ps
CPU time 2.33 seconds
Started Jun 28 06:33:39 PM PDT 24
Finished Jun 28 06:33:42 PM PDT 24
Peak memory 218704 kb
Host smart-501a0ba6-bc10-4acb-8552-d76622d6fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911708921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1911708921
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1065303274
Short name T928
Test name
Test status
Simulation time 8435714910 ps
CPU time 45.88 seconds
Started Jun 28 06:33:38 PM PDT 24
Finished Jun 28 06:34:25 PM PDT 24
Peak memory 240848 kb
Host smart-413977ad-c8b2-4e06-96b7-5b1b34598557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065303274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1065303274
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3628712087
Short name T783
Test name
Test status
Simulation time 1999605318 ps
CPU time 5.8 seconds
Started Jun 28 06:33:38 PM PDT 24
Finished Jun 28 06:33:45 PM PDT 24
Peak memory 232592 kb
Host smart-cbcec50a-8cef-4820-af52-e8b694749e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628712087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3628712087
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3814914559
Short name T1024
Test name
Test status
Simulation time 156830402 ps
CPU time 2.83 seconds
Started Jun 28 06:33:41 PM PDT 24
Finished Jun 28 06:33:45 PM PDT 24
Peak memory 232636 kb
Host smart-fbda2c65-cd45-4e35-837c-daa45e0aad6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814914559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3814914559
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.995754072
Short name T328
Test name
Test status
Simulation time 827420049 ps
CPU time 12.64 seconds
Started Jun 28 06:33:39 PM PDT 24
Finished Jun 28 06:33:53 PM PDT 24
Peak memory 218984 kb
Host smart-549e31de-31f5-43c8-b4ac-658012180ab0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=995754072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.995754072
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2185437706
Short name T881
Test name
Test status
Simulation time 22860879410 ps
CPU time 199.76 seconds
Started Jun 28 06:33:39 PM PDT 24
Finished Jun 28 06:37:00 PM PDT 24
Peak memory 232888 kb
Host smart-42e02200-cee4-481d-a22c-91501994f5dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185437706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2185437706
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2680970115
Short name T282
Test name
Test status
Simulation time 224844757 ps
CPU time 2.37 seconds
Started Jun 28 06:33:28 PM PDT 24
Finished Jun 28 06:33:33 PM PDT 24
Peak memory 216168 kb
Host smart-118e578e-3304-4931-8d8f-de0e84ba790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680970115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2680970115
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3070991067
Short name T715
Test name
Test status
Simulation time 968618285 ps
CPU time 5.99 seconds
Started Jun 28 06:33:28 PM PDT 24
Finished Jun 28 06:33:37 PM PDT 24
Peak memory 216200 kb
Host smart-1b46f787-4156-4578-8315-27c05f233004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070991067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3070991067
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4026916195
Short name T800
Test name
Test status
Simulation time 70407803 ps
CPU time 0.91 seconds
Started Jun 28 06:33:40 PM PDT 24
Finished Jun 28 06:33:42 PM PDT 24
Peak memory 206900 kb
Host smart-58d84707-4536-4b17-bab6-221c372543c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026916195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4026916195
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1395420299
Short name T330
Test name
Test status
Simulation time 61015124 ps
CPU time 0.82 seconds
Started Jun 28 06:33:27 PM PDT 24
Finished Jun 28 06:33:29 PM PDT 24
Peak memory 205884 kb
Host smart-58b361e8-10f1-4b9d-9951-ddd1ad2c1b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395420299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1395420299
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.253920581
Short name T582
Test name
Test status
Simulation time 8788053494 ps
CPU time 13.83 seconds
Started Jun 28 06:33:39 PM PDT 24
Finished Jun 28 06:33:54 PM PDT 24
Peak memory 248984 kb
Host smart-6e0481f2-6856-48c4-99c8-5a3b71b6d230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253920581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.253920581
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2187905316
Short name T902
Test name
Test status
Simulation time 139087254 ps
CPU time 0.73 seconds
Started Jun 28 06:33:51 PM PDT 24
Finished Jun 28 06:33:53 PM PDT 24
Peak memory 204840 kb
Host smart-d2887ec5-87c4-4a9a-aa75-e696eb60bfe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187905316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2187905316
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2281354640
Short name T625
Test name
Test status
Simulation time 180936340 ps
CPU time 2.63 seconds
Started Jun 28 06:33:51 PM PDT 24
Finished Jun 28 06:33:55 PM PDT 24
Peak memory 224448 kb
Host smart-6c8eb81a-bfae-47e1-98f0-babe5338016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281354640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2281354640
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1136759679
Short name T368
Test name
Test status
Simulation time 34021792 ps
CPU time 0.76 seconds
Started Jun 28 06:33:39 PM PDT 24
Finished Jun 28 06:33:41 PM PDT 24
Peak memory 206844 kb
Host smart-933a76e2-da64-4052-aa69-3ad2250edd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136759679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1136759679
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1518072636
Short name T372
Test name
Test status
Simulation time 512942204 ps
CPU time 8.89 seconds
Started Jun 28 06:33:51 PM PDT 24
Finished Jun 28 06:34:02 PM PDT 24
Peak memory 240820 kb
Host smart-bbc03bc1-cf4e-43a5-8440-d98a746480df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518072636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1518072636
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1797644521
Short name T159
Test name
Test status
Simulation time 11622300678 ps
CPU time 96.53 seconds
Started Jun 28 06:33:50 PM PDT 24
Finished Jun 28 06:35:28 PM PDT 24
Peak memory 249240 kb
Host smart-e1f269a9-d4cf-4ac6-b5e5-3ef65f3e09f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797644521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1797644521
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2565339935
Short name T377
Test name
Test status
Simulation time 7321098316 ps
CPU time 124.56 seconds
Started Jun 28 06:33:50 PM PDT 24
Finished Jun 28 06:35:56 PM PDT 24
Peak memory 256184 kb
Host smart-94d870de-78c0-415f-b07e-cb9590eb1eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565339935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2565339935
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.209831497
Short name T268
Test name
Test status
Simulation time 10716725673 ps
CPU time 33.54 seconds
Started Jun 28 06:33:49 PM PDT 24
Finished Jun 28 06:34:24 PM PDT 24
Peak memory 240980 kb
Host smart-e0647ecb-22c7-497e-b1f3-f9650fe92328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209831497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.209831497
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2863938735
Short name T555
Test name
Test status
Simulation time 11196454456 ps
CPU time 35.94 seconds
Started Jun 28 06:33:49 PM PDT 24
Finished Jun 28 06:34:27 PM PDT 24
Peak memory 239756 kb
Host smart-d762046c-abd7-450b-80f2-9049a79ffaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863938735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2863938735
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1000223858
Short name T207
Test name
Test status
Simulation time 1783133783 ps
CPU time 4.71 seconds
Started Jun 28 06:33:50 PM PDT 24
Finished Jun 28 06:33:56 PM PDT 24
Peak memory 224392 kb
Host smart-92949a01-a268-4c96-a8a4-dbe1634e7965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000223858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1000223858
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3180383405
Short name T223
Test name
Test status
Simulation time 16132364696 ps
CPU time 14.81 seconds
Started Jun 28 06:33:50 PM PDT 24
Finished Jun 28 06:34:07 PM PDT 24
Peak memory 224548 kb
Host smart-e47a397b-3a5c-4a88-9b0c-49c141a75b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180383405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3180383405
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.952755554
Short name T770
Test name
Test status
Simulation time 1737870734 ps
CPU time 8.04 seconds
Started Jun 28 06:33:49 PM PDT 24
Finished Jun 28 06:33:58 PM PDT 24
Peak memory 232640 kb
Host smart-e206ff9e-3068-4c2d-a48e-519db387eede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952755554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.952755554
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2695142850
Short name T75
Test name
Test status
Simulation time 962863041 ps
CPU time 5.78 seconds
Started Jun 28 06:33:49 PM PDT 24
Finished Jun 28 06:33:56 PM PDT 24
Peak memory 232632 kb
Host smart-75c4328a-69bf-4a88-bd01-190dccbc6415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695142850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2695142850
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1221875582
Short name T464
Test name
Test status
Simulation time 1377247819 ps
CPU time 14.67 seconds
Started Jun 28 06:33:53 PM PDT 24
Finished Jun 28 06:34:09 PM PDT 24
Peak memory 220652 kb
Host smart-e50e1d70-cf0a-4f67-82eb-a9e2c4581ea4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1221875582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1221875582
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2604121244
Short name T855
Test name
Test status
Simulation time 94532787113 ps
CPU time 202.26 seconds
Started Jun 28 06:33:51 PM PDT 24
Finished Jun 28 06:37:15 PM PDT 24
Peak memory 261388 kb
Host smart-3c3e7957-301f-4ea1-add3-dd420b59e39b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604121244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2604121244
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.626433265
Short name T279
Test name
Test status
Simulation time 1755918910 ps
CPU time 25.93 seconds
Started Jun 28 06:33:39 PM PDT 24
Finished Jun 28 06:34:06 PM PDT 24
Peak memory 216268 kb
Host smart-ffd25e89-97d1-4d12-97fb-4e5c93fe61d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626433265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.626433265
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2033683034
Short name T539
Test name
Test status
Simulation time 1024064473 ps
CPU time 1.89 seconds
Started Jun 28 06:33:38 PM PDT 24
Finished Jun 28 06:33:41 PM PDT 24
Peak memory 206952 kb
Host smart-1fcb9e00-420e-4d8a-9c29-47f961e12443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033683034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2033683034
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.10111125
Short name T559
Test name
Test status
Simulation time 539357882 ps
CPU time 5.65 seconds
Started Jun 28 06:33:39 PM PDT 24
Finished Jun 28 06:33:46 PM PDT 24
Peak memory 216204 kb
Host smart-8b433ca7-67c7-48be-9b31-234af2b88e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10111125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.10111125
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.244962244
Short name T919
Test name
Test status
Simulation time 87416141 ps
CPU time 0.87 seconds
Started Jun 28 06:33:38 PM PDT 24
Finished Jun 28 06:33:40 PM PDT 24
Peak memory 205892 kb
Host smart-537d8c9b-c991-420f-bcfd-caa04c6c3991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244962244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.244962244
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2568347692
Short name T403
Test name
Test status
Simulation time 1323529718 ps
CPU time 7 seconds
Started Jun 28 06:33:51 PM PDT 24
Finished Jun 28 06:33:59 PM PDT 24
Peak memory 236172 kb
Host smart-c4dcdb2d-2f81-44b1-b758-430a4bf918b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568347692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2568347692
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1733627168
Short name T537
Test name
Test status
Simulation time 48753608 ps
CPU time 0.8 seconds
Started Jun 28 06:34:01 PM PDT 24
Finished Jun 28 06:34:04 PM PDT 24
Peak memory 204836 kb
Host smart-ebb12b67-8464-483b-82d4-6dc431ff68cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733627168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1733627168
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1191950326
Short name T821
Test name
Test status
Simulation time 162452314 ps
CPU time 2.96 seconds
Started Jun 28 06:33:49 PM PDT 24
Finished Jun 28 06:33:54 PM PDT 24
Peak memory 232668 kb
Host smart-8f544eb0-8581-4c5a-9647-e695029e87bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191950326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1191950326
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2547826099
Short name T581
Test name
Test status
Simulation time 45355285 ps
CPU time 0.77 seconds
Started Jun 28 06:33:50 PM PDT 24
Finished Jun 28 06:33:53 PM PDT 24
Peak memory 206544 kb
Host smart-5a6c24a0-5e31-4635-b888-b295fdb93efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547826099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2547826099
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2612499350
Short name T1002
Test name
Test status
Simulation time 8570433862 ps
CPU time 74.44 seconds
Started Jun 28 06:34:01 PM PDT 24
Finished Jun 28 06:35:18 PM PDT 24
Peak memory 239452 kb
Host smart-9e57a2ba-337b-4799-a870-58bfae9c562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612499350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2612499350
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1875889965
Short name T10
Test name
Test status
Simulation time 126909691807 ps
CPU time 94 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:35:37 PM PDT 24
Peak memory 257060 kb
Host smart-88970bf5-4ee2-41e4-bd8b-aec6de512ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875889965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1875889965
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4099011432
Short name T284
Test name
Test status
Simulation time 4208811859 ps
CPU time 96.32 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:35:39 PM PDT 24
Peak memory 255764 kb
Host smart-00492410-1542-4081-bbba-10ad2b8126fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099011432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4099011432
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3192336894
Short name T645
Test name
Test status
Simulation time 2724218029 ps
CPU time 8.23 seconds
Started Jun 28 06:33:50 PM PDT 24
Finished Jun 28 06:34:00 PM PDT 24
Peak memory 239880 kb
Host smart-db22c743-b64d-459f-915c-5703154d8086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192336894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3192336894
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.134926157
Short name T190
Test name
Test status
Simulation time 6169125160 ps
CPU time 49.96 seconds
Started Jun 28 06:33:54 PM PDT 24
Finished Jun 28 06:34:45 PM PDT 24
Peak memory 238792 kb
Host smart-b58119af-1c01-4437-af95-db371800896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134926157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.134926157
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4271484739
Short name T364
Test name
Test status
Simulation time 4109424112 ps
CPU time 9.68 seconds
Started Jun 28 06:33:51 PM PDT 24
Finished Jun 28 06:34:02 PM PDT 24
Peak memory 224592 kb
Host smart-3455ec2b-aa68-4d58-8686-bd66d6565cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271484739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4271484739
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2123418925
Short name T527
Test name
Test status
Simulation time 9821433064 ps
CPU time 84.44 seconds
Started Jun 28 06:33:49 PM PDT 24
Finished Jun 28 06:35:14 PM PDT 24
Peak memory 240980 kb
Host smart-b05e8b56-6038-4834-a39d-a7546690f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123418925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2123418925
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1836229500
Short name T511
Test name
Test status
Simulation time 2996431387 ps
CPU time 4.36 seconds
Started Jun 28 06:33:51 PM PDT 24
Finished Jun 28 06:33:57 PM PDT 24
Peak memory 232760 kb
Host smart-60f9edab-2983-4adf-9ff4-aee20d086efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836229500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1836229500
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.294367846
Short name T180
Test name
Test status
Simulation time 6423532108 ps
CPU time 11.67 seconds
Started Jun 28 06:33:49 PM PDT 24
Finished Jun 28 06:34:02 PM PDT 24
Peak memory 239452 kb
Host smart-657e1f60-d638-422f-934f-7c92ae57896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294367846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.294367846
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3847616876
Short name T948
Test name
Test status
Simulation time 3579517847 ps
CPU time 5.94 seconds
Started Jun 28 06:33:52 PM PDT 24
Finished Jun 28 06:33:59 PM PDT 24
Peak memory 222740 kb
Host smart-47ef7d67-14c2-4ac8-b8f4-c9a3ec610bd6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3847616876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3847616876
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3629291056
Short name T832
Test name
Test status
Simulation time 765786263 ps
CPU time 5.26 seconds
Started Jun 28 06:33:50 PM PDT 24
Finished Jun 28 06:33:57 PM PDT 24
Peak memory 216164 kb
Host smart-56d68e6a-9cfa-4366-b13f-70fb0959a5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629291056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3629291056
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3149359966
Short name T586
Test name
Test status
Simulation time 1134750810 ps
CPU time 3.51 seconds
Started Jun 28 06:33:50 PM PDT 24
Finished Jun 28 06:33:55 PM PDT 24
Peak memory 216152 kb
Host smart-8e0ba1ee-8373-4218-b95c-38b64072594f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149359966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3149359966
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3541650282
Short name T603
Test name
Test status
Simulation time 123906830 ps
CPU time 2.03 seconds
Started Jun 28 06:33:50 PM PDT 24
Finished Jun 28 06:33:54 PM PDT 24
Peak memory 216116 kb
Host smart-26e2c2a5-4adb-4ea3-9908-adb9777a859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541650282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3541650282
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.234880472
Short name T743
Test name
Test status
Simulation time 65326885 ps
CPU time 0.87 seconds
Started Jun 28 06:33:52 PM PDT 24
Finished Jun 28 06:33:55 PM PDT 24
Peak memory 205880 kb
Host smart-0dbf22f8-2a30-408e-b259-b8978064f3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234880472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.234880472
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3233931042
Short name T475
Test name
Test status
Simulation time 25324396180 ps
CPU time 18.55 seconds
Started Jun 28 06:33:50 PM PDT 24
Finished Jun 28 06:34:10 PM PDT 24
Peak memory 232776 kb
Host smart-f593a4e9-14bf-4bef-b94e-2fec759e362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233931042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3233931042
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3479221720
Short name T46
Test name
Test status
Simulation time 99661031 ps
CPU time 0.75 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:34:03 PM PDT 24
Peak memory 204816 kb
Host smart-4d1cef18-2555-4155-b6bd-e3261f1b063a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479221720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3479221720
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2340508966
Short name T210
Test name
Test status
Simulation time 723189914 ps
CPU time 7.77 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:34:10 PM PDT 24
Peak memory 232648 kb
Host smart-8d74b296-0746-4083-89a5-eedd47dee47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340508966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2340508966
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2511759818
Short name T1015
Test name
Test status
Simulation time 60508568 ps
CPU time 0.8 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:34:02 PM PDT 24
Peak memory 206540 kb
Host smart-2d682cc6-a1df-41c1-8cf4-57ec41bfad01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511759818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2511759818
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1639866769
Short name T529
Test name
Test status
Simulation time 89679510973 ps
CPU time 176.38 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:36:59 PM PDT 24
Peak memory 257364 kb
Host smart-8dd6adcf-3e8f-40c6-95a4-b04be3b58419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639866769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1639866769
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.234072423
Short name T261
Test name
Test status
Simulation time 16093720227 ps
CPU time 68.62 seconds
Started Jun 28 06:34:03 PM PDT 24
Finished Jun 28 06:35:13 PM PDT 24
Peak memory 261048 kb
Host smart-32eccdc4-aca3-4318-b222-67eb79ecd2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234072423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.234072423
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3188909976
Short name T120
Test name
Test status
Simulation time 90261091329 ps
CPU time 251.31 seconds
Started Jun 28 06:34:01 PM PDT 24
Finished Jun 28 06:38:15 PM PDT 24
Peak memory 257392 kb
Host smart-e062a2a7-e76f-4af5-8973-3b6dc32c7ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188909976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3188909976
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.717556794
Short name T680
Test name
Test status
Simulation time 1957544080 ps
CPU time 10.64 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:34:13 PM PDT 24
Peak memory 232632 kb
Host smart-3cdcda37-899d-40a9-8365-ddc398e23377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717556794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.717556794
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.27687111
Short name T921
Test name
Test status
Simulation time 22991074556 ps
CPU time 172.92 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:36:56 PM PDT 24
Peak memory 253040 kb
Host smart-88f2ab3c-cc9f-45d6-98af-5ec452f26ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27687111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.27687111
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.53448260
Short name T221
Test name
Test status
Simulation time 2858149444 ps
CPU time 10.76 seconds
Started Jun 28 06:34:04 PM PDT 24
Finished Jun 28 06:34:16 PM PDT 24
Peak memory 224548 kb
Host smart-b3e42c26-c5f3-49c2-b264-a7940b284e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53448260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.53448260
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3150166834
Short name T730
Test name
Test status
Simulation time 3796054021 ps
CPU time 12.46 seconds
Started Jun 28 06:34:01 PM PDT 24
Finished Jun 28 06:34:16 PM PDT 24
Peak memory 224512 kb
Host smart-509bf4b8-82ed-4a42-8420-6beaa799f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150166834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3150166834
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.395968423
Short name T232
Test name
Test status
Simulation time 1532230365 ps
CPU time 5.28 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:34:08 PM PDT 24
Peak memory 232664 kb
Host smart-9bb215b7-0f21-4062-aaca-d69838a92519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395968423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.395968423
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1300310485
Short name T772
Test name
Test status
Simulation time 14339330597 ps
CPU time 11.36 seconds
Started Jun 28 06:34:04 PM PDT 24
Finished Jun 28 06:34:17 PM PDT 24
Peak memory 224560 kb
Host smart-d9c7d906-5908-4004-b84a-8ac42037927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300310485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1300310485
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1610673799
Short name T611
Test name
Test status
Simulation time 797323476 ps
CPU time 12.18 seconds
Started Jun 28 06:34:03 PM PDT 24
Finished Jun 28 06:34:17 PM PDT 24
Peak memory 218832 kb
Host smart-ca3d7b3a-12e7-4684-a504-9777d3f7c7ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1610673799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1610673799
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3920321148
Short name T760
Test name
Test status
Simulation time 50956714 ps
CPU time 1.03 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:34:04 PM PDT 24
Peak memory 206864 kb
Host smart-5d7a8e33-71ba-44bf-bec2-28a53a9d334e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920321148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3920321148
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1162348696
Short name T487
Test name
Test status
Simulation time 8431420591 ps
CPU time 21.43 seconds
Started Jun 28 06:34:01 PM PDT 24
Finished Jun 28 06:34:25 PM PDT 24
Peak memory 216348 kb
Host smart-fe3d83a2-b03a-43a7-93d4-13343192575d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162348696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1162348696
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3442668604
Short name T703
Test name
Test status
Simulation time 12928391 ps
CPU time 0.72 seconds
Started Jun 28 06:34:02 PM PDT 24
Finished Jun 28 06:34:05 PM PDT 24
Peak memory 205652 kb
Host smart-1e5521e2-f28e-4b83-af7b-e40e53dd2444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442668604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3442668604
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3427781254
Short name T777
Test name
Test status
Simulation time 20667590 ps
CPU time 0.67 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:34:02 PM PDT 24
Peak memory 205556 kb
Host smart-3ff45b88-4a40-427c-a8a6-21a0b26ae7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427781254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3427781254
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2005507978
Short name T670
Test name
Test status
Simulation time 38103648 ps
CPU time 0.84 seconds
Started Jun 28 06:34:03 PM PDT 24
Finished Jun 28 06:34:06 PM PDT 24
Peak memory 205860 kb
Host smart-2002ba1d-8854-46c4-9d8d-82779c6cb10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005507978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2005507978
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.914505672
Short name T220
Test name
Test status
Simulation time 129072688 ps
CPU time 3.12 seconds
Started Jun 28 06:34:03 PM PDT 24
Finished Jun 28 06:34:08 PM PDT 24
Peak memory 224464 kb
Host smart-d15f6bfc-b133-4b02-9b7b-97b36b6521e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914505672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.914505672
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.55542098
Short name T851
Test name
Test status
Simulation time 175452789 ps
CPU time 0.71 seconds
Started Jun 28 06:34:14 PM PDT 24
Finished Jun 28 06:34:16 PM PDT 24
Peak memory 204840 kb
Host smart-0f468dd9-c6ba-4356-995b-6b5634a53743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55542098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.55542098
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.264365807
Short name T545
Test name
Test status
Simulation time 2649751358 ps
CPU time 13.83 seconds
Started Jun 28 06:34:13 PM PDT 24
Finished Jun 28 06:34:28 PM PDT 24
Peak memory 232668 kb
Host smart-aef5205d-fe1b-42d4-ae59-3d257dd2f79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264365807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.264365807
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1878051251
Short name T307
Test name
Test status
Simulation time 37677908 ps
CPU time 0.83 seconds
Started Jun 28 06:34:01 PM PDT 24
Finished Jun 28 06:34:04 PM PDT 24
Peak memory 206580 kb
Host smart-e5d8cafb-74eb-446e-9f7a-e0ac9562ca11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878051251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1878051251
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2903812501
Short name T614
Test name
Test status
Simulation time 1091390391 ps
CPU time 24.2 seconds
Started Jun 28 06:34:12 PM PDT 24
Finished Jun 28 06:34:38 PM PDT 24
Peak memory 252484 kb
Host smart-de2dfee4-463b-46f9-b250-6139aa1d2650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903812501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2903812501
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.609743452
Short name T719
Test name
Test status
Simulation time 1811474671 ps
CPU time 41.72 seconds
Started Jun 28 06:34:22 PM PDT 24
Finished Jun 28 06:35:05 PM PDT 24
Peak memory 249212 kb
Host smart-a102f747-4699-4715-9fd2-700b04ed26e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609743452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.609743452
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2157098775
Short name T59
Test name
Test status
Simulation time 36171013741 ps
CPU time 118.82 seconds
Started Jun 28 06:34:13 PM PDT 24
Finished Jun 28 06:36:14 PM PDT 24
Peak memory 253180 kb
Host smart-4d167405-487e-4953-ac00-72b91612241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157098775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2157098775
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2035879311
Short name T378
Test name
Test status
Simulation time 127678766 ps
CPU time 3.48 seconds
Started Jun 28 06:34:23 PM PDT 24
Finished Jun 28 06:34:27 PM PDT 24
Peak memory 224468 kb
Host smart-ee899fc4-bbb0-41a7-b285-847971f1bb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035879311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2035879311
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4225430542
Short name T541
Test name
Test status
Simulation time 2283267024 ps
CPU time 30.29 seconds
Started Jun 28 06:34:21 PM PDT 24
Finished Jun 28 06:34:52 PM PDT 24
Peak memory 239284 kb
Host smart-7755da8e-01d4-4825-a100-22c5551741e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225430542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4225430542
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1819048236
Short name T956
Test name
Test status
Simulation time 3217471386 ps
CPU time 8.78 seconds
Started Jun 28 06:34:14 PM PDT 24
Finished Jun 28 06:34:24 PM PDT 24
Peak memory 224508 kb
Host smart-0fead154-6447-4b90-8d1a-d1bf23b65397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819048236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1819048236
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3033339671
Short name T756
Test name
Test status
Simulation time 947028228 ps
CPU time 5.08 seconds
Started Jun 28 06:34:23 PM PDT 24
Finished Jun 28 06:34:29 PM PDT 24
Peak memory 224432 kb
Host smart-b993219e-0313-4787-896a-f55bc88189f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033339671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3033339671
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3115378550
Short name T518
Test name
Test status
Simulation time 5510930423 ps
CPU time 16.01 seconds
Started Jun 28 06:34:13 PM PDT 24
Finished Jun 28 06:34:31 PM PDT 24
Peak memory 232752 kb
Host smart-d6c937b1-4b8c-4d34-8027-b5a9a5de7a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115378550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3115378550
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.327006959
Short name T879
Test name
Test status
Simulation time 824159392 ps
CPU time 7.28 seconds
Started Jun 28 06:34:21 PM PDT 24
Finished Jun 28 06:34:29 PM PDT 24
Peak memory 232644 kb
Host smart-12fd4ec3-e228-4741-a423-e0fcd22f828e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327006959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.327006959
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3178430905
Short name T831
Test name
Test status
Simulation time 1614287974 ps
CPU time 10.68 seconds
Started Jun 28 06:34:15 PM PDT 24
Finished Jun 28 06:34:27 PM PDT 24
Peak memory 222248 kb
Host smart-02b04055-5b77-4575-aee0-c7c27ff263b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3178430905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3178430905
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.414034933
Short name T229
Test name
Test status
Simulation time 24586731885 ps
CPU time 332.06 seconds
Started Jun 28 06:34:13 PM PDT 24
Finished Jun 28 06:39:46 PM PDT 24
Peak memory 278980 kb
Host smart-dddb3456-f9a1-488b-9ec4-5f765828f78a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414034933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.414034933
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.81185290
Short name T857
Test name
Test status
Simulation time 2027872462 ps
CPU time 13.09 seconds
Started Jun 28 06:33:59 PM PDT 24
Finished Jun 28 06:34:13 PM PDT 24
Peak memory 216192 kb
Host smart-50679644-6910-472d-acb6-37f8555d0914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81185290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.81185290
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3834944699
Short name T626
Test name
Test status
Simulation time 6448627889 ps
CPU time 12.2 seconds
Started Jun 28 06:34:00 PM PDT 24
Finished Jun 28 06:34:14 PM PDT 24
Peak memory 216280 kb
Host smart-50048c08-c33a-45c0-9f9c-3f07d5760d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834944699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3834944699
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1013503405
Short name T453
Test name
Test status
Simulation time 85609783 ps
CPU time 0.87 seconds
Started Jun 28 06:34:13 PM PDT 24
Finished Jun 28 06:34:15 PM PDT 24
Peak memory 206908 kb
Host smart-3938ccd3-ea6f-4505-a506-b7cc2c7d314d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013503405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1013503405
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3106141055
Short name T369
Test name
Test status
Simulation time 103928868 ps
CPU time 0.81 seconds
Started Jun 28 06:34:01 PM PDT 24
Finished Jun 28 06:34:04 PM PDT 24
Peak memory 205888 kb
Host smart-bc2c3add-7285-475f-80a1-ba924e298691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106141055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3106141055
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1793640969
Short name T791
Test name
Test status
Simulation time 894559410 ps
CPU time 8.3 seconds
Started Jun 28 06:34:14 PM PDT 24
Finished Jun 28 06:34:24 PM PDT 24
Peak memory 240624 kb
Host smart-b5d0a857-f1ab-4b76-91e5-8ce0028ffdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793640969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1793640969
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1878559008
Short name T55
Test name
Test status
Simulation time 11437861 ps
CPU time 0.79 seconds
Started Jun 28 06:34:31 PM PDT 24
Finished Jun 28 06:34:33 PM PDT 24
Peak memory 205416 kb
Host smart-e8b8a6e7-c241-4363-90b0-9000039ad550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878559008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1878559008
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2832270020
Short name T938
Test name
Test status
Simulation time 923828212 ps
CPU time 3.61 seconds
Started Jun 28 06:34:35 PM PDT 24
Finished Jun 28 06:34:39 PM PDT 24
Peak memory 224472 kb
Host smart-d94ebe34-f0f3-490d-a033-8a7a2162ba72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832270020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2832270020
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3947449389
Short name T910
Test name
Test status
Simulation time 24244728 ps
CPU time 0.81 seconds
Started Jun 28 06:34:22 PM PDT 24
Finished Jun 28 06:34:24 PM PDT 24
Peak memory 205512 kb
Host smart-6daa9151-5a59-4ed6-a6ef-47b42bb0c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947449389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3947449389
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2491442450
Short name T753
Test name
Test status
Simulation time 1658070320 ps
CPU time 17.39 seconds
Started Jun 28 06:34:28 PM PDT 24
Finished Jun 28 06:34:48 PM PDT 24
Peak memory 235692 kb
Host smart-f0b759b4-5378-423a-98b4-125b929c523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491442450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2491442450
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4175274740
Short name T33
Test name
Test status
Simulation time 13504839004 ps
CPU time 101.56 seconds
Started Jun 28 06:34:28 PM PDT 24
Finished Jun 28 06:36:11 PM PDT 24
Peak memory 238728 kb
Host smart-13ab5458-372b-49fc-8264-f0fab4561b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175274740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4175274740
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2401984453
Short name T365
Test name
Test status
Simulation time 734775231 ps
CPU time 11.78 seconds
Started Jun 28 06:34:31 PM PDT 24
Finished Jun 28 06:34:44 PM PDT 24
Peak memory 224548 kb
Host smart-67997105-bce5-4848-9657-af8200d8f480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401984453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2401984453
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3817591375
Short name T276
Test name
Test status
Simulation time 1737152584 ps
CPU time 7.05 seconds
Started Jun 28 06:34:32 PM PDT 24
Finished Jun 28 06:34:40 PM PDT 24
Peak memory 240820 kb
Host smart-dccb5dfe-0c5a-451e-a992-62c8016f1a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817591375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3817591375
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1912500827
Short name T752
Test name
Test status
Simulation time 40832907891 ps
CPU time 141.13 seconds
Started Jun 28 06:34:31 PM PDT 24
Finished Jun 28 06:36:53 PM PDT 24
Peak memory 249144 kb
Host smart-c0c8c16a-ced3-4b00-9530-d35dfb02e6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912500827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1912500827
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4096991011
Short name T402
Test name
Test status
Simulation time 146702234 ps
CPU time 5.93 seconds
Started Jun 28 06:34:19 PM PDT 24
Finished Jun 28 06:34:25 PM PDT 24
Peak memory 232632 kb
Host smart-cb44d960-848a-497c-8b4f-046520fc02fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096991011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4096991011
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.486862282
Short name T859
Test name
Test status
Simulation time 3808356838 ps
CPU time 29.13 seconds
Started Jun 28 06:34:21 PM PDT 24
Finished Jun 28 06:34:51 PM PDT 24
Peak memory 240732 kb
Host smart-f24f3223-4532-4917-bb6b-57a04dcadb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486862282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.486862282
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.377029683
Short name T247
Test name
Test status
Simulation time 890398840 ps
CPU time 5.05 seconds
Started Jun 28 06:34:22 PM PDT 24
Finished Jun 28 06:34:28 PM PDT 24
Peak memory 224460 kb
Host smart-54122be2-4a17-4c5b-85e3-177a26ccbd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377029683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.377029683
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.958573110
Short name T218
Test name
Test status
Simulation time 3761092324 ps
CPU time 16.84 seconds
Started Jun 28 06:34:14 PM PDT 24
Finished Jun 28 06:34:32 PM PDT 24
Peak memory 232720 kb
Host smart-51971547-2708-4acf-98dd-e609646dc135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958573110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.958573110
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3789025007
Short name T802
Test name
Test status
Simulation time 1110579080 ps
CPU time 8.03 seconds
Started Jun 28 06:34:27 PM PDT 24
Finished Jun 28 06:34:37 PM PDT 24
Peak memory 218948 kb
Host smart-a0d49288-2872-4055-b971-f3354fb82e55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3789025007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3789025007
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.230355290
Short name T815
Test name
Test status
Simulation time 46020102062 ps
CPU time 460.46 seconds
Started Jun 28 06:34:28 PM PDT 24
Finished Jun 28 06:42:11 PM PDT 24
Peak memory 271600 kb
Host smart-0782826a-c94c-4bdd-9024-ae91679918dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230355290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.230355290
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3934370782
Short name T550
Test name
Test status
Simulation time 13103789229 ps
CPU time 22.4 seconds
Started Jun 28 06:34:13 PM PDT 24
Finished Jun 28 06:34:37 PM PDT 24
Peak memory 216432 kb
Host smart-9e8e5f46-6c51-40b9-82cc-6e0bb495c72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934370782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3934370782
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4189153395
Short name T613
Test name
Test status
Simulation time 428686087 ps
CPU time 3.41 seconds
Started Jun 28 06:34:21 PM PDT 24
Finished Jun 28 06:34:25 PM PDT 24
Peak memory 216200 kb
Host smart-1aca8b7d-b04b-46a8-bbfc-31f3c1d3cc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189153395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4189153395
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2122846298
Short name T629
Test name
Test status
Simulation time 63447556 ps
CPU time 1.97 seconds
Started Jun 28 06:34:21 PM PDT 24
Finished Jun 28 06:34:24 PM PDT 24
Peak memory 207936 kb
Host smart-3d4a2655-ba9f-4450-9fe1-2fb1f210b3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122846298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2122846298
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1538817823
Short name T717
Test name
Test status
Simulation time 60695151 ps
CPU time 0.92 seconds
Started Jun 28 06:34:21 PM PDT 24
Finished Jun 28 06:34:23 PM PDT 24
Peak memory 205852 kb
Host smart-933e8161-bb04-4ac9-bf71-f717bc8aef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538817823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1538817823
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1577290650
Short name T1006
Test name
Test status
Simulation time 357169077 ps
CPU time 3.43 seconds
Started Jun 28 06:34:28 PM PDT 24
Finished Jun 28 06:34:34 PM PDT 24
Peak memory 224424 kb
Host smart-43e689a1-07cd-4ed0-a498-f4cbff209b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577290650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1577290650
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.803453132
Short name T878
Test name
Test status
Simulation time 49292436 ps
CPU time 0.74 seconds
Started Jun 28 06:34:29 PM PDT 24
Finished Jun 28 06:34:32 PM PDT 24
Peak memory 205412 kb
Host smart-b04a5e6d-9b5d-4792-b6b7-128889a5bfe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803453132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.803453132
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.378962819
Short name T222
Test name
Test status
Simulation time 302515368 ps
CPU time 4.09 seconds
Started Jun 28 06:34:33 PM PDT 24
Finished Jun 28 06:34:38 PM PDT 24
Peak memory 232680 kb
Host smart-fb5ee9b2-7622-4d87-beca-d12beec90f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378962819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.378962819
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3249958085
Short name T833
Test name
Test status
Simulation time 40172145 ps
CPU time 0.77 seconds
Started Jun 28 06:34:31 PM PDT 24
Finished Jun 28 06:34:33 PM PDT 24
Peak memory 206860 kb
Host smart-730952ed-8f97-4459-8793-ec98f868d098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249958085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3249958085
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.635788230
Short name T260
Test name
Test status
Simulation time 5284032533 ps
CPU time 35.94 seconds
Started Jun 28 06:34:30 PM PDT 24
Finished Jun 28 06:35:08 PM PDT 24
Peak memory 250124 kb
Host smart-6ffc20ff-51c6-4e4b-9d31-d334b270ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635788230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.635788230
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.4130600138
Short name T785
Test name
Test status
Simulation time 16369143908 ps
CPU time 69.69 seconds
Started Jun 28 06:34:27 PM PDT 24
Finished Jun 28 06:35:38 PM PDT 24
Peak memory 249336 kb
Host smart-b6a75711-586a-4e7e-a4f0-eef2852a8451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130600138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.4130600138
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2981248874
Short name T275
Test name
Test status
Simulation time 799947929 ps
CPU time 9.4 seconds
Started Jun 28 06:34:30 PM PDT 24
Finished Jun 28 06:34:41 PM PDT 24
Peak memory 232712 kb
Host smart-850510b1-692a-4152-95bf-8d265d9c0274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981248874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2981248874
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1817586658
Short name T735
Test name
Test status
Simulation time 9165881968 ps
CPU time 63.69 seconds
Started Jun 28 06:34:30 PM PDT 24
Finished Jun 28 06:35:35 PM PDT 24
Peak memory 237428 kb
Host smart-e7f94557-4eb0-4b1e-8613-68a74570c16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817586658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1817586658
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2624366367
Short name T162
Test name
Test status
Simulation time 836379895 ps
CPU time 8.52 seconds
Started Jun 28 06:34:32 PM PDT 24
Finished Jun 28 06:34:41 PM PDT 24
Peak memory 224428 kb
Host smart-71a5fd7f-07c9-4fa8-9666-6ca2bcf54db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624366367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2624366367
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3961052029
Short name T547
Test name
Test status
Simulation time 556854550 ps
CPU time 6.78 seconds
Started Jun 28 06:34:34 PM PDT 24
Finished Jun 28 06:34:41 PM PDT 24
Peak memory 232640 kb
Host smart-4b7256db-2754-4ef7-8961-86604cf8056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961052029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3961052029
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2445464130
Short name T578
Test name
Test status
Simulation time 275808719 ps
CPU time 2.61 seconds
Started Jun 28 06:34:27 PM PDT 24
Finished Jun 28 06:34:30 PM PDT 24
Peak memory 224464 kb
Host smart-15e8fabc-252b-41ac-a20f-131ab0be6d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445464130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2445464130
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2910392143
Short name T310
Test name
Test status
Simulation time 406085771 ps
CPU time 2.17 seconds
Started Jun 28 06:34:29 PM PDT 24
Finished Jun 28 06:34:33 PM PDT 24
Peak memory 224428 kb
Host smart-45a9912c-fc27-4ffd-beeb-5e2c8be8552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910392143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2910392143
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.608972286
Short name T839
Test name
Test status
Simulation time 1743235515 ps
CPU time 10.89 seconds
Started Jun 28 06:34:29 PM PDT 24
Finished Jun 28 06:34:42 PM PDT 24
Peak memory 222092 kb
Host smart-df4285a4-470c-4945-badc-908ba1238f0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=608972286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.608972286
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.898374007
Short name T255
Test name
Test status
Simulation time 64273508551 ps
CPU time 471.11 seconds
Started Jun 28 06:34:29 PM PDT 24
Finished Jun 28 06:42:22 PM PDT 24
Peak memory 254260 kb
Host smart-9aace316-d3db-4588-955c-babc61cc2dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898374007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.898374007
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4185241703
Short name T794
Test name
Test status
Simulation time 12207412735 ps
CPU time 14.54 seconds
Started Jun 28 06:34:28 PM PDT 24
Finished Jun 28 06:34:45 PM PDT 24
Peak memory 216304 kb
Host smart-d7d24a81-331a-49af-a91a-21a17903b63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185241703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4185241703
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3329819353
Short name T846
Test name
Test status
Simulation time 5140200720 ps
CPU time 8.38 seconds
Started Jun 28 06:34:29 PM PDT 24
Finished Jun 28 06:34:39 PM PDT 24
Peak memory 216312 kb
Host smart-f3237fbe-f792-44d1-a86c-b3aa56b9b8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329819353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3329819353
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1962575514
Short name T526
Test name
Test status
Simulation time 396437135 ps
CPU time 4.45 seconds
Started Jun 28 06:34:35 PM PDT 24
Finished Jun 28 06:34:40 PM PDT 24
Peak memory 216184 kb
Host smart-b4671ad9-4c07-4ca1-b6ff-8811cc9f7d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962575514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1962575514
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2783412511
Short name T315
Test name
Test status
Simulation time 111969180 ps
CPU time 0.91 seconds
Started Jun 28 06:34:33 PM PDT 24
Finished Jun 28 06:34:35 PM PDT 24
Peak memory 205884 kb
Host smart-1c5b85c1-9c20-4842-9901-c92fd94986cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783412511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2783412511
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1233614084
Short name T892
Test name
Test status
Simulation time 265417706 ps
CPU time 4.64 seconds
Started Jun 28 06:34:34 PM PDT 24
Finished Jun 28 06:34:40 PM PDT 24
Peak memory 232672 kb
Host smart-cda014ec-1f43-4528-b45c-9c57d7a80bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233614084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1233614084
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3551308474
Short name T497
Test name
Test status
Simulation time 46818762 ps
CPU time 0.76 seconds
Started Jun 28 06:34:48 PM PDT 24
Finished Jun 28 06:34:51 PM PDT 24
Peak memory 204840 kb
Host smart-15612da2-6564-45d8-9f70-5d0a37b6e0d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551308474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3551308474
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4196522725
Short name T745
Test name
Test status
Simulation time 1822435941 ps
CPU time 15.27 seconds
Started Jun 28 06:34:29 PM PDT 24
Finished Jun 28 06:34:46 PM PDT 24
Peak memory 232676 kb
Host smart-a4a01be1-544d-4471-a6a1-b4cc989a4faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196522725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4196522725
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1574445227
Short name T602
Test name
Test status
Simulation time 18992031 ps
CPU time 0.78 seconds
Started Jun 28 06:34:31 PM PDT 24
Finished Jun 28 06:34:33 PM PDT 24
Peak memory 205484 kb
Host smart-037e08dc-ac09-4c13-b93e-439f20513e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574445227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1574445227
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.621749575
Short name T200
Test name
Test status
Simulation time 7282075679 ps
CPU time 36.55 seconds
Started Jun 28 06:34:32 PM PDT 24
Finished Jun 28 06:35:09 PM PDT 24
Peak memory 254032 kb
Host smart-24a99c12-f177-43d4-ba85-29c888c6ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621749575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.621749575
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1722150733
Short name T993
Test name
Test status
Simulation time 237864332552 ps
CPU time 203.62 seconds
Started Jun 28 06:34:27 PM PDT 24
Finished Jun 28 06:37:51 PM PDT 24
Peak memory 262768 kb
Host smart-2720c418-c1ec-4e28-82b3-394f21265843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722150733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1722150733
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4172212760
Short name T750
Test name
Test status
Simulation time 5709357482 ps
CPU time 42.82 seconds
Started Jun 28 06:34:44 PM PDT 24
Finished Jun 28 06:35:29 PM PDT 24
Peak memory 253432 kb
Host smart-003c8924-b92c-49a9-9f13-020ef2aff202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172212760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4172212760
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2109824502
Short name T129
Test name
Test status
Simulation time 5288793033 ps
CPU time 15.31 seconds
Started Jun 28 06:34:28 PM PDT 24
Finished Jun 28 06:34:45 PM PDT 24
Peak memory 232732 kb
Host smart-14d86fc6-cfa4-47fe-9d04-4b2b3c75313a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109824502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2109824502
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3444072657
Short name T676
Test name
Test status
Simulation time 4671748326 ps
CPU time 36.93 seconds
Started Jun 28 06:34:27 PM PDT 24
Finished Jun 28 06:35:05 PM PDT 24
Peak memory 241376 kb
Host smart-adbc232d-6420-4b20-b0bb-bfb9be30fe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444072657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3444072657
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3912831569
Short name T204
Test name
Test status
Simulation time 591203300 ps
CPU time 4.46 seconds
Started Jun 28 06:34:33 PM PDT 24
Finished Jun 28 06:34:39 PM PDT 24
Peak memory 232660 kb
Host smart-5536ea5e-939f-4dd3-a4e7-88554e7577df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912831569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3912831569
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.381930014
Short name T615
Test name
Test status
Simulation time 1318714534 ps
CPU time 13.54 seconds
Started Jun 28 06:34:29 PM PDT 24
Finished Jun 28 06:34:45 PM PDT 24
Peak memory 248628 kb
Host smart-b7cfff0f-42d7-41a8-90e1-c01afd9a877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381930014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.381930014
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3849293487
Short name T761
Test name
Test status
Simulation time 5328042082 ps
CPU time 9.85 seconds
Started Jun 28 06:34:28 PM PDT 24
Finished Jun 28 06:34:40 PM PDT 24
Peak memory 224588 kb
Host smart-e78a78a4-4e5f-4aec-aaca-7ea58a5d2ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849293487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3849293487
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1780947752
Short name T305
Test name
Test status
Simulation time 7032537540 ps
CPU time 21.34 seconds
Started Jun 28 06:34:28 PM PDT 24
Finished Jun 28 06:34:51 PM PDT 24
Peak memory 224568 kb
Host smart-0444c2f0-ac6a-40ce-9cfc-a4a88cc25f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780947752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1780947752
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2817352582
Short name T758
Test name
Test status
Simulation time 2876028638 ps
CPU time 12.13 seconds
Started Jun 28 06:34:28 PM PDT 24
Finished Jun 28 06:34:42 PM PDT 24
Peak memory 220048 kb
Host smart-93a086cc-684a-4b7f-9e0f-3f68d5b3fd91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2817352582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2817352582
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2031388260
Short name T118
Test name
Test status
Simulation time 42188888288 ps
CPU time 474.7 seconds
Started Jun 28 06:34:45 PM PDT 24
Finished Jun 28 06:42:42 PM PDT 24
Peak memory 265660 kb
Host smart-8f5ff33a-b9f2-41d6-985d-36d9558dd8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031388260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2031388260
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2256203719
Short name T912
Test name
Test status
Simulation time 40167451685 ps
CPU time 52.75 seconds
Started Jun 28 06:34:31 PM PDT 24
Finished Jun 28 06:35:25 PM PDT 24
Peak memory 216316 kb
Host smart-ff005fca-8518-4b2c-8489-196407edc7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256203719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2256203719
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2497335990
Short name T592
Test name
Test status
Simulation time 43446849 ps
CPU time 0.73 seconds
Started Jun 28 06:34:33 PM PDT 24
Finished Jun 28 06:34:35 PM PDT 24
Peak memory 205656 kb
Host smart-47da207e-7d35-41b4-b357-712fbad7812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497335990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2497335990
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3777326917
Short name T288
Test name
Test status
Simulation time 306412919 ps
CPU time 1.93 seconds
Started Jun 28 06:34:33 PM PDT 24
Finished Jun 28 06:34:36 PM PDT 24
Peak memory 216220 kb
Host smart-1cd41831-18a0-465e-875b-b7efc0003686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777326917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3777326917
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3691826690
Short name T299
Test name
Test status
Simulation time 120316554 ps
CPU time 0.98 seconds
Started Jun 28 06:34:42 PM PDT 24
Finished Jun 28 06:34:44 PM PDT 24
Peak memory 206912 kb
Host smart-ceae11fc-1740-42d4-825b-314b141507db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691826690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3691826690
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1584635634
Short name T818
Test name
Test status
Simulation time 6595527339 ps
CPU time 4.36 seconds
Started Jun 28 06:34:27 PM PDT 24
Finished Jun 28 06:34:33 PM PDT 24
Peak memory 232944 kb
Host smart-243fe882-88d0-4197-9cfb-75acf19f868e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584635634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1584635634
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.283236019
Short name T989
Test name
Test status
Simulation time 42242929 ps
CPU time 0.73 seconds
Started Jun 28 06:28:37 PM PDT 24
Finished Jun 28 06:28:39 PM PDT 24
Peak memory 204832 kb
Host smart-cb7c6586-6ad1-42df-a126-9b7e11c7a07b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283236019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.283236019
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1244485407
Short name T157
Test name
Test status
Simulation time 105950017 ps
CPU time 3.24 seconds
Started Jun 28 06:28:27 PM PDT 24
Finished Jun 28 06:28:31 PM PDT 24
Peak memory 232620 kb
Host smart-7eeb2fad-bdf6-45f4-bb09-06a188853757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244485407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1244485407
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1702340383
Short name T337
Test name
Test status
Simulation time 15818025 ps
CPU time 0.74 seconds
Started Jun 28 06:28:28 PM PDT 24
Finished Jun 28 06:28:30 PM PDT 24
Peak memory 205428 kb
Host smart-fdddd7bc-8e5c-4a4d-8efa-e94b21d35810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702340383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1702340383
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.110293165
Short name T739
Test name
Test status
Simulation time 6153735726 ps
CPU time 25.99 seconds
Started Jun 28 06:28:36 PM PDT 24
Finished Jun 28 06:29:04 PM PDT 24
Peak memory 235392 kb
Host smart-bec6c339-b698-4f59-920e-a44e9e482239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110293165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.110293165
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2181379829
Short name T962
Test name
Test status
Simulation time 7140208016 ps
CPU time 110.56 seconds
Started Jun 28 06:28:39 PM PDT 24
Finished Jun 28 06:30:30 PM PDT 24
Peak memory 252184 kb
Host smart-77577bed-f83d-47cb-b4db-be8693e14f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181379829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2181379829
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3236101825
Short name T1
Test name
Test status
Simulation time 10451812909 ps
CPU time 51.11 seconds
Started Jun 28 06:28:34 PM PDT 24
Finished Jun 28 06:29:26 PM PDT 24
Peak memory 249264 kb
Host smart-c07e30a1-ec24-4631-befe-8703611d508a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236101825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3236101825
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2031224928
Short name T263
Test name
Test status
Simulation time 590884621 ps
CPU time 12.49 seconds
Started Jun 28 06:28:28 PM PDT 24
Finished Jun 28 06:28:41 PM PDT 24
Peak memory 232628 kb
Host smart-50c8bc08-a378-4669-adf3-586a27bc4676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031224928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2031224928
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1279160184
Short name T780
Test name
Test status
Simulation time 473228631896 ps
CPU time 204.8 seconds
Started Jun 28 06:28:36 PM PDT 24
Finished Jun 28 06:32:03 PM PDT 24
Peak memory 249172 kb
Host smart-19543e3e-6503-4f58-9a09-8b9a95ffcb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279160184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1279160184
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1667432146
Short name T696
Test name
Test status
Simulation time 1426821458 ps
CPU time 15.96 seconds
Started Jun 28 06:28:29 PM PDT 24
Finished Jun 28 06:28:46 PM PDT 24
Peak memory 232664 kb
Host smart-f0db4b0a-a642-473c-9a93-e8f9e0533bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667432146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1667432146
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1987009707
Short name T398
Test name
Test status
Simulation time 3203064581 ps
CPU time 29.88 seconds
Started Jun 28 06:28:32 PM PDT 24
Finished Jun 28 06:29:03 PM PDT 24
Peak memory 232688 kb
Host smart-22b1103c-0251-418f-8f19-bcef6d4ab610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987009707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1987009707
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1795195424
Short name T773
Test name
Test status
Simulation time 130691657 ps
CPU time 1.16 seconds
Started Jun 28 06:28:33 PM PDT 24
Finished Jun 28 06:28:35 PM PDT 24
Peak memory 216776 kb
Host smart-ea969566-9631-41e4-910d-c3376e329d72
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795195424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1795195424
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2389623183
Short name T40
Test name
Test status
Simulation time 21437038292 ps
CPU time 15.22 seconds
Started Jun 28 06:28:33 PM PDT 24
Finished Jun 28 06:28:49 PM PDT 24
Peak memory 233772 kb
Host smart-533549cb-60fc-47dd-bf4d-895288e8a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389623183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2389623183
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.568391737
Short name T842
Test name
Test status
Simulation time 5174132508 ps
CPU time 8.29 seconds
Started Jun 28 06:28:27 PM PDT 24
Finished Jun 28 06:28:36 PM PDT 24
Peak memory 224552 kb
Host smart-5a70a34c-04a8-44c5-8878-d61e8883c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568391737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.568391737
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2551491160
Short name T115
Test name
Test status
Simulation time 3499614354 ps
CPU time 9.69 seconds
Started Jun 28 06:28:38 PM PDT 24
Finished Jun 28 06:28:49 PM PDT 24
Peak memory 222160 kb
Host smart-cc291d9c-9404-44ec-b3b4-456b99d4308e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2551491160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2551491160
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1207949132
Short name T250
Test name
Test status
Simulation time 188041008183 ps
CPU time 474.03 seconds
Started Jun 28 06:28:38 PM PDT 24
Finished Jun 28 06:36:33 PM PDT 24
Peak memory 257440 kb
Host smart-87e82c9f-195f-40a2-afac-3b9be97f85ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207949132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1207949132
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1639847406
Short name T984
Test name
Test status
Simulation time 6054181504 ps
CPU time 17.01 seconds
Started Jun 28 06:28:29 PM PDT 24
Finished Jun 28 06:28:47 PM PDT 24
Peak memory 216304 kb
Host smart-cace7c37-a990-46d3-a830-55475e072c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639847406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1639847406
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2821180591
Short name T619
Test name
Test status
Simulation time 34400302 ps
CPU time 0.72 seconds
Started Jun 28 06:28:28 PM PDT 24
Finished Jun 28 06:28:29 PM PDT 24
Peak memory 205680 kb
Host smart-870669f7-f9eb-402b-ae19-2245f70ef3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821180591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2821180591
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1305288809
Short name T665
Test name
Test status
Simulation time 237827109 ps
CPU time 1.78 seconds
Started Jun 28 06:28:33 PM PDT 24
Finished Jun 28 06:28:35 PM PDT 24
Peak memory 216208 kb
Host smart-275d7380-9ae6-4e1f-acdd-7019aa70664a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305288809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1305288809
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1537850587
Short name T348
Test name
Test status
Simulation time 17353106 ps
CPU time 0.75 seconds
Started Jun 28 06:28:27 PM PDT 24
Finished Jun 28 06:28:28 PM PDT 24
Peak memory 205888 kb
Host smart-539dee0a-689a-4fa0-9142-b5a890f7498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537850587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1537850587
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3666295426
Short name T393
Test name
Test status
Simulation time 682181740 ps
CPU time 3.67 seconds
Started Jun 28 06:28:32 PM PDT 24
Finished Jun 28 06:28:36 PM PDT 24
Peak memory 232676 kb
Host smart-ddeed5a5-e268-4aeb-9895-101eec33365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666295426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3666295426
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.837129376
Short name T970
Test name
Test status
Simulation time 52481564 ps
CPU time 0.73 seconds
Started Jun 28 06:28:50 PM PDT 24
Finished Jun 28 06:28:52 PM PDT 24
Peak memory 204836 kb
Host smart-ada665bc-099e-41d1-a709-af9dfc346d52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837129376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.837129376
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.512006938
Short name T239
Test name
Test status
Simulation time 134381657 ps
CPU time 2.64 seconds
Started Jun 28 06:28:38 PM PDT 24
Finished Jun 28 06:28:42 PM PDT 24
Peak memory 232664 kb
Host smart-c8ffe221-1806-4eae-b0cc-b0bf8c1696a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512006938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.512006938
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3000639451
Short name T1021
Test name
Test status
Simulation time 72867395 ps
CPU time 0.83 seconds
Started Jun 28 06:28:37 PM PDT 24
Finished Jun 28 06:28:39 PM PDT 24
Peak memory 206588 kb
Host smart-67b710f8-3a32-403f-9f24-902583a369de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000639451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3000639451
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3913518286
Short name T176
Test name
Test status
Simulation time 17841954332 ps
CPU time 68.12 seconds
Started Jun 28 06:28:36 PM PDT 24
Finished Jun 28 06:29:46 PM PDT 24
Peak memory 249180 kb
Host smart-fb3861df-78f5-4601-874a-858e31821063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913518286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3913518286
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.942636060
Short name T699
Test name
Test status
Simulation time 1752236225 ps
CPU time 17.49 seconds
Started Jun 28 06:28:36 PM PDT 24
Finished Jun 28 06:28:55 PM PDT 24
Peak memory 217236 kb
Host smart-0db20509-4977-4c56-b5c9-a16027511864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942636060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.942636060
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2276164878
Short name T285
Test name
Test status
Simulation time 3265823712 ps
CPU time 42.26 seconds
Started Jun 28 06:28:36 PM PDT 24
Finished Jun 28 06:29:19 PM PDT 24
Peak memory 238608 kb
Host smart-e7c7518b-2f4f-4c0f-b3cb-036a04b11603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276164878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2276164878
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1266454652
Short name T127
Test name
Test status
Simulation time 50921125 ps
CPU time 3.66 seconds
Started Jun 28 06:28:39 PM PDT 24
Finished Jun 28 06:28:43 PM PDT 24
Peak memory 232676 kb
Host smart-a30cc44f-0154-4402-a82e-5d8834fc890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266454652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1266454652
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2698732650
Short name T694
Test name
Test status
Simulation time 32574032015 ps
CPU time 74.62 seconds
Started Jun 28 06:28:36 PM PDT 24
Finished Jun 28 06:29:52 PM PDT 24
Peak memory 254420 kb
Host smart-fbed3d54-e9cc-4035-9372-6d12b1f7df43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698732650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2698732650
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4171925347
Short name T358
Test name
Test status
Simulation time 365370417 ps
CPU time 6.49 seconds
Started Jun 28 06:28:37 PM PDT 24
Finished Jun 28 06:28:45 PM PDT 24
Peak memory 232668 kb
Host smart-60d2e24e-1bd0-4062-a5ec-1f53dd01dabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171925347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4171925347
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.443984406
Short name T757
Test name
Test status
Simulation time 951372768 ps
CPU time 14.89 seconds
Started Jun 28 06:28:38 PM PDT 24
Finished Jun 28 06:28:54 PM PDT 24
Peak memory 232668 kb
Host smart-4974012f-55db-4abc-826b-a6fc183065bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443984406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.443984406
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3698041732
Short name T387
Test name
Test status
Simulation time 18895604 ps
CPU time 1.05 seconds
Started Jun 28 06:28:36 PM PDT 24
Finished Jun 28 06:28:39 PM PDT 24
Peak memory 216716 kb
Host smart-bcc9beeb-b94a-4728-a07d-36ba34341c6c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698041732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3698041732
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3209180384
Short name T747
Test name
Test status
Simulation time 615681970 ps
CPU time 5.77 seconds
Started Jun 28 06:28:36 PM PDT 24
Finished Jun 28 06:28:43 PM PDT 24
Peak memory 232664 kb
Host smart-7106fdee-ebbf-4a04-a856-a84ffb5110fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209180384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3209180384
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3307665337
Short name T490
Test name
Test status
Simulation time 1025342094 ps
CPU time 4.18 seconds
Started Jun 28 06:28:36 PM PDT 24
Finished Jun 28 06:28:42 PM PDT 24
Peak memory 224468 kb
Host smart-52e4b8e9-4191-47d4-afce-9e228f1f3baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307665337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3307665337
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4109980979
Short name T656
Test name
Test status
Simulation time 249047342 ps
CPU time 3.46 seconds
Started Jun 28 06:28:37 PM PDT 24
Finished Jun 28 06:28:42 PM PDT 24
Peak memory 222548 kb
Host smart-eafde40b-8717-4e2e-a760-d0c2cdb14f84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4109980979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4109980979
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.38227902
Short name T691
Test name
Test status
Simulation time 52768127084 ps
CPU time 492.44 seconds
Started Jun 28 06:28:49 PM PDT 24
Finished Jun 28 06:37:02 PM PDT 24
Peak memory 250324 kb
Host smart-ae10e2cc-4ec5-4847-8d8e-d01884c13f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_
all.38227902
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.758676733
Short name T712
Test name
Test status
Simulation time 3059333903 ps
CPU time 23.19 seconds
Started Jun 28 06:28:37 PM PDT 24
Finished Jun 28 06:29:01 PM PDT 24
Peak memory 216316 kb
Host smart-f6d51539-2d96-4736-83c7-18d6fa011c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758676733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.758676733
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3333162384
Short name T361
Test name
Test status
Simulation time 1008946123 ps
CPU time 3.51 seconds
Started Jun 28 06:28:37 PM PDT 24
Finished Jun 28 06:28:42 PM PDT 24
Peak memory 216224 kb
Host smart-8d26577a-c8f6-4505-8f07-c265a88c66d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333162384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3333162384
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3365711156
Short name T43
Test name
Test status
Simulation time 46356456 ps
CPU time 1.18 seconds
Started Jun 28 06:28:37 PM PDT 24
Finished Jun 28 06:28:39 PM PDT 24
Peak memory 216032 kb
Host smart-977fbc6f-4fcb-4373-9e83-9c7d784598a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365711156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3365711156
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.120210073
Short name T325
Test name
Test status
Simulation time 50638071 ps
CPU time 0.84 seconds
Started Jun 28 06:28:37 PM PDT 24
Finished Jun 28 06:28:39 PM PDT 24
Peak memory 205848 kb
Host smart-04e17525-bebc-493c-8ecb-29cd2e3cf3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120210073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.120210073
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2248186072
Short name T535
Test name
Test status
Simulation time 721119890 ps
CPU time 3.1 seconds
Started Jun 28 06:28:35 PM PDT 24
Finished Jun 28 06:28:40 PM PDT 24
Peak memory 224440 kb
Host smart-e359a257-7d3d-4d4f-9dde-c4dfaaf189f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248186072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2248186072
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.100036413
Short name T303
Test name
Test status
Simulation time 15205055 ps
CPU time 0.77 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:29:03 PM PDT 24
Peak memory 204836 kb
Host smart-dbbd7ce3-f70a-4ab1-a619-614dd5f2698a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100036413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.100036413
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3486796187
Short name T419
Test name
Test status
Simulation time 519366455 ps
CPU time 4.46 seconds
Started Jun 28 06:28:51 PM PDT 24
Finished Jun 28 06:28:56 PM PDT 24
Peak memory 232644 kb
Host smart-a10244b8-bc41-44f8-bb31-ad9ad4dfd4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486796187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3486796187
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.920912443
Short name T306
Test name
Test status
Simulation time 19168263 ps
CPU time 0.8 seconds
Started Jun 28 06:28:48 PM PDT 24
Finished Jun 28 06:28:50 PM PDT 24
Peak memory 205528 kb
Host smart-0de454e9-c467-4b84-b134-bbbd0eb2d64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920912443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.920912443
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.869949418
Short name T768
Test name
Test status
Simulation time 124791552644 ps
CPU time 96.12 seconds
Started Jun 28 06:28:58 PM PDT 24
Finished Jun 28 06:30:36 PM PDT 24
Peak memory 256936 kb
Host smart-010219b8-21ec-4078-a7f2-b5c7a457555b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869949418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.869949418
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2603092799
Short name T520
Test name
Test status
Simulation time 1969331110 ps
CPU time 11.06 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:29:11 PM PDT 24
Peak memory 220600 kb
Host smart-09279090-2c46-42b4-830d-10f4fbcd6a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603092799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2603092799
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.534017466
Short name T41
Test name
Test status
Simulation time 29335168761 ps
CPU time 277.65 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:33:38 PM PDT 24
Peak memory 256716 kb
Host smart-abc7b7e0-48f5-4e37-98aa-804394d6975f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534017466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
534017466
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.379835770
Short name T322
Test name
Test status
Simulation time 16358515684 ps
CPU time 47.66 seconds
Started Jun 28 06:28:49 PM PDT 24
Finished Jun 28 06:29:38 PM PDT 24
Peak memory 232716 kb
Host smart-4231c5f2-1155-4b8e-829d-6298c27c49e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379835770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.379835770
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1962306662
Short name T922
Test name
Test status
Simulation time 2018340528 ps
CPU time 22.97 seconds
Started Jun 28 06:28:53 PM PDT 24
Finished Jun 28 06:29:17 PM PDT 24
Peak memory 248712 kb
Host smart-01c56ddc-a416-4b3e-b4ab-c8cd1b24acb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962306662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1962306662
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.556108729
Short name T642
Test name
Test status
Simulation time 162664381 ps
CPU time 4.19 seconds
Started Jun 28 06:28:52 PM PDT 24
Finished Jun 28 06:28:57 PM PDT 24
Peak memory 232664 kb
Host smart-7a8e7534-f5a7-4852-bc6c-8ff5a67df1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556108729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.556108729
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2187635669
Short name T988
Test name
Test status
Simulation time 46077505820 ps
CPU time 27 seconds
Started Jun 28 06:28:51 PM PDT 24
Finished Jun 28 06:29:19 PM PDT 24
Peak memory 240940 kb
Host smart-467090bc-443d-4884-b652-f01467b34ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187635669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2187635669
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1117591347
Short name T485
Test name
Test status
Simulation time 52950151 ps
CPU time 0.98 seconds
Started Jun 28 06:28:49 PM PDT 24
Finished Jun 28 06:28:51 PM PDT 24
Peak memory 218040 kb
Host smart-48d0fd41-b729-49ed-a990-79d9589d88b5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117591347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1117591347
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2779545405
Short name T816
Test name
Test status
Simulation time 2525525178 ps
CPU time 11.37 seconds
Started Jun 28 06:28:50 PM PDT 24
Finished Jun 28 06:29:03 PM PDT 24
Peak memory 232756 kb
Host smart-f6c0d4e6-fcd1-4a33-bfa3-9aff8a1bf94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779545405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2779545405
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1188669408
Short name T214
Test name
Test status
Simulation time 9008610470 ps
CPU time 7.19 seconds
Started Jun 28 06:28:50 PM PDT 24
Finished Jun 28 06:28:59 PM PDT 24
Peak memory 224628 kb
Host smart-c21d3fc8-9240-4ca2-b17e-91d1435ea24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188669408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1188669408
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2040454066
Short name T727
Test name
Test status
Simulation time 1511662469 ps
CPU time 4.14 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:29:06 PM PDT 24
Peak memory 221936 kb
Host smart-f00e08b6-de41-4189-9994-7a7427163257
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2040454066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2040454066
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.66534426
Short name T3
Test name
Test status
Simulation time 4585572859 ps
CPU time 24.71 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:29:27 PM PDT 24
Peak memory 217512 kb
Host smart-1a1d6f8c-cd7e-4fb7-8bab-6b810f6d58c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66534426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_
all.66534426
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4187249196
Short name T278
Test name
Test status
Simulation time 1219957849 ps
CPU time 5.63 seconds
Started Jun 28 06:28:51 PM PDT 24
Finished Jun 28 06:28:58 PM PDT 24
Peak memory 216140 kb
Host smart-4d3d1938-095e-44b8-9259-fb6f1258d3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187249196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4187249196
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3200136468
Short name T702
Test name
Test status
Simulation time 3605048409 ps
CPU time 4.37 seconds
Started Jun 28 06:28:51 PM PDT 24
Finished Jun 28 06:28:56 PM PDT 24
Peak memory 216292 kb
Host smart-e767d329-d7ef-400e-8e98-06d8c07bbc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200136468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3200136468
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1940711532
Short name T652
Test name
Test status
Simulation time 60273603 ps
CPU time 3.67 seconds
Started Jun 28 06:28:48 PM PDT 24
Finished Jun 28 06:28:52 PM PDT 24
Peak memory 216128 kb
Host smart-c2f0a421-18a6-472d-a3e3-d687010f919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940711532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1940711532
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2888436073
Short name T796
Test name
Test status
Simulation time 24390505 ps
CPU time 0.73 seconds
Started Jun 28 06:28:50 PM PDT 24
Finished Jun 28 06:28:52 PM PDT 24
Peak memory 205888 kb
Host smart-7a2a91db-e7dd-4281-9b3f-2891d70840b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888436073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2888436073
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3920165853
Short name T914
Test name
Test status
Simulation time 72652644 ps
CPU time 2.28 seconds
Started Jun 28 06:28:50 PM PDT 24
Finished Jun 28 06:28:53 PM PDT 24
Peak memory 223800 kb
Host smart-b176d0b0-d831-4176-9105-c46f5d7f651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920165853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3920165853
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1889953036
Short name T654
Test name
Test status
Simulation time 14033942 ps
CPU time 0.74 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:29:02 PM PDT 24
Peak memory 205360 kb
Host smart-85dfe1b8-b75f-4493-8331-423903f19fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889953036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
889953036
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3239346971
Short name T788
Test name
Test status
Simulation time 774945091 ps
CPU time 5.27 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:29:06 PM PDT 24
Peak memory 224464 kb
Host smart-d45a09a3-2e6b-4965-970b-17db63ab31ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239346971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3239346971
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2344628507
Short name T573
Test name
Test status
Simulation time 34371085 ps
CPU time 0.79 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:29:02 PM PDT 24
Peak memory 206564 kb
Host smart-e8565c95-34af-425f-8319-e2f8ec799df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344628507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2344628507
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1617192677
Short name T192
Test name
Test status
Simulation time 2177162100 ps
CPU time 44.67 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:29:47 PM PDT 24
Peak memory 250068 kb
Host smart-8111b227-d2b0-41ab-8a5e-d7e0bb14587e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617192677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1617192677
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1071004675
Short name T353
Test name
Test status
Simulation time 9223013134 ps
CPU time 63.9 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:30:06 PM PDT 24
Peak memory 253036 kb
Host smart-700ae100-70da-4028-a501-81b21630ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071004675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1071004675
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1659288923
Short name T778
Test name
Test status
Simulation time 68769482727 ps
CPU time 146.11 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:31:28 PM PDT 24
Peak memory 251356 kb
Host smart-d1144e71-3e55-45c0-a76f-f33bcdf9ebde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659288923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1659288923
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3183373801
Short name T324
Test name
Test status
Simulation time 1063018653 ps
CPU time 11.49 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:29:14 PM PDT 24
Peak memory 224368 kb
Host smart-909e9610-90ce-4965-9647-143c2c10d383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183373801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3183373801
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.964071224
Short name T155
Test name
Test status
Simulation time 14761217477 ps
CPU time 93.95 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:30:34 PM PDT 24
Peak memory 256776 kb
Host smart-d84a61c1-9593-41bf-ba1a-8b0bee048540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964071224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
964071224
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2576933599
Short name T669
Test name
Test status
Simulation time 825626972 ps
CPU time 8.54 seconds
Started Jun 28 06:29:01 PM PDT 24
Finished Jun 28 06:29:11 PM PDT 24
Peak memory 224424 kb
Host smart-ced04753-389f-4c0d-8be5-da83ca352832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576933599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2576933599
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1531684879
Short name T219
Test name
Test status
Simulation time 2412399036 ps
CPU time 22.3 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:29:24 PM PDT 24
Peak memory 231820 kb
Host smart-69f72cda-cdae-42e2-9fae-fdf77e5af242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531684879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1531684879
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3008284391
Short name T460
Test name
Test status
Simulation time 27493867 ps
CPU time 1.11 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:29:02 PM PDT 24
Peak memory 216772 kb
Host smart-800b3493-63f4-433c-b5f9-ae07dbb887dc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008284391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3008284391
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2790623280
Short name T376
Test name
Test status
Simulation time 2720542907 ps
CPU time 8.57 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:29:10 PM PDT 24
Peak memory 224496 kb
Host smart-6932070b-587e-4bc5-857a-73dd5648e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790623280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2790623280
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2328082712
Short name T1018
Test name
Test status
Simulation time 6925521963 ps
CPU time 19.36 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:29:20 PM PDT 24
Peak memory 224628 kb
Host smart-ffd621b1-14a0-4539-a143-273cbe4da80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328082712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2328082712
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2859664101
Short name T999
Test name
Test status
Simulation time 1097562411 ps
CPU time 9.27 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:29:09 PM PDT 24
Peak memory 219096 kb
Host smart-2b64e459-7511-4105-b2c5-09fc5421c4e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2859664101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2859664101
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2154825988
Short name T657
Test name
Test status
Simulation time 31422581778 ps
CPU time 322.74 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:34:25 PM PDT 24
Peak memory 257008 kb
Host smart-f5fcde05-e808-4241-a803-14c3c64221c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154825988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2154825988
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3281768339
Short name T281
Test name
Test status
Simulation time 20518791519 ps
CPU time 17.59 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:29:19 PM PDT 24
Peak memory 216524 kb
Host smart-47f08db0-92cf-4396-b37e-ae231e7ff17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281768339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3281768339
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2912669884
Short name T457
Test name
Test status
Simulation time 264317775 ps
CPU time 1.43 seconds
Started Jun 28 06:29:00 PM PDT 24
Finished Jun 28 06:29:03 PM PDT 24
Peak memory 207720 kb
Host smart-000e4c9e-17ef-4dd2-8261-6451ea8a770f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912669884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2912669884
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1249718784
Short name T352
Test name
Test status
Simulation time 29381189 ps
CPU time 0.77 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:29:02 PM PDT 24
Peak memory 205604 kb
Host smart-8282b30c-03c3-4790-91c9-7f4c65d92c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249718784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1249718784
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2925682244
Short name T441
Test name
Test status
Simulation time 76029336 ps
CPU time 0.87 seconds
Started Jun 28 06:28:58 PM PDT 24
Finished Jun 28 06:29:00 PM PDT 24
Peak memory 205892 kb
Host smart-2a5e0130-ea79-44a8-8346-0a5381f1b29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925682244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2925682244
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.711364057
Short name T932
Test name
Test status
Simulation time 385439626 ps
CPU time 7.48 seconds
Started Jun 28 06:28:59 PM PDT 24
Finished Jun 28 06:29:08 PM PDT 24
Peak memory 240676 kb
Host smart-439090e3-7fa4-4e7e-a2a9-fab8e8bd6c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711364057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.711364057
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2563713403
Short name T890
Test name
Test status
Simulation time 15123946 ps
CPU time 0.73 seconds
Started Jun 28 06:29:14 PM PDT 24
Finished Jun 28 06:29:16 PM PDT 24
Peak memory 205408 kb
Host smart-56f8da46-6b43-4af8-b44a-4ac40634d01f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563713403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
563713403
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3281844070
Short name T342
Test name
Test status
Simulation time 123470495 ps
CPU time 2.52 seconds
Started Jun 28 06:29:10 PM PDT 24
Finished Jun 28 06:29:14 PM PDT 24
Peak memory 232624 kb
Host smart-b2209e58-9b8c-4d08-b3f2-23026c7bc1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281844070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3281844070
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2010467052
Short name T571
Test name
Test status
Simulation time 40147641 ps
CPU time 0.8 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:12 PM PDT 24
Peak memory 206564 kb
Host smart-3bb95867-ae23-4a62-bf73-c7d07df54e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010467052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2010467052
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.109867972
Short name T955
Test name
Test status
Simulation time 34818739956 ps
CPU time 120.27 seconds
Started Jun 28 06:29:10 PM PDT 24
Finished Jun 28 06:31:12 PM PDT 24
Peak memory 247736 kb
Host smart-7b7ec4cc-dddb-46a7-b37e-590b7ec90289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109867972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.109867972
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2590686986
Short name T924
Test name
Test status
Simulation time 15206284273 ps
CPU time 211.41 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:32:42 PM PDT 24
Peak memory 265624 kb
Host smart-adc53419-2051-4b03-bba1-bf7f58277b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590686986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2590686986
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1080754232
Short name T164
Test name
Test status
Simulation time 25442974886 ps
CPU time 97.17 seconds
Started Jun 28 06:29:18 PM PDT 24
Finished Jun 28 06:30:57 PM PDT 24
Peak memory 253364 kb
Host smart-9772a04a-f3c3-4d45-8b3f-f6640f49a66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080754232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1080754232
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.113023372
Short name T265
Test name
Test status
Simulation time 830788715 ps
CPU time 20.51 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:31 PM PDT 24
Peak memory 240868 kb
Host smart-99d33d92-1cbe-43a6-8ece-6eb59f54710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113023372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.113023372
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2051220023
Short name T213
Test name
Test status
Simulation time 23822417624 ps
CPU time 159.26 seconds
Started Jun 28 06:29:17 PM PDT 24
Finished Jun 28 06:31:57 PM PDT 24
Peak memory 254388 kb
Host smart-579fbd30-0d62-4912-8361-068c2ee952e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051220023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2051220023
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2402794057
Short name T991
Test name
Test status
Simulation time 872026877 ps
CPU time 6.81 seconds
Started Jun 28 06:29:18 PM PDT 24
Finished Jun 28 06:29:26 PM PDT 24
Peak memory 232860 kb
Host smart-7ff8b57c-e0b9-4667-b463-4017f74190b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402794057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2402794057
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.652885202
Short name T189
Test name
Test status
Simulation time 315727582 ps
CPU time 2.35 seconds
Started Jun 28 06:29:10 PM PDT 24
Finished Jun 28 06:29:14 PM PDT 24
Peak memory 224420 kb
Host smart-91c7a5eb-97cd-4305-a47b-59a9bb1e82fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652885202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.652885202
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3562242425
Short name T32
Test name
Test status
Simulation time 96032400 ps
CPU time 1.09 seconds
Started Jun 28 06:29:14 PM PDT 24
Finished Jun 28 06:29:16 PM PDT 24
Peak memory 216784 kb
Host smart-dd01b7ac-5dda-4c0d-bd95-21fff147e540
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562242425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3562242425
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3044966068
Short name T803
Test name
Test status
Simulation time 26701299217 ps
CPU time 19.98 seconds
Started Jun 28 06:29:11 PM PDT 24
Finished Jun 28 06:29:33 PM PDT 24
Peak memory 224508 kb
Host smart-38cf5198-c56e-42d3-a048-6f6b52b7cc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044966068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3044966068
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1375456605
Short name T483
Test name
Test status
Simulation time 4211955804 ps
CPU time 7.55 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:19 PM PDT 24
Peak memory 224592 kb
Host smart-2b46d2e1-749a-4f69-80ec-8f94a055b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375456605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1375456605
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2615879833
Short name T1022
Test name
Test status
Simulation time 1263115243 ps
CPU time 15.57 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:27 PM PDT 24
Peak memory 219056 kb
Host smart-0fe476ed-5d23-4e3d-95c5-8a5351dfd4a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2615879833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2615879833
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2084051111
Short name T145
Test name
Test status
Simulation time 93358254281 ps
CPU time 469.46 seconds
Started Jun 28 06:29:11 PM PDT 24
Finished Jun 28 06:37:02 PM PDT 24
Peak memory 254968 kb
Host smart-02f93dd9-d663-4a64-b572-6e0e79113778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084051111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2084051111
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3307054798
Short name T675
Test name
Test status
Simulation time 4932084497 ps
CPU time 25.41 seconds
Started Jun 28 06:29:11 PM PDT 24
Finished Jun 28 06:29:38 PM PDT 24
Peak memory 216344 kb
Host smart-0d2991aa-6093-4031-a702-b407538b3598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307054798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3307054798
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2841759249
Short name T430
Test name
Test status
Simulation time 1575655916 ps
CPU time 8.98 seconds
Started Jun 28 06:29:11 PM PDT 24
Finished Jun 28 06:29:21 PM PDT 24
Peak memory 216172 kb
Host smart-2503c30b-6f49-439e-841d-2bf2b8856293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841759249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2841759249
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2337699565
Short name T406
Test name
Test status
Simulation time 42248822 ps
CPU time 1.13 seconds
Started Jun 28 06:29:09 PM PDT 24
Finished Jun 28 06:29:12 PM PDT 24
Peak memory 207832 kb
Host smart-b1d13edb-c4ef-4f41-946e-db58f5855161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337699565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2337699565
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1171954983
Short name T828
Test name
Test status
Simulation time 105663576 ps
CPU time 0.79 seconds
Started Jun 28 06:29:11 PM PDT 24
Finished Jun 28 06:29:14 PM PDT 24
Peak memory 205896 kb
Host smart-e252a3a9-f4cc-4fb8-ac90-14b2e22cabf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171954983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1171954983
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.948700390
Short name T414
Test name
Test status
Simulation time 533431545 ps
CPU time 4.36 seconds
Started Jun 28 06:29:14 PM PDT 24
Finished Jun 28 06:29:20 PM PDT 24
Peak memory 238152 kb
Host smart-18a7692d-45e3-4ed8-9eaa-c92a08444eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948700390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.948700390
Directory /workspace/9.spi_device_upload/latest
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