Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2816721	1			T1	23550		T2	1		T3	1
all_values[1]	2816721	1			T1	23550		T2	1		T3	1
all_values[2]	2816721	1			T1	23550		T2	1		T3	1
all_values[3]	2816721	1			T1	23550		T2	1		T3	1
all_values[4]	2816721	1			T1	23550		T2	1		T3	1
all_values[5]	2816721	1			T1	23550		T2	1		T3	1
all_values[6]	2816721	1			T1	23550		T2	1		T3	1
all_values[7]	2816721	1			T1	23550		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21984006

1

T1

188363

T2

8

T3

8

auto[1]

549762

1

T1

37

T17

84

T18

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22506966

1

T1

188199

T2

8

T3

8

auto[1]

26802

1

T1

201

T8

323

T35

95

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2667405	1			T1	23420		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13120	1			T1	125		T8	138		T35	37
all_values[0]	auto[1]	auto[0]	135811	1			T1	5		T17	2		T18	5
all_values[0]	auto[1]	auto[1]	385	1			T17	3		T18	1		T22	4
all_values[1]	auto[0]	auto[0]	2708851	1			T1	23495		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	8160	1			T1	53		T8	114		T35	37
all_values[1]	auto[1]	auto[0]	99417	1			T1	2		T17	3		T18	2
all_values[1]	auto[1]	auto[1]	293	1			T17	4		T18	5		T22	2
all_values[2]	auto[0]	auto[0]	2789426	1			T1	23535		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3062	1			T1	7		T8	71		T35	21
all_values[2]	auto[1]	auto[0]	24033	1			T1	7		T17	6		T18	7
all_values[2]	auto[1]	auto[1]	200	1			T1	1		T17	8		T22	3
all_values[3]	auto[0]	auto[0]	2688153	1			T1	23542		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	173	1			T17	6		T18	2		T22	1
all_values[3]	auto[1]	auto[0]	128237	1			T1	4		T17	6		T18	2
all_values[3]	auto[1]	auto[1]	158	1			T1	4		T17	4		T29	2
all_values[4]	auto[0]	auto[0]	2667425	1			T1	23544		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	176	1			T1	2		T17	4		T18	4
all_values[4]	auto[1]	auto[0]	148948	1			T1	4		T17	11		T18	4
all_values[4]	auto[1]	auto[1]	172	1			T17	1		T18	1		T22	1
all_values[5]	auto[0]	auto[0]	2811595	1			T1	23546		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	133	1			T17	3		T18	3		T22	3
all_values[5]	auto[1]	auto[0]	4865	1			T1	2		T17	5		T18	2
all_values[5]	auto[1]	auto[1]	128	1			T1	2		T17	4		T18	3
all_values[6]	auto[0]	auto[0]	2812998	1			T1	23546		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	159	1			T1	2		T17	2		T18	1
all_values[6]	auto[1]	auto[0]	3410	1			T1	1		T17	5		T18	5
all_values[6]	auto[1]	auto[1]	154	1			T1	1		T17	8		T18	3
all_values[7]	auto[0]	auto[0]	2813000	1			T1	23544		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	170	1			T1	2		T17	3		T18	3
all_values[7]	auto[1]	auto[0]	3392	1			T1	2		T17	8		T18	3
all_values[7]	auto[1]	auto[1]	159	1			T1	2		T17	6		T18	4