Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	39318	1			T1	307		T4	219		T8	77
auto[SpiFlashAddrCfg]	8135	1			T1	65		T3	6		T4	34
auto[SpiFlashAddr3b]	9948	1			T1	105		T3	2		T4	22
auto[SpiFlashAddr4b]	8289	1			T1	64		T3	18		T4	25

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37615

1

T1

344

T3

26

T4

151

auto[1]

28075

1

T1

197

T4

149

T7

2

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35520

1

T1

266

T3

18

T4

155

auto[1]

30170

1

T1

275

T3

8

T4

145

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	44088	1			T1	355		T3	14		T4	229
values[1]	1248	1			T1	9		T4	6		T8	2
values[2]	1622	1			T1	22		T4	2		T8	3
values[3]	1605	1			T1	11		T4	6		T8	4
values[4]	1498	1			T1	14		T4	6		T8	10
values[5]	1619	1			T1	19		T3	6		T4	5
values[6]	1629	1			T1	15		T4	5		T8	3
values[7]	1571	1			T1	13		T4	6		T8	2
values[8]	10810	1			T1	83		T3	6		T4	35

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33018

1

T3

26

T7

2

T8

148

auto[1]

32672

1

T1

541

T4

300

T38

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

62164

1

T1

513

T3

16

T4

287

write

3526

1

T1

28

T3

10

T4

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20913

1

T1

199

T3

6

T4

64

valids[0x1]

44777

1

T1

342

T3

20

T4

236

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1649	1			T1	24		T4	3		T8	3
internal_process_ops[0x5a]	1740	1			T1	20		T3	2		T4	3
internal_process_ops[0x05]	23954	1			T1	144		T4	166		T8	30
internal_process_ops[0x35]	1767	1			T1	8		T4	7		T8	7
internal_process_ops[0x15]	1656	1			T1	11		T4	4		T8	4
internal_process_ops[0x03]	1170	1			T1	4		T4	3		T8	3
internal_process_ops[0x0b]	1135	1			T1	6		T4	1		T8	5
internal_process_ops[0x3b]	1103	1			T1	7		T4	2		T8	3
internal_process_ops[0x6b]	1142	1			T1	1		T3	4		T8	1
internal_process_ops[0xbb]	1105	1			T1	4		T3	2		T4	1
internal_process_ops[0xeb]	1101	1			T1	4		T4	2		T8	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64009

1

T1

529

T3

26

T4

295

auto[1]

1681

1

T1

12

T4

5

T7

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63084

1

T1

519

T3

26

T4

291

auto[1]

2606

1

T1

22

T4

9

T8

12

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11567

1

T8

46

T13

44

T15

48

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6656

1

T8

27

T12

4

T15

20

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2105

1

T3

2

T8

5

T13

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1883

1

T8

7

T15

32

T34

11

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2625

1

T3

2

T8

6

T13

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2349

1

T8

21

T12

8

T15

23

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2217

1

T3

12

T8

11

T13

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1938

1

T8

11

T12

10

T15

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

131

1

T8

1

T15

4

T16

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T8

1

T34

3

T42

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

111

1

T15

1

T35

4

T41

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

97

1

T8

2

T42

1

T44

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

135

1

T3

4

T8

3

T15

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T8

1

T15

2

T35

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

86

1

T15

4

T34

2

T35

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

113

1

T8

2

T15

1

T40

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

121

1

T13

2

T15

3

T34

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

83

1

T15

2

T34

2

T35

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

92

1

T34

2

T42

1

T44

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

104

1

T34

2

T41

1

T44

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

127

1

T3

6

T8

2

T34

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T8

2

T35

1

T41

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

91

1

T42

1

T44

1

T77

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

88

1

T7

2

T42

3

T44

5

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11850

1

T1

242

T4

124

T39

271

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8319

1

T1

62

T4

91

T39

54

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1630

1

T1

22

T4

11

T38

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1613

1

T1

32

T4

17

T39

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2023

1

T1

44

T4

4

T38

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2100

1

T1

50

T4

16

T39

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1723

1

T1

28

T4

8

T38

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1566

1

T1

33

T4

16

T39

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

124

1

T4

3

T17

3

T92

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

150

1

T1

2

T39

1

T36

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

111

1

T39

1

T36

1

T92

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

104

1

T1

1

T4

1

T36

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

121

1

T1

2

T39

1

T17

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

127

1

T1

1

T4

1

T17

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

136

1

T1

6

T4

2

T39

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

86

1

T1

2

T4

3

T39

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

117

1

T1

1

T36

1

T17

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

107

1

T1

1

T39

2

T36

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

111

1

T1

6

T4

2

T36

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

116

1

T1

3

T17

2

T87

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

132

1

T39

1

T36

4

T92

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T1

1

T39

1

T17

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

99

1

T1

1

T4

1

T39

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

106

1

T1

1

T36

2

T17

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4079	1			T8	24		T13	6		T15	45
auto[0]	values[0]	valids[0x1]	17038	1			T3	14		T7	2		T8	66
auto[0]	values[1]	valids[0x1]	630	1			T8	2		T15	5		T34	3
auto[0]	values[2]	valids[0x0]	555	1			T8	2		T15	7		T34	3
auto[0]	values[2]	valids[0x1]	324	1			T8	1		T12	2		T15	2
auto[0]	values[3]	valids[0x0]	578	1			T8	3		T13	2		T15	5
auto[0]	values[3]	valids[0x1]	330	1			T8	1		T15	2		T34	3
auto[0]	values[4]	valids[0x0]	534	1			T8	3		T15	4		T34	6
auto[0]	values[4]	valids[0x1]	319	1			T8	7		T13	2		T15	2
auto[0]	values[5]	valids[0x0]	533	1			T3	4		T8	4		T12	6
auto[0]	values[5]	valids[0x1]	339	1			T3	2		T8	5		T13	2
auto[0]	values[6]	valids[0x0]	640	1			T8	3		T12	2		T15	6
auto[0]	values[6]	valids[0x1]	268	1			T13	2		T15	4		T34	4
auto[0]	values[7]	valids[0x0]	553	1			T8	1		T15	4		T34	5
auto[0]	values[7]	valids[0x1]	336	1			T8	1		T12	2		T15	3
auto[0]	values[8]	valids[0x0]	3698	1			T3	2		T8	15		T15	40
auto[0]	values[8]	valids[0x1]	2264	1			T3	4		T8	10		T12	4
auto[1]	values[0]	valids[0x0]	4496	1			T1	101		T4	28		T39	49
auto[1]	values[0]	valids[0x1]	18475	1			T1	254		T4	201		T39	300
auto[1]	values[1]	valids[0x1]	618	1			T1	9		T4	6		T39	5
auto[1]	values[2]	valids[0x0]	425	1			T1	10		T39	4		T36	4
auto[1]	values[2]	valids[0x1]	318	1			T1	12		T4	2		T39	1
auto[1]	values[3]	valids[0x0]	390	1			T1	5		T4	2		T39	6
auto[1]	values[3]	valids[0x1]	307	1			T1	6		T4	4		T39	2
auto[1]	values[4]	valids[0x0]	367	1			T1	10		T4	6		T39	2
auto[1]	values[4]	valids[0x1]	278	1			T1	4		T39	4		T17	3
auto[1]	values[5]	valids[0x0]	439	1			T1	8		T4	3		T38	1
auto[1]	values[5]	valids[0x1]	308	1			T1	11		T4	2		T39	2
auto[1]	values[6]	valids[0x0]	431	1			T1	4		T4	3		T38	1
auto[1]	values[6]	valids[0x1]	290	1			T1	11		T4	2		T39	2
auto[1]	values[7]	valids[0x0]	439	1			T1	9		T4	5		T36	1
auto[1]	values[7]	valids[0x1]	243	1			T1	4		T4	1		T38	4
auto[1]	values[8]	valids[0x0]	2756	1			T1	52		T4	17		T38	1
auto[1]	values[8]	valids[0x1]	2092	1			T1	31		T4	18		T38	2