Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3311633

1

T1

10898

T2

1

T3

1

auto[1]

33020

1

T1

121

T4

160

T8

28

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

747751

1

T1

117

T2

1

T3

1

auto[1]

2596902

1

T1

10902

T4

8571

T8

9568

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	639003	1			T1	137		T2	1		T3	1
auto[524288:1048575]	389323	1			T1	1686		T4	259		T8	1832
auto[1048576:1572863]	385202	1			T1	1844		T4	519		T8	158
auto[1572864:2097151]	376435	1			T1	1890		T4	2045		T8	130
auto[2097152:2621439]	394459	1			T1	1643		T4	327		T15	2720
auto[2621440:3145727]	373446	1			T1	990		T4	34		T8	5880
auto[3145728:3670015]	383280	1			T1	1649		T4	999		T8	6
auto[3670016:4194303]	403505	1			T1	1180		T4	3401		T8	389

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2632154

1

T1

11011

T2

1

T3

1

auto[1]

712499

1

T1

8

T4

11

T8

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2860173

1

T1

8305

T2

1

T3

1

auto[1]

484480

1

T1

2714

T4

290

T8

186

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	166076	1			T1	5		T2	1		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	377480	1			T1	129		T4	1024		T8	1026
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	70128	1			T1	14		T4	4		T8	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	258351	1			T1	884		T4	210		T8	1831
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	92566	1			T1	6		T4	4		T8	11
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	238869	1			T1	1570		T4	515		T8	133
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	73636	1			T1	6		T8	2		T15	65
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	236066	1			T1	1857		T4	2045		T8	128
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	107372	1			T1	3		T4	6		T15	41
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	241249	1			T1	1031		T4	5		T15	2404
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	73696	1			T1	16		T4	4		T8	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	245302	1			T1	955		T4	1		T8	5874
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	69444	1			T1	5		T4	4		T8	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	240586	1			T1	1125		T4	994		T34	517
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	83082	1			T1	6		T4	10		T8	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	259223	1			T1	645		T4	3368		T8	385
auto[0]	auto[1]	auto[0:524287]	auto[0]	1055	1			T1	1		T4	2		T8	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	88123	1			T4	1		T8	173		T36	133
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	858	1			T1	3		T15	17		T35	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	56807	1			T1	769		T35	5		T39	514
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	918	1			T1	7		T8	2		T39	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	49137	1			T1	257		T8	1		T39	526
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1177	1			T1	4		T15	57		T39	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	61533	1			T1	2		T15	9		T39	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1046	1			T1	5		T4	3		T15	19
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	41059	1			T1	549		T4	257		T15	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	788	1			T1	5		T34	3		T39	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	50047	1			T1	6		T34	1223		T39	128
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	698	1			T4	1		T8	2		T15	22
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	67804	1			T1	512		T8	1		T15	2770
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	967	1			T1	9		T4	1		T15	19
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	56490	1			T1	512		T15	3081		T34	384
auto[1]	auto[0]	auto[0:524287]	auto[0]	592	1			T1	1		T8	2		T13	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	4792	1			T1	1		T8	8		T13	32
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	395	1			T1	1		T4	2		T15	16
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2306	1			T1	4		T4	43		T15	60
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	419	1			T1	2		T8	5		T15	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2752	1			T1	1		T8	5		T39	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	393	1			T1	1		T34	3		T42	18
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2295	1			T1	15		T34	14		T92	9
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	412	1			T1	1		T4	3		T34	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2670	1			T1	1		T4	36		T34	17
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	356	1			T1	3		T4	1		T8	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2540	1			T1	2		T4	28		T8	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	386	1			T1	2		T34	5		T39	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3848	1			T1	5		T34	38		T39	22
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	384	1			T1	3		T4	1		T8	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2507	1			T1	5		T4	21		T34	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	108	1			T4	1		T8	1		T36	5
auto[1]	auto[1]	auto[0:524287]	auto[1]	777	1			T4	7		T8	1		T36	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	103	1			T1	1		T39	2		T17	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	375	1			T1	10		T39	10		T17	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	101	1			T1	1		T8	1		T36	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	440	1			T36	5		T17	11		T41	7
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	158	1			T1	2		T15	13		T41	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1177	1			T1	3		T41	7		T44	22
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	86	1			T1	3		T4	1		T41	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	565	1			T1	50		T4	16		T41	11
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	94	1			T1	1		T34	1		T78	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	623	1			T1	2		T34	6		T78	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	114	1			T8	1		T15	4		T17	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	400	1			T8	1		T200	30		T49	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	143	1			T15	12		T36	3		T78	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	709	1			T15	59		T36	3		T200	14

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2122960	1			T1	8256		T2	1		T3	1
auto[0]	auto[0]	auto[1]	710166	1			T1	1		T4	4		T8	1
auto[0]	auto[1]	auto[0]	476930	1			T1	2638		T4	263		T8	181
auto[0]	auto[1]	auto[1]	1577	1			T1	3		T4	2		T41	1
auto[1]	auto[0]	auto[0]	26422	1			T1	47		T4	131		T8	21
auto[1]	auto[0]	auto[1]	625	1			T1	1		T4	4		T8	2
auto[1]	auto[1]	auto[0]	5842	1			T1	70		T4	24		T8	5
auto[1]	auto[1]	auto[1]	131	1			T1	3		T4	1		T15	4