Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2816721	1			T1	23550		T2	1		T3	1
all_pins[1]	2816721	1			T1	23550		T2	1		T3	1
all_pins[2]	2816721	1			T1	23550		T2	1		T3	1
all_pins[3]	2816721	1			T1	23550		T2	1		T3	1
all_pins[4]	2816721	1			T1	23550		T2	1		T3	1
all_pins[5]	2816721	1			T1	23550		T2	1		T3	1
all_pins[6]	2816721	1			T1	23550		T2	1		T3	1
all_pins[7]	2816721	1			T1	23550		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22531655	1			T1	188390		T2	8		T3	8
values[0x1]	2113	1			T1	10		T17	38		T18	17
transitions[0x0=>0x1]	1738	1			T1	9		T17	22		T18	14
transitions[0x1=>0x0]	1750	1			T1	9		T17	22		T18	15

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2816265	1			T1	23550		T2	1		T3	1
all_pins[0]	values[0x1]	456	1			T17	3		T18	1		T22	4
all_pins[0]	transitions[0x0=>0x1]	380	1			T17	2		T22	2		T29	1
all_pins[0]	transitions[0x1=>0x0]	239	1			T17	3		T18	4		T29	2
all_pins[1]	values[0x0]	2816406	1			T1	23550		T2	1		T3	1
all_pins[1]	values[0x1]	315	1			T17	4		T18	5		T22	2
all_pins[1]	transitions[0x0=>0x1]	242	1			T18	5		T22	2		T29	2
all_pins[1]	transitions[0x1=>0x0]	138	1			T1	1		T17	4		T22	3
all_pins[2]	values[0x0]	2816510	1			T1	23549		T2	1		T3	1
all_pins[2]	values[0x1]	211	1			T1	1		T17	8		T22	3
all_pins[2]	transitions[0x0=>0x1]	157	1			T1	1		T17	5		T22	3
all_pins[2]	transitions[0x1=>0x0]	104	1			T1	4		T17	1		T29	2
all_pins[3]	values[0x0]	2816563	1			T1	23546		T2	1		T3	1
all_pins[3]	values[0x1]	158	1			T1	4		T17	4		T29	2
all_pins[3]	transitions[0x0=>0x1]	115	1			T1	4		T17	4		T158	4
all_pins[3]	transitions[0x1=>0x0]	129	1			T17	1		T18	1		T22	1
all_pins[4]	values[0x0]	2816549	1			T1	23550		T2	1		T3	1
all_pins[4]	values[0x1]	172	1			T17	1		T18	1		T22	1
all_pins[4]	transitions[0x0=>0x1]	142	1			T18	1		T22	1		T29	2
all_pins[4]	transitions[0x1=>0x0]	458	1			T1	2		T17	3		T18	3
all_pins[5]	values[0x0]	2816233	1			T1	23548		T2	1		T3	1
all_pins[5]	values[0x1]	488	1			T1	2		T17	4		T18	3
all_pins[5]	transitions[0x0=>0x1]	472	1			T1	1		T17	2		T18	3
all_pins[5]	transitions[0x1=>0x0]	138	1			T17	6		T18	3		T22	3
all_pins[6]	values[0x0]	2816567	1			T1	23549		T2	1		T3	1
all_pins[6]	values[0x1]	154	1			T1	1		T17	8		T18	3
all_pins[6]	transitions[0x0=>0x1]	116	1			T1	1		T17	4		T18	3
all_pins[6]	transitions[0x1=>0x0]	121	1			T1	2		T17	2		T18	4
all_pins[7]	values[0x0]	2816562	1			T1	23548		T2	1		T3	1
all_pins[7]	values[0x1]	159	1			T1	2		T17	6		T18	4
all_pins[7]	transitions[0x0=>0x1]	114	1			T1	2		T17	5		T18	2
all_pins[7]	transitions[0x1=>0x0]	423	1			T17	2		T22	4		T29	1