Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19410

1

T3

26

T8

78

T13

54

auto[1]

13608

1

T7

2

T8

70

T12

22

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4626	1			T3	26		T8	54		T15	40
values[1]	3781	1			T8	28		T15	40		T34	59
values[2]	3606	1			T8	20		T15	20		T34	37
values[3]	4117	1			T35	20		T41	20		T192	6
values[4]	4037	1			T15	40		T35	20		T41	97
values[5]	4770	1			T7	2		T12	22		T15	20
values[6]	4061	1			T8	22		T34	65		T35	66
values[7]	4020	1			T8	24		T13	54		T15	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3623	1			T12	22		T13	54		T15	20
values[1]	4186	1			T8	20		T15	20		T34	98
values[2]	4424	1			T15	20		T16	12		T34	20
values[3]	3918	1			T15	40		T35	70		T94	20
values[4]	4193	1			T8	57		T15	20		T114	10
values[5]	4853	1			T15	40		T34	87		T57	56
values[6]	3870	1			T3	26		T8	71		T15	20
values[7]	3951	1			T7	2		T15	20		T34	65

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	372	1			T35	13		T44	30		T200	15
auto[0]	values[0]	values[1]	187	1			T49	16		T224	10		T201	25
auto[0]	values[0]	values[2]	378	1			T15	11		T16	12		T91	22
auto[0]	values[0]	values[3]	530	1			T35	13		T94	20		T225	4
auto[0]	values[0]	values[4]	280	1			T8	17		T194	13		T226	12
auto[0]	values[0]	values[5]	288	1			T34	11		T222	2		T227	4
auto[0]	values[0]	values[6]	167	1			T3	26		T8	8		T35	12
auto[0]	values[0]	values[7]	581	1			T15	14		T41	13		T42	12
auto[0]	values[1]	values[0]	276	1			T228	2		T194	12		T28	14
auto[0]	values[1]	values[1]	272	1			T34	50		T42	9		T187	17
auto[0]	values[1]	values[2]	303	1			T93	12		T187	53		T194	9
auto[0]	values[1]	values[3]	318	1			T229	14		T88	10		T28	66
auto[0]	values[1]	values[4]	544	1			T8	13		T202	8		T20	44
auto[0]	values[1]	values[5]	244	1			T15	28		T88	7		T198	8
auto[0]	values[1]	values[6]	197	1			T200	19		T202	13		T20	7
auto[0]	values[1]	values[7]	140	1			T44	27		T20	9		T201	10
auto[0]	values[2]	values[0]	143	1			T187	12		T28	6		T230	13
auto[0]	values[2]	values[1]	230	1			T8	13		T35	10		T187	28
auto[0]	values[2]	values[2]	222	1			T42	16		T77	9		T180	13
auto[0]	values[2]	values[3]	263	1			T15	10		T44	14		T231	4
auto[0]	values[2]	values[4]	90	1			T29	10		T170	8		T196	11
auto[0]	values[2]	values[5]	498	1			T34	31		T210	12		T232	11
auto[0]	values[2]	values[6]	193	1			T41	31		T88	6		T199	10
auto[0]	values[2]	values[7]	311	1			T194	13		T233	4		T21	10
auto[0]	values[3]	values[0]	220	1			T192	6		T200	10		T194	10
auto[0]	values[3]	values[1]	266	1			T44	11		T180	11		T88	14
auto[0]	values[3]	values[2]	345	1			T35	5		T234	14		T200	79
auto[0]	values[3]	values[3]	341	1			T193	18		T235	4		T236	57
auto[0]	values[3]	values[4]	550	1			T42	10		T200	47		T194	17
auto[0]	values[3]	values[5]	318	1			T41	18		T194	11		T21	5
auto[0]	values[3]	values[6]	330	1			T21	63		T237	4		T201	31
auto[0]	values[3]	values[7]	173	1			T210	3		T28	24		T207	11
auto[0]	values[4]	values[0]	385	1			T15	5		T42	11		T232	14
auto[0]	values[4]	values[1]	311	1			T15	13		T35	9		T44	12
auto[0]	values[4]	values[2]	298	1			T200	67		T194	18		T170	10
auto[0]	values[4]	values[3]	151	1			T20	39		T29	19		T130	11
auto[0]	values[4]	values[4]	226	1			T200	7		T238	6		T69	17
auto[0]	values[4]	values[5]	287	1			T203	8		T88	6		T206	18
auto[0]	values[4]	values[6]	211	1			T41	23		T189	10		T42	13
auto[0]	values[4]	values[7]	359	1			T44	39		T69	16		T28	63
auto[0]	values[5]	values[0]	205	1			T34	11		T89	10		T212	12
auto[0]	values[5]	values[1]	501	1			T41	41		T194	9		T198	11
auto[0]	values[5]	values[2]	373	1			T34	11		T77	73		T200	13
auto[0]	values[5]	values[3]	296	1			T58	10		T41	21		T42	12
auto[0]	values[5]	values[4]	360	1			T202	61		T21	16		T206	14
auto[0]	values[5]	values[5]	316	1			T57	56		T42	21		T200	9
auto[0]	values[5]	values[6]	498	1			T15	13		T77	114		T180	15
auto[0]	values[5]	values[7]	208	1			T20	25		T217	8		T239	6
auto[0]	values[6]	values[0]	244	1			T200	18		T210	10		T20	11
auto[0]	values[6]	values[1]	269	1			T86	2		T42	12		T77	9
auto[0]	values[6]	values[2]	318	1			T35	21		T41	18		T219	11
auto[0]	values[6]	values[3]	195	1			T35	12		T42	11		T77	50
auto[0]	values[6]	values[4]	538	1			T200	11		T210	11		T28	178
auto[0]	values[6]	values[5]	275	1			T77	123		T203	9		T240	4
auto[0]	values[6]	values[6]	178	1			T8	11		T44	10		T180	14
auto[0]	values[6]	values[7]	348	1			T34	17		T44	17		T202	17
auto[0]	values[7]	values[0]	283	1			T13	54		T241	6		T20	5
auto[0]	values[7]	values[1]	305	1			T34	28		T44	14		T202	10
auto[0]	values[7]	values[2]	296	1			T42	12		T77	12		T180	12
auto[0]	values[7]	values[3]	334	1			T15	11		T35	11		T44	28
auto[0]	values[7]	values[4]	222	1			T15	8		T114	10		T242	8
auto[0]	values[7]	values[5]	375	1			T41	11		T243	6		T49	24
auto[0]	values[7]	values[6]	253	1			T8	16		T21	4		T49	13
auto[0]	values[7]	values[7]	422	1			T244	30		T202	15		T204	12
auto[1]	values[0]	values[0]	193	1			T35	7		T44	13		T200	5
auto[1]	values[0]	values[1]	184	1			T49	16		T224	10		T201	15
auto[1]	values[0]	values[2]	174	1			T15	9		T224	9		T28	77
auto[1]	values[0]	values[3]	290	1			T35	7		T77	4		T200	20
auto[1]	values[0]	values[4]	158	1			T8	12		T194	7		T21	9
auto[1]	values[0]	values[5]	371	1			T34	39		T44	41		T20	7
auto[1]	values[0]	values[6]	334	1			T8	17		T35	8		T219	15
auto[1]	values[0]	values[7]	139	1			T15	6		T41	7		T42	8
auto[1]	values[1]	values[0]	180	1			T194	8		T28	35		T236	16
auto[1]	values[1]	values[1]	177	1			T34	9		T42	11		T187	7
auto[1]	values[1]	values[2]	176	1			T187	8		T194	11		T202	7
auto[1]	values[1]	values[3]	130	1			T88	10		T28	7		T201	17
auto[1]	values[1]	values[4]	266	1			T8	15		T202	12		T20	23
auto[1]	values[1]	values[5]	284	1			T15	12		T88	13		T198	12
auto[1]	values[1]	values[6]	167	1			T200	21		T202	10		T20	18
auto[1]	values[1]	values[7]	107	1			T44	7		T245	8		T20	11
auto[1]	values[2]	values[0]	189	1			T187	18		T28	14		T230	7
auto[1]	values[2]	values[1]	181	1			T8	7		T35	12		T187	10
auto[1]	values[2]	values[2]	340	1			T42	4		T77	129		T180	7
auto[1]	values[2]	values[3]	220	1			T15	10		T44	39		T20	8
auto[1]	values[2]	values[4]	91	1			T29	11		T170	12		T196	9
auto[1]	values[2]	values[5]	248	1			T34	6		T210	8		T232	17
auto[1]	values[2]	values[6]	145	1			T41	10		T88	14		T199	11
auto[1]	values[2]	values[7]	242	1			T194	7		T21	10		T50	8
auto[1]	values[3]	values[0]	148	1			T200	25		T194	10		T202	7
auto[1]	values[3]	values[1]	184	1			T44	9		T180	9		T88	6
auto[1]	values[3]	values[2]	227	1			T35	15		T200	38		T198	11
auto[1]	values[3]	values[3]	80	1			T236	4		T199	12		T246	11
auto[1]	values[3]	values[4]	201	1			T42	10		T200	6		T188	8
auto[1]	values[3]	values[5]	369	1			T41	2		T194	9		T21	34
auto[1]	values[3]	values[6]	254	1			T21	8		T201	41		T247	14
auto[1]	values[3]	values[7]	111	1			T210	17		T28	20		T207	9
auto[1]	values[4]	values[0]	288	1			T15	15		T42	9		T232	6
auto[1]	values[4]	values[1]	362	1			T15	7		T35	11		T44	15
auto[1]	values[4]	values[2]	142	1			T200	6		T194	2		T170	10
auto[1]	values[4]	values[3]	80	1			T20	23		T29	10		T130	9
auto[1]	values[4]	values[4]	114	1			T200	13		T69	6		T224	10
auto[1]	values[4]	values[5]	363	1			T248	16		T203	12		T88	14
auto[1]	values[4]	values[6]	275	1			T41	74		T42	7		T194	8
auto[1]	values[4]	values[7]	185	1			T44	13		T69	4		T28	6
auto[1]	values[5]	values[0]	216	1			T12	22		T34	54		T212	8
auto[1]	values[5]	values[1]	322	1			T41	8		T213	22		T194	11
auto[1]	values[5]	values[2]	391	1			T34	9		T77	8		T200	133
auto[1]	values[5]	values[3]	354	1			T41	9		T42	8		T194	10
auto[1]	values[5]	values[4]	197	1			T202	4		T21	4		T206	50
auto[1]	values[5]	values[5]	132	1			T42	19		T200	11		T187	16
auto[1]	values[5]	values[6]	192	1			T15	7		T77	12		T180	5
auto[1]	values[5]	values[7]	209	1			T7	2		T20	10		T217	12
auto[1]	values[6]	values[0]	191	1			T43	6		T200	2		T210	10
auto[1]	values[6]	values[1]	192	1			T42	8		T77	11		T49	21
auto[1]	values[6]	values[2]	259	1			T35	19		T41	2		T219	9
auto[1]	values[6]	values[3]	105	1			T35	14		T42	9		T77	3
auto[1]	values[6]	values[4]	171	1			T200	34		T210	9		T28	13
auto[1]	values[6]	values[5]	227	1			T77	12		T203	75		T159	18
auto[1]	values[6]	values[6]	275	1			T8	11		T44	10		T180	6
auto[1]	values[6]	values[7]	276	1			T34	48		T44	7		T202	13
auto[1]	values[7]	values[0]	90	1			T20	15		T249	7		T199	10
auto[1]	values[7]	values[1]	243	1			T34	11		T44	6		T202	21
auto[1]	values[7]	values[2]	182	1			T42	8		T77	52		T180	8
auto[1]	values[7]	values[3]	231	1			T15	9		T35	13		T44	5
auto[1]	values[7]	values[4]	185	1			T15	12		T29	13		T199	9
auto[1]	values[7]	values[5]	258	1			T41	9		T250	10		T49	9
auto[1]	values[7]	values[6]	201	1			T8	8		T40	24		T21	16
auto[1]	values[7]	values[7]	140	1			T202	5		T50	8		T201	18