Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	430	1			T8	1		T15	3		T34	4
auto[ReadAddrCrossIntoMailbox]	353	1			T8	3		T15	4		T34	5
auto[ReadAddrCrossOutOfMailbox]	328	1			T8	1		T15	4		T34	2
auto[ReadAddrCrossAllMailbox]	200	1			T8	1		T42	3		T44	3
auto[ReadAddrOutsideMailbox]	3764	1			T3	6		T8	10		T12	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2450

1

T3

3

T8

10

T12

3

auto[1]

2625

1

T3

3

T8

6

T12

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	861	1			T8	3		T12	2		T15	6
read_ops[0x0b]	858	1			T8	5		T12	2		T15	5
read_ops[0x3b]	813	1			T8	3		T15	12		T16	2
read_ops[0x6b]	862	1			T3	4		T8	1		T15	7
read_ops[0xbb]	843	1			T3	2		T8	3		T12	2
read_ops[0xeb]	838	1			T8	1		T15	3		T34	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T34	1		T42	1		T193	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T193	2		T44	1		T200	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T8	1		T15	1		T194	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T210	2		T203	1		T88	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T8	1		T194	2		T210	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T42	1		T44	2		T194	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T42	1		T194	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T44	1		T88	1		T236	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	344	1			T12	1		T15	1		T16	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T8	1		T12	1		T15	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T34	1		T234	1		T194	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T41	2		T42	2		T234	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T8	1		T34	2		T234	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T34	1		T234	1		T194	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T42	1		T20	2		T88	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T15	2		T34	1		T42	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T194	1		T201	4		T199	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T44	1		T21	1		T69	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T8	4		T12	1		T34	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	332	1			T12	1		T15	3		T34	6
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T15	1		T41	2		T42	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T8	1		T42	1		T44	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T8	1		T42	1		T202	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T15	3		T34	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T15	1		T41	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T35	1		T200	1		T187	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T194	1		T202	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T42	1		T77	1		T211	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T15	2		T16	1		T34	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T8	1		T15	5		T16	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T77	2		T203	1		T88	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	49	1			T15	2		T180	1		T20	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T44	1		T200	1		T203	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	43	1			T44	1		T200	1		T180	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T200	2		T88	2		T251	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T15	1		T42	3		T202	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T194	1		T202	1		T219	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T42	1		T201	1		T230	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T3	2		T8	1		T15	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T3	2		T15	2		T34	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T34	1		T44	2		T77	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T35	2		T194	1		T206	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T34	1		T42	1		T202	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T42	2		T194	1		T219	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T34	1		T200	2		T194	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T187	1		T21	1		T201	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T210	1		T242	1		T251	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T8	1		T44	1		T242	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	321	1			T3	1		T12	1		T15	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T3	1		T8	2		T12	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T34	1		T41	2		T42	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T41	1		T42	1		T193	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T42	1		T77	1		T200	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T41	1		T42	1		T69	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T180	1		T20	2		T88	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T44	1		T251	2		T206	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T210	1		T21	1		T88	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T210	1		T69	2		T29	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	282	1			T8	1		T15	3		T34	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	347	1			T34	2		T35	2		T93	2