Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4799	1			T8	24		T15	40		T41	41
values[1]	3897	1			T8	28		T15	60		T35	40
values[2]	3807	1			T8	42		T15	20		T34	59
values[3]	4079	1			T7	2		T12	22		T15	40
values[4]	3893	1			T34	82		T41	20		T222	2
values[5]	3993	1			T8	25		T15	20		T35	42
values[6]	3995	1			T13	54		T15	20		T34	174
values[7]	4555	1			T3	26		T8	29		T16	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4142	1			T15	20		T34	50		T35	22
values[1]	4160	1			T13	54		T15	20		T34	22
values[2]	4019	1			T15	40		T34	20		T35	40
values[3]	4129	1			T15	20		T34	59		T35	24
values[4]	4039	1			T3	26		T8	24		T15	40
values[5]	4678	1			T8	25		T15	20		T89	10
values[6]	3329	1			T8	99		T12	22		T15	20
values[7]	4522	1			T7	2		T15	20		T34	145

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32234

1

T3

26

T8

140

T12

22

auto[1]

784

1

T7

2

T8

8

T15

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	485	1			T244	30		T225	4		T187	37
auto[0]	values[0]	values[1]	603	1			T77	20		T235	4		T198	50
auto[0]	values[0]	values[2]	575	1			T187	24		T236	28		T201	49
auto[0]	values[0]	values[3]	605	1			T200	78		T194	20		T202	30
auto[0]	values[0]	values[4]	686	1			T8	22		T15	20		T193	18
auto[0]	values[0]	values[5]	633	1			T41	41		T42	20		T200	71
auto[0]	values[0]	values[6]	534	1			T210	61		T217	19		T212	20
auto[0]	values[0]	values[7]	558	1			T15	20		T192	6		T200	39
auto[0]	values[1]	values[0]	828	1			T42	20		T250	10		T194	23
auto[0]	values[1]	values[1]	850	1			T15	18		T35	20		T42	18
auto[0]	values[1]	values[2]	326	1			T15	20		T35	20		T42	39
auto[0]	values[1]	values[3]	362	1			T15	19		T41	75		T44	26
auto[0]	values[1]	values[4]	377	1			T94	20		T41	48		T210	20
auto[0]	values[1]	values[5]	282	1			T245	6		T194	20		T211	52
auto[0]	values[1]	values[6]	309	1			T8	26		T188	8		T21	25
auto[0]	values[1]	values[7]	462	1			T187	36		T20	25		T21	20
auto[0]	values[2]	values[0]	396	1			T42	20		T219	19		T29	20
auto[0]	values[2]	values[1]	482	1			T34	22		T35	20		T21	32
auto[0]	values[2]	values[2]	396	1			T15	20		T49	31		T209	12
auto[0]	values[2]	values[3]	358	1			T40	22		T42	18		T44	33
auto[0]	values[2]	values[4]	737	1			T41	19		T42	20		T200	20
auto[0]	values[2]	values[5]	662	1			T35	20		T189	10		T77	106
auto[0]	values[2]	values[6]	266	1			T8	42		T241	6		T252	4
auto[0]	values[2]	values[7]	432	1			T34	36		T44	43		T213	22
auto[0]	values[3]	values[0]	406	1			T77	20		T202	30		T21	20
auto[0]	values[3]	values[1]	365	1			T58	10		T200	20		T20	20
auto[0]	values[3]	values[2]	517	1			T41	20		T200	28		T187	61
auto[0]	values[3]	values[3]	408	1			T35	24		T187	17		T194	20
auto[0]	values[3]	values[4]	350	1			T15	20		T77	78		T200	20
auto[0]	values[3]	values[5]	760	1			T77	75		T20	40		T21	70
auto[0]	values[3]	values[6]	558	1			T12	22		T15	18		T86	2
auto[0]	values[3]	values[7]	582	1			T202	19		T29	21		T201	45
auto[0]	values[4]	values[0]	352	1			T194	38		T253	14		T158	72
auto[0]	values[4]	values[1]	278	1			T194	20		T210	20		T232	20
auto[0]	values[4]	values[2]	529	1			T222	2		T42	19		T200	20
auto[0]	values[4]	values[3]	547	1			T44	48		T77	136		T200	33
auto[0]	values[4]	values[4]	394	1			T34	39		T44	20		T234	14
auto[0]	values[4]	values[5]	521	1			T42	19		T180	18		T202	19
auto[0]	values[4]	values[6]	447	1			T41	20		T229	14		T227	4
auto[0]	values[4]	values[7]	743	1			T34	43		T44	19		T88	18
auto[0]	values[5]	values[0]	415	1			T35	21		T77	81		T88	20
auto[0]	values[5]	values[1]	323	1			T42	20		T202	19		T20	23
auto[0]	values[5]	values[2]	668	1			T202	63		T237	4		T224	20
auto[0]	values[5]	values[3]	496	1			T254	14		T255	78		T190	29
auto[0]	values[5]	values[4]	441	1			T77	20		T180	20		T194	20
auto[0]	values[5]	values[5]	796	1			T8	23		T15	20		T57	56
auto[0]	values[5]	values[6]	256	1			T44	24		T77	20		T210	20
auto[0]	values[5]	values[7]	526	1			T35	20		T77	39		T194	19
auto[0]	values[6]	values[0]	440	1			T15	20		T34	50		T77	59
auto[0]	values[6]	values[1]	488	1			T13	54		T93	12		T43	4
auto[0]	values[6]	values[2]	413	1			T35	19		T206	27		T28	20
auto[0]	values[6]	values[3]	778	1			T34	56		T88	20		T28	20
auto[0]	values[6]	values[4]	467	1			T42	20		T187	62		T49	43
auto[0]	values[6]	values[5]	464	1			T41	39		T220	4		T210	20
auto[0]	values[6]	values[6]	273	1			T210	20		T226	12		T256	2
auto[0]	values[6]	values[7]	577	1			T34	62		T77	110		T210	54
auto[0]	values[7]	values[0]	736	1			T228	2		T180	38		T88	17
auto[0]	values[7]	values[1]	684	1			T114	10		T200	20		T202	31
auto[0]	values[7]	values[2]	501	1			T34	20		T41	28		T20	34
auto[0]	values[7]	values[3]	455	1			T44	20		T194	20		T20	22
auto[0]	values[7]	values[4]	476	1			T3	26		T91	22		T202	54
auto[0]	values[7]	values[5]	452	1			T89	10		T35	24		T194	18
auto[0]	values[7]	values[6]	616	1			T8	27		T16	12		T77	53
auto[0]	values[7]	values[7]	532	1			T35	20		T200	143		T201	39
auto[1]	values[0]	values[0]	13	1			T187	1		T206	1		T69	1
auto[1]	values[0]	values[1]	8	1			T198	1		T257	1		T258	2
auto[1]	values[0]	values[2]	11	1			T201	1		T199	1		T259	1
auto[1]	values[0]	values[3]	25	1			T194	1		T202	2		T207	2
auto[1]	values[0]	values[4]	27	1			T8	2		T44	3		T20	3
auto[1]	values[0]	values[5]	13	1			T200	2		T255	1		T196	2
auto[1]	values[0]	values[6]	9	1			T217	1		T88	1		T28	1
auto[1]	values[0]	values[7]	14	1			T219	4		T28	2		T50	3
auto[1]	values[1]	values[0]	13	1			T194	2		T203	1		T206	1
auto[1]	values[1]	values[1]	27	1			T15	2		T42	2		T217	2
auto[1]	values[1]	values[2]	11	1			T42	1		T69	2		T28	2
auto[1]	values[1]	values[3]	11	1			T15	1		T41	2		T44	1
auto[1]	values[1]	values[4]	8	1			T41	1		T21	4		T201	1
auto[1]	values[1]	values[5]	10	1			T245	2		T260	2		T54	1
auto[1]	values[1]	values[6]	8	1			T8	2		T261	4		T262	1
auto[1]	values[1]	values[7]	13	1			T207	2		T196	2		T191	1
auto[1]	values[2]	values[0]	7	1			T219	1		T263	2		T264	1
auto[1]	values[2]	values[1]	10	1			T21	1		T198	2		T50	1
auto[1]	values[2]	values[2]	16	1			T49	2		T209	2		T230	1
auto[1]	values[2]	values[3]	10	1			T40	2		T42	2		T201	1
auto[1]	values[2]	values[4]	14	1			T41	1		T20	1		T219	1
auto[1]	values[2]	values[5]	10	1			T199	1		T196	2		T30	1
auto[1]	values[2]	values[6]	6	1			T249	1		T265	2		T266	3
auto[1]	values[2]	values[7]	5	1			T34	1		T187	1		T267	1
auto[1]	values[3]	values[0]	8	1			T203	2		T268	2		T269	1
auto[1]	values[3]	values[1]	10	1			T224	2		T54	1		T270	2
auto[1]	values[3]	values[2]	11	1			T200	1		T29	1		T170	2
auto[1]	values[3]	values[3]	28	1			T187	5		T20	4		T130	2
auto[1]	values[3]	values[4]	17	1			T77	3		T219	2		T201	1
auto[1]	values[3]	values[5]	22	1			T77	1		T21	1		T29	3
auto[1]	values[3]	values[6]	17	1			T15	2		T44	3		T88	2
auto[1]	values[3]	values[7]	20	1			T7	2		T202	1		T29	1
auto[1]	values[4]	values[0]	6	1			T194	2		T170	3		T263	1
auto[1]	values[4]	values[1]	3	1			T49	1		T69	1		T230	1
auto[1]	values[4]	values[2]	13	1			T42	1		T180	1		T199	1
auto[1]	values[4]	values[3]	11	1			T77	2		T200	2		T271	1
auto[1]	values[4]	values[4]	8	1			T187	1		T207	2		T272	2
auto[1]	values[4]	values[5]	19	1			T42	1		T180	2		T202	1
auto[1]	values[4]	values[6]	4	1			T20	1		T273	1		T274	1
auto[1]	values[4]	values[7]	18	1			T44	1		T88	2		T28	3
auto[1]	values[5]	values[0]	13	1			T35	1		T272	1		T275	2
auto[1]	values[5]	values[1]	4	1			T202	1		T196	1		T276	2
auto[1]	values[5]	values[2]	11	1			T202	2		T50	2		T29	1
auto[1]	values[5]	values[3]	7	1			T277	1		T278	2		T265	1
auto[1]	values[5]	values[4]	10	1			T194	2		T210	2		T190	3
auto[1]	values[5]	values[5]	11	1			T8	2		T44	2		T202	1
auto[1]	values[5]	values[6]	4	1			T279	3		T280	1		-	-
auto[1]	values[5]	values[7]	12	1			T77	2		T194	1		T219	1
auto[1]	values[6]	values[0]	3	1			T255	1		T281	2		-	-
auto[1]	values[6]	values[1]	12	1			T43	2		T202	2		T29	4
auto[1]	values[6]	values[2]	8	1			T35	1		T201	3		T128	3
auto[1]	values[6]	values[3]	19	1			T34	3		T236	2		T282	1
auto[1]	values[6]	values[4]	17	1			T187	2		T49	3		T28	1
auto[1]	values[6]	values[5]	11	1			T41	1		T49	2		T28	3
auto[1]	values[6]	values[6]	9	1			T88	2		T255	2		T54	1
auto[1]	values[6]	values[7]	16	1			T34	3		T77	3		T210	2
auto[1]	values[7]	values[0]	21	1			T180	2		T88	3		T28	2
auto[1]	values[7]	values[1]	13	1			T29	2		T255	2		T159	1
auto[1]	values[7]	values[2]	13	1			T41	2		T20	1		T28	1
auto[1]	values[7]	values[3]	9	1			T198	1		T267	4		T269	2
auto[1]	values[7]	values[4]	10	1			T49	1		T201	2		T283	3
auto[1]	values[7]	values[5]	12	1			T35	2		T194	2		T88	2
auto[1]	values[7]	values[6]	13	1			T8	2		T200	2		T201	2
auto[1]	values[7]	values[7]	12	1			T200	3		T201	1		T272	2