Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	667	1			T1	7		T17	14		T18	11
all_values[1]	667	1			T1	7		T17	14		T18	11
all_values[2]	667	1			T1	7		T17	14		T18	11
all_values[3]	667	1			T1	7		T17	14		T18	11
all_values[4]	667	1			T1	7		T17	14		T18	11
all_values[5]	667	1			T1	7		T17	14		T18	11
all_values[6]	667	1			T1	7		T17	14		T18	11
all_values[7]	667	1			T1	7		T17	14		T18	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2804

1

T1

28

T17

46

T18

51

auto[1]

2532

1

T1

28

T17

66

T18

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2141

1

T1

25

T17

35

T18

43

auto[1]

3195

1

T1

31

T17

77

T18

45

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3047

1

T1

35

T17

56

T18

57

auto[1]

2289

1

T1

21

T17

56

T18

31

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	135	1			T1	2		T17	4		T18	5
all_values[0]	auto[0]	auto[0]	auto[1]	59	1			T17	1		T134	1		T159	1
all_values[0]	auto[0]	auto[1]	auto[0]	124	1			T1	4		T17	2		T18	2
all_values[0]	auto[0]	auto[1]	auto[1]	56	1			T18	1		T22	2		T29	1
all_values[0]	auto[1]	auto[0]	auto[1]	150	1			T17	3		T18	2		T22	3
all_values[0]	auto[1]	auto[1]	auto[1]	143	1			T1	1		T17	4		T18	1
all_values[1]	auto[0]	auto[0]	auto[0]	153	1			T1	1		T17	4		T18	1
all_values[1]	auto[0]	auto[0]	auto[1]	54	1			T1	2		T17	1		T18	2
all_values[1]	auto[0]	auto[1]	auto[0]	121	1			T18	1		T158	2		T134	1
all_values[1]	auto[0]	auto[1]	auto[1]	65	1			T1	1		T17	2		T18	4
all_values[1]	auto[1]	auto[0]	auto[1]	156	1			T1	3		T17	4		T18	3
all_values[1]	auto[1]	auto[1]	auto[1]	118	1			T17	3		T22	1		T29	1
all_values[2]	auto[0]	auto[0]	auto[0]	143	1			T17	1		T18	6		T22	3
all_values[2]	auto[0]	auto[0]	auto[1]	60	1			T29	1		T134	1		T160	4
all_values[2]	auto[0]	auto[1]	auto[0]	100	1			T1	3		T17	1		T18	4
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T1	1		T17	4		T22	1
all_values[2]	auto[1]	auto[0]	auto[1]	138	1			T1	1		T17	2		T22	1
all_values[2]	auto[1]	auto[1]	auto[1]	156	1			T1	2		T17	6		T18	1
all_values[3]	auto[0]	auto[0]	auto[0]	128	1			T1	2		T18	6		T22	4
all_values[3]	auto[0]	auto[0]	auto[1]	70	1			T17	2		T29	1		T158	3
all_values[3]	auto[0]	auto[1]	auto[0]	112	1			T17	3		T18	2		T22	2
all_values[3]	auto[0]	auto[1]	auto[1]	65	1			T1	2		T17	2		T29	1
all_values[3]	auto[1]	auto[0]	auto[1]	153	1			T17	3		T18	3		T22	4
all_values[3]	auto[1]	auto[1]	auto[1]	139	1			T1	3		T17	4		T158	3
all_values[4]	auto[0]	auto[0]	auto[0]	109	1			T1	1		T17	1		T18	1
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T1	1		T17	2		T18	3
all_values[4]	auto[0]	auto[1]	auto[0]	111	1			T1	2		T17	6		T18	3
all_values[4]	auto[0]	auto[1]	auto[1]	63	1			T29	1		T134	1		T159	1
all_values[4]	auto[1]	auto[0]	auto[1]	145	1			T1	3		T17	2		T18	2
all_values[4]	auto[1]	auto[1]	auto[1]	163	1			T17	3		T18	2		T22	3
all_values[5]	auto[0]	auto[0]	auto[0]	246	1			T1	4		T17	4		T18	2
all_values[5]	auto[0]	auto[1]	auto[0]	160	1			T1	1		T17	3		T18	3
all_values[5]	auto[1]	auto[0]	auto[1]	133	1			T17	1		T18	3		T22	3
all_values[5]	auto[1]	auto[1]	auto[1]	128	1			T1	2		T17	6		T18	3
all_values[6]	auto[0]	auto[0]	auto[0]	132	1			T1	2		T17	2		T18	2
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T1	2		T158	1		T159	1
all_values[6]	auto[0]	auto[1]	auto[0]	123	1			T1	1		T17	1		T18	2
all_values[6]	auto[0]	auto[1]	auto[1]	67	1			T17	2		T18	1		T22	2
all_values[6]	auto[1]	auto[0]	auto[1]	157	1			T1	1		T17	5		T18	5
all_values[6]	auto[1]	auto[1]	auto[1]	124	1			T1	1		T17	4		T18	1
all_values[7]	auto[0]	auto[0]	auto[0]	120	1			T1	1		T18	1		T22	2
all_values[7]	auto[0]	auto[0]	auto[1]	66	1			T1	1		T17	1		T18	2
all_values[7]	auto[0]	auto[1]	auto[0]	124	1			T1	1		T17	3		T18	2
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T17	4		T18	1		T158	1
all_values[7]	auto[1]	auto[0]	auto[1]	157	1			T1	1		T17	3		T18	2
all_values[7]	auto[1]	auto[1]	auto[1]	129	1			T1	3		T17	3		T18	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal