Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1674

1

T1

8

T5

13

T6

4

auto[1]

1636

1

T1

13

T5

16

T6

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1710

1

T1

17

T9

1

T10

8

auto[1]

1600

1

T1

4

T5

29

T6

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2643

1

T1

9

T5

29

T6

13

auto[1]

667

1

T1

12

T9

1

T10

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	672	1			T1	3		T5	5		T6	3
valid[1]	618	1			T1	3		T5	5		T6	2
valid[2]	658	1			T1	1		T5	9		T6	5
valid[3]	659	1			T1	5		T5	6		T6	2
valid[4]	703	1			T1	9		T5	4		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	99	1			T24	1		T39	1		T307	1
auto[0]	auto[0]	valid[0]	auto[1]	167	1			T5	2		T23	2		T35	1
auto[0]	auto[0]	valid[1]	auto[0]	97	1			T24	1		T45	1		T35	1
auto[0]	auto[0]	valid[1]	auto[1]	155	1			T5	2		T6	1		T10	1
auto[0]	auto[0]	valid[2]	auto[0]	105	1			T24	3		T39	1		T307	1
auto[0]	auto[0]	valid[2]	auto[1]	151	1			T5	5		T6	2		T23	2
auto[0]	auto[0]	valid[3]	auto[0]	126	1			T45	1		T35	1		T39	1
auto[0]	auto[0]	valid[3]	auto[1]	169	1			T1	1		T5	4		T6	1
auto[0]	auto[0]	valid[4]	auto[0]	94	1			T1	2		T10	1		T24	2
auto[0]	auto[0]	valid[4]	auto[1]	169	1			T10	2		T23	1		T26	2
auto[0]	auto[1]	valid[0]	auto[0]	104	1			T10	1		T24	2		T45	1
auto[0]	auto[1]	valid[0]	auto[1]	167	1			T5	3		T6	3		T23	1
auto[0]	auto[1]	valid[1]	auto[0]	100	1			T1	1		T10	2		T24	1
auto[0]	auto[1]	valid[1]	auto[1]	131	1			T5	3		T6	1		T10	1
auto[0]	auto[1]	valid[2]	auto[0]	113	1			T35	1		T300	2		T17	1
auto[0]	auto[1]	valid[2]	auto[1]	174	1			T1	1		T5	4		T6	3
auto[0]	auto[1]	valid[3]	auto[0]	72	1			T39	1		T300	1		T194	1
auto[0]	auto[1]	valid[3]	auto[1]	175	1			T1	1		T5	2		T6	1
auto[0]	auto[1]	valid[4]	auto[0]	133	1			T1	2		T48	2		T35	1
auto[0]	auto[1]	valid[4]	auto[1]	142	1			T1	1		T5	4		T6	1
auto[1]	auto[0]	valid[0]	auto[0]	70	1			T1	1		T10	1		T25	1
auto[1]	auto[0]	valid[1]	auto[0]	63	1			T10	1		T45	1		T48	1
auto[1]	auto[0]	valid[2]	auto[0]	61	1			T48	1		T78	1		T216	1
auto[1]	auto[0]	valid[3]	auto[0]	61	1			T1	1		T17	1		T78	1
auto[1]	auto[0]	valid[4]	auto[0]	87	1			T1	3		T9	1		T10	1
auto[1]	auto[1]	valid[0]	auto[0]	65	1			T1	2		T24	1		T45	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T1	2		T10	1		T45	2
auto[1]	auto[1]	valid[2]	auto[0]	54	1			T48	1		T35	1		T39	1
auto[1]	auto[1]	valid[3]	auto[0]	56	1			T1	2		T24	1		T48	1
auto[1]	auto[1]	valid[4]	auto[0]	78	1			T1	1		T24	1		T25	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal