Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45837

1

T1

492

T8

75

T9

7

auto[1]

16085

1

T1

108

T5

279

T6

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45155

1

T1

422

T5

279

T6

13

auto[1]

16767

1

T1

178

T8

16

T9

5

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31973	1			T1	305		T5	146		T6	13
others[1]	5209	1			T1	49		T5	27		T8	4
others[2]	5249	1			T1	56		T5	26		T8	7
others[3]	5839	1			T1	52		T5	26		T8	8
interest[1]	3389	1			T1	37		T5	11		T8	1
interest[4]	21109	1			T1	195		T5	103		T6	13
interest[64]	10263	1			T1	101		T5	43		T8	14

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14910	1			T1	153		T8	30		T10	53
auto[0]	auto[0]	others[1]	2519	1			T1	29		T8	4		T10	16
auto[0]	auto[0]	others[2]	2443	1			T1	29		T8	5		T10	11
auto[0]	auto[0]	others[3]	2711	1			T1	31		T8	7		T9	1
auto[0]	auto[0]	interest[1]	1605	1			T1	18		T8	1		T10	12
auto[0]	auto[0]	interest[4]	9810	1			T1	99		T8	20		T10	42
auto[0]	auto[0]	interest[64]	4882	1			T1	54		T8	12		T9	1
auto[0]	auto[1]	others[0]	8491	1			T1	63		T5	146		T6	13
auto[0]	auto[1]	others[1]	1302	1			T1	6		T5	27		T10	2
auto[0]	auto[1]	others[2]	1322	1			T1	9		T5	26		T10	2
auto[0]	auto[1]	others[3]	1491	1			T1	6		T5	26		T10	3
auto[0]	auto[1]	interest[1]	875	1			T1	8		T5	11		T10	4
auto[0]	auto[1]	interest[4]	5705	1			T1	42		T5	103		T6	13
auto[0]	auto[1]	interest[64]	2604	1			T1	16		T5	43		T10	8
auto[1]	auto[0]	others[0]	8572	1			T1	89		T8	11		T9	3
auto[1]	auto[0]	others[1]	1388	1			T1	14		T10	6		T24	10
auto[1]	auto[0]	others[2]	1484	1			T1	18		T8	2		T10	9
auto[1]	auto[0]	others[3]	1637	1			T1	15		T8	1		T9	1
auto[1]	auto[0]	interest[1]	909	1			T1	11		T10	7		T24	11
auto[1]	auto[0]	interest[4]	5594	1			T1	54		T8	8		T9	1
auto[1]	auto[0]	interest[64]	2777	1			T1	31		T8	2		T9	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal