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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html

T1036 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3327474612 Jun 29 05:27:02 PM PDT 24 Jun 29 05:27:04 PM PDT 24 13857006 ps
T1037 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.875097922 Jun 29 05:26:54 PM PDT 24 Jun 29 05:26:55 PM PDT 24 11629582 ps
T1038 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1639273204 Jun 29 05:27:00 PM PDT 24 Jun 29 05:27:02 PM PDT 24 222710359 ps
T1039 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2139920631 Jun 29 05:26:59 PM PDT 24 Jun 29 05:27:00 PM PDT 24 13938021 ps
T119 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3679751224 Jun 29 05:26:31 PM PDT 24 Jun 29 05:27:06 PM PDT 24 541967364 ps
T1040 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.842963566 Jun 29 05:26:55 PM PDT 24 Jun 29 05:26:56 PM PDT 24 22646593 ps
T143 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4229061749 Jun 29 05:27:00 PM PDT 24 Jun 29 05:27:02 PM PDT 24 149337314 ps
T153 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4125238398 Jun 29 05:26:54 PM PDT 24 Jun 29 05:27:03 PM PDT 24 1341709429 ps
T120 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1194524177 Jun 29 05:26:48 PM PDT 24 Jun 29 05:26:58 PM PDT 24 363174805 ps
T1041 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.153132082 Jun 29 05:27:01 PM PDT 24 Jun 29 05:27:03 PM PDT 24 12082117 ps
T121 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1975479430 Jun 29 05:27:01 PM PDT 24 Jun 29 05:27:05 PM PDT 24 204932199 ps
T106 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1856540335 Jun 29 05:26:51 PM PDT 24 Jun 29 05:26:54 PM PDT 24 160048170 ps
T113 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.315217663 Jun 29 05:26:53 PM PDT 24 Jun 29 05:26:57 PM PDT 24 102835148 ps
T1042 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.902304048 Jun 29 05:27:09 PM PDT 24 Jun 29 05:27:11 PM PDT 24 42136232 ps
T173 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2003066182 Jun 29 05:26:59 PM PDT 24 Jun 29 05:27:13 PM PDT 24 213956797 ps
T122 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3291053532 Jun 29 05:27:03 PM PDT 24 Jun 29 05:27:06 PM PDT 24 82866203 ps
T110 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1513692877 Jun 29 05:26:41 PM PDT 24 Jun 29 05:26:47 PM PDT 24 861028653 ps
T123 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1476702761 Jun 29 05:26:46 PM PDT 24 Jun 29 05:26:49 PM PDT 24 122858325 ps
T1043 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1928814726 Jun 29 05:26:50 PM PDT 24 Jun 29 05:27:02 PM PDT 24 416195690 ps
T178 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1021256296 Jun 29 05:27:00 PM PDT 24 Jun 29 05:27:07 PM PDT 24 106643168 ps
T1044 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1494368930 Jun 29 05:27:05 PM PDT 24 Jun 29 05:27:08 PM PDT 24 12742843 ps
T1045 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.266602057 Jun 29 05:27:04 PM PDT 24 Jun 29 05:27:06 PM PDT 24 14057037 ps
T124 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.982843275 Jun 29 05:26:50 PM PDT 24 Jun 29 05:26:52 PM PDT 24 76148604 ps
T1046 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.448895079 Jun 29 05:27:05 PM PDT 24 Jun 29 05:27:07 PM PDT 24 51662260 ps
T125 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3886258558 Jun 29 05:27:02 PM PDT 24 Jun 29 05:27:05 PM PDT 24 191444487 ps
T1047 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3844955428 Jun 29 05:26:56 PM PDT 24 Jun 29 05:26:57 PM PDT 24 14972873 ps
T154 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.493579634 Jun 29 05:26:55 PM PDT 24 Jun 29 05:27:11 PM PDT 24 745168837 ps
T105 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3781673334 Jun 29 05:27:03 PM PDT 24 Jun 29 05:27:08 PM PDT 24 149605980 ps
T1048 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1787856286 Jun 29 05:27:01 PM PDT 24 Jun 29 05:27:03 PM PDT 24 32894645 ps
T155 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3039856831 Jun 29 05:26:54 PM PDT 24 Jun 29 05:27:04 PM PDT 24 766392561 ps
T1049 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2293010494 Jun 29 05:27:15 PM PDT 24 Jun 29 05:27:17 PM PDT 24 161276142 ps
T1050 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3058329768 Jun 29 05:26:55 PM PDT 24 Jun 29 05:26:57 PM PDT 24 36337355 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1195500605 Jun 29 05:26:42 PM PDT 24 Jun 29 05:26:44 PM PDT 24 18479954 ps
T1051 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1497277837 Jun 29 05:27:03 PM PDT 24 Jun 29 05:27:05 PM PDT 24 16733973 ps
T1052 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4020717305 Jun 29 05:26:55 PM PDT 24 Jun 29 05:26:56 PM PDT 24 14582503 ps
T1053 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2776532309 Jun 29 05:27:11 PM PDT 24 Jun 29 05:27:13 PM PDT 24 755859820 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.109295963 Jun 29 05:26:52 PM PDT 24 Jun 29 05:26:53 PM PDT 24 11291941 ps
T107 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1156068539 Jun 29 05:26:33 PM PDT 24 Jun 29 05:26:38 PM PDT 24 72677374 ps
T1055 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4020511640 Jun 29 05:27:09 PM PDT 24 Jun 29 05:27:10 PM PDT 24 22200540 ps
T156 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3544118276 Jun 29 05:26:51 PM PDT 24 Jun 29 05:27:07 PM PDT 24 2194394364 ps
T108 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1168411976 Jun 29 05:26:38 PM PDT 24 Jun 29 05:26:41 PM PDT 24 1384941995 ps
T157 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3928286581 Jun 29 05:26:32 PM PDT 24 Jun 29 05:26:58 PM PDT 24 2181614504 ps
T1056 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1894665011 Jun 29 05:26:58 PM PDT 24 Jun 29 05:27:00 PM PDT 24 26508685 ps
T1057 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2095885718 Jun 29 05:27:08 PM PDT 24 Jun 29 05:27:10 PM PDT 24 48805418 ps
T1058 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3474755535 Jun 29 05:27:10 PM PDT 24 Jun 29 05:27:13 PM PDT 24 202424948 ps
T1059 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2545277990 Jun 29 05:26:55 PM PDT 24 Jun 29 05:26:59 PM PDT 24 404354396 ps
T1060 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2407247052 Jun 29 05:26:39 PM PDT 24 Jun 29 05:26:40 PM PDT 24 29619426 ps
T174 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2533853881 Jun 29 05:27:01 PM PDT 24 Jun 29 05:27:13 PM PDT 24 195938629 ps
T109 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3094970659 Jun 29 05:27:02 PM PDT 24 Jun 29 05:27:08 PM PDT 24 843033266 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3554676351 Jun 29 05:26:44 PM PDT 24 Jun 29 05:27:07 PM PDT 24 4479975118 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.717360357 Jun 29 05:26:34 PM PDT 24 Jun 29 05:26:38 PM PDT 24 104271793 ps
T1062 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2340688396 Jun 29 05:27:06 PM PDT 24 Jun 29 05:27:08 PM PDT 24 21749978 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2217922209 Jun 29 05:26:35 PM PDT 24 Jun 29 05:26:36 PM PDT 24 18969598 ps
T1064 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2307315259 Jun 29 05:26:57 PM PDT 24 Jun 29 05:27:01 PM PDT 24 187729766 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2682710453 Jun 29 05:26:46 PM PDT 24 Jun 29 05:26:49 PM PDT 24 247210986 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.58721954 Jun 29 05:26:51 PM PDT 24 Jun 29 05:26:52 PM PDT 24 61296217 ps
T175 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.156058986 Jun 29 05:27:02 PM PDT 24 Jun 29 05:27:10 PM PDT 24 217079301 ps
T176 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2010008544 Jun 29 05:26:48 PM PDT 24 Jun 29 05:27:12 PM PDT 24 4249573545 ps
T1067 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1643204533 Jun 29 05:27:00 PM PDT 24 Jun 29 05:27:02 PM PDT 24 411618924 ps
T1068 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2214341609 Jun 29 05:27:05 PM PDT 24 Jun 29 05:27:08 PM PDT 24 15922050 ps
T1069 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2483742298 Jun 29 05:27:05 PM PDT 24 Jun 29 05:27:06 PM PDT 24 28739875 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2426119824 Jun 29 05:26:50 PM PDT 24 Jun 29 05:26:52 PM PDT 24 31788628 ps
T1071 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3503504882 Jun 29 05:26:38 PM PDT 24 Jun 29 05:26:39 PM PDT 24 16264617 ps
T1072 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4126430304 Jun 29 05:27:05 PM PDT 24 Jun 29 05:27:09 PM PDT 24 101026642 ps
T1073 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.346340569 Jun 29 05:26:54 PM PDT 24 Jun 29 05:27:02 PM PDT 24 421953216 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.349830153 Jun 29 05:26:38 PM PDT 24 Jun 29 05:26:42 PM PDT 24 335393073 ps
T1075 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1182854129 Jun 29 05:26:33 PM PDT 24 Jun 29 05:26:34 PM PDT 24 49442561 ps
T1076 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3900180614 Jun 29 05:27:00 PM PDT 24 Jun 29 05:27:01 PM PDT 24 75393391 ps
T1077 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2768003778 Jun 29 05:26:57 PM PDT 24 Jun 29 05:26:59 PM PDT 24 242612273 ps
T177 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1002072398 Jun 29 05:26:53 PM PDT 24 Jun 29 05:27:06 PM PDT 24 212270504 ps
T1078 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2401723438 Jun 29 05:26:56 PM PDT 24 Jun 29 05:26:58 PM PDT 24 38047224 ps
T1079 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1039846397 Jun 29 05:27:06 PM PDT 24 Jun 29 05:27:08 PM PDT 24 15986877 ps
T1080 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2794564890 Jun 29 05:26:38 PM PDT 24 Jun 29 05:26:47 PM PDT 24 396216689 ps
T1081 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1454357889 Jun 29 05:26:58 PM PDT 24 Jun 29 05:27:06 PM PDT 24 529269717 ps
T1082 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.516562585 Jun 29 05:26:55 PM PDT 24 Jun 29 05:26:57 PM PDT 24 26841001 ps
T1083 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1311177609 Jun 29 05:26:49 PM PDT 24 Jun 29 05:26:54 PM PDT 24 170291006 ps
T1084 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1488047431 Jun 29 05:26:51 PM PDT 24 Jun 29 05:26:54 PM PDT 24 39881395 ps
T1085 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1727945988 Jun 29 05:26:33 PM PDT 24 Jun 29 05:27:00 PM PDT 24 6537435161 ps
T1086 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3094118862 Jun 29 05:26:38 PM PDT 24 Jun 29 05:26:41 PM PDT 24 95734668 ps
T79 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2321415961 Jun 29 05:26:43 PM PDT 24 Jun 29 05:26:45 PM PDT 24 25546373 ps
T1087 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1625985889 Jun 29 05:26:52 PM PDT 24 Jun 29 05:26:54 PM PDT 24 82836233 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4029031871 Jun 29 05:26:37 PM PDT 24 Jun 29 05:26:42 PM PDT 24 766564147 ps
T1089 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3651036246 Jun 29 05:26:58 PM PDT 24 Jun 29 05:27:01 PM PDT 24 98948847 ps
T1090 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.577490506 Jun 29 05:27:11 PM PDT 24 Jun 29 05:27:12 PM PDT 24 56201028 ps
T1091 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3970088570 Jun 29 05:26:44 PM PDT 24 Jun 29 05:26:49 PM PDT 24 122925177 ps
T1092 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3614937027 Jun 29 05:27:16 PM PDT 24 Jun 29 05:27:20 PM PDT 24 71054297 ps
T1093 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2628347308 Jun 29 05:26:59 PM PDT 24 Jun 29 05:27:01 PM PDT 24 27000615 ps
T1094 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.187634527 Jun 29 05:26:52 PM PDT 24 Jun 29 05:27:00 PM PDT 24 66544182 ps
T1095 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1866675877 Jun 29 05:26:55 PM PDT 24 Jun 29 05:26:59 PM PDT 24 108026339 ps
T1096 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1676720975 Jun 29 05:26:37 PM PDT 24 Jun 29 05:26:49 PM PDT 24 184843504 ps
T1097 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.367460373 Jun 29 05:27:05 PM PDT 24 Jun 29 05:27:07 PM PDT 24 18698138 ps
T1098 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.487523591 Jun 29 05:26:53 PM PDT 24 Jun 29 05:26:55 PM PDT 24 14543739 ps
T1099 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4046881852 Jun 29 05:27:00 PM PDT 24 Jun 29 05:27:01 PM PDT 24 14933079 ps
T1100 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.377518276 Jun 29 05:26:39 PM PDT 24 Jun 29 05:26:42 PM PDT 24 442328880 ps
T1101 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4099344534 Jun 29 05:27:05 PM PDT 24 Jun 29 05:27:07 PM PDT 24 12858176 ps
T1102 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1930641992 Jun 29 05:26:32 PM PDT 24 Jun 29 05:26:35 PM PDT 24 228359971 ps
T1103 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3213853059 Jun 29 05:27:05 PM PDT 24 Jun 29 05:27:09 PM PDT 24 64696730 ps
T1104 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3155596762 Jun 29 05:26:39 PM PDT 24 Jun 29 05:26:42 PM PDT 24 60885650 ps
T1105 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1304885710 Jun 29 05:27:01 PM PDT 24 Jun 29 05:27:21 PM PDT 24 314816987 ps
T80 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.169345170 Jun 29 05:26:45 PM PDT 24 Jun 29 05:26:47 PM PDT 24 117382189 ps
T1106 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3400797475 Jun 29 05:27:04 PM PDT 24 Jun 29 05:27:05 PM PDT 24 32446769 ps
T1107 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.759650289 Jun 29 05:26:48 PM PDT 24 Jun 29 05:26:50 PM PDT 24 238511319 ps
T1108 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2928604684 Jun 29 05:26:53 PM PDT 24 Jun 29 05:26:55 PM PDT 24 28752322 ps
T1109 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2472269515 Jun 29 05:27:02 PM PDT 24 Jun 29 05:27:03 PM PDT 24 30527179 ps
T1110 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1186803353 Jun 29 05:27:02 PM PDT 24 Jun 29 05:27:03 PM PDT 24 21252210 ps
T172 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.414070389 Jun 29 05:26:53 PM PDT 24 Jun 29 05:26:58 PM PDT 24 129729030 ps
T1111 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.634637664 Jun 29 05:27:05 PM PDT 24 Jun 29 05:27:10 PM PDT 24 263018851 ps
T1112 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3631002518 Jun 29 05:26:31 PM PDT 24 Jun 29 05:26:34 PM PDT 24 438228429 ps
T1113 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3062874966 Jun 29 05:26:53 PM PDT 24 Jun 29 05:26:57 PM PDT 24 102396174 ps
T1114 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2641110545 Jun 29 05:26:57 PM PDT 24 Jun 29 05:27:00 PM PDT 24 70693246 ps
T1115 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2377679014 Jun 29 05:27:01 PM PDT 24 Jun 29 05:27:07 PM PDT 24 174966555 ps
T1116 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4125981451 Jun 29 05:26:45 PM PDT 24 Jun 29 05:26:50 PM PDT 24 129024313 ps
T1117 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.848046215 Jun 29 05:26:58 PM PDT 24 Jun 29 05:27:01 PM PDT 24 166745893 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.268958177 Jun 29 05:26:52 PM PDT 24 Jun 29 05:26:54 PM PDT 24 46014011 ps
T1119 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2205136059 Jun 29 05:26:50 PM PDT 24 Jun 29 05:26:51 PM PDT 24 161823973 ps
T1120 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3989517108 Jun 29 05:26:42 PM PDT 24 Jun 29 05:26:46 PM PDT 24 271352566 ps
T1121 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3685638000 Jun 29 05:27:03 PM PDT 24 Jun 29 05:27:04 PM PDT 24 18217333 ps
T1122 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1790614926 Jun 29 05:26:40 PM PDT 24 Jun 29 05:26:44 PM PDT 24 705746223 ps
T1123 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4042642038 Jun 29 05:27:01 PM PDT 24 Jun 29 05:27:09 PM PDT 24 54012499 ps
T1124 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.26717053 Jun 29 05:26:47 PM PDT 24 Jun 29 05:26:49 PM PDT 24 59309129 ps
T1125 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2638449114 Jun 29 05:26:45 PM PDT 24 Jun 29 05:26:50 PM PDT 24 1768659984 ps
T1126 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.313809867 Jun 29 05:27:25 PM PDT 24 Jun 29 05:27:29 PM PDT 24 143734678 ps
T1127 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3851685329 Jun 29 05:26:54 PM PDT 24 Jun 29 05:26:56 PM PDT 24 45059537 ps
T81 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3485619637 Jun 29 05:26:55 PM PDT 24 Jun 29 05:26:57 PM PDT 24 58384196 ps
T179 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.9032774 Jun 29 05:26:45 PM PDT 24 Jun 29 05:27:10 PM PDT 24 1758371041 ps
T1128 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3769215505 Jun 29 05:26:50 PM PDT 24 Jun 29 05:26:51 PM PDT 24 29510156 ps
T1129 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3530570674 Jun 29 05:26:45 PM PDT 24 Jun 29 05:26:48 PM PDT 24 175776639 ps
T1130 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1498172740 Jun 29 05:27:06 PM PDT 24 Jun 29 05:27:08 PM PDT 24 20437862 ps
T1131 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.931894127 Jun 29 05:26:51 PM PDT 24 Jun 29 05:26:59 PM PDT 24 547095926 ps
T82 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1870911944 Jun 29 05:26:50 PM PDT 24 Jun 29 05:26:51 PM PDT 24 81167983 ps
T1132 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3832818743 Jun 29 05:26:32 PM PDT 24 Jun 29 05:26:48 PM PDT 24 1132350618 ps
T1133 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4292363768 Jun 29 05:27:01 PM PDT 24 Jun 29 05:27:04 PM PDT 24 104446139 ps
T1134 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2095482075 Jun 29 05:27:02 PM PDT 24 Jun 29 05:27:04 PM PDT 24 23019063 ps
T1135 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1667007301 Jun 29 05:26:55 PM PDT 24 Jun 29 05:26:57 PM PDT 24 53348771 ps
T1136 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3033882532 Jun 29 05:26:52 PM PDT 24 Jun 29 05:26:57 PM PDT 24 234784837 ps
T1137 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.130245368 Jun 29 05:26:55 PM PDT 24 Jun 29 05:26:57 PM PDT 24 19809864 ps
T1138 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.993220050 Jun 29 05:26:33 PM PDT 24 Jun 29 05:26:35 PM PDT 24 113596737 ps
T1139 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2170539607 Jun 29 05:26:34 PM PDT 24 Jun 29 05:26:35 PM PDT 24 13551123 ps
T1140 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2311171651 Jun 29 05:26:51 PM PDT 24 Jun 29 05:26:53 PM PDT 24 26626810 ps
T1141 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1015378158 Jun 29 05:26:50 PM PDT 24 Jun 29 05:26:52 PM PDT 24 97758641 ps
T1142 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1565873845 Jun 29 05:26:35 PM PDT 24 Jun 29 05:26:59 PM PDT 24 1593756266 ps
T1143 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3165983760 Jun 29 05:26:57 PM PDT 24 Jun 29 05:26:58 PM PDT 24 18708606 ps
T1144 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4281325343 Jun 29 05:26:57 PM PDT 24 Jun 29 05:26:58 PM PDT 24 11808225 ps
T83 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1432985042 Jun 29 05:26:41 PM PDT 24 Jun 29 05:26:42 PM PDT 24 63309694 ps
T1145 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.707743241 Jun 29 05:26:51 PM PDT 24 Jun 29 05:26:52 PM PDT 24 18425862 ps
T1146 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3658084013 Jun 29 05:26:35 PM PDT 24 Jun 29 05:26:40 PM PDT 24 324240922 ps
T1147 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2885114811 Jun 29 05:26:53 PM PDT 24 Jun 29 05:26:59 PM PDT 24 834257997 ps
T1148 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3674185056 Jun 29 05:26:55 PM PDT 24 Jun 29 05:27:00 PM PDT 24 680239154 ps
T1149 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4213843732 Jun 29 05:26:58 PM PDT 24 Jun 29 05:27:01 PM PDT 24 395337179 ps
T1150 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1655565471 Jun 29 05:26:59 PM PDT 24 Jun 29 05:27:01 PM PDT 24 18273480 ps
T1151 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.470104781 Jun 29 05:26:46 PM PDT 24 Jun 29 05:26:47 PM PDT 24 143876640 ps


Test location /workspace/coverage/default/4.spi_device_stress_all.879430772
Short name T1
Test name
Test status
Simulation time 193397485585 ps
CPU time 298.02 seconds
Started Jun 29 06:48:22 PM PDT 24
Finished Jun 29 06:53:20 PM PDT 24
Peak memory 270692 kb
Host smart-db31aa5e-21a5-454c-afcc-1ab05b38ee60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879430772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.879430772
Directory /workspace/4.spi_device_stress_all/latest


Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2426094204
Short name T15
Test name
Test status
Simulation time 33442430596 ps
CPU time 105.73 seconds
Started Jun 29 06:48:22 PM PDT 24
Finished Jun 29 06:50:08 PM PDT 24
Peak memory 254852 kb
Host smart-d5d654b6-5d2e-4be6-b374-897a046e9a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426094204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2426094204
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/33.spi_device_stress_all.1362989963
Short name T17
Test name
Test status
Simulation time 11727108187 ps
CPU time 144.55 seconds
Started Jun 29 06:50:19 PM PDT 24
Finished Jun 29 06:52:44 PM PDT 24
Peak memory 265688 kb
Host smart-af9d33e3-bdc6-4637-ab29-0518b7131e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362989963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1362989963
Directory /workspace/33.spi_device_stress_all/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.670280374
Short name T111
Test name
Test status
Simulation time 142958889 ps
CPU time 3.91 seconds
Started Jun 29 05:26:52 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 218196 kb
Host smart-57995218-02ae-4113-a92e-89fd93cf4a02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670280374 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.670280374
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/default/11.spi_device_stress_all.2536652334
Short name T201
Test name
Test status
Simulation time 1173651289138 ps
CPU time 926.08 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 07:04:12 PM PDT 24
Peak memory 306592 kb
Host smart-2b007ce8-5caa-47ed-90ac-8a5d58df300d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536652334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2536652334
Directory /workspace/11.spi_device_stress_all/latest


Test location /workspace/coverage/default/35.spi_device_stress_all.3004367305
Short name T28
Test name
Test status
Simulation time 24447912814 ps
CPU time 410.34 seconds
Started Jun 29 06:50:18 PM PDT 24
Finished Jun 29 06:57:08 PM PDT 24
Peak memory 305528 kb
Host smart-b29a10e9-1f89-4c34-bc6c-2ba12cb12396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004367305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3004367305
Directory /workspace/35.spi_device_stress_all/latest


Test location /workspace/coverage/default/0.spi_device_ram_cfg.2747147053
Short name T63
Test name
Test status
Simulation time 27780483 ps
CPU time 0.77 seconds
Started Jun 29 06:48:07 PM PDT 24
Finished Jun 29 06:48:08 PM PDT 24
Peak memory 216136 kb
Host smart-bd5cf04e-788e-4d11-882c-f83e8fcd4035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747147053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2747147053
Directory /workspace/0.spi_device_ram_cfg/latest


Test location /workspace/coverage/default/39.spi_device_stress_all.491629022
Short name T20
Test name
Test status
Simulation time 304540732010 ps
CPU time 616.97 seconds
Started Jun 29 06:50:47 PM PDT 24
Finished Jun 29 07:01:04 PM PDT 24
Peak memory 273744 kb
Host smart-ca5ec4aa-921a-4c77-82d9-0e7540fc4cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491629022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.491629022
Directory /workspace/39.spi_device_stress_all/latest


Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.728641257
Short name T41
Test name
Test status
Simulation time 28248774897 ps
CPU time 115.61 seconds
Started Jun 29 06:48:36 PM PDT 24
Finished Jun 29 06:50:32 PM PDT 24
Peak memory 255892 kb
Host smart-632457e5-9d81-4ca4-809f-0802641dfa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728641257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.728641257
Directory /workspace/5.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/1.spi_device_sec_cm.1812164265
Short name T27
Test name
Test status
Simulation time 337829422 ps
CPU time 1.02 seconds
Started Jun 29 06:48:17 PM PDT 24
Finished Jun 29 06:48:19 PM PDT 24
Peak memory 235460 kb
Host smart-c77cd797-b1e8-418b-995b-ff8d1a89bde8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812164265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1812164265
Directory /workspace/1.spi_device_sec_cm/latest


Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1984669659
Short name T69
Test name
Test status
Simulation time 69540790861 ps
CPU time 314.06 seconds
Started Jun 29 06:48:16 PM PDT 24
Finished Jun 29 06:53:31 PM PDT 24
Peak memory 256320 kb
Host smart-dadf71e0-1f2e-4d0a-b56d-0bd6c9a04dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984669659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1984669659
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/14.spi_device_flash_mode.1362701523
Short name T38
Test name
Test status
Simulation time 3836821495 ps
CPU time 12.53 seconds
Started Jun 29 06:49:02 PM PDT 24
Finished Jun 29 06:49:15 PM PDT 24
Peak memory 224576 kb
Host smart-4f888f02-ee0e-4f62-8d5c-2a3ddc75fe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362701523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1362701523
Directory /workspace/14.spi_device_flash_mode/latest


Test location /workspace/coverage/default/0.spi_device_stress_all.3850062699
Short name T29
Test name
Test status
Simulation time 1038670839026 ps
CPU time 758.11 seconds
Started Jun 29 06:48:05 PM PDT 24
Finished Jun 29 07:00:43 PM PDT 24
Peak memory 288936 kb
Host smart-17c50e97-d24f-4f5d-839e-23fb140b48b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850062699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3850062699
Directory /workspace/0.spi_device_stress_all/latest


Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4159488563
Short name T194
Test name
Test status
Simulation time 43372434361 ps
CPU time 458.2 seconds
Started Jun 29 06:48:39 PM PDT 24
Finished Jun 29 06:56:19 PM PDT 24
Peak memory 271356 kb
Host smart-2ccdae38-4733-4e6e-ab1d-e792c93ffa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159488563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4159488563
Directory /workspace/10.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.353927157
Short name T99
Test name
Test status
Simulation time 295197598 ps
CPU time 20.16 seconds
Started Jun 29 05:26:59 PM PDT 24
Finished Jun 29 05:27:20 PM PDT 24
Peak memory 215736 kb
Host smart-c1a50cd6-d72e-491e-8c7c-e360750d2f51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353927157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.353927157
Directory /workspace/17.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3291053532
Short name T122
Test name
Test status
Simulation time 82866203 ps
CPU time 2.18 seconds
Started Jun 29 05:27:03 PM PDT 24
Finished Jun 29 05:27:06 PM PDT 24
Peak memory 207152 kb
Host smart-e0ec9ec1-df66-481c-8826-b2e820e65dbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291053532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3291053532
Directory /workspace/12.spi_device_csr_rw/latest


Test location /workspace/coverage/default/49.spi_device_flash_all.2280549748
Short name T77
Test name
Test status
Simulation time 43853009858 ps
CPU time 153.93 seconds
Started Jun 29 06:51:18 PM PDT 24
Finished Jun 29 06:53:53 PM PDT 24
Peak memory 273316 kb
Host smart-35e87619-3046-4a58-9c49-8b7d02269948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280549748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2280549748
Directory /workspace/49.spi_device_flash_all/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1714371098
Short name T104
Test name
Test status
Simulation time 43623039 ps
CPU time 2.87 seconds
Started Jun 29 05:26:40 PM PDT 24
Finished Jun 29 05:26:43 PM PDT 24
Peak memory 215564 kb
Host smart-79335032-6a48-41df-ac06-6245315c7090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714371098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
714371098
Directory /workspace/9.spi_device_tl_errors/latest


Test location /workspace/coverage/default/1.spi_device_mem_parity.1605836081
Short name T340
Test name
Test status
Simulation time 54815847 ps
CPU time 1.04 seconds
Started Jun 29 06:48:05 PM PDT 24
Finished Jun 29 06:48:07 PM PDT 24
Peak memory 216776 kb
Host smart-9efb23a2-f6c6-4adf-8e17-d72fe437e9c5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605836081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1605836081
Directory /workspace/1.spi_device_mem_parity/latest


Test location /workspace/coverage/default/1.spi_device_stress_all.2756121238
Short name T21
Test name
Test status
Simulation time 203378112820 ps
CPU time 510.75 seconds
Started Jun 29 06:48:14 PM PDT 24
Finished Jun 29 06:56:45 PM PDT 24
Peak memory 288708 kb
Host smart-ebb24955-5a07-4d22-941b-26950db6f9d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756121238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2756121238
Directory /workspace/1.spi_device_stress_all/latest


Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.386739606
Short name T273
Test name
Test status
Simulation time 5572497296 ps
CPU time 114.33 seconds
Started Jun 29 06:49:10 PM PDT 24
Finished Jun 29 06:51:05 PM PDT 24
Peak memory 249584 kb
Host smart-640d1272-5fc8-4211-8fa1-da92858bfa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386739606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.386739606
Directory /workspace/16.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/38.spi_device_stress_all.2902719763
Short name T160
Test name
Test status
Simulation time 18337264723 ps
CPU time 187.68 seconds
Started Jun 29 06:50:42 PM PDT 24
Finished Jun 29 06:53:50 PM PDT 24
Peak memory 249272 kb
Host smart-9a8c6103-cc8a-4f46-8642-9096e12feacc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902719763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2902719763
Directory /workspace/38.spi_device_stress_all/latest


Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3188303996
Short name T54
Test name
Test status
Simulation time 47928036543 ps
CPU time 133.38 seconds
Started Jun 29 06:49:34 PM PDT 24
Finished Jun 29 06:51:48 PM PDT 24
Peak memory 265152 kb
Host smart-256f6880-feae-494f-8d00-3d220dbb7fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188303996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3188303996
Directory /workspace/22.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3187872256
Short name T277
Test name
Test status
Simulation time 191172607047 ps
CPU time 173.69 seconds
Started Jun 29 06:49:20 PM PDT 24
Finished Jun 29 06:52:14 PM PDT 24
Peak memory 249372 kb
Host smart-e0b987fb-70a8-4508-921e-b51c045a96b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187872256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3187872256
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/0.spi_device_alert_test.2307586274
Short name T404
Test name
Test status
Simulation time 15495642 ps
CPU time 0.76 seconds
Started Jun 29 06:48:09 PM PDT 24
Finished Jun 29 06:48:11 PM PDT 24
Peak memory 204784 kb
Host smart-293bea65-0503-4623-83ce-991ff9b2761e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307586274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
307586274
Directory /workspace/0.spi_device_alert_test/latest


Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3546320367
Short name T36
Test name
Test status
Simulation time 62820434196 ps
CPU time 302.14 seconds
Started Jun 29 06:51:15 PM PDT 24
Finished Jun 29 06:56:18 PM PDT 24
Peak memory 256936 kb
Host smart-21fa099f-b75c-4609-97c4-f53c4c91a2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546320367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3546320367
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.277100109
Short name T23
Test name
Test status
Simulation time 131818116 ps
CPU time 0.96 seconds
Started Jun 29 06:49:42 PM PDT 24
Finished Jun 29 06:49:43 PM PDT 24
Peak memory 206868 kb
Host smart-941ef75e-8266-4719-9551-f32c18ab1671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277100109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.277100109
Directory /workspace/24.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.9032774
Short name T179
Test name
Test status
Simulation time 1758371041 ps
CPU time 24.98 seconds
Started Jun 29 05:26:45 PM PDT 24
Finished Jun 29 05:27:10 PM PDT 24
Peak memory 215836 kb
Host smart-47984a09-dc00-4a38-a60f-d02039b3784a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9032774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl
_intg_err.9032774
Directory /workspace/7.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/22.spi_device_flash_all.1281138423
Short name T34
Test name
Test status
Simulation time 32800446221 ps
CPU time 227.85 seconds
Started Jun 29 06:49:33 PM PDT 24
Finished Jun 29 06:53:21 PM PDT 24
Peak memory 250564 kb
Host smart-34db8f9b-864c-4661-90c2-1631f66ebd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281138423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1281138423
Directory /workspace/22.spi_device_flash_all/latest


Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.228561205
Short name T198
Test name
Test status
Simulation time 91236071756 ps
CPU time 157.9 seconds
Started Jun 29 06:50:42 PM PDT 24
Finished Jun 29 06:53:21 PM PDT 24
Peak memory 250256 kb
Host smart-de460c7b-79c0-455e-b84d-e8181c8ac53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228561205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.228561205
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3809453003
Short name T87
Test name
Test status
Simulation time 15176748582 ps
CPU time 63.71 seconds
Started Jun 29 06:51:23 PM PDT 24
Finished Jun 29 06:52:27 PM PDT 24
Peak memory 239828 kb
Host smart-2bc29a16-a69a-4639-8856-938f967558cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809453003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3809453003
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.414070389
Short name T172
Test name
Test status
Simulation time 129729030 ps
CPU time 4.26 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:58 PM PDT 24
Peak memory 215716 kb
Host smart-1a972648-b10e-4433-84e5-2915cc5ae385
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414070389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.414070389
Directory /workspace/6.spi_device_tl_errors/latest


Test location /workspace/coverage/default/28.spi_device_tpm_all.1756125954
Short name T48
Test name
Test status
Simulation time 7535517866 ps
CPU time 13.3 seconds
Started Jun 29 06:49:55 PM PDT 24
Finished Jun 29 06:50:09 PM PDT 24
Peak memory 216468 kb
Host smart-7835ebaf-de95-4168-b8f7-bab0d240b158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756125954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1756125954
Directory /workspace/28.spi_device_tpm_all/latest


Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.920641594
Short name T887
Test name
Test status
Simulation time 5120365326 ps
CPU time 100.38 seconds
Started Jun 29 06:48:07 PM PDT 24
Finished Jun 29 06:49:48 PM PDT 24
Peak memory 264336 kb
Host smart-d18a893d-076a-4bb5-b40e-328079a066be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920641594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
920641594
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/11.spi_device_flash_all.752733679
Short name T246
Test name
Test status
Simulation time 111076640819 ps
CPU time 200.33 seconds
Started Jun 29 06:48:45 PM PDT 24
Finished Jun 29 06:52:06 PM PDT 24
Peak memory 250624 kb
Host smart-ae020c7a-81ad-4325-9f4b-06da5ad55465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752733679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.752733679
Directory /workspace/11.spi_device_flash_all/latest


Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2802152631
Short name T8
Test name
Test status
Simulation time 37306445079 ps
CPU time 307.46 seconds
Started Jun 29 06:49:03 PM PDT 24
Finished Jun 29 06:54:11 PM PDT 24
Peak memory 269864 kb
Host smart-424bfe9e-9c6a-4c23-9ca9-9ab955dec377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802152631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2802152631
Directory /workspace/14.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/47.spi_device_flash_mode.1140656257
Short name T958
Test name
Test status
Simulation time 3565525937 ps
CPU time 23.22 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:37 PM PDT 24
Peak memory 249072 kb
Host smart-e376d7da-2f0c-4229-9eee-d72372dc0cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140656257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1140656257
Directory /workspace/47.spi_device_flash_mode/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4029031871
Short name T1088
Test name
Test status
Simulation time 766564147 ps
CPU time 4.42 seconds
Started Jun 29 05:26:37 PM PDT 24
Finished Jun 29 05:26:42 PM PDT 24
Peak memory 215624 kb
Host smart-7d7dd705-c50a-43c0-b890-6ba2d077f242
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029031871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
029031871
Directory /workspace/2.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2533853881
Short name T174
Test name
Test status
Simulation time 195938629 ps
CPU time 11.52 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:13 PM PDT 24
Peak memory 215536 kb
Host smart-3221bd82-69eb-4c63-b6bb-01ad63348363
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533853881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2533853881
Directory /workspace/12.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/11.spi_device_flash_mode.1709383273
Short name T70
Test name
Test status
Simulation time 606540600 ps
CPU time 6.29 seconds
Started Jun 29 06:48:50 PM PDT 24
Finished Jun 29 06:48:57 PM PDT 24
Peak memory 236384 kb
Host smart-67eac9ac-50e4-4b79-8ddc-cd83a39a9fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709383273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1709383273
Directory /workspace/11.spi_device_flash_mode/latest


Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3900513751
Short name T276
Test name
Test status
Simulation time 1153666932 ps
CPU time 4.32 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 06:48:50 PM PDT 24
Peak memory 232544 kb
Host smart-c26985a3-d723-45ef-8fa3-48c412ea6b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900513751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3900513751
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1137378832
Short name T264
Test name
Test status
Simulation time 81380373244 ps
CPU time 200.45 seconds
Started Jun 29 06:48:53 PM PDT 24
Finished Jun 29 06:52:14 PM PDT 24
Peak memory 249220 kb
Host smart-4c794ee2-ae9a-4658-88ae-1ff3dccebc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137378832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1137378832
Directory /workspace/13.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/14.spi_device_flash_all.494570193
Short name T281
Test name
Test status
Simulation time 8463490322 ps
CPU time 63.07 seconds
Started Jun 29 06:49:02 PM PDT 24
Finished Jun 29 06:50:06 PM PDT 24
Peak memory 243812 kb
Host smart-894370ea-907a-4e79-8bc8-69c58967582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494570193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.494570193
Directory /workspace/14.spi_device_flash_all/latest


Test location /workspace/coverage/default/15.spi_device_tpm_all.268850032
Short name T494
Test name
Test status
Simulation time 23180736401 ps
CPU time 25.04 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:29 PM PDT 24
Peak memory 216308 kb
Host smart-7934db94-8893-4144-9522-2206bb0b5d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268850032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.268850032
Directory /workspace/15.spi_device_tpm_all/latest


Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2335847479
Short name T266
Test name
Test status
Simulation time 5393659627 ps
CPU time 97.44 seconds
Started Jun 29 06:49:11 PM PDT 24
Finished Jun 29 06:50:49 PM PDT 24
Peak memory 263400 kb
Host smart-37912382-0fdb-422b-8b66-8e4a85d8e30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335847479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2335847479
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.997164555
Short name T309
Test name
Test status
Simulation time 36032264267 ps
CPU time 357.86 seconds
Started Jun 29 06:49:35 PM PDT 24
Finished Jun 29 06:55:33 PM PDT 24
Peak memory 255364 kb
Host smart-016aed9c-7041-40ca-8118-452330c78248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997164555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.997164555
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1724010754
Short name T279
Test name
Test status
Simulation time 15271506790 ps
CPU time 117.49 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:52:00 PM PDT 24
Peak memory 254724 kb
Host smart-18c92a57-b638-4d23-ba60-9f9784a2f2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724010754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1724010754
Directory /workspace/29.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/35.spi_device_flash_mode.1716520696
Short name T288
Test name
Test status
Simulation time 1997364652 ps
CPU time 12.54 seconds
Started Jun 29 06:50:24 PM PDT 24
Finished Jun 29 06:50:37 PM PDT 24
Peak memory 224448 kb
Host smart-be363bbe-0f53-4a6f-a95d-52f512430bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716520696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1716520696
Directory /workspace/35.spi_device_flash_mode/latest


Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.629787249
Short name T94
Test name
Test status
Simulation time 26788234883 ps
CPU time 31.93 seconds
Started Jun 29 06:48:40 PM PDT 24
Finished Jun 29 06:49:13 PM PDT 24
Peak memory 250064 kb
Host smart-8028a4b2-7278-4fbe-805e-671b615fd1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629787249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.629787249
Directory /workspace/10.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1870911944
Short name T82
Test name
Test status
Simulation time 81167983 ps
CPU time 1.01 seconds
Started Jun 29 05:26:50 PM PDT 24
Finished Jun 29 05:26:51 PM PDT 24
Peak memory 206944 kb
Host smart-eaa6f747-9e71-4a79-acc1-e358932d1e14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870911944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1870911944
Directory /workspace/0.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1194524177
Short name T120
Test name
Test status
Simulation time 363174805 ps
CPU time 8.77 seconds
Started Jun 29 05:26:48 PM PDT 24
Finished Jun 29 05:26:58 PM PDT 24
Peak memory 207144 kb
Host smart-3002161f-593b-4622-9de5-77ac14a12bb7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194524177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1194524177
Directory /workspace/0.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1928814726
Short name T1043
Test name
Test status
Simulation time 416195690 ps
CPU time 11.06 seconds
Started Jun 29 05:26:50 PM PDT 24
Finished Jun 29 05:27:02 PM PDT 24
Peak memory 207144 kb
Host smart-5e25164e-0135-441e-8e9a-bd8ae6d5040d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928814726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1928814726
Directory /workspace/0.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2311171651
Short name T1140
Test name
Test status
Simulation time 26626810 ps
CPU time 1.93 seconds
Started Jun 29 05:26:51 PM PDT 24
Finished Jun 29 05:26:53 PM PDT 24
Peak memory 215740 kb
Host smart-77ec5158-8346-4825-a8b8-85b675d61aa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311171651 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2311171651
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1476702761
Short name T123
Test name
Test status
Simulation time 122858325 ps
CPU time 2.35 seconds
Started Jun 29 05:26:46 PM PDT 24
Finished Jun 29 05:26:49 PM PDT 24
Peak memory 215576 kb
Host smart-e5505cd0-07eb-45ca-ad5f-6cf0097315a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476702761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
476702761
Directory /workspace/0.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.109295963
Short name T1054
Test name
Test status
Simulation time 11291941 ps
CPU time 0.82 seconds
Started Jun 29 05:26:52 PM PDT 24
Finished Jun 29 05:26:53 PM PDT 24
Peak memory 204140 kb
Host smart-ad6a2208-8f5f-4cfa-99d0-dead72c819f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109295963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.109295963
Directory /workspace/0.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3631002518
Short name T1112
Test name
Test status
Simulation time 438228429 ps
CPU time 2.13 seconds
Started Jun 29 05:26:31 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 215468 kb
Host smart-34cb5ba6-6f05-4784-991d-0dda49e520c7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631002518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3631002518
Directory /workspace/0.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2407247052
Short name T1060
Test name
Test status
Simulation time 29619426 ps
CPU time 0.68 seconds
Started Jun 29 05:26:39 PM PDT 24
Finished Jun 29 05:26:40 PM PDT 24
Peak memory 203724 kb
Host smart-e9cff282-2c57-4eb1-9c04-8ecebeae24eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407247052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2407247052
Directory /workspace/0.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2682710453
Short name T1065
Test name
Test status
Simulation time 247210986 ps
CPU time 1.92 seconds
Started Jun 29 05:26:46 PM PDT 24
Finished Jun 29 05:26:49 PM PDT 24
Peak memory 207252 kb
Host smart-9dbb4734-e29d-4666-ad89-ab6aa990fd96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682710453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2682710453
Directory /workspace/0.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1156068539
Short name T107
Test name
Test status
Simulation time 72677374 ps
CPU time 4.81 seconds
Started Jun 29 05:26:33 PM PDT 24
Finished Jun 29 05:26:38 PM PDT 24
Peak memory 216644 kb
Host smart-dbd420fc-a287-443c-ab3c-1af4c0ce7474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156068539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
156068539
Directory /workspace/0.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.931894127
Short name T1131
Test name
Test status
Simulation time 547095926 ps
CPU time 7.07 seconds
Started Jun 29 05:26:51 PM PDT 24
Finished Jun 29 05:26:59 PM PDT 24
Peak memory 215468 kb
Host smart-f9241614-a7f9-44f0-b8ea-e99fc0161b7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931894127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.931894127
Directory /workspace/0.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3554676351
Short name T126
Test name
Test status
Simulation time 4479975118 ps
CPU time 22.62 seconds
Started Jun 29 05:26:44 PM PDT 24
Finished Jun 29 05:27:07 PM PDT 24
Peak memory 207268 kb
Host smart-eae7939d-4e0c-4df2-8301-b329245bbcdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554676351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3554676351
Directory /workspace/1.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1727945988
Short name T1085
Test name
Test status
Simulation time 6537435161 ps
CPU time 25.87 seconds
Started Jun 29 05:26:33 PM PDT 24
Finished Jun 29 05:27:00 PM PDT 24
Peak memory 215352 kb
Host smart-265a58a4-9e65-45cf-9bdf-6ebe2693195b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727945988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1727945988
Directory /workspace/1.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.169345170
Short name T80
Test name
Test status
Simulation time 117382189 ps
CPU time 1.21 seconds
Started Jun 29 05:26:45 PM PDT 24
Finished Jun 29 05:26:47 PM PDT 24
Peak memory 207188 kb
Host smart-32cdad69-2c6c-4e99-bb83-ef3020f851c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169345170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.169345170
Directory /workspace/1.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.349830153
Short name T1074
Test name
Test status
Simulation time 335393073 ps
CPU time 3.4 seconds
Started Jun 29 05:26:38 PM PDT 24
Finished Jun 29 05:26:42 PM PDT 24
Peak memory 217500 kb
Host smart-64df1bcd-ba97-403e-b0a2-5bdc03a8004b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349830153 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.349830153
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.717360357
Short name T1061
Test name
Test status
Simulation time 104271793 ps
CPU time 2.74 seconds
Started Jun 29 05:26:34 PM PDT 24
Finished Jun 29 05:26:38 PM PDT 24
Peak memory 215408 kb
Host smart-8165b3f4-7af7-4453-8217-acfa052c1309
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717360357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.717360357
Directory /workspace/1.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.58721954
Short name T1066
Test name
Test status
Simulation time 61296217 ps
CPU time 0.76 seconds
Started Jun 29 05:26:51 PM PDT 24
Finished Jun 29 05:26:52 PM PDT 24
Peak memory 204136 kb
Host smart-b6462039-55d9-41d5-ba11-8c3c667c9541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58721954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.58721954
Directory /workspace/1.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.544882222
Short name T115
Test name
Test status
Simulation time 283098124 ps
CPU time 2.25 seconds
Started Jun 29 05:26:45 PM PDT 24
Finished Jun 29 05:26:48 PM PDT 24
Peak memory 215476 kb
Host smart-4f06be01-e81a-4dde-9d54-1968a68aaee4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544882222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.544882222
Directory /workspace/1.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2472269515
Short name T1109
Test name
Test status
Simulation time 30527179 ps
CPU time 0.71 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:03 PM PDT 24
Peak memory 203720 kb
Host smart-6f4c4fea-6200-46cc-bd63-47c5c0af3d0a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472269515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2472269515
Directory /workspace/1.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2545277990
Short name T1059
Test name
Test status
Simulation time 404354396 ps
CPU time 2.77 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:26:59 PM PDT 24
Peak memory 215404 kb
Host smart-b2aeacbe-acea-4d3c-9336-75560298af90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545277990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2545277990
Directory /workspace/1.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.848046215
Short name T1117
Test name
Test status
Simulation time 166745893 ps
CPU time 2.57 seconds
Started Jun 29 05:26:58 PM PDT 24
Finished Jun 29 05:27:01 PM PDT 24
Peak memory 215604 kb
Host smart-55081867-ab67-42cd-a48e-9b185c3bb5ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848046215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.848046215
Directory /workspace/1.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3928286581
Short name T157
Test name
Test status
Simulation time 2181614504 ps
CPU time 25.12 seconds
Started Jun 29 05:26:32 PM PDT 24
Finished Jun 29 05:26:58 PM PDT 24
Peak memory 215724 kb
Host smart-168ca9c2-a431-48fa-b991-fb555621462f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928286581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3928286581
Directory /workspace/1.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2628347308
Short name T1093
Test name
Test status
Simulation time 27000615 ps
CPU time 1.77 seconds
Started Jun 29 05:26:59 PM PDT 24
Finished Jun 29 05:27:01 PM PDT 24
Peak memory 216460 kb
Host smart-1ee180e2-0334-4041-8e93-9ce101ca1e9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628347308 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2628347308
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4229061749
Short name T143
Test name
Test status
Simulation time 149337314 ps
CPU time 1.45 seconds
Started Jun 29 05:27:00 PM PDT 24
Finished Jun 29 05:27:02 PM PDT 24
Peak memory 207212 kb
Host smart-f200559f-2a94-466a-b38b-795df560600c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229061749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4229061749
Directory /workspace/10.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2928604684
Short name T1108
Test name
Test status
Simulation time 28752322 ps
CPU time 0.8 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:55 PM PDT 24
Peak memory 204120 kb
Host smart-fa82994a-ef4e-497e-9c7a-d8318317d642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928604684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2928604684
Directory /workspace/10.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3474755535
Short name T1058
Test name
Test status
Simulation time 202424948 ps
CPU time 1.72 seconds
Started Jun 29 05:27:10 PM PDT 24
Finished Jun 29 05:27:13 PM PDT 24
Peak memory 215368 kb
Host smart-969e46a8-6eea-4c3f-adaa-c122b1278b8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474755535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3474755535
Directory /workspace/10.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1866675877
Short name T1095
Test name
Test status
Simulation time 108026339 ps
CPU time 2.34 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:26:59 PM PDT 24
Peak memory 215596 kb
Host smart-eef4cfe5-22b2-4de9-a2a4-a946645240d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866675877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1866675877
Directory /workspace/10.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1304885710
Short name T1105
Test name
Test status
Simulation time 314816987 ps
CPU time 19.46 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:21 PM PDT 24
Peak memory 215360 kb
Host smart-dcc5adc8-5ba2-4a3d-858e-fd9501408892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304885710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1304885710
Directory /workspace/10.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2401723438
Short name T1078
Test name
Test status
Simulation time 38047224 ps
CPU time 1.37 seconds
Started Jun 29 05:26:56 PM PDT 24
Finished Jun 29 05:26:58 PM PDT 24
Peak memory 207152 kb
Host smart-84b895c0-a241-4280-9708-4891f44750f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401723438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2401723438
Directory /workspace/11.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2483742298
Short name T1069
Test name
Test status
Simulation time 28739875 ps
CPU time 0.79 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:06 PM PDT 24
Peak memory 203840 kb
Host smart-ba8c3193-e975-445d-a602-002998ed164d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483742298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2483742298
Directory /workspace/11.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3062874966
Short name T1113
Test name
Test status
Simulation time 102396174 ps
CPU time 3.06 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 215452 kb
Host smart-839cae66-768d-442e-9110-ae828bd64f56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062874966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3062874966
Directory /workspace/11.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1311177609
Short name T1083
Test name
Test status
Simulation time 170291006 ps
CPU time 4.83 seconds
Started Jun 29 05:26:49 PM PDT 24
Finished Jun 29 05:26:54 PM PDT 24
Peak memory 215692 kb
Host smart-9d080630-1f3c-4ccf-98db-66b8093ffd76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311177609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1311177609
Directory /workspace/11.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3039856831
Short name T155
Test name
Test status
Simulation time 766392561 ps
CPU time 9.13 seconds
Started Jun 29 05:26:54 PM PDT 24
Finished Jun 29 05:27:04 PM PDT 24
Peak memory 215464 kb
Host smart-58f0c9fa-22b8-44dc-aed3-420e7b9189a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039856831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3039856831
Directory /workspace/11.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4163502292
Short name T95
Test name
Test status
Simulation time 50723363 ps
CPU time 1.77 seconds
Started Jun 29 05:26:54 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 216452 kb
Host smart-97617b8a-a25b-4c8f-aa0a-e926d97b09ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163502292 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4163502292
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4020717305
Short name T1052
Test name
Test status
Simulation time 14582503 ps
CPU time 0.77 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:26:56 PM PDT 24
Peak memory 203788 kb
Host smart-9248cc29-065a-4ef0-8321-b035f8bf7308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020717305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4020717305
Directory /workspace/12.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.881669813
Short name T142
Test name
Test status
Simulation time 113460643 ps
CPU time 3.61 seconds
Started Jun 29 05:27:07 PM PDT 24
Finished Jun 29 05:27:12 PM PDT 24
Peak memory 215400 kb
Host smart-5b9597af-9589-438c-ac94-5e5b6d704543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881669813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.881669813
Directory /workspace/12.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2377679014
Short name T1115
Test name
Test status
Simulation time 174966555 ps
CPU time 4.83 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:07 PM PDT 24
Peak memory 215676 kb
Host smart-5c37ccb3-1dc5-4458-817c-89e5a2dead0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377679014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2377679014
Directory /workspace/12.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2095482075
Short name T1134
Test name
Test status
Simulation time 23019063 ps
CPU time 1.64 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:04 PM PDT 24
Peak memory 215460 kb
Host smart-6f3ce185-6e41-411b-864f-108e0cd9062f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095482075 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2095482075
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2307315259
Short name T1064
Test name
Test status
Simulation time 187729766 ps
CPU time 2.79 seconds
Started Jun 29 05:26:57 PM PDT 24
Finished Jun 29 05:27:01 PM PDT 24
Peak memory 207188 kb
Host smart-78267f7d-2608-4b24-bb13-b32b926e3900
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307315259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2307315259
Directory /workspace/13.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.487523591
Short name T1098
Test name
Test status
Simulation time 14543739 ps
CPU time 0.72 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:55 PM PDT 24
Peak memory 203780 kb
Host smart-af3a896e-8519-45b9-b831-5cb30bf85d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487523591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.487523591
Directory /workspace/13.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1625985889
Short name T1087
Test name
Test status
Simulation time 82836233 ps
CPU time 1.83 seconds
Started Jun 29 05:26:52 PM PDT 24
Finished Jun 29 05:26:54 PM PDT 24
Peak memory 215360 kb
Host smart-8043e346-46c3-493a-b94b-6b6931f84d5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625985889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1625985889
Directory /workspace/13.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3094970659
Short name T109
Test name
Test status
Simulation time 843033266 ps
CPU time 4.75 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 215712 kb
Host smart-2e1280c1-b0b3-4821-9645-89a39786ee7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094970659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3094970659
Directory /workspace/13.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1454357889
Short name T1081
Test name
Test status
Simulation time 529269717 ps
CPU time 7.84 seconds
Started Jun 29 05:26:58 PM PDT 24
Finished Jun 29 05:27:06 PM PDT 24
Peak memory 215812 kb
Host smart-4ce3adf5-a46d-4270-9412-081b9738b1fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454357889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1454357889
Directory /workspace/13.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.211493024
Short name T100
Test name
Test status
Simulation time 102896764 ps
CPU time 1.79 seconds
Started Jun 29 05:26:52 PM PDT 24
Finished Jun 29 05:26:55 PM PDT 24
Peak memory 216468 kb
Host smart-8036fcf2-cf52-4785-8633-7e3030a8743c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211493024 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.211493024
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1199298098
Short name T117
Test name
Test status
Simulation time 659391627 ps
CPU time 1.84 seconds
Started Jun 29 05:27:00 PM PDT 24
Finished Jun 29 05:27:03 PM PDT 24
Peak memory 215324 kb
Host smart-e6a711b1-4b7f-4ee9-805e-2d473ccbc8f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199298098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1199298098
Directory /workspace/14.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.707743241
Short name T1145
Test name
Test status
Simulation time 18425862 ps
CPU time 0.75 seconds
Started Jun 29 05:26:51 PM PDT 24
Finished Jun 29 05:26:52 PM PDT 24
Peak memory 203844 kb
Host smart-cd3125e7-4090-4e7f-ac3c-500271e0fbe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707743241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.707743241
Directory /workspace/14.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3033882532
Short name T1136
Test name
Test status
Simulation time 234784837 ps
CPU time 4.16 seconds
Started Jun 29 05:26:52 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 215464 kb
Host smart-fad06051-86a0-4fb0-ba75-0cc58d7dd31e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033882532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3033882532
Directory /workspace/14.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2885114811
Short name T1147
Test name
Test status
Simulation time 834257997 ps
CPU time 5.34 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:59 PM PDT 24
Peak memory 215656 kb
Host smart-2b4b1381-f742-47db-8a48-227913981624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885114811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2885114811
Directory /workspace/14.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.156058986
Short name T175
Test name
Test status
Simulation time 217079301 ps
CPU time 6.83 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:10 PM PDT 24
Peak memory 215468 kb
Host smart-6570573c-9d8c-467e-93b8-875263a76f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156058986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.156058986
Directory /workspace/14.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.315217663
Short name T113
Test name
Test status
Simulation time 102835148 ps
CPU time 2.79 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 216396 kb
Host smart-5ec82eb6-e306-4ddd-8113-75d5f5a4fac9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315217663 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.315217663
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3614937027
Short name T1092
Test name
Test status
Simulation time 71054297 ps
CPU time 2.41 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:27:20 PM PDT 24
Peak memory 215408 kb
Host smart-5cce17a1-091f-411e-8e82-1a3ddd678584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614937027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3614937027
Directory /workspace/15.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4281325343
Short name T1144
Test name
Test status
Simulation time 11808225 ps
CPU time 0.69 seconds
Started Jun 29 05:26:57 PM PDT 24
Finished Jun 29 05:26:58 PM PDT 24
Peak memory 204140 kb
Host smart-40797d94-695c-4e44-86d1-0a58b02f31fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281325343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4281325343
Directory /workspace/15.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1015378158
Short name T1141
Test name
Test status
Simulation time 97758641 ps
CPU time 1.78 seconds
Started Jun 29 05:26:50 PM PDT 24
Finished Jun 29 05:26:52 PM PDT 24
Peak memory 215408 kb
Host smart-c2006b26-e507-43aa-b5fc-eea5d4e9cb72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015378158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1015378158
Directory /workspace/15.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2386446194
Short name T102
Test name
Test status
Simulation time 54516481 ps
CPU time 1.81 seconds
Started Jun 29 05:26:57 PM PDT 24
Finished Jun 29 05:27:00 PM PDT 24
Peak memory 215596 kb
Host smart-676156e5-2ad5-4c44-81a8-5f0abe692f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386446194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2386446194
Directory /workspace/15.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.493579634
Short name T154
Test name
Test status
Simulation time 745168837 ps
CPU time 15.69 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:27:11 PM PDT 24
Peak memory 216672 kb
Host smart-eebad3ba-50ad-445e-a1ac-ccf5f414f6ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493579634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.493579634
Directory /workspace/15.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3651036246
Short name T1089
Test name
Test status
Simulation time 98948847 ps
CPU time 2.51 seconds
Started Jun 29 05:26:58 PM PDT 24
Finished Jun 29 05:27:01 PM PDT 24
Peak memory 216960 kb
Host smart-3862926c-276c-4b88-b0c5-f0a0e1e82b23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651036246 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3651036246
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.709737857
Short name T140
Test name
Test status
Simulation time 402081601 ps
CPU time 1.29 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:55 PM PDT 24
Peak memory 207192 kb
Host smart-053875c7-4f1d-47ff-a843-baad3cbbabc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709737857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.709737857
Directory /workspace/16.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.130245368
Short name T1137
Test name
Test status
Simulation time 19809864 ps
CPU time 0.71 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 203816 kb
Host smart-4aca0860-5d87-4347-b27d-4101681e7e12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130245368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.130245368
Directory /workspace/16.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1643204533
Short name T1067
Test name
Test status
Simulation time 411618924 ps
CPU time 2.02 seconds
Started Jun 29 05:27:00 PM PDT 24
Finished Jun 29 05:27:02 PM PDT 24
Peak memory 215976 kb
Host smart-0e8599c1-9b55-4c7a-b8c5-a5e5212f82ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643204533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1643204533
Directory /workspace/16.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4000539043
Short name T96
Test name
Test status
Simulation time 24418221 ps
CPU time 1.58 seconds
Started Jun 29 05:27:03 PM PDT 24
Finished Jun 29 05:27:06 PM PDT 24
Peak memory 215620 kb
Host smart-17598e18-e8a6-4a2b-ac43-2340c6e52402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000539043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4000539043
Directory /workspace/16.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4125238398
Short name T153
Test name
Test status
Simulation time 1341709429 ps
CPU time 7.89 seconds
Started Jun 29 05:26:54 PM PDT 24
Finished Jun 29 05:27:03 PM PDT 24
Peak memory 215996 kb
Host smart-ed99cdca-1178-4e8a-990f-7a07af83319c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125238398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4125238398
Directory /workspace/16.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2095885718
Short name T1057
Test name
Test status
Simulation time 48805418 ps
CPU time 1.69 seconds
Started Jun 29 05:27:08 PM PDT 24
Finished Jun 29 05:27:10 PM PDT 24
Peak memory 215532 kb
Host smart-62450075-2a18-4b7d-96fa-d834e47a4471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095885718 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2095885718
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4292363768
Short name T1133
Test name
Test status
Simulation time 104446139 ps
CPU time 1.9 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:04 PM PDT 24
Peak memory 215324 kb
Host smart-5dde1c51-cae6-45f7-b63a-43667d05ed41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292363768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4292363768
Directory /workspace/17.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.153132082
Short name T1041
Test name
Test status
Simulation time 12082117 ps
CPU time 0.79 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:03 PM PDT 24
Peak memory 203872 kb
Host smart-d37352c3-6378-4d13-a4e6-93a0e6790edf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153132082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.153132082
Directory /workspace/17.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.313809867
Short name T1126
Test name
Test status
Simulation time 143734678 ps
CPU time 3.36 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:29 PM PDT 24
Peak memory 215440 kb
Host smart-7307bb58-7cd3-4b07-9329-80ecb7a24b1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313809867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.313809867
Directory /workspace/17.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3213853059
Short name T1103
Test name
Test status
Simulation time 64696730 ps
CPU time 1.92 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:09 PM PDT 24
Peak memory 215592 kb
Host smart-a12109c0-4cd1-4f19-9157-b0208d8eeb21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213853059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3213853059
Directory /workspace/17.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2293010494
Short name T1049
Test name
Test status
Simulation time 161276142 ps
CPU time 2.51 seconds
Started Jun 29 05:27:15 PM PDT 24
Finished Jun 29 05:27:17 PM PDT 24
Peak memory 215516 kb
Host smart-f2a395fa-a203-4122-a74c-a881e83c865b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293010494 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2293010494
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1655565471
Short name T1150
Test name
Test status
Simulation time 18273480 ps
CPU time 1.35 seconds
Started Jun 29 05:26:59 PM PDT 24
Finished Jun 29 05:27:01 PM PDT 24
Peak memory 215304 kb
Host smart-3566a47e-27bf-4df1-a51a-bdcf78956621
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655565471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1655565471
Directory /workspace/18.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4042642038
Short name T1123
Test name
Test status
Simulation time 54012499 ps
CPU time 0.76 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:09 PM PDT 24
Peak memory 204040 kb
Host smart-5318a8d9-110d-4c20-a78b-68a6fb11b004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042642038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4042642038
Directory /workspace/18.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4126430304
Short name T1072
Test name
Test status
Simulation time 101026642 ps
CPU time 1.59 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:09 PM PDT 24
Peak memory 215472 kb
Host smart-b80bf22d-bd95-46ce-a454-f8e46c1d6e10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126430304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4126430304
Directory /workspace/18.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.634637664
Short name T1111
Test name
Test status
Simulation time 263018851 ps
CPU time 2.4 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:10 PM PDT 24
Peak memory 215600 kb
Host smart-8cc4f68e-db7d-4f2d-bf2b-47bb9ca2056c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634637664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.634637664
Directory /workspace/18.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1021256296
Short name T178
Test name
Test status
Simulation time 106643168 ps
CPU time 7.03 seconds
Started Jun 29 05:27:00 PM PDT 24
Finished Jun 29 05:27:07 PM PDT 24
Peak memory 215880 kb
Host smart-4eb677fc-318a-4272-ad8e-be8ac7e3e117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021256296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1021256296
Directory /workspace/18.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.279742740
Short name T112
Test name
Test status
Simulation time 50100115 ps
CPU time 2.01 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:04 PM PDT 24
Peak memory 215496 kb
Host smart-2e77ebee-ad5f-4669-b774-82261ccef0b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279742740 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.279742740
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3886258558
Short name T125
Test name
Test status
Simulation time 191444487 ps
CPU time 1.27 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:05 PM PDT 24
Peak memory 207128 kb
Host smart-bc73cdc0-13b7-4216-8a4a-a6541fe5303c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886258558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3886258558
Directory /workspace/19.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1497277837
Short name T1051
Test name
Test status
Simulation time 16733973 ps
CPU time 0.77 seconds
Started Jun 29 05:27:03 PM PDT 24
Finished Jun 29 05:27:05 PM PDT 24
Peak memory 203792 kb
Host smart-5cf231fc-b0d3-41c0-8100-bb239646d3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497277837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1497277837
Directory /workspace/19.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2776532309
Short name T1053
Test name
Test status
Simulation time 755859820 ps
CPU time 1.76 seconds
Started Jun 29 05:27:11 PM PDT 24
Finished Jun 29 05:27:13 PM PDT 24
Peak memory 215396 kb
Host smart-6cb63aff-d5dd-4b37-a552-b493cba396ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776532309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2776532309
Directory /workspace/19.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3781673334
Short name T105
Test name
Test status
Simulation time 149605980 ps
CPU time 4.09 seconds
Started Jun 29 05:27:03 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 215620 kb
Host smart-13d9b227-daee-4f40-8694-2cc2205408a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781673334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3781673334
Directory /workspace/19.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2003066182
Short name T173
Test name
Test status
Simulation time 213956797 ps
CPU time 13.1 seconds
Started Jun 29 05:26:59 PM PDT 24
Finished Jun 29 05:27:13 PM PDT 24
Peak memory 215460 kb
Host smart-fd52a81d-625a-40d2-aec3-b2a6ba6129e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003066182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2003066182
Directory /workspace/19.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.137815225
Short name T118
Test name
Test status
Simulation time 212117459 ps
CPU time 15.28 seconds
Started Jun 29 05:26:30 PM PDT 24
Finished Jun 29 05:26:46 PM PDT 24
Peak memory 207208 kb
Host smart-f5b28766-28e3-4fdc-bff3-41379becfc6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137815225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.137815225
Directory /workspace/2.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1565873845
Short name T1142
Test name
Test status
Simulation time 1593756266 ps
CPU time 23.34 seconds
Started Jun 29 05:26:35 PM PDT 24
Finished Jun 29 05:26:59 PM PDT 24
Peak memory 207308 kb
Host smart-c6bc984a-516b-41d8-a34d-6822eba6022f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565873845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1565873845
Directory /workspace/2.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2321415961
Short name T79
Test name
Test status
Simulation time 25546373 ps
CPU time 1.02 seconds
Started Jun 29 05:26:43 PM PDT 24
Finished Jun 29 05:26:45 PM PDT 24
Peak memory 206840 kb
Host smart-dc4877ae-20a3-4b02-95dc-bf13ffa145bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321415961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2321415961
Directory /workspace/2.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1930641992
Short name T1102
Test name
Test status
Simulation time 228359971 ps
CPU time 2.88 seconds
Started Jun 29 05:26:32 PM PDT 24
Finished Jun 29 05:26:35 PM PDT 24
Peak memory 217332 kb
Host smart-4015afb4-accf-4a93-8f1d-0252dce08ea7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930641992 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1930641992
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.26717053
Short name T1124
Test name
Test status
Simulation time 59309129 ps
CPU time 1.92 seconds
Started Jun 29 05:26:47 PM PDT 24
Finished Jun 29 05:26:49 PM PDT 24
Peak memory 215328 kb
Host smart-0e9deb67-26a8-4152-bb55-93428be2df3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26717053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.26717053
Directory /workspace/2.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1182854129
Short name T1075
Test name
Test status
Simulation time 49442561 ps
CPU time 0.75 seconds
Started Jun 29 05:26:33 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 203872 kb
Host smart-e982940e-4a29-4ee9-bd7c-3c7f75a464a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182854129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
182854129
Directory /workspace/2.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.993220050
Short name T1138
Test name
Test status
Simulation time 113596737 ps
CPU time 1.44 seconds
Started Jun 29 05:26:33 PM PDT 24
Finished Jun 29 05:26:35 PM PDT 24
Peak memory 215468 kb
Host smart-3293b4a8-03b4-4135-b424-a23c80273e84
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993220050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.993220050
Directory /workspace/2.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3528812493
Short name T1032
Test name
Test status
Simulation time 21873844 ps
CPU time 0.67 seconds
Started Jun 29 05:26:33 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 203628 kb
Host smart-c01ccb26-4a40-458c-99f8-c0856a08e539
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528812493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3528812493
Directory /workspace/2.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3658084013
Short name T1146
Test name
Test status
Simulation time 324240922 ps
CPU time 4.78 seconds
Started Jun 29 05:26:35 PM PDT 24
Finished Jun 29 05:26:40 PM PDT 24
Peak memory 215460 kb
Host smart-15cff627-1463-4a12-9ca5-9eee86ce569f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658084013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3658084013
Directory /workspace/2.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2010008544
Short name T176
Test name
Test status
Simulation time 4249573545 ps
CPU time 23.53 seconds
Started Jun 29 05:26:48 PM PDT 24
Finished Jun 29 05:27:12 PM PDT 24
Peak memory 215536 kb
Host smart-8e0b1a7a-21c7-4878-b84a-038c3e2dc1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010008544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2010008544
Directory /workspace/2.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.367460373
Short name T1097
Test name
Test status
Simulation time 18698138 ps
CPU time 0.7 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:07 PM PDT 24
Peak memory 203800 kb
Host smart-4618640a-8d1a-4dc9-9a5b-8dd31a5a8000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367460373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.367460373
Directory /workspace/20.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.875097922
Short name T1037
Test name
Test status
Simulation time 11629582 ps
CPU time 0.75 seconds
Started Jun 29 05:26:54 PM PDT 24
Finished Jun 29 05:26:55 PM PDT 24
Peak memory 203872 kb
Host smart-2dc93acc-d59e-42c3-90e9-2d9b1303f631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875097922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.875097922
Directory /workspace/21.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.516562585
Short name T1082
Test name
Test status
Simulation time 26841001 ps
CPU time 0.75 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 203824 kb
Host smart-c6bee543-6b0e-4d94-a76d-fbf2810cc59e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516562585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.516562585
Directory /workspace/22.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1894665011
Short name T1056
Test name
Test status
Simulation time 26508685 ps
CPU time 0.76 seconds
Started Jun 29 05:26:58 PM PDT 24
Finished Jun 29 05:27:00 PM PDT 24
Peak memory 203820 kb
Host smart-19ee44be-e421-4521-af71-38a81e3b053f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894665011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1894665011
Directory /workspace/23.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.448895079
Short name T1046
Test name
Test status
Simulation time 51662260 ps
CPU time 0.77 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:07 PM PDT 24
Peak memory 203800 kb
Host smart-95ba7aa1-c03d-4820-be53-e7bcb13897f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448895079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.448895079
Directory /workspace/24.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3058329768
Short name T1050
Test name
Test status
Simulation time 36337355 ps
CPU time 0.68 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 203796 kb
Host smart-9420a63d-5933-4c0a-b8b2-049d1961a1ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058329768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3058329768
Directory /workspace/25.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3900180614
Short name T1076
Test name
Test status
Simulation time 75393391 ps
CPU time 0.82 seconds
Started Jun 29 05:27:00 PM PDT 24
Finished Jun 29 05:27:01 PM PDT 24
Peak memory 203788 kb
Host smart-b2f35fa3-e519-4429-90ed-cb9bfe7b4cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900180614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3900180614
Directory /workspace/26.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2244833929
Short name T1030
Test name
Test status
Simulation time 39534796 ps
CPU time 0.69 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 203820 kb
Host smart-f64378bc-2a6b-428e-ab7a-d5e3a3b8e905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244833929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2244833929
Directory /workspace/27.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3327474612
Short name T1036
Test name
Test status
Simulation time 13857006 ps
CPU time 0.82 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:04 PM PDT 24
Peak memory 203656 kb
Host smart-a9dfa47b-393f-493f-9218-12939644d423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327474612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3327474612
Directory /workspace/28.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4099344534
Short name T1101
Test name
Test status
Simulation time 12858176 ps
CPU time 0.74 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:07 PM PDT 24
Peak memory 203872 kb
Host smart-d1ed64ca-a43d-43cc-9df9-d2eb192ce598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099344534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4099344534
Directory /workspace/29.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2794564890
Short name T1080
Test name
Test status
Simulation time 396216689 ps
CPU time 8.67 seconds
Started Jun 29 05:26:38 PM PDT 24
Finished Jun 29 05:26:47 PM PDT 24
Peak memory 207204 kb
Host smart-848d614d-043b-4564-a01a-3d8e5f23d74f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794564890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2794564890
Directory /workspace/3.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3679751224
Short name T119
Test name
Test status
Simulation time 541967364 ps
CPU time 34.83 seconds
Started Jun 29 05:26:31 PM PDT 24
Finished Jun 29 05:27:06 PM PDT 24
Peak memory 207144 kb
Host smart-a734995d-f389-44ff-8aed-c00301bd2c3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679751224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3679751224
Directory /workspace/3.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1432985042
Short name T83
Test name
Test status
Simulation time 63309694 ps
CPU time 1.31 seconds
Started Jun 29 05:26:41 PM PDT 24
Finished Jun 29 05:26:42 PM PDT 24
Peak memory 207184 kb
Host smart-bbbc5e6b-7699-4ae7-b26a-ade63907eaea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432985042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1432985042
Directory /workspace/3.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.268958177
Short name T1118
Test name
Test status
Simulation time 46014011 ps
CPU time 1.65 seconds
Started Jun 29 05:26:52 PM PDT 24
Finished Jun 29 05:26:54 PM PDT 24
Peak memory 215528 kb
Host smart-5ac47e8c-06fd-46f5-9439-340faf0d84a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268958177 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.268958177
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2217922209
Short name T1063
Test name
Test status
Simulation time 18969598 ps
CPU time 1.22 seconds
Started Jun 29 05:26:35 PM PDT 24
Finished Jun 29 05:26:36 PM PDT 24
Peak memory 215380 kb
Host smart-f9904959-84e8-467e-8829-22a7bd34adb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217922209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
217922209
Directory /workspace/3.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2426119824
Short name T1070
Test name
Test status
Simulation time 31788628 ps
CPU time 0.77 seconds
Started Jun 29 05:26:50 PM PDT 24
Finished Jun 29 05:26:52 PM PDT 24
Peak memory 203848 kb
Host smart-5136aea6-7519-4830-8dc6-b7216296f13e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426119824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
426119824
Directory /workspace/3.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1648659973
Short name T116
Test name
Test status
Simulation time 51465997 ps
CPU time 1.85 seconds
Started Jun 29 05:26:32 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 215448 kb
Host smart-443d0925-b1f8-41fd-bd0d-cfd56966fa7d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648659973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1648659973
Directory /workspace/3.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3769215505
Short name T1128
Test name
Test status
Simulation time 29510156 ps
CPU time 0.67 seconds
Started Jun 29 05:26:50 PM PDT 24
Finished Jun 29 05:26:51 PM PDT 24
Peak memory 203708 kb
Host smart-d9740533-1b0f-44b8-93b6-0cd265ae510c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769215505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3769215505
Directory /workspace/3.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2328581146
Short name T141
Test name
Test status
Simulation time 164034515 ps
CPU time 2.86 seconds
Started Jun 29 05:26:35 PM PDT 24
Finished Jun 29 05:26:38 PM PDT 24
Peak memory 215448 kb
Host smart-bbbb9278-7fda-4e31-b810-564a543fb87f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328581146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2328581146
Directory /workspace/3.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1856540335
Short name T106
Test name
Test status
Simulation time 160048170 ps
CPU time 2.23 seconds
Started Jun 29 05:26:51 PM PDT 24
Finished Jun 29 05:26:54 PM PDT 24
Peak memory 215864 kb
Host smart-86b85512-cafd-43aa-aa86-2edaa51f05fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856540335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
856540335
Directory /workspace/3.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.947889978
Short name T97
Test name
Test status
Simulation time 1124280401 ps
CPU time 8.27 seconds
Started Jun 29 05:26:34 PM PDT 24
Finished Jun 29 05:26:43 PM PDT 24
Peak memory 215728 kb
Host smart-3d22e623-9a59-48f6-9ebe-99bb3d308c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947889978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.947889978
Directory /workspace/3.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1498172740
Short name T1130
Test name
Test status
Simulation time 20437862 ps
CPU time 0.7 seconds
Started Jun 29 05:27:06 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 203796 kb
Host smart-5ba87b79-9d80-4399-bef7-33351aa8397a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498172740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1498172740
Directory /workspace/30.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4020511640
Short name T1055
Test name
Test status
Simulation time 22200540 ps
CPU time 0.73 seconds
Started Jun 29 05:27:09 PM PDT 24
Finished Jun 29 05:27:10 PM PDT 24
Peak memory 203864 kb
Host smart-371a8fd3-5df8-43b7-94aa-0010fdff1e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020511640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4020511640
Directory /workspace/31.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3400797475
Short name T1106
Test name
Test status
Simulation time 32446769 ps
CPU time 0.74 seconds
Started Jun 29 05:27:04 PM PDT 24
Finished Jun 29 05:27:05 PM PDT 24
Peak memory 203812 kb
Host smart-7d55d2c3-51a7-46d8-ae5a-8297999e1a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400797475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3400797475
Directory /workspace/32.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3685638000
Short name T1121
Test name
Test status
Simulation time 18217333 ps
CPU time 0.8 seconds
Started Jun 29 05:27:03 PM PDT 24
Finished Jun 29 05:27:04 PM PDT 24
Peak memory 204056 kb
Host smart-4e2f140c-7a4e-48ad-bf0c-d5e2d6fad51b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685638000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3685638000
Directory /workspace/33.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3897677597
Short name T1033
Test name
Test status
Simulation time 39727841 ps
CPU time 0.72 seconds
Started Jun 29 05:27:08 PM PDT 24
Finished Jun 29 05:27:10 PM PDT 24
Peak memory 203820 kb
Host smart-6edc9335-d03e-4705-a9b1-317d4c34a6bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897677597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3897677597
Directory /workspace/34.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2340688396
Short name T1062
Test name
Test status
Simulation time 21749978 ps
CPU time 0.7 seconds
Started Jun 29 05:27:06 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 204112 kb
Host smart-9ada60d9-e182-4ccb-9a04-279a1adaef47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340688396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2340688396
Directory /workspace/35.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1186803353
Short name T1110
Test name
Test status
Simulation time 21252210 ps
CPU time 0.73 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:03 PM PDT 24
Peak memory 203800 kb
Host smart-6f473071-572b-4d8b-b4fa-85a91b7e2d1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186803353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1186803353
Directory /workspace/36.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1639273204
Short name T1038
Test name
Test status
Simulation time 222710359 ps
CPU time 0.84 seconds
Started Jun 29 05:27:00 PM PDT 24
Finished Jun 29 05:27:02 PM PDT 24
Peak memory 203876 kb
Host smart-18627672-e62f-4f90-b83d-58c29634f818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639273204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1639273204
Directory /workspace/37.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2139920631
Short name T1039
Test name
Test status
Simulation time 13938021 ps
CPU time 0.74 seconds
Started Jun 29 05:26:59 PM PDT 24
Finished Jun 29 05:27:00 PM PDT 24
Peak memory 203820 kb
Host smart-4047b700-a495-434f-9233-2eae01624d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139920631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2139920631
Directory /workspace/38.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2214341609
Short name T1068
Test name
Test status
Simulation time 15922050 ps
CPU time 0.76 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 203840 kb
Host smart-ddbdc335-3b8b-4c57-a21f-523fe7becbab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214341609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2214341609
Directory /workspace/39.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2364891330
Short name T1031
Test name
Test status
Simulation time 616084684 ps
CPU time 16.6 seconds
Started Jun 29 05:26:42 PM PDT 24
Finished Jun 29 05:26:59 PM PDT 24
Peak memory 207184 kb
Host smart-1200524c-91d0-4406-9ce6-6fdc430f0e68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364891330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2364891330
Directory /workspace/4.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1676720975
Short name T1096
Test name
Test status
Simulation time 184843504 ps
CPU time 12.41 seconds
Started Jun 29 05:26:37 PM PDT 24
Finished Jun 29 05:26:49 PM PDT 24
Peak memory 207060 kb
Host smart-76a36485-ad01-4048-b5e4-2c2360811677
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676720975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1676720975
Directory /workspace/4.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3485619637
Short name T81
Test name
Test status
Simulation time 58384196 ps
CPU time 1.16 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 216352 kb
Host smart-0364708d-674e-420e-9989-6302969134c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485619637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3485619637
Directory /workspace/4.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2768003778
Short name T1077
Test name
Test status
Simulation time 242612273 ps
CPU time 1.86 seconds
Started Jun 29 05:26:57 PM PDT 24
Finished Jun 29 05:26:59 PM PDT 24
Peak memory 215468 kb
Host smart-78a2628c-51f5-4023-af0c-d410ec9fc753
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768003778 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2768003778
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4213843732
Short name T1149
Test name
Test status
Simulation time 395337179 ps
CPU time 2.6 seconds
Started Jun 29 05:26:58 PM PDT 24
Finished Jun 29 05:27:01 PM PDT 24
Peak memory 215372 kb
Host smart-5881fb9f-71f8-4aa0-9d32-d6208104ad4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213843732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
213843732
Directory /workspace/4.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2170539607
Short name T1139
Test name
Test status
Simulation time 13551123 ps
CPU time 0.71 seconds
Started Jun 29 05:26:34 PM PDT 24
Finished Jun 29 05:26:35 PM PDT 24
Peak memory 204096 kb
Host smart-fa66662e-07c1-4563-a967-5cc9c42cd73a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170539607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
170539607
Directory /workspace/4.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1195500605
Short name T127
Test name
Test status
Simulation time 18479954 ps
CPU time 1.21 seconds
Started Jun 29 05:26:42 PM PDT 24
Finished Jun 29 05:26:44 PM PDT 24
Peak memory 215412 kb
Host smart-b4df8247-460b-4b6a-a9d8-495bea145536
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195500605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1195500605
Directory /workspace/4.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2244027602
Short name T1034
Test name
Test status
Simulation time 17878049 ps
CPU time 0.67 seconds
Started Jun 29 05:26:33 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 203712 kb
Host smart-c1af79e8-eecb-4686-bcef-2235b07ae251
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244027602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2244027602
Directory /workspace/4.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.187634527
Short name T1094
Test name
Test status
Simulation time 66544182 ps
CPU time 1.98 seconds
Started Jun 29 05:26:52 PM PDT 24
Finished Jun 29 05:27:00 PM PDT 24
Peak memory 215408 kb
Host smart-21d542c6-af76-4db2-8ff7-d9f71d35f1bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187634527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.187634527
Directory /workspace/4.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3989503295
Short name T101
Test name
Test status
Simulation time 158643547 ps
CPU time 2.3 seconds
Started Jun 29 05:26:46 PM PDT 24
Finished Jun 29 05:26:48 PM PDT 24
Peak memory 215624 kb
Host smart-7f1e2623-083b-4f10-9295-9ab83d9129f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989503295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
989503295
Directory /workspace/4.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3832818743
Short name T1132
Test name
Test status
Simulation time 1132350618 ps
CPU time 14.9 seconds
Started Jun 29 05:26:32 PM PDT 24
Finished Jun 29 05:26:48 PM PDT 24
Peak memory 215480 kb
Host smart-21e982d9-29c8-4fc4-9506-9cfe133c2520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832818743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3832818743
Directory /workspace/4.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1039846397
Short name T1079
Test name
Test status
Simulation time 15986877 ps
CPU time 0.71 seconds
Started Jun 29 05:27:06 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 203796 kb
Host smart-766d4705-502c-4f76-9fd3-e9d51c1d1427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039846397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1039846397
Directory /workspace/40.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3844955428
Short name T1047
Test name
Test status
Simulation time 14972873 ps
CPU time 0.81 seconds
Started Jun 29 05:26:56 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 204144 kb
Host smart-1b922d01-3590-44c2-8d61-2e3db0f3de37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844955428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3844955428
Directory /workspace/41.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.902304048
Short name T1042
Test name
Test status
Simulation time 42136232 ps
CPU time 0.72 seconds
Started Jun 29 05:27:09 PM PDT 24
Finished Jun 29 05:27:11 PM PDT 24
Peak memory 203880 kb
Host smart-f17c5fca-1e0d-4e5b-9ded-d63a9ba0cfe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902304048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.902304048
Directory /workspace/42.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4046881852
Short name T1099
Test name
Test status
Simulation time 14933079 ps
CPU time 0.78 seconds
Started Jun 29 05:27:00 PM PDT 24
Finished Jun 29 05:27:01 PM PDT 24
Peak memory 203784 kb
Host smart-2d60315c-0703-42e4-aca0-10413aae14a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046881852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4046881852
Directory /workspace/43.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1787856286
Short name T1048
Test name
Test status
Simulation time 32894645 ps
CPU time 0.78 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:03 PM PDT 24
Peak memory 204044 kb
Host smart-c4f9352c-23b8-4b5e-9623-86f9ab04e712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787856286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1787856286
Directory /workspace/44.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.577490506
Short name T1090
Test name
Test status
Simulation time 56201028 ps
CPU time 0.75 seconds
Started Jun 29 05:27:11 PM PDT 24
Finished Jun 29 05:27:12 PM PDT 24
Peak memory 204140 kb
Host smart-9acbf930-257f-4fff-b34e-c6b5d67b8696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577490506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.577490506
Directory /workspace/45.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1667007301
Short name T1135
Test name
Test status
Simulation time 53348771 ps
CPU time 0.75 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:26:57 PM PDT 24
Peak memory 204020 kb
Host smart-5286a6e1-2979-4a6c-a39c-f1bb78eca566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667007301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1667007301
Directory /workspace/46.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3851685329
Short name T1127
Test name
Test status
Simulation time 45059537 ps
CPU time 0.78 seconds
Started Jun 29 05:26:54 PM PDT 24
Finished Jun 29 05:26:56 PM PDT 24
Peak memory 203788 kb
Host smart-f54497fe-4ec7-44c2-a6d1-ca91438db95e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851685329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3851685329
Directory /workspace/47.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1494368930
Short name T1044
Test name
Test status
Simulation time 12742843 ps
CPU time 0.77 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 203872 kb
Host smart-7bcad744-24e4-4e4a-9015-c3ec94025530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494368930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1494368930
Directory /workspace/48.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.266602057
Short name T1045
Test name
Test status
Simulation time 14057037 ps
CPU time 0.71 seconds
Started Jun 29 05:27:04 PM PDT 24
Finished Jun 29 05:27:06 PM PDT 24
Peak memory 203848 kb
Host smart-0c4d6e9d-6eec-42c8-8aca-1e508f53a614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266602057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.266602057
Directory /workspace/49.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1488047431
Short name T1084
Test name
Test status
Simulation time 39881395 ps
CPU time 2.57 seconds
Started Jun 29 05:26:51 PM PDT 24
Finished Jun 29 05:26:54 PM PDT 24
Peak memory 216948 kb
Host smart-bd384d03-cc11-427e-b4ee-0b08500f7a70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488047431 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1488047431
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1975479430
Short name T121
Test name
Test status
Simulation time 204932199 ps
CPU time 2.58 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:05 PM PDT 24
Peak memory 215384 kb
Host smart-4ed6f8b5-7a9a-4d20-96e8-78120bfa020b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975479430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
975479430
Directory /workspace/5.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3476995992
Short name T1035
Test name
Test status
Simulation time 14539006 ps
CPU time 0.75 seconds
Started Jun 29 05:26:47 PM PDT 24
Finished Jun 29 05:26:49 PM PDT 24
Peak memory 203868 kb
Host smart-bd4ce1da-053d-4eb7-b79e-91852296dc85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476995992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
476995992
Directory /workspace/5.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3970088570
Short name T1091
Test name
Test status
Simulation time 122925177 ps
CPU time 4.01 seconds
Started Jun 29 05:26:44 PM PDT 24
Finished Jun 29 05:26:49 PM PDT 24
Peak memory 215320 kb
Host smart-05ad0e59-932b-4820-a532-ce9a42525352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970088570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3970088570
Directory /workspace/5.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1168411976
Short name T108
Test name
Test status
Simulation time 1384941995 ps
CPU time 2.7 seconds
Started Jun 29 05:26:38 PM PDT 24
Finished Jun 29 05:26:41 PM PDT 24
Peak memory 215480 kb
Host smart-c4c7200d-bcba-4f27-8d39-ee4292ddbe85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168411976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
168411976
Directory /workspace/5.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.290687828
Short name T98
Test name
Test status
Simulation time 1426528216 ps
CPU time 8.26 seconds
Started Jun 29 05:26:38 PM PDT 24
Finished Jun 29 05:26:47 PM PDT 24
Peak memory 215468 kb
Host smart-00311efc-0b78-4129-bfc7-50cb5a8dc1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290687828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.290687828
Directory /workspace/5.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3094118862
Short name T1086
Test name
Test status
Simulation time 95734668 ps
CPU time 2.86 seconds
Started Jun 29 05:26:38 PM PDT 24
Finished Jun 29 05:26:41 PM PDT 24
Peak memory 217120 kb
Host smart-168eee7e-667c-45b5-9410-13056754b3d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094118862 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3094118862
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2205136059
Short name T1119
Test name
Test status
Simulation time 161823973 ps
CPU time 1.32 seconds
Started Jun 29 05:26:50 PM PDT 24
Finished Jun 29 05:26:51 PM PDT 24
Peak memory 215408 kb
Host smart-1d167b13-51d9-4fd6-991f-6e9cfc4944cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205136059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
205136059
Directory /workspace/6.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3503504882
Short name T1071
Test name
Test status
Simulation time 16264617 ps
CPU time 0.76 seconds
Started Jun 29 05:26:38 PM PDT 24
Finished Jun 29 05:26:39 PM PDT 24
Peak memory 204144 kb
Host smart-178fa384-6ee2-497c-b1c4-c9ed67ee528d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503504882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
503504882
Directory /workspace/6.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2641110545
Short name T1114
Test name
Test status
Simulation time 70693246 ps
CPU time 1.79 seconds
Started Jun 29 05:26:57 PM PDT 24
Finished Jun 29 05:27:00 PM PDT 24
Peak memory 207180 kb
Host smart-3fbd0600-3d5f-49d0-ac1b-76fae0188ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641110545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2641110545
Directory /workspace/6.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.346340569
Short name T1073
Test name
Test status
Simulation time 421953216 ps
CPU time 6.57 seconds
Started Jun 29 05:26:54 PM PDT 24
Finished Jun 29 05:27:02 PM PDT 24
Peak memory 215440 kb
Host smart-217d6139-3782-499a-8c70-ed17172e30bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346340569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.346340569
Directory /workspace/6.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1790614926
Short name T1122
Test name
Test status
Simulation time 705746223 ps
CPU time 3.83 seconds
Started Jun 29 05:26:40 PM PDT 24
Finished Jun 29 05:26:44 PM PDT 24
Peak memory 218156 kb
Host smart-d574cb95-7b3a-41c1-bbf0-21e097a19022
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790614926 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1790614926
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.982843275
Short name T124
Test name
Test status
Simulation time 76148604 ps
CPU time 1.34 seconds
Started Jun 29 05:26:50 PM PDT 24
Finished Jun 29 05:26:52 PM PDT 24
Peak memory 215376 kb
Host smart-d899faa2-28e6-4330-9a66-a4668fd07910
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982843275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.982843275
Directory /workspace/7.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.470104781
Short name T1151
Test name
Test status
Simulation time 143876640 ps
CPU time 0.72 seconds
Started Jun 29 05:26:46 PM PDT 24
Finished Jun 29 05:26:47 PM PDT 24
Peak memory 203824 kb
Host smart-882777a1-b6f7-47b7-8d0c-d454a03c4d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470104781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.470104781
Directory /workspace/7.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3674185056
Short name T1148
Test name
Test status
Simulation time 680239154 ps
CPU time 4.04 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:27:00 PM PDT 24
Peak memory 215328 kb
Host smart-6100231a-6245-47e7-b469-acf1f12bcec2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674185056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3674185056
Directory /workspace/7.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1513692877
Short name T110
Test name
Test status
Simulation time 861028653 ps
CPU time 5.55 seconds
Started Jun 29 05:26:41 PM PDT 24
Finished Jun 29 05:26:47 PM PDT 24
Peak memory 215768 kb
Host smart-b75fb1c7-c697-46ae-81f3-d01222c227aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513692877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
513692877
Directory /workspace/7.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.377518276
Short name T1100
Test name
Test status
Simulation time 442328880 ps
CPU time 2.8 seconds
Started Jun 29 05:26:39 PM PDT 24
Finished Jun 29 05:26:42 PM PDT 24
Peak memory 216904 kb
Host smart-1b42a16b-72d9-4b10-91e5-93a907a2bc67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377518276 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.377518276
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.759650289
Short name T1107
Test name
Test status
Simulation time 238511319 ps
CPU time 1.96 seconds
Started Jun 29 05:26:48 PM PDT 24
Finished Jun 29 05:26:50 PM PDT 24
Peak memory 215272 kb
Host smart-cbb31a07-bb44-4256-a70f-8ee94f83e731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759650289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.759650289
Directory /workspace/8.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3165983760
Short name T1143
Test name
Test status
Simulation time 18708606 ps
CPU time 0.74 seconds
Started Jun 29 05:26:57 PM PDT 24
Finished Jun 29 05:26:58 PM PDT 24
Peak memory 204144 kb
Host smart-aa279ab0-e8f3-4ead-824e-4ebc34ec70d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165983760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
165983760
Directory /workspace/8.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3155596762
Short name T1104
Test name
Test status
Simulation time 60885650 ps
CPU time 1.77 seconds
Started Jun 29 05:26:39 PM PDT 24
Finished Jun 29 05:26:42 PM PDT 24
Peak memory 215900 kb
Host smart-eb5ff8f8-178a-4fe6-bbe3-59119aa0ee65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155596762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3155596762
Directory /workspace/8.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2638449114
Short name T1125
Test name
Test status
Simulation time 1768659984 ps
CPU time 4.62 seconds
Started Jun 29 05:26:45 PM PDT 24
Finished Jun 29 05:26:50 PM PDT 24
Peak memory 215464 kb
Host smart-07772854-6712-4501-ad72-6da78973b2ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638449114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
638449114
Directory /workspace/8.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1002072398
Short name T177
Test name
Test status
Simulation time 212270504 ps
CPU time 12.13 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:27:06 PM PDT 24
Peak memory 215456 kb
Host smart-6aca6243-4453-41da-abc9-7c0f3c1aa109
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002072398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1002072398
Directory /workspace/8.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3989517108
Short name T1120
Test name
Test status
Simulation time 271352566 ps
CPU time 3.97 seconds
Started Jun 29 05:26:42 PM PDT 24
Finished Jun 29 05:26:46 PM PDT 24
Peak memory 217572 kb
Host smart-bdd12a2e-d54f-4abd-b866-fc677e6d1e6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989517108 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3989517108
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3530570674
Short name T1129
Test name
Test status
Simulation time 175776639 ps
CPU time 2.56 seconds
Started Jun 29 05:26:45 PM PDT 24
Finished Jun 29 05:26:48 PM PDT 24
Peak memory 215364 kb
Host smart-38673049-9039-44f8-97a7-b4ee3e0a48e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530570674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
530570674
Directory /workspace/9.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.842963566
Short name T1040
Test name
Test status
Simulation time 22646593 ps
CPU time 0.74 seconds
Started Jun 29 05:26:55 PM PDT 24
Finished Jun 29 05:26:56 PM PDT 24
Peak memory 203824 kb
Host smart-6505cd6f-995a-4f40-bdd6-680c714d5d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842963566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.842963566
Directory /workspace/9.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4125981451
Short name T1116
Test name
Test status
Simulation time 129024313 ps
CPU time 4.15 seconds
Started Jun 29 05:26:45 PM PDT 24
Finished Jun 29 05:26:50 PM PDT 24
Peak memory 215352 kb
Host smart-b179ff91-c688-4e2b-8205-d95591eeb264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125981451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4125981451
Directory /workspace/9.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3544118276
Short name T156
Test name
Test status
Simulation time 2194394364 ps
CPU time 15.24 seconds
Started Jun 29 05:26:51 PM PDT 24
Finished Jun 29 05:27:07 PM PDT 24
Peak memory 216668 kb
Host smart-b5436753-b7b8-4da8-a5bf-f7bea53d450f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544118276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3544118276
Directory /workspace/9.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2769530774
Short name T397
Test name
Test status
Simulation time 3137920544 ps
CPU time 5.79 seconds
Started Jun 29 06:48:08 PM PDT 24
Finished Jun 29 06:48:14 PM PDT 24
Peak memory 232828 kb
Host smart-7bedbf4d-a7a9-4ae2-8c5c-5bd4d7b41df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769530774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2769530774
Directory /workspace/0.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/0.spi_device_csb_read.1024993975
Short name T548
Test name
Test status
Simulation time 53019735 ps
CPU time 0.72 seconds
Started Jun 29 06:48:08 PM PDT 24
Finished Jun 29 06:48:09 PM PDT 24
Peak memory 205488 kb
Host smart-636b4aec-7d24-4596-91c0-b06c020529e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024993975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1024993975
Directory /workspace/0.spi_device_csb_read/latest


Test location /workspace/coverage/default/0.spi_device_flash_all.4270797526
Short name T4
Test name
Test status
Simulation time 47107629435 ps
CPU time 95.3 seconds
Started Jun 29 06:48:10 PM PDT 24
Finished Jun 29 06:49:46 PM PDT 24
Peak memory 252200 kb
Host smart-11a39b85-4a58-48b6-b2eb-04a200e2acc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270797526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4270797526
Directory /workspace/0.spi_device_flash_all/latest


Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2318280627
Short name T50
Test name
Test status
Simulation time 30890000590 ps
CPU time 298.2 seconds
Started Jun 29 06:48:06 PM PDT 24
Finished Jun 29 06:53:05 PM PDT 24
Peak memory 255676 kb
Host smart-8c6f2e03-d212-45c6-a5dc-7e96ad383091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318280627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2318280627
Directory /workspace/0.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3631327245
Short name T474
Test name
Test status
Simulation time 5298577633 ps
CPU time 36.51 seconds
Started Jun 29 06:48:06 PM PDT 24
Finished Jun 29 06:48:43 PM PDT 24
Peak memory 237764 kb
Host smart-9fb64e23-a36c-43b2-ac78-20d431261979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631327245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3631327245
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/0.spi_device_flash_mode.996636213
Short name T978
Test name
Test status
Simulation time 10239967921 ps
CPU time 37.48 seconds
Started Jun 29 06:48:09 PM PDT 24
Finished Jun 29 06:48:46 PM PDT 24
Peak memory 232804 kb
Host smart-1f5f5631-f80e-44b0-87cf-6ed6ff200c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996636213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.996636213
Directory /workspace/0.spi_device_flash_mode/latest


Test location /workspace/coverage/default/0.spi_device_intercept.3421802459
Short name T719
Test name
Test status
Simulation time 261979090 ps
CPU time 4.8 seconds
Started Jun 29 06:48:09 PM PDT 24
Finished Jun 29 06:48:14 PM PDT 24
Peak memory 232616 kb
Host smart-2a4f641d-2f2d-4be3-b0f8-cd1b32b27906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421802459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3421802459
Directory /workspace/0.spi_device_intercept/latest


Test location /workspace/coverage/default/0.spi_device_mailbox.3610239199
Short name T928
Test name
Test status
Simulation time 3492491868 ps
CPU time 31.39 seconds
Started Jun 29 06:48:05 PM PDT 24
Finished Jun 29 06:48:37 PM PDT 24
Peak memory 218928 kb
Host smart-61e1a4fd-41a2-413a-81d7-4afcb7b9d5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610239199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3610239199
Directory /workspace/0.spi_device_mailbox/latest


Test location /workspace/coverage/default/0.spi_device_mem_parity.2423059079
Short name T659
Test name
Test status
Simulation time 35341605 ps
CPU time 1.09 seconds
Started Jun 29 06:48:05 PM PDT 24
Finished Jun 29 06:48:07 PM PDT 24
Peak memory 216792 kb
Host smart-ceeb2162-5551-4977-8544-89917ee6c677
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423059079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2423059079
Directory /workspace/0.spi_device_mem_parity/latest


Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.267851997
Short name T40
Test name
Test status
Simulation time 10388370995 ps
CPU time 13.7 seconds
Started Jun 29 06:48:09 PM PDT 24
Finished Jun 29 06:48:23 PM PDT 24
Peak memory 232760 kb
Host smart-2e133d57-1e31-4ce0-a063-81d60ffcd117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267851997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
267851997
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2564396170
Short name T606
Test name
Test status
Simulation time 1294791211 ps
CPU time 5.71 seconds
Started Jun 29 06:48:06 PM PDT 24
Finished Jun 29 06:48:13 PM PDT 24
Peak memory 232648 kb
Host smart-48583adf-b4d3-426e-93a2-ffcae9c0844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564396170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2564396170
Directory /workspace/0.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.285647006
Short name T482
Test name
Test status
Simulation time 1259067561 ps
CPU time 6.84 seconds
Started Jun 29 06:48:08 PM PDT 24
Finished Jun 29 06:48:15 PM PDT 24
Peak memory 219140 kb
Host smart-fcf2c53b-60f1-4d0d-a852-05289ddfbd5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=285647006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.285647006
Directory /workspace/0.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/0.spi_device_sec_cm.1037522477
Short name T66
Test name
Test status
Simulation time 269554658 ps
CPU time 1.07 seconds
Started Jun 29 06:48:07 PM PDT 24
Finished Jun 29 06:48:08 PM PDT 24
Peak memory 235928 kb
Host smart-379ceda5-769d-4f3f-a4ac-84bf185779f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037522477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1037522477
Directory /workspace/0.spi_device_sec_cm/latest


Test location /workspace/coverage/default/0.spi_device_tpm_all.1700968104
Short name T783
Test name
Test status
Simulation time 9665698096 ps
CPU time 7.72 seconds
Started Jun 29 06:48:08 PM PDT 24
Finished Jun 29 06:48:16 PM PDT 24
Peak memory 216656 kb
Host smart-da505513-d93e-4b2c-a479-3e614e3e64d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700968104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1700968104
Directory /workspace/0.spi_device_tpm_all/latest


Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4120542936
Short name T702
Test name
Test status
Simulation time 2666713980 ps
CPU time 5.78 seconds
Started Jun 29 06:48:08 PM PDT 24
Finished Jun 29 06:48:14 PM PDT 24
Peak memory 216344 kb
Host smart-df74bd4a-f873-4d1d-8ccf-bdeb71acdec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120542936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4120542936
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/0.spi_device_tpm_rw.1336309914
Short name T627
Test name
Test status
Simulation time 30804782 ps
CPU time 0.72 seconds
Started Jun 29 06:48:08 PM PDT 24
Finished Jun 29 06:48:09 PM PDT 24
Peak memory 205596 kb
Host smart-c61972ad-596e-4e35-8933-d7d2afaf7895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336309914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1336309914
Directory /workspace/0.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.277552844
Short name T324
Test name
Test status
Simulation time 22530266 ps
CPU time 0.79 seconds
Started Jun 29 06:48:10 PM PDT 24
Finished Jun 29 06:48:11 PM PDT 24
Peak memory 205884 kb
Host smart-be1be5d1-9f9b-4b67-8576-2c375851623d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277552844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.277552844
Directory /workspace/0.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/0.spi_device_upload.2917009713
Short name T795
Test name
Test status
Simulation time 169361259 ps
CPU time 4.5 seconds
Started Jun 29 06:48:08 PM PDT 24
Finished Jun 29 06:48:13 PM PDT 24
Peak memory 232648 kb
Host smart-d0d4783b-c77a-4c5d-af8e-61f1c836f321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917009713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2917009713
Directory /workspace/0.spi_device_upload/latest


Test location /workspace/coverage/default/1.spi_device_alert_test.3806706988
Short name T749
Test name
Test status
Simulation time 127659198 ps
CPU time 0.75 seconds
Started Jun 29 06:48:15 PM PDT 24
Finished Jun 29 06:48:17 PM PDT 24
Peak memory 205772 kb
Host smart-f951274a-624e-4b04-a657-dcbe54c9e49c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806706988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
806706988
Directory /workspace/1.spi_device_alert_test/latest


Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2873736895
Short name T675
Test name
Test status
Simulation time 247496018 ps
CPU time 2.62 seconds
Started Jun 29 06:48:14 PM PDT 24
Finished Jun 29 06:48:17 PM PDT 24
Peak memory 223888 kb
Host smart-ee890948-41ca-4a0b-9f06-7f1a7d0ccd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873736895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2873736895
Directory /workspace/1.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/1.spi_device_csb_read.2037188682
Short name T537
Test name
Test status
Simulation time 58291990 ps
CPU time 0.83 seconds
Started Jun 29 06:48:09 PM PDT 24
Finished Jun 29 06:48:10 PM PDT 24
Peak memory 206892 kb
Host smart-101ffc63-fa1e-4ba7-b69a-3794e44e68c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037188682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2037188682
Directory /workspace/1.spi_device_csb_read/latest


Test location /workspace/coverage/default/1.spi_device_flash_all.2119996066
Short name T860
Test name
Test status
Simulation time 51695497403 ps
CPU time 124.41 seconds
Started Jun 29 06:48:14 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 255416 kb
Host smart-c436e38a-7c7b-4124-a166-8d481c8aefad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119996066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2119996066
Directory /workspace/1.spi_device_flash_all/latest


Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3266361663
Short name T214
Test name
Test status
Simulation time 192148361949 ps
CPU time 458.36 seconds
Started Jun 29 06:48:12 PM PDT 24
Finished Jun 29 06:55:51 PM PDT 24
Peak memory 254240 kb
Host smart-7e873a2b-5f7a-40cc-823c-b082d730b2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266361663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3266361663
Directory /workspace/1.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2965419784
Short name T616
Test name
Test status
Simulation time 2955576034 ps
CPU time 42.56 seconds
Started Jun 29 06:48:14 PM PDT 24
Finished Jun 29 06:48:57 PM PDT 24
Peak memory 249244 kb
Host smart-f907e302-cb1c-46b8-86bb-56a538bca854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965419784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2965419784
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/1.spi_device_flash_mode.1587248878
Short name T171
Test name
Test status
Simulation time 9131727991 ps
CPU time 16.43 seconds
Started Jun 29 06:48:16 PM PDT 24
Finished Jun 29 06:48:33 PM PDT 24
Peak memory 249468 kb
Host smart-dbd93e4e-c5bd-49c8-bcfc-67a1b85d0dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587248878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1587248878
Directory /workspace/1.spi_device_flash_mode/latest


Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1685102411
Short name T271
Test name
Test status
Simulation time 928857454 ps
CPU time 22.26 seconds
Started Jun 29 06:48:12 PM PDT 24
Finished Jun 29 06:48:34 PM PDT 24
Peak memory 233928 kb
Host smart-22dfacbd-89b7-4fe2-8f91-53c766c648d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685102411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1685102411
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/1.spi_device_intercept.2505342663
Short name T753
Test name
Test status
Simulation time 586347753 ps
CPU time 6.03 seconds
Started Jun 29 06:48:14 PM PDT 24
Finished Jun 29 06:48:20 PM PDT 24
Peak memory 232604 kb
Host smart-e1be7eba-fbfb-4984-bb24-87eba235bfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505342663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2505342663
Directory /workspace/1.spi_device_intercept/latest


Test location /workspace/coverage/default/1.spi_device_mailbox.1803437654
Short name T757
Test name
Test status
Simulation time 322413117 ps
CPU time 2.74 seconds
Started Jun 29 06:48:19 PM PDT 24
Finished Jun 29 06:48:22 PM PDT 24
Peak memory 226980 kb
Host smart-b4bc058e-4560-454a-b64d-99e560bbe9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803437654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1803437654
Directory /workspace/1.spi_device_mailbox/latest


Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2629268446
Short name T770
Test name
Test status
Simulation time 76463666 ps
CPU time 2.14 seconds
Started Jun 29 06:48:18 PM PDT 24
Finished Jun 29 06:48:21 PM PDT 24
Peak memory 223160 kb
Host smart-238b927f-d421-46fb-91e9-14a76c006b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629268446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2629268446
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1534308650
Short name T971
Test name
Test status
Simulation time 591588976 ps
CPU time 5.02 seconds
Started Jun 29 06:48:15 PM PDT 24
Finished Jun 29 06:48:21 PM PDT 24
Peak memory 232580 kb
Host smart-121347f3-86c4-4ff6-875c-e3f97a6e7e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534308650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1534308650
Directory /workspace/1.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1340830230
Short name T381
Test name
Test status
Simulation time 1325718749 ps
CPU time 9.8 seconds
Started Jun 29 06:48:16 PM PDT 24
Finished Jun 29 06:48:27 PM PDT 24
Peak memory 219156 kb
Host smart-12817fcc-7097-49c4-8b7b-8b779a49c603
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1340830230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1340830230
Directory /workspace/1.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/1.spi_device_tpm_all.3906922949
Short name T25
Test name
Test status
Simulation time 1668284601 ps
CPU time 9.51 seconds
Started Jun 29 06:48:16 PM PDT 24
Finished Jun 29 06:48:26 PM PDT 24
Peak memory 216188 kb
Host smart-352d2191-af97-40d2-b504-cf8561ad384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906922949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3906922949
Directory /workspace/1.spi_device_tpm_all/latest


Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1295975829
Short name T707
Test name
Test status
Simulation time 1007195242 ps
CPU time 7.01 seconds
Started Jun 29 06:48:18 PM PDT 24
Finished Jun 29 06:48:25 PM PDT 24
Peak memory 216176 kb
Host smart-48793b99-ecf6-44c1-a853-f7f6e65d7e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295975829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1295975829
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/1.spi_device_tpm_rw.528221551
Short name T685
Test name
Test status
Simulation time 46383023 ps
CPU time 1.39 seconds
Started Jun 29 06:48:14 PM PDT 24
Finished Jun 29 06:48:16 PM PDT 24
Peak memory 215640 kb
Host smart-58e43906-6f55-451d-8045-2452dcfe975c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528221551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.528221551
Directory /workspace/1.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.185776816
Short name T847
Test name
Test status
Simulation time 15137856 ps
CPU time 0.73 seconds
Started Jun 29 06:48:18 PM PDT 24
Finished Jun 29 06:48:19 PM PDT 24
Peak memory 205816 kb
Host smart-d60a562e-91ed-415f-93c9-32962ee21f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185776816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.185776816
Directory /workspace/1.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/1.spi_device_upload.2080597252
Short name T632
Test name
Test status
Simulation time 646483543 ps
CPU time 4.19 seconds
Started Jun 29 06:48:19 PM PDT 24
Finished Jun 29 06:48:23 PM PDT 24
Peak memory 224416 kb
Host smart-7da4f257-3fe0-4e51-9a72-88eb148923a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080597252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2080597252
Directory /workspace/1.spi_device_upload/latest


Test location /workspace/coverage/default/10.spi_device_alert_test.93593401
Short name T816
Test name
Test status
Simulation time 12052423 ps
CPU time 0.71 seconds
Started Jun 29 06:48:41 PM PDT 24
Finished Jun 29 06:48:42 PM PDT 24
Peak memory 204840 kb
Host smart-dcded1b8-65c8-4b5c-a971-ccfb00d9e87f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93593401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.93593401
Directory /workspace/10.spi_device_alert_test/latest


Test location /workspace/coverage/default/10.spi_device_cfg_cmd.385841211
Short name T425
Test name
Test status
Simulation time 263426669 ps
CPU time 2.6 seconds
Started Jun 29 06:48:42 PM PDT 24
Finished Jun 29 06:48:46 PM PDT 24
Peak memory 224444 kb
Host smart-d6b52814-3db7-44da-91c5-7ff26222a0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385841211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.385841211
Directory /workspace/10.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/10.spi_device_csb_read.29324836
Short name T964
Test name
Test status
Simulation time 68456258 ps
CPU time 0.8 seconds
Started Jun 29 06:48:42 PM PDT 24
Finished Jun 29 06:48:44 PM PDT 24
Peak memory 206556 kb
Host smart-6ede3154-4763-4e79-ac49-7210af258095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29324836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.29324836
Directory /workspace/10.spi_device_csb_read/latest


Test location /workspace/coverage/default/10.spi_device_flash_all.1614361545
Short name T221
Test name
Test status
Simulation time 31182200418 ps
CPU time 102.78 seconds
Started Jun 29 06:48:43 PM PDT 24
Finished Jun 29 06:50:27 PM PDT 24
Peak memory 253072 kb
Host smart-7d7563fd-cdef-416f-b76c-aeeff9077e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614361545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1614361545
Directory /workspace/10.spi_device_flash_all/latest


Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.678053549
Short name T352
Test name
Test status
Simulation time 19981349948 ps
CPU time 219.24 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 06:52:26 PM PDT 24
Peak memory 268996 kb
Host smart-29ac1acd-4a0b-4b80-ac43-c1eb23e10d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678053549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.678053549
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/10.spi_device_flash_mode.4289729018
Short name T360
Test name
Test status
Simulation time 2918433041 ps
CPU time 11.44 seconds
Started Jun 29 06:48:43 PM PDT 24
Finished Jun 29 06:48:56 PM PDT 24
Peak memory 224508 kb
Host smart-95ef81a7-e04a-4d28-95f4-ed018e2b6548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289729018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4289729018
Directory /workspace/10.spi_device_flash_mode/latest


Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.629150198
Short name T456
Test name
Test status
Simulation time 6469198152 ps
CPU time 21.07 seconds
Started Jun 29 06:48:45 PM PDT 24
Finished Jun 29 06:49:06 PM PDT 24
Peak memory 237572 kb
Host smart-5cacdc08-36b4-43c8-b1d1-56118d49c52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629150198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.629150198
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/10.spi_device_intercept.1250921133
Short name T553
Test name
Test status
Simulation time 326305690 ps
CPU time 5.08 seconds
Started Jun 29 06:48:40 PM PDT 24
Finished Jun 29 06:48:46 PM PDT 24
Peak memory 232676 kb
Host smart-82075f16-8f55-4018-a119-337f492422aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250921133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1250921133
Directory /workspace/10.spi_device_intercept/latest


Test location /workspace/coverage/default/10.spi_device_mailbox.3462038613
Short name T871
Test name
Test status
Simulation time 31711981 ps
CPU time 2.5 seconds
Started Jun 29 06:48:41 PM PDT 24
Finished Jun 29 06:48:45 PM PDT 24
Peak memory 232384 kb
Host smart-875c01fc-0b90-4190-b420-2e2dbd291feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462038613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3462038613
Directory /workspace/10.spi_device_mailbox/latest


Test location /workspace/coverage/default/10.spi_device_mem_parity.1592079063
Short name T516
Test name
Test status
Simulation time 61065087 ps
CPU time 1.05 seconds
Started Jun 29 06:48:42 PM PDT 24
Finished Jun 29 06:48:44 PM PDT 24
Peak memory 216780 kb
Host smart-26928c44-e2a4-4fa9-962a-cb88411651fa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592079063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1592079063
Directory /workspace/10.spi_device_mem_parity/latest


Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3937475454
Short name T12
Test name
Test status
Simulation time 7118182699 ps
CPU time 19.06 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 06:49:06 PM PDT 24
Peak memory 232632 kb
Host smart-9682ea4c-41af-465f-a2e5-bc00fa114609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937475454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3937475454
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3909499149
Short name T640
Test name
Test status
Simulation time 3252434820 ps
CPU time 13.54 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 06:49:00 PM PDT 24
Peak memory 223176 kb
Host smart-8f54d603-d8e4-4d5c-8a86-2cf46845d2eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3909499149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3909499149
Directory /workspace/10.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/10.spi_device_stress_all.537806143
Short name T528
Test name
Test status
Simulation time 322674656 ps
CPU time 1.1 seconds
Started Jun 29 06:48:43 PM PDT 24
Finished Jun 29 06:48:46 PM PDT 24
Peak memory 207060 kb
Host smart-54fb39a2-6e07-4e59-8af7-574fa465a707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537806143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.537806143
Directory /workspace/10.spi_device_stress_all/latest


Test location /workspace/coverage/default/10.spi_device_tpm_all.794389135
Short name T464
Test name
Test status
Simulation time 569475515 ps
CPU time 5.7 seconds
Started Jun 29 06:48:42 PM PDT 24
Finished Jun 29 06:48:50 PM PDT 24
Peak memory 216144 kb
Host smart-65eb577c-bf67-4511-aa02-6b85e08dfb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794389135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.794389135
Directory /workspace/10.spi_device_tpm_all/latest


Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4176184969
Short name T5
Test name
Test status
Simulation time 645426343 ps
CPU time 4.29 seconds
Started Jun 29 06:48:41 PM PDT 24
Finished Jun 29 06:48:46 PM PDT 24
Peak memory 216128 kb
Host smart-c3f551ef-d801-4d54-8565-730bbd835e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176184969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4176184969
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/10.spi_device_tpm_rw.4289401669
Short name T9
Test name
Test status
Simulation time 313160513 ps
CPU time 1.22 seconds
Started Jun 29 06:48:42 PM PDT 24
Finished Jun 29 06:48:45 PM PDT 24
Peak memory 207852 kb
Host smart-3d41db25-3600-4684-a8a2-609032c6325a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289401669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4289401669
Directory /workspace/10.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1648676859
Short name T333
Test name
Test status
Simulation time 209696849 ps
CPU time 0.79 seconds
Started Jun 29 06:48:39 PM PDT 24
Finished Jun 29 06:48:41 PM PDT 24
Peak memory 205884 kb
Host smart-189a70d2-60a1-429d-ae4a-6f59dd5c5f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648676859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1648676859
Directory /workspace/10.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/10.spi_device_upload.2138771773
Short name T643
Test name
Test status
Simulation time 1574353393 ps
CPU time 8.68 seconds
Started Jun 29 06:48:48 PM PDT 24
Finished Jun 29 06:48:57 PM PDT 24
Peak memory 237124 kb
Host smart-03c8cdde-e22a-4176-8564-1a91eeaf859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138771773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2138771773
Directory /workspace/10.spi_device_upload/latest


Test location /workspace/coverage/default/11.spi_device_alert_test.4234084659
Short name T974
Test name
Test status
Simulation time 59071637 ps
CPU time 0.82 seconds
Started Jun 29 06:48:52 PM PDT 24
Finished Jun 29 06:48:53 PM PDT 24
Peak memory 204844 kb
Host smart-9ef3bf3d-5194-4e5a-8255-d1dfe940ff14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234084659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4234084659
Directory /workspace/11.spi_device_alert_test/latest


Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3751672858
Short name T825
Test name
Test status
Simulation time 685433425 ps
CPU time 3.72 seconds
Started Jun 29 06:48:48 PM PDT 24
Finished Jun 29 06:48:52 PM PDT 24
Peak memory 224476 kb
Host smart-1f799b31-81e7-40f5-9bd2-b15f7d32ed6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751672858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3751672858
Directory /workspace/11.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/11.spi_device_csb_read.1098580471
Short name T552
Test name
Test status
Simulation time 25905930 ps
CPU time 0.76 seconds
Started Jun 29 06:48:55 PM PDT 24
Finished Jun 29 06:48:57 PM PDT 24
Peak memory 205852 kb
Host smart-e3fa0b42-eafa-4d8d-aacf-f2fff99eb610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098580471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1098580471
Directory /workspace/11.spi_device_csb_read/latest


Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1360319510
Short name T612
Test name
Test status
Simulation time 48054770166 ps
CPU time 160.98 seconds
Started Jun 29 06:48:49 PM PDT 24
Finished Jun 29 06:51:30 PM PDT 24
Peak memory 249164 kb
Host smart-2f522476-d059-4cdd-bff0-e4ba5f9838eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360319510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1360319510
Directory /workspace/11.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1881217098
Short name T191
Test name
Test status
Simulation time 105949310162 ps
CPU time 221.17 seconds
Started Jun 29 06:48:50 PM PDT 24
Finished Jun 29 06:52:32 PM PDT 24
Peak memory 257372 kb
Host smart-a162a345-11db-4abc-ae92-623837858a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881217098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1881217098
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2066583296
Short name T453
Test name
Test status
Simulation time 12591180865 ps
CPU time 79.8 seconds
Started Jun 29 06:48:48 PM PDT 24
Finished Jun 29 06:50:08 PM PDT 24
Peak memory 239628 kb
Host smart-c7408980-274e-4501-8d36-b8ff551bfdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066583296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2066583296
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/11.spi_device_intercept.2326744164
Short name T585
Test name
Test status
Simulation time 8776694845 ps
CPU time 18.86 seconds
Started Jun 29 06:48:52 PM PDT 24
Finished Jun 29 06:49:12 PM PDT 24
Peak memory 232736 kb
Host smart-1435e84e-2a75-4090-a79c-0e582425e259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326744164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2326744164
Directory /workspace/11.spi_device_intercept/latest


Test location /workspace/coverage/default/11.spi_device_mailbox.2166604055
Short name T836
Test name
Test status
Simulation time 215430609001 ps
CPU time 166.79 seconds
Started Jun 29 06:48:48 PM PDT 24
Finished Jun 29 06:51:36 PM PDT 24
Peak memory 233776 kb
Host smart-08cc5b5e-bb33-491c-94ae-fa60951143b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166604055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2166604055
Directory /workspace/11.spi_device_mailbox/latest


Test location /workspace/coverage/default/11.spi_device_mem_parity.944590061
Short name T31
Test name
Test status
Simulation time 28257088 ps
CPU time 1.07 seconds
Started Jun 29 06:48:47 PM PDT 24
Finished Jun 29 06:48:49 PM PDT 24
Peak memory 216776 kb
Host smart-93b4066a-c7c8-4b9f-b2f8-6985a3517fb5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944590061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.944590061
Directory /workspace/11.spi_device_mem_parity/latest


Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3346952274
Short name T671
Test name
Test status
Simulation time 2191050325 ps
CPU time 2.51 seconds
Started Jun 29 06:48:55 PM PDT 24
Finished Jun 29 06:48:58 PM PDT 24
Peak memory 224536 kb
Host smart-b8caacbe-d894-4a22-afaf-76e20505c90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346952274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3346952274
Directory /workspace/11.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4232818676
Short name T492
Test name
Test status
Simulation time 1609817457 ps
CPU time 6.41 seconds
Started Jun 29 06:48:45 PM PDT 24
Finished Jun 29 06:48:51 PM PDT 24
Peak memory 222916 kb
Host smart-e02ab53d-caf8-4c60-8b7a-79e588dd3b5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4232818676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4232818676
Directory /workspace/11.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/11.spi_device_tpm_all.2134988891
Short name T910
Test name
Test status
Simulation time 370519770 ps
CPU time 4.73 seconds
Started Jun 29 06:48:54 PM PDT 24
Finished Jun 29 06:48:59 PM PDT 24
Peak memory 216224 kb
Host smart-515f2e9e-b3d2-4104-8b4c-4b27876c2515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134988891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2134988891
Directory /workspace/11.spi_device_tpm_all/latest


Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2665309040
Short name T350
Test name
Test status
Simulation time 16339486568 ps
CPU time 10.21 seconds
Started Jun 29 06:48:51 PM PDT 24
Finished Jun 29 06:49:02 PM PDT 24
Peak memory 216312 kb
Host smart-e256a45b-8f68-4d4d-b64b-387096dd704f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665309040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2665309040
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/11.spi_device_tpm_rw.1051175351
Short name T319
Test name
Test status
Simulation time 29756241 ps
CPU time 0.7 seconds
Started Jun 29 06:48:50 PM PDT 24
Finished Jun 29 06:48:51 PM PDT 24
Peak memory 205592 kb
Host smart-ae145de0-c1d1-46b7-aa1a-9ab7fc250fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051175351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1051175351
Directory /workspace/11.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2268996282
Short name T332
Test name
Test status
Simulation time 38225072 ps
CPU time 0.86 seconds
Started Jun 29 06:48:47 PM PDT 24
Finished Jun 29 06:48:49 PM PDT 24
Peak memory 205852 kb
Host smart-fb6b6b79-57fb-4acc-aca0-47f4b24d27ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268996282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2268996282
Directory /workspace/11.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/11.spi_device_upload.3457864019
Short name T735
Test name
Test status
Simulation time 5719613952 ps
CPU time 18 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 06:49:05 PM PDT 24
Peak memory 232792 kb
Host smart-0780f95b-46cc-4165-9e5a-09cdc1fd0f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457864019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3457864019
Directory /workspace/11.spi_device_upload/latest


Test location /workspace/coverage/default/12.spi_device_alert_test.3585305705
Short name T384
Test name
Test status
Simulation time 40125878 ps
CPU time 0.7 seconds
Started Jun 29 06:48:56 PM PDT 24
Finished Jun 29 06:48:57 PM PDT 24
Peak memory 205384 kb
Host smart-27550593-45c2-4ba3-8351-d2a8f38b2082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585305705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3585305705
Directory /workspace/12.spi_device_alert_test/latest


Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1402847075
Short name T1007
Test name
Test status
Simulation time 40059248 ps
CPU time 2.41 seconds
Started Jun 29 06:48:52 PM PDT 24
Finished Jun 29 06:48:56 PM PDT 24
Peak memory 232676 kb
Host smart-c3b5cea8-b431-491c-bbda-9bd4dfe2f8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402847075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1402847075
Directory /workspace/12.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/12.spi_device_csb_read.1518095293
Short name T312
Test name
Test status
Simulation time 176241994 ps
CPU time 0.77 seconds
Started Jun 29 06:48:54 PM PDT 24
Finished Jun 29 06:48:55 PM PDT 24
Peak memory 205860 kb
Host smart-3ee2c74a-1488-4fe5-b3b1-5a7db5bd0903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518095293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1518095293
Directory /workspace/12.spi_device_csb_read/latest


Test location /workspace/coverage/default/12.spi_device_flash_all.2817372629
Short name T450
Test name
Test status
Simulation time 2184326655 ps
CPU time 11.44 seconds
Started Jun 29 06:48:51 PM PDT 24
Finished Jun 29 06:49:02 PM PDT 24
Peak memory 232724 kb
Host smart-59579127-4c32-45cf-8c3d-72db4f0b0894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817372629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2817372629
Directory /workspace/12.spi_device_flash_all/latest


Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3651057222
Short name T814
Test name
Test status
Simulation time 83823888192 ps
CPU time 58.85 seconds
Started Jun 29 06:48:55 PM PDT 24
Finished Jun 29 06:49:54 PM PDT 24
Peak memory 249228 kb
Host smart-d677db46-741d-4650-8a58-18020bff9f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651057222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3651057222
Directory /workspace/12.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4186126563
Short name T51
Test name
Test status
Simulation time 70600767604 ps
CPU time 179.39 seconds
Started Jun 29 06:48:54 PM PDT 24
Finished Jun 29 06:51:53 PM PDT 24
Peak memory 256112 kb
Host smart-9d4219b6-418a-43ce-b7e3-c19e624dd160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186126563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4186126563
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/12.spi_device_flash_mode.3068944371
Short name T521
Test name
Test status
Simulation time 3806435291 ps
CPU time 20.46 seconds
Started Jun 29 06:48:48 PM PDT 24
Finished Jun 29 06:49:09 PM PDT 24
Peak memory 232744 kb
Host smart-b2736105-fed8-40fe-a74c-4c93e86a3dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068944371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3068944371
Directory /workspace/12.spi_device_flash_mode/latest


Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.709888841
Short name T576
Test name
Test status
Simulation time 44941848257 ps
CPU time 175.2 seconds
Started Jun 29 06:48:50 PM PDT 24
Finished Jun 29 06:51:46 PM PDT 24
Peak memory 252444 kb
Host smart-40217551-cdc1-4341-a120-bd519fabcc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709888841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.709888841
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/12.spi_device_intercept.3625057319
Short name T771
Test name
Test status
Simulation time 331706681 ps
CPU time 3.71 seconds
Started Jun 29 06:48:52 PM PDT 24
Finished Jun 29 06:48:57 PM PDT 24
Peak memory 232676 kb
Host smart-e64e2160-20ea-4838-8cff-a70aa8d1537c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625057319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3625057319
Directory /workspace/12.spi_device_intercept/latest


Test location /workspace/coverage/default/12.spi_device_mailbox.3655239803
Short name T1020
Test name
Test status
Simulation time 218669468 ps
CPU time 2.78 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 06:48:50 PM PDT 24
Peak memory 224460 kb
Host smart-5c5e3b05-c8f4-4890-8846-a5ed6d6cbb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655239803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3655239803
Directory /workspace/12.spi_device_mailbox/latest


Test location /workspace/coverage/default/12.spi_device_mem_parity.4182585333
Short name T986
Test name
Test status
Simulation time 15335507 ps
CPU time 1.04 seconds
Started Jun 29 06:48:51 PM PDT 24
Finished Jun 29 06:48:53 PM PDT 24
Peak memory 216776 kb
Host smart-e2153beb-f5c9-498d-a825-835058a43791
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182585333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.4182585333
Directory /workspace/12.spi_device_mem_parity/latest


Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3840473091
Short name T432
Test name
Test status
Simulation time 146630734 ps
CPU time 2.31 seconds
Started Jun 29 06:48:52 PM PDT 24
Finished Jun 29 06:48:55 PM PDT 24
Peak memory 232576 kb
Host smart-99d10bf5-f2e6-4b95-be41-1c3cc92dffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840473091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3840473091
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3202557487
Short name T223
Test name
Test status
Simulation time 3268982772 ps
CPU time 7.83 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 06:48:55 PM PDT 24
Peak memory 224552 kb
Host smart-43ab4ec4-e035-403f-af92-38a4d792bdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202557487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3202557487
Directory /workspace/12.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1285485109
Short name T151
Test name
Test status
Simulation time 1390340250 ps
CPU time 6.7 seconds
Started Jun 29 06:48:51 PM PDT 24
Finished Jun 29 06:48:58 PM PDT 24
Peak memory 221892 kb
Host smart-e5eba8ed-998f-4dbd-a47e-0c4727309306
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1285485109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1285485109
Directory /workspace/12.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/12.spi_device_stress_all.3386223669
Short name T161
Test name
Test status
Simulation time 30034261049 ps
CPU time 246.43 seconds
Started Jun 29 06:48:58 PM PDT 24
Finished Jun 29 06:53:04 PM PDT 24
Peak memory 249264 kb
Host smart-be0e4c52-5c9e-4871-8885-9e71d46a91ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386223669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3386223669
Directory /workspace/12.spi_device_stress_all/latest


Test location /workspace/coverage/default/12.spi_device_tpm_all.3657361475
Short name T573
Test name
Test status
Simulation time 12247840 ps
CPU time 0.73 seconds
Started Jun 29 06:48:52 PM PDT 24
Finished Jun 29 06:48:53 PM PDT 24
Peak memory 205692 kb
Host smart-6598755e-a45f-4bc5-8556-19e6e4f367ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657361475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3657361475
Directory /workspace/12.spi_device_tpm_all/latest


Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3726775225
Short name T803
Test name
Test status
Simulation time 694759320 ps
CPU time 2.17 seconds
Started Jun 29 06:48:52 PM PDT 24
Finished Jun 29 06:48:55 PM PDT 24
Peak memory 216088 kb
Host smart-15e34f37-bbb6-4073-bcc3-ef7ec283e719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726775225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3726775225
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/12.spi_device_tpm_rw.1296422321
Short name T325
Test name
Test status
Simulation time 24989913 ps
CPU time 0.93 seconds
Started Jun 29 06:48:50 PM PDT 24
Finished Jun 29 06:48:51 PM PDT 24
Peak memory 207252 kb
Host smart-8e2b3440-f6fe-46e4-be4f-aef2f3014a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296422321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1296422321
Directory /workspace/12.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2287081984
Short name T950
Test name
Test status
Simulation time 38877446 ps
CPU time 0.74 seconds
Started Jun 29 06:48:55 PM PDT 24
Finished Jun 29 06:48:57 PM PDT 24
Peak memory 205868 kb
Host smart-9ce578f0-f8ce-4caf-a915-e5e9da935c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287081984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2287081984
Directory /workspace/12.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/12.spi_device_upload.2528492666
Short name T57
Test name
Test status
Simulation time 2776069474 ps
CPU time 10.3 seconds
Started Jun 29 06:48:48 PM PDT 24
Finished Jun 29 06:48:59 PM PDT 24
Peak memory 224624 kb
Host smart-9f9eb604-1747-4a5c-9d27-6f72cd77e9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528492666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2528492666
Directory /workspace/12.spi_device_upload/latest


Test location /workspace/coverage/default/13.spi_device_alert_test.385153927
Short name T743
Test name
Test status
Simulation time 12590521 ps
CPU time 0.76 seconds
Started Jun 29 06:49:02 PM PDT 24
Finished Jun 29 06:49:03 PM PDT 24
Peak memory 204844 kb
Host smart-994fa183-7f14-4120-9f55-f0535f57b62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385153927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.385153927
Directory /workspace/13.spi_device_alert_test/latest


Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1798374043
Short name T980
Test name
Test status
Simulation time 765464798 ps
CPU time 3.55 seconds
Started Jun 29 06:48:57 PM PDT 24
Finished Jun 29 06:49:01 PM PDT 24
Peak memory 232712 kb
Host smart-12fec489-e122-484e-9488-a89a9c75221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798374043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1798374043
Directory /workspace/13.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/13.spi_device_csb_read.2316494309
Short name T869
Test name
Test status
Simulation time 17519811 ps
CPU time 0.76 seconds
Started Jun 29 06:48:55 PM PDT 24
Finished Jun 29 06:48:56 PM PDT 24
Peak memory 205476 kb
Host smart-b96a74ed-529d-4a23-9a88-d10babe0bd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316494309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2316494309
Directory /workspace/13.spi_device_csb_read/latest


Test location /workspace/coverage/default/13.spi_device_flash_all.2657974051
Short name T200
Test name
Test status
Simulation time 3520915266 ps
CPU time 82.3 seconds
Started Jun 29 06:48:56 PM PDT 24
Finished Jun 29 06:50:19 PM PDT 24
Peak memory 256344 kb
Host smart-2af4dce2-6dad-4552-940c-94e25ea05909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657974051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2657974051
Directory /workspace/13.spi_device_flash_all/latest


Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2051933475
Short name T138
Test name
Test status
Simulation time 7876946797 ps
CPU time 116.97 seconds
Started Jun 29 06:48:58 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 253692 kb
Host smart-5ab58d80-527e-434d-b92a-3491675ce033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051933475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2051933475
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/13.spi_device_flash_mode.1612351026
Short name T1027
Test name
Test status
Simulation time 4306850966 ps
CPU time 9.09 seconds
Started Jun 29 06:48:56 PM PDT 24
Finished Jun 29 06:49:05 PM PDT 24
Peak memory 233008 kb
Host smart-724eae8e-e6fd-420a-92bc-5c33ab66aac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612351026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1612351026
Directory /workspace/13.spi_device_flash_mode/latest


Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3562811121
Short name T275
Test name
Test status
Simulation time 52556565570 ps
CPU time 83.03 seconds
Started Jun 29 06:48:55 PM PDT 24
Finished Jun 29 06:50:19 PM PDT 24
Peak memory 251244 kb
Host smart-3e4606a6-7bbd-48e7-9dc4-860b37016e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562811121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3562811121
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/13.spi_device_intercept.4060604736
Short name T439
Test name
Test status
Simulation time 3964353079 ps
CPU time 29.72 seconds
Started Jun 29 06:49:00 PM PDT 24
Finished Jun 29 06:49:30 PM PDT 24
Peak memory 233756 kb
Host smart-1bd93b42-76a9-4c71-b024-eec5fae94b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060604736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4060604736
Directory /workspace/13.spi_device_intercept/latest


Test location /workspace/coverage/default/13.spi_device_mailbox.3757659955
Short name T592
Test name
Test status
Simulation time 1335942572 ps
CPU time 16.24 seconds
Started Jun 29 06:48:55 PM PDT 24
Finished Jun 29 06:49:12 PM PDT 24
Peak memory 232640 kb
Host smart-304e1041-1d8b-4f90-a636-a926796b1239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757659955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3757659955
Directory /workspace/13.spi_device_mailbox/latest


Test location /workspace/coverage/default/13.spi_device_mem_parity.206244841
Short name T618
Test name
Test status
Simulation time 117205645 ps
CPU time 1.09 seconds
Started Jun 29 06:48:58 PM PDT 24
Finished Jun 29 06:48:59 PM PDT 24
Peak memory 218012 kb
Host smart-e2ce49fd-eaa5-468f-a440-1465ea07f526
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206244841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.206244841
Directory /workspace/13.spi_device_mem_parity/latest


Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2339261256
Short name T2
Test name
Test status
Simulation time 34603977 ps
CPU time 2.39 seconds
Started Jun 29 06:48:56 PM PDT 24
Finished Jun 29 06:48:59 PM PDT 24
Peak memory 232348 kb
Host smart-a4aef0c8-23c5-4f8c-a933-deec5362eaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339261256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2339261256
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4265724755
Short name T503
Test name
Test status
Simulation time 8031315606 ps
CPU time 11.5 seconds
Started Jun 29 06:48:56 PM PDT 24
Finished Jun 29 06:49:08 PM PDT 24
Peak memory 232752 kb
Host smart-f31c969f-a821-4f17-bc87-21f120558f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265724755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4265724755
Directory /workspace/13.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1665060200
Short name T403
Test name
Test status
Simulation time 563761223 ps
CPU time 5.94 seconds
Started Jun 29 06:48:54 PM PDT 24
Finished Jun 29 06:49:01 PM PDT 24
Peak memory 218764 kb
Host smart-903bd652-27fc-4754-95d4-24c197cd2c08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1665060200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1665060200
Directory /workspace/13.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/13.spi_device_stress_all.3542092794
Short name T30
Test name
Test status
Simulation time 120228767632 ps
CPU time 434.51 seconds
Started Jun 29 06:49:05 PM PDT 24
Finished Jun 29 06:56:20 PM PDT 24
Peak memory 287288 kb
Host smart-fe078b99-c152-4358-98bb-d3af4fe9e047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542092794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3542092794
Directory /workspace/13.spi_device_stress_all/latest


Test location /workspace/coverage/default/13.spi_device_tpm_all.2884082138
Short name T1022
Test name
Test status
Simulation time 497985890 ps
CPU time 6.22 seconds
Started Jun 29 06:48:55 PM PDT 24
Finished Jun 29 06:49:02 PM PDT 24
Peak memory 219500 kb
Host smart-8247c088-1dea-451a-90e3-955189fa3403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884082138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2884082138
Directory /workspace/13.spi_device_tpm_all/latest


Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3300779916
Short name T748
Test name
Test status
Simulation time 7888269914 ps
CPU time 6.87 seconds
Started Jun 29 06:48:54 PM PDT 24
Finished Jun 29 06:49:02 PM PDT 24
Peak memory 216316 kb
Host smart-619bdb38-8359-4773-a2a3-b030096cc148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300779916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3300779916
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/13.spi_device_tpm_rw.2459467216
Short name T485
Test name
Test status
Simulation time 607849588 ps
CPU time 2.48 seconds
Started Jun 29 06:48:54 PM PDT 24
Finished Jun 29 06:48:57 PM PDT 24
Peak memory 216184 kb
Host smart-7818f480-6bef-462f-ae94-7797d65bad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459467216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2459467216
Directory /workspace/13.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2811805885
Short name T846
Test name
Test status
Simulation time 358407773 ps
CPU time 0.94 seconds
Started Jun 29 06:48:55 PM PDT 24
Finished Jun 29 06:48:56 PM PDT 24
Peak memory 206360 kb
Host smart-9e3b6df9-4ff1-4845-8363-deb7959caf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811805885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2811805885
Directory /workspace/13.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/13.spi_device_upload.91651372
Short name T660
Test name
Test status
Simulation time 3931396966 ps
CPU time 6.58 seconds
Started Jun 29 06:48:58 PM PDT 24
Finished Jun 29 06:49:05 PM PDT 24
Peak memory 218116 kb
Host smart-b4af0e6a-85d9-4bda-bd6e-15081e0f4056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91651372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.91651372
Directory /workspace/13.spi_device_upload/latest


Test location /workspace/coverage/default/14.spi_device_alert_test.3377352636
Short name T972
Test name
Test status
Simulation time 11609621 ps
CPU time 0.77 seconds
Started Jun 29 06:49:06 PM PDT 24
Finished Jun 29 06:49:08 PM PDT 24
Peak memory 205740 kb
Host smart-db937f01-cb47-48e6-90d1-1473916e3c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377352636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3377352636
Directory /workspace/14.spi_device_alert_test/latest


Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1461263336
Short name T968
Test name
Test status
Simulation time 120892083 ps
CPU time 3.63 seconds
Started Jun 29 06:49:05 PM PDT 24
Finished Jun 29 06:49:09 PM PDT 24
Peak memory 232600 kb
Host smart-2f10567e-4aa1-4aa8-9633-8896e964fcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461263336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1461263336
Directory /workspace/14.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/14.spi_device_csb_read.2737361155
Short name T815
Test name
Test status
Simulation time 30912426 ps
CPU time 0.8 seconds
Started Jun 29 06:49:02 PM PDT 24
Finished Jun 29 06:49:03 PM PDT 24
Peak memory 206552 kb
Host smart-ccd00060-d0e5-46cb-a804-007e5c9e763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737361155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2737361155
Directory /workspace/14.spi_device_csb_read/latest


Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3898951611
Short name T922
Test name
Test status
Simulation time 19230704025 ps
CPU time 75.23 seconds
Started Jun 29 06:49:07 PM PDT 24
Finished Jun 29 06:50:22 PM PDT 24
Peak memory 234196 kb
Host smart-c45730b1-88d0-49e2-b163-6deb40844a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898951611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3898951611
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3255910597
Short name T764
Test name
Test status
Simulation time 86449574587 ps
CPU time 301.5 seconds
Started Jun 29 06:49:03 PM PDT 24
Finished Jun 29 06:54:05 PM PDT 24
Peak memory 265272 kb
Host smart-e57fb8e8-f462-4044-9962-1f326be3f358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255910597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3255910597
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/14.spi_device_intercept.2221671098
Short name T487
Test name
Test status
Simulation time 1748755756 ps
CPU time 7.9 seconds
Started Jun 29 06:49:06 PM PDT 24
Finished Jun 29 06:49:14 PM PDT 24
Peak memory 232644 kb
Host smart-3a729666-888b-460d-9c5d-cca97763c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221671098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2221671098
Directory /workspace/14.spi_device_intercept/latest


Test location /workspace/coverage/default/14.spi_device_mailbox.3778091059
Short name T251
Test name
Test status
Simulation time 444699256 ps
CPU time 5.17 seconds
Started Jun 29 06:49:03 PM PDT 24
Finished Jun 29 06:49:08 PM PDT 24
Peak memory 232672 kb
Host smart-ca4031b7-f64d-40e5-97cc-9ef9711f3dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778091059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3778091059
Directory /workspace/14.spi_device_mailbox/latest


Test location /workspace/coverage/default/14.spi_device_mem_parity.2467608801
Short name T742
Test name
Test status
Simulation time 29379732 ps
CPU time 1.07 seconds
Started Jun 29 06:49:01 PM PDT 24
Finished Jun 29 06:49:02 PM PDT 24
Peak memory 216784 kb
Host smart-d8d2b7e8-9283-4094-9484-418535dfa3f8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467608801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2467608801
Directory /workspace/14.spi_device_mem_parity/latest


Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.632418303
Short name T822
Test name
Test status
Simulation time 2530527335 ps
CPU time 4.88 seconds
Started Jun 29 06:49:02 PM PDT 24
Finished Jun 29 06:49:07 PM PDT 24
Peak memory 232756 kb
Host smart-6b772139-de78-41eb-8f0b-52ee2ca32b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632418303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.632418303
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2723449725
Short name T583
Test name
Test status
Simulation time 605421313 ps
CPU time 6.79 seconds
Started Jun 29 06:49:02 PM PDT 24
Finished Jun 29 06:49:09 PM PDT 24
Peak memory 232644 kb
Host smart-af3b552d-d496-463e-b44a-c602133409a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723449725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2723449725
Directory /workspace/14.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3958812284
Short name T954
Test name
Test status
Simulation time 1326785507 ps
CPU time 10.49 seconds
Started Jun 29 06:49:05 PM PDT 24
Finished Jun 29 06:49:16 PM PDT 24
Peak memory 221364 kb
Host smart-b4291f79-cb08-4108-891a-6ea827322a36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3958812284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3958812284
Directory /workspace/14.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/14.spi_device_stress_all.1392375014
Short name T648
Test name
Test status
Simulation time 23060246600 ps
CPU time 227.83 seconds
Started Jun 29 06:49:03 PM PDT 24
Finished Jun 29 06:52:51 PM PDT 24
Peak memory 251992 kb
Host smart-1e480667-f7e2-419e-8755-1323df2d1eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392375014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1392375014
Directory /workspace/14.spi_device_stress_all/latest


Test location /workspace/coverage/default/14.spi_device_tpm_all.1731404944
Short name T635
Test name
Test status
Simulation time 3118038224 ps
CPU time 10.17 seconds
Started Jun 29 06:49:08 PM PDT 24
Finished Jun 29 06:49:18 PM PDT 24
Peak memory 216316 kb
Host smart-ba17671c-80c5-430b-b1bf-3289e4260067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731404944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1731404944
Directory /workspace/14.spi_device_tpm_all/latest


Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2424005036
Short name T565
Test name
Test status
Simulation time 974741506 ps
CPU time 3.24 seconds
Started Jun 29 06:49:03 PM PDT 24
Finished Jun 29 06:49:07 PM PDT 24
Peak memory 216184 kb
Host smart-a30a1039-9bbf-416d-b37a-428c280a5f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424005036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2424005036
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/14.spi_device_tpm_rw.3898772464
Short name T354
Test name
Test status
Simulation time 111029942 ps
CPU time 3.04 seconds
Started Jun 29 06:49:03 PM PDT 24
Finished Jun 29 06:49:06 PM PDT 24
Peak memory 216116 kb
Host smart-04699a17-d0e1-4b17-a052-0774aba3221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898772464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3898772464
Directory /workspace/14.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1313898234
Short name T486
Test name
Test status
Simulation time 33420336 ps
CPU time 0.88 seconds
Started Jun 29 06:49:03 PM PDT 24
Finished Jun 29 06:49:05 PM PDT 24
Peak memory 205884 kb
Host smart-935d1f5e-8850-4706-8d12-2d58b48bfac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313898234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1313898234
Directory /workspace/14.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/14.spi_device_upload.3746843551
Short name T541
Test name
Test status
Simulation time 226268879 ps
CPU time 2.31 seconds
Started Jun 29 06:49:06 PM PDT 24
Finished Jun 29 06:49:09 PM PDT 24
Peak memory 224380 kb
Host smart-3b7622fb-4a5f-4db3-99be-45abf8a3cfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746843551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3746843551
Directory /workspace/14.spi_device_upload/latest


Test location /workspace/coverage/default/15.spi_device_alert_test.553078506
Short name T840
Test name
Test status
Simulation time 32019623 ps
CPU time 0.69 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:06 PM PDT 24
Peak memory 205380 kb
Host smart-bb81cc75-c40f-40c9-b4ea-dac084328a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553078506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.553078506
Directory /workspace/15.spi_device_alert_test/latest


Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1415460357
Short name T235
Test name
Test status
Simulation time 14139919969 ps
CPU time 8.51 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:14 PM PDT 24
Peak memory 224564 kb
Host smart-fa1fd5b1-05ed-4a8e-86bf-acf93dced6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415460357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1415460357
Directory /workspace/15.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/15.spi_device_csb_read.1148750765
Short name T977
Test name
Test status
Simulation time 15118869 ps
CPU time 0.76 seconds
Started Jun 29 06:49:08 PM PDT 24
Finished Jun 29 06:49:09 PM PDT 24
Peak memory 205864 kb
Host smart-dac31ac1-32f6-4c14-9243-c67e5522f782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148750765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1148750765
Directory /workspace/15.spi_device_csb_read/latest


Test location /workspace/coverage/default/15.spi_device_flash_all.3232929805
Short name T921
Test name
Test status
Simulation time 62167526172 ps
CPU time 206.16 seconds
Started Jun 29 06:49:07 PM PDT 24
Finished Jun 29 06:52:34 PM PDT 24
Peak memory 256516 kb
Host smart-8bd3a437-8754-41b2-813f-5135a79842b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232929805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3232929805
Directory /workspace/15.spi_device_flash_all/latest


Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2152462468
Short name T555
Test name
Test status
Simulation time 16358029336 ps
CPU time 61.65 seconds
Started Jun 29 06:49:08 PM PDT 24
Finished Jun 29 06:50:10 PM PDT 24
Peak memory 250296 kb
Host smart-997a20e1-9896-4b9e-897b-0320d36f953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152462468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2152462468
Directory /workspace/15.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2245667254
Short name T216
Test name
Test status
Simulation time 30183838126 ps
CPU time 81.12 seconds
Started Jun 29 06:49:07 PM PDT 24
Finished Jun 29 06:50:28 PM PDT 24
Peak memory 250280 kb
Host smart-3a209365-4185-480f-a25b-7ce5793a0199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245667254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2245667254
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/15.spi_device_flash_mode.562812040
Short name T1024
Test name
Test status
Simulation time 9338073891 ps
CPU time 10.8 seconds
Started Jun 29 06:49:06 PM PDT 24
Finished Jun 29 06:49:17 PM PDT 24
Peak memory 224596 kb
Host smart-198415b9-14f4-460c-8812-94bfe392fcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562812040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.562812040
Directory /workspace/15.spi_device_flash_mode/latest


Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.161340421
Short name T366
Test name
Test status
Simulation time 7765371627 ps
CPU time 54.93 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:59 PM PDT 24
Peak memory 238424 kb
Host smart-c1dda015-9ebb-4ad3-b635-f4e8218927a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161340421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.161340421
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/15.spi_device_intercept.3823082271
Short name T854
Test name
Test status
Simulation time 1604544167 ps
CPU time 6.96 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:11 PM PDT 24
Peak memory 224424 kb
Host smart-f0311845-5211-4c64-b1d8-700a5385a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823082271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3823082271
Directory /workspace/15.spi_device_intercept/latest


Test location /workspace/coverage/default/15.spi_device_mailbox.2489620941
Short name T394
Test name
Test status
Simulation time 3764803115 ps
CPU time 30.86 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:35 PM PDT 24
Peak memory 232796 kb
Host smart-399ddd8c-c285-46f9-a25b-583465b45b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489620941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2489620941
Directory /workspace/15.spi_device_mailbox/latest


Test location /workspace/coverage/default/15.spi_device_mem_parity.3754311229
Short name T698
Test name
Test status
Simulation time 100150976 ps
CPU time 1.12 seconds
Started Jun 29 06:49:02 PM PDT 24
Finished Jun 29 06:49:04 PM PDT 24
Peak memory 218088 kb
Host smart-82c63ed7-c81b-404d-a7ec-b093a966be6c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754311229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3754311229
Directory /workspace/15.spi_device_mem_parity/latest


Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2928626799
Short name T682
Test name
Test status
Simulation time 2337310256 ps
CPU time 5.95 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:10 PM PDT 24
Peak memory 224616 kb
Host smart-978c4113-988a-43af-a270-381a17ba6e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928626799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2928626799
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2679377928
Short name T3
Test name
Test status
Simulation time 49752859996 ps
CPU time 37.64 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:42 PM PDT 24
Peak memory 248748 kb
Host smart-054696b5-46cd-42ef-a3c6-e87c8f130277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679377928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2679377928
Directory /workspace/15.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3902523838
Short name T761
Test name
Test status
Simulation time 8273794089 ps
CPU time 16.41 seconds
Started Jun 29 06:49:05 PM PDT 24
Finished Jun 29 06:49:22 PM PDT 24
Peak memory 220372 kb
Host smart-6f205eee-8f3c-41f6-ad73-9eaf731ac0ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3902523838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3902523838
Directory /workspace/15.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/15.spi_device_stress_all.1080056748
Short name T56
Test name
Test status
Simulation time 48187088725 ps
CPU time 379.71 seconds
Started Jun 29 06:49:05 PM PDT 24
Finished Jun 29 06:55:25 PM PDT 24
Peak memory 267480 kb
Host smart-9a8b26a9-7de2-4784-9c75-89371fae65ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080056748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1080056748
Directory /workspace/15.spi_device_stress_all/latest


Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.208983864
Short name T372
Test name
Test status
Simulation time 1502810270 ps
CPU time 5.12 seconds
Started Jun 29 06:49:05 PM PDT 24
Finished Jun 29 06:49:11 PM PDT 24
Peak memory 216168 kb
Host smart-be13a3d7-e656-40ad-9420-9cad77b107e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208983864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.208983864
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/15.spi_device_tpm_rw.2740252463
Short name T864
Test name
Test status
Simulation time 31075595 ps
CPU time 1.04 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:05 PM PDT 24
Peak memory 207240 kb
Host smart-f3000b74-f947-4af0-a46e-ab7418c6002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740252463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2740252463
Directory /workspace/15.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3025376542
Short name T392
Test name
Test status
Simulation time 44534185 ps
CPU time 0.71 seconds
Started Jun 29 06:49:05 PM PDT 24
Finished Jun 29 06:49:06 PM PDT 24
Peak memory 205888 kb
Host smart-7577fbbd-cfa6-473a-a364-639683e97dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025376542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3025376542
Directory /workspace/15.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/15.spi_device_upload.497841745
Short name T13
Test name
Test status
Simulation time 19934366745 ps
CPU time 16.43 seconds
Started Jun 29 06:49:08 PM PDT 24
Finished Jun 29 06:49:24 PM PDT 24
Peak memory 224628 kb
Host smart-8427d120-d64b-4049-a7dc-e7bfae7ccdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497841745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.497841745
Directory /workspace/15.spi_device_upload/latest


Test location /workspace/coverage/default/16.spi_device_alert_test.1576397252
Short name T402
Test name
Test status
Simulation time 29390248 ps
CPU time 0.7 seconds
Started Jun 29 06:49:09 PM PDT 24
Finished Jun 29 06:49:10 PM PDT 24
Peak memory 205392 kb
Host smart-cd26e150-4353-441c-9188-54d5c7428d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576397252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1576397252
Directory /workspace/16.spi_device_alert_test/latest


Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4006648747
Short name T508
Test name
Test status
Simulation time 946923996 ps
CPU time 2.77 seconds
Started Jun 29 06:49:08 PM PDT 24
Finished Jun 29 06:49:11 PM PDT 24
Peak memory 224356 kb
Host smart-3381d76c-f148-4b71-b31f-f233311031ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006648747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4006648747
Directory /workspace/16.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/16.spi_device_csb_read.350461982
Short name T929
Test name
Test status
Simulation time 32665995 ps
CPU time 0.78 seconds
Started Jun 29 06:49:05 PM PDT 24
Finished Jun 29 06:49:06 PM PDT 24
Peak memory 206872 kb
Host smart-928b2e73-e13e-402c-965d-61bee4dae671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350461982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.350461982
Directory /workspace/16.spi_device_csb_read/latest


Test location /workspace/coverage/default/16.spi_device_flash_all.1133716769
Short name T593
Test name
Test status
Simulation time 1636742551 ps
CPU time 8.04 seconds
Started Jun 29 06:49:16 PM PDT 24
Finished Jun 29 06:49:25 PM PDT 24
Peak memory 237008 kb
Host smart-8c1531c4-d2bd-467d-99bd-aa1cbb9c0495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133716769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1133716769
Directory /workspace/16.spi_device_flash_all/latest


Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4184099138
Short name T39
Test name
Test status
Simulation time 15384014498 ps
CPU time 62.48 seconds
Started Jun 29 06:49:12 PM PDT 24
Finished Jun 29 06:50:14 PM PDT 24
Peak memory 265084 kb
Host smart-52564b24-f009-4843-b582-afc7e33a2e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184099138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4184099138
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/16.spi_device_flash_mode.4080644461
Short name T939
Test name
Test status
Simulation time 527730309 ps
CPU time 3.02 seconds
Started Jun 29 06:49:11 PM PDT 24
Finished Jun 29 06:49:14 PM PDT 24
Peak memory 224492 kb
Host smart-09a0f135-1308-4dd8-84ae-c3e231f1ce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080644461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4080644461
Directory /workspace/16.spi_device_flash_mode/latest


Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2560832970
Short name T692
Test name
Test status
Simulation time 19873887879 ps
CPU time 148.44 seconds
Started Jun 29 06:49:16 PM PDT 24
Finished Jun 29 06:51:45 PM PDT 24
Peak memory 249284 kb
Host smart-cfeb7426-0dc6-4ffb-97f1-64c4bba7b09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560832970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2560832970
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/16.spi_device_intercept.4186495722
Short name T600
Test name
Test status
Simulation time 636803723 ps
CPU time 5.96 seconds
Started Jun 29 06:49:10 PM PDT 24
Finished Jun 29 06:49:16 PM PDT 24
Peak memory 232668 kb
Host smart-5d2de1c2-bdf0-4cbc-bf2c-8c55d08e7e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186495722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4186495722
Directory /workspace/16.spi_device_intercept/latest


Test location /workspace/coverage/default/16.spi_device_mailbox.971957264
Short name T420
Test name
Test status
Simulation time 74489087 ps
CPU time 2.22 seconds
Started Jun 29 06:49:11 PM PDT 24
Finished Jun 29 06:49:14 PM PDT 24
Peak memory 223004 kb
Host smart-b9891548-8da8-4c00-9c26-88e81fdc0887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971957264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.971957264
Directory /workspace/16.spi_device_mailbox/latest


Test location /workspace/coverage/default/16.spi_device_mem_parity.3703355032
Short name T920
Test name
Test status
Simulation time 25656384 ps
CPU time 1.05 seconds
Started Jun 29 06:49:06 PM PDT 24
Finished Jun 29 06:49:07 PM PDT 24
Peak memory 216780 kb
Host smart-4cb98536-24c9-4d04-9bbc-fc4cf92de8f9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703355032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3703355032
Directory /workspace/16.spi_device_mem_parity/latest


Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.588421192
Short name T250
Test name
Test status
Simulation time 11312321410 ps
CPU time 4.84 seconds
Started Jun 29 06:49:10 PM PDT 24
Finished Jun 29 06:49:15 PM PDT 24
Peak memory 224584 kb
Host smart-6babc0b2-f72a-473e-9c3f-d20fe2553d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588421192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.588421192
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1388041434
Short name T775
Test name
Test status
Simulation time 4102260372 ps
CPU time 8.64 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:13 PM PDT 24
Peak memory 232744 kb
Host smart-516e0ede-903b-4f51-8bc1-bea9d25d77ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388041434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1388041434
Directory /workspace/16.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1234950825
Short name T547
Test name
Test status
Simulation time 961075619 ps
CPU time 15.81 seconds
Started Jun 29 06:49:16 PM PDT 24
Finished Jun 29 06:49:32 PM PDT 24
Peak memory 219220 kb
Host smart-29e220d5-265d-4285-8a8a-1baa9eaf6ac5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1234950825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1234950825
Directory /workspace/16.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/16.spi_device_stress_all.99403573
Short name T572
Test name
Test status
Simulation time 8878082647 ps
CPU time 54.73 seconds
Started Jun 29 06:49:06 PM PDT 24
Finished Jun 29 06:50:01 PM PDT 24
Peak memory 256788 kb
Host smart-3617042d-e427-46cc-8ee7-f5b4bd81f18d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99403573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress
_all.99403573
Directory /workspace/16.spi_device_stress_all/latest


Test location /workspace/coverage/default/16.spi_device_tpm_all.732678900
Short name T842
Test name
Test status
Simulation time 3001510329 ps
CPU time 19.46 seconds
Started Jun 29 06:49:05 PM PDT 24
Finished Jun 29 06:49:25 PM PDT 24
Peak memory 216252 kb
Host smart-823eb903-b0d0-4080-98e0-9773120bad9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732678900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.732678900
Directory /workspace/16.spi_device_tpm_all/latest


Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2695688434
Short name T843
Test name
Test status
Simulation time 10654995859 ps
CPU time 11.19 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:16 PM PDT 24
Peak memory 216224 kb
Host smart-eccd659b-9866-4e1a-8d3a-cfd7788e4082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695688434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2695688434
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/16.spi_device_tpm_rw.133042359
Short name T624
Test name
Test status
Simulation time 102106875 ps
CPU time 2.51 seconds
Started Jun 29 06:49:04 PM PDT 24
Finished Jun 29 06:49:08 PM PDT 24
Peak memory 216184 kb
Host smart-76e670ba-dc35-409c-abb4-f462925fc5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133042359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.133042359
Directory /workspace/16.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.214682759
Short name T669
Test name
Test status
Simulation time 29139114 ps
CPU time 0.83 seconds
Started Jun 29 06:49:05 PM PDT 24
Finished Jun 29 06:49:07 PM PDT 24
Peak memory 205884 kb
Host smart-bfd73521-170d-43b2-92f1-189de40b5447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214682759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.214682759
Directory /workspace/16.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/16.spi_device_upload.2255691876
Short name T663
Test name
Test status
Simulation time 299681306 ps
CPU time 4.59 seconds
Started Jun 29 06:49:15 PM PDT 24
Finished Jun 29 06:49:20 PM PDT 24
Peak memory 232692 kb
Host smart-c50a5252-2331-46b6-a069-bb95c5267079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255691876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2255691876
Directory /workspace/16.spi_device_upload/latest


Test location /workspace/coverage/default/17.spi_device_alert_test.2217988097
Short name T490
Test name
Test status
Simulation time 20261699 ps
CPU time 0.7 seconds
Started Jun 29 06:49:16 PM PDT 24
Finished Jun 29 06:49:18 PM PDT 24
Peak memory 205420 kb
Host smart-c55bab82-37e7-4be6-a68e-f6f64b26a8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217988097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2217988097
Directory /workspace/17.spi_device_alert_test/latest


Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2374638851
Short name T863
Test name
Test status
Simulation time 2213461430 ps
CPU time 6.4 seconds
Started Jun 29 06:49:16 PM PDT 24
Finished Jun 29 06:49:23 PM PDT 24
Peak memory 224508 kb
Host smart-c67c7e8c-b5ef-465a-bcda-5be7e600cb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374638851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2374638851
Directory /workspace/17.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/17.spi_device_csb_read.3776954660
Short name T884
Test name
Test status
Simulation time 29304748 ps
CPU time 0.77 seconds
Started Jun 29 06:49:10 PM PDT 24
Finished Jun 29 06:49:11 PM PDT 24
Peak memory 206564 kb
Host smart-c2577805-9683-4d78-a5cd-05025cadee91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776954660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3776954660
Directory /workspace/17.spi_device_csb_read/latest


Test location /workspace/coverage/default/17.spi_device_flash_all.766363554
Short name T190
Test name
Test status
Simulation time 33227646786 ps
CPU time 52.2 seconds
Started Jun 29 06:49:10 PM PDT 24
Finished Jun 29 06:50:03 PM PDT 24
Peak memory 249220 kb
Host smart-4c3cafcf-7633-497e-9bb8-c4cff394e8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766363554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.766363554
Directory /workspace/17.spi_device_flash_all/latest


Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1856954551
Short name T544
Test name
Test status
Simulation time 6334816268 ps
CPU time 23.62 seconds
Started Jun 29 06:49:07 PM PDT 24
Finished Jun 29 06:49:31 PM PDT 24
Peak memory 224652 kb
Host smart-d0bd28f5-a918-434f-bdc9-331382e765b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856954551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1856954551
Directory /workspace/17.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2457931882
Short name T938
Test name
Test status
Simulation time 16526614126 ps
CPU time 17.98 seconds
Started Jun 29 06:49:10 PM PDT 24
Finished Jun 29 06:49:29 PM PDT 24
Peak memory 217640 kb
Host smart-c66135ac-88ca-42b5-b2b0-5fff0b2701d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457931882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2457931882
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/17.spi_device_flash_mode.3543147021
Short name T919
Test name
Test status
Simulation time 2105642825 ps
CPU time 4.54 seconds
Started Jun 29 06:49:10 PM PDT 24
Finished Jun 29 06:49:15 PM PDT 24
Peak memory 224480 kb
Host smart-18bfc5f3-50a5-4e55-9ab7-284bb0a8914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543147021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3543147021
Directory /workspace/17.spi_device_flash_mode/latest


Test location /workspace/coverage/default/17.spi_device_intercept.1337639277
Short name T723
Test name
Test status
Simulation time 102786171 ps
CPU time 3.97 seconds
Started Jun 29 06:49:13 PM PDT 24
Finished Jun 29 06:49:18 PM PDT 24
Peak memory 232672 kb
Host smart-bb2fa762-895f-4295-89c4-9301be6e8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337639277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1337639277
Directory /workspace/17.spi_device_intercept/latest


Test location /workspace/coverage/default/17.spi_device_mailbox.448026487
Short name T588
Test name
Test status
Simulation time 2230235932 ps
CPU time 12.56 seconds
Started Jun 29 06:49:16 PM PDT 24
Finished Jun 29 06:49:29 PM PDT 24
Peak memory 232728 kb
Host smart-f7a6e189-5813-4008-bf87-4124d5fef1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448026487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.448026487
Directory /workspace/17.spi_device_mailbox/latest


Test location /workspace/coverage/default/17.spi_device_mem_parity.1296701603
Short name T728
Test name
Test status
Simulation time 124713770 ps
CPU time 1.14 seconds
Started Jun 29 06:49:09 PM PDT 24
Finished Jun 29 06:49:10 PM PDT 24
Peak memory 216784 kb
Host smart-438efff7-ad57-42c6-9800-161974407299
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296701603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1296701603
Directory /workspace/17.spi_device_mem_parity/latest


Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.341027515
Short name T657
Test name
Test status
Simulation time 1040859648 ps
CPU time 3.24 seconds
Started Jun 29 06:49:11 PM PDT 24
Finished Jun 29 06:49:14 PM PDT 24
Peak memory 224424 kb
Host smart-1fa5242e-b29a-4ed2-a9e7-470fd0c94836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341027515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.341027515
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3221155813
Short name T959
Test name
Test status
Simulation time 4208450540 ps
CPU time 4.69 seconds
Started Jun 29 06:49:10 PM PDT 24
Finished Jun 29 06:49:15 PM PDT 24
Peak memory 224532 kb
Host smart-f07f93e6-f3a2-4a32-86fb-ecb7fed80f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221155813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3221155813
Directory /workspace/17.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.795251304
Short name T818
Test name
Test status
Simulation time 137242691 ps
CPU time 4.05 seconds
Started Jun 29 06:49:15 PM PDT 24
Finished Jun 29 06:49:20 PM PDT 24
Peak memory 220032 kb
Host smart-dbee2620-ad0b-4bbd-bb17-aeb32c4b2e86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=795251304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.795251304
Directory /workspace/17.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/17.spi_device_stress_all.2031111335
Short name T824
Test name
Test status
Simulation time 2361351383 ps
CPU time 28.49 seconds
Started Jun 29 06:49:17 PM PDT 24
Finished Jun 29 06:49:46 PM PDT 24
Peak memory 252108 kb
Host smart-e3662719-79fc-4a5c-82d5-3d5ce6ccc947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031111335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2031111335
Directory /workspace/17.spi_device_stress_all/latest


Test location /workspace/coverage/default/17.spi_device_tpm_all.2859373607
Short name T844
Test name
Test status
Simulation time 3911707404 ps
CPU time 17.68 seconds
Started Jun 29 06:49:09 PM PDT 24
Finished Jun 29 06:49:27 PM PDT 24
Peak memory 216316 kb
Host smart-241cc4e6-6a11-4dfb-99fe-74ce6d5da1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859373607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2859373607
Directory /workspace/17.spi_device_tpm_all/latest


Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1188183652
Short name T442
Test name
Test status
Simulation time 1562986884 ps
CPU time 1.62 seconds
Started Jun 29 06:49:08 PM PDT 24
Finished Jun 29 06:49:10 PM PDT 24
Peak memory 207748 kb
Host smart-c4e03ed3-4aba-41a2-8bbe-02b4efa1645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188183652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1188183652
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/17.spi_device_tpm_rw.3171415399
Short name T609
Test name
Test status
Simulation time 536539538 ps
CPU time 11.17 seconds
Started Jun 29 06:49:10 PM PDT 24
Finished Jun 29 06:49:22 PM PDT 24
Peak memory 216212 kb
Host smart-67ddf034-f543-4169-a878-303644effc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171415399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3171415399
Directory /workspace/17.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3889468738
Short name T399
Test name
Test status
Simulation time 40910091 ps
CPU time 0.77 seconds
Started Jun 29 06:49:12 PM PDT 24
Finished Jun 29 06:49:13 PM PDT 24
Peak memory 205836 kb
Host smart-417ffc45-e8f0-4a94-b682-4937fddf36bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889468738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3889468738
Directory /workspace/17.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/17.spi_device_upload.1360523391
Short name T114
Test name
Test status
Simulation time 10506793111 ps
CPU time 8.77 seconds
Started Jun 29 06:49:17 PM PDT 24
Finished Jun 29 06:49:26 PM PDT 24
Peak memory 232740 kb
Host smart-b07baec5-dbe4-45cc-8f1a-07a872777137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360523391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1360523391
Directory /workspace/17.spi_device_upload/latest


Test location /workspace/coverage/default/18.spi_device_alert_test.973698578
Short name T515
Test name
Test status
Simulation time 44241961 ps
CPU time 0.72 seconds
Started Jun 29 06:49:19 PM PDT 24
Finished Jun 29 06:49:20 PM PDT 24
Peak memory 205404 kb
Host smart-48f5c877-5f09-4915-9f1b-a8a9e466fecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973698578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.973698578
Directory /workspace/18.spi_device_alert_test/latest


Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1320791683
Short name T433
Test name
Test status
Simulation time 118864580 ps
CPU time 2.54 seconds
Started Jun 29 06:49:18 PM PDT 24
Finished Jun 29 06:49:21 PM PDT 24
Peak memory 232380 kb
Host smart-6060fbe4-1dc2-4ca2-bdb7-38cb4ad3d0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320791683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1320791683
Directory /workspace/18.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/18.spi_device_csb_read.339099163
Short name T874
Test name
Test status
Simulation time 16797734 ps
CPU time 0.75 seconds
Started Jun 29 06:49:08 PM PDT 24
Finished Jun 29 06:49:09 PM PDT 24
Peak memory 205864 kb
Host smart-1e970565-7624-4c74-8cb3-6666b39a6daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339099163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.339099163
Directory /workspace/18.spi_device_csb_read/latest


Test location /workspace/coverage/default/18.spi_device_flash_all.1307872407
Short name T218
Test name
Test status
Simulation time 7504428713 ps
CPU time 79.49 seconds
Started Jun 29 06:49:20 PM PDT 24
Finished Jun 29 06:50:40 PM PDT 24
Peak memory 251592 kb
Host smart-04c47f2a-480e-484c-b4bd-b15ebcdffbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307872407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1307872407
Directory /workspace/18.spi_device_flash_all/latest


Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4167246242
Short name T268
Test name
Test status
Simulation time 31889059043 ps
CPU time 123.18 seconds
Started Jun 29 06:49:18 PM PDT 24
Finished Jun 29 06:51:22 PM PDT 24
Peak memory 263772 kb
Host smart-fdae23ca-b0f6-45fc-8148-c76ab958450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167246242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4167246242
Directory /workspace/18.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1246946159
Short name T10
Test name
Test status
Simulation time 3372667289 ps
CPU time 19.93 seconds
Started Jun 29 06:49:22 PM PDT 24
Finished Jun 29 06:49:42 PM PDT 24
Peak memory 219520 kb
Host smart-1aa2c057-d75e-406b-8e44-7de526ebeb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246946159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1246946159
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/18.spi_device_flash_mode.205284949
Short name T817
Test name
Test status
Simulation time 226596476 ps
CPU time 3.97 seconds
Started Jun 29 06:49:21 PM PDT 24
Finished Jun 29 06:49:25 PM PDT 24
Peak memory 232712 kb
Host smart-c76fdb8d-ebd7-4ec0-add5-521d81974248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205284949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.205284949
Directory /workspace/18.spi_device_flash_mode/latest


Test location /workspace/coverage/default/18.spi_device_intercept.2724887046
Short name T239
Test name
Test status
Simulation time 6595921038 ps
CPU time 17.62 seconds
Started Jun 29 06:49:19 PM PDT 24
Finished Jun 29 06:49:37 PM PDT 24
Peak memory 224636 kb
Host smart-511ba08d-7729-41db-993c-362d640c9e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724887046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2724887046
Directory /workspace/18.spi_device_intercept/latest


Test location /workspace/coverage/default/18.spi_device_mailbox.411619294
Short name T933
Test name
Test status
Simulation time 304877577 ps
CPU time 2.81 seconds
Started Jun 29 06:49:21 PM PDT 24
Finished Jun 29 06:49:24 PM PDT 24
Peak memory 232628 kb
Host smart-791ac16a-1d54-48f9-a1a1-80ec1b3d02ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411619294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.411619294
Directory /workspace/18.spi_device_mailbox/latest


Test location /workspace/coverage/default/18.spi_device_mem_parity.1739330835
Short name T423
Test name
Test status
Simulation time 28714713 ps
CPU time 1.09 seconds
Started Jun 29 06:49:12 PM PDT 24
Finished Jun 29 06:49:13 PM PDT 24
Peak memory 217960 kb
Host smart-b7268b78-c20f-4e1c-a056-1f7d752c9146
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739330835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1739330835
Directory /workspace/18.spi_device_mem_parity/latest


Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2946626859
Short name T245
Test name
Test status
Simulation time 756734657 ps
CPU time 4.64 seconds
Started Jun 29 06:49:18 PM PDT 24
Finished Jun 29 06:49:23 PM PDT 24
Peak memory 232668 kb
Host smart-5894be98-11e3-4994-ac58-115406fdb6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946626859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2946626859
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.532793008
Short name T89
Test name
Test status
Simulation time 1109899848 ps
CPU time 4.52 seconds
Started Jun 29 06:49:19 PM PDT 24
Finished Jun 29 06:49:24 PM PDT 24
Peak memory 224476 kb
Host smart-2575d661-25c8-4c0a-b445-a3d0877e2413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532793008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.532793008
Directory /workspace/18.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.468980845
Short name T639
Test name
Test status
Simulation time 2395416450 ps
CPU time 8.94 seconds
Started Jun 29 06:49:18 PM PDT 24
Finished Jun 29 06:49:28 PM PDT 24
Peak memory 222836 kb
Host smart-fb20fe6d-a8ca-449b-b26d-d2793befaabb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=468980845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.468980845
Directory /workspace/18.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/18.spi_device_stress_all.1772841939
Short name T705
Test name
Test status
Simulation time 3670635177 ps
CPU time 66.12 seconds
Started Jun 29 06:49:18 PM PDT 24
Finished Jun 29 06:50:24 PM PDT 24
Peak memory 253080 kb
Host smart-45f23bfe-41a6-4335-b277-df9ab5e68f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772841939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1772841939
Directory /workspace/18.spi_device_stress_all/latest


Test location /workspace/coverage/default/18.spi_device_tpm_all.2481762478
Short name T568
Test name
Test status
Simulation time 6206817553 ps
CPU time 27.27 seconds
Started Jun 29 06:49:16 PM PDT 24
Finished Jun 29 06:49:44 PM PDT 24
Peak memory 216348 kb
Host smart-43eb50bf-bae4-4ae8-ba33-fd576662ec72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481762478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2481762478
Directory /workspace/18.spi_device_tpm_all/latest


Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4100017432
Short name T408
Test name
Test status
Simulation time 13570554122 ps
CPU time 8.34 seconds
Started Jun 29 06:49:17 PM PDT 24
Finished Jun 29 06:49:25 PM PDT 24
Peak memory 216380 kb
Host smart-eb81ef0d-240a-4a81-9fc6-e10deb1678b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100017432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4100017432
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/18.spi_device_tpm_rw.3687886249
Short name T302
Test name
Test status
Simulation time 55783371 ps
CPU time 1.19 seconds
Started Jun 29 06:49:20 PM PDT 24
Finished Jun 29 06:49:22 PM PDT 24
Peak memory 207976 kb
Host smart-2f55e625-32b6-4149-adb8-3a22276e89bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687886249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3687886249
Directory /workspace/18.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2944309818
Short name T1005
Test name
Test status
Simulation time 33144421 ps
CPU time 0.74 seconds
Started Jun 29 06:49:21 PM PDT 24
Finished Jun 29 06:49:22 PM PDT 24
Peak memory 205888 kb
Host smart-694ab627-7481-4ebe-bfc8-4e027fe8c098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944309818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2944309818
Directory /workspace/18.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/18.spi_device_upload.2638564832
Short name T422
Test name
Test status
Simulation time 1170608140 ps
CPU time 5.86 seconds
Started Jun 29 06:49:20 PM PDT 24
Finished Jun 29 06:49:26 PM PDT 24
Peak memory 224464 kb
Host smart-eef38a6f-6dc3-4ac7-87c7-efd948529d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638564832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2638564832
Directory /workspace/18.spi_device_upload/latest


Test location /workspace/coverage/default/19.spi_device_alert_test.1620871058
Short name T595
Test name
Test status
Simulation time 12829000 ps
CPU time 0.74 seconds
Started Jun 29 06:49:28 PM PDT 24
Finished Jun 29 06:49:30 PM PDT 24
Peak memory 205416 kb
Host smart-0f590b9a-c493-4d6a-9a4c-1aae120b2238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620871058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1620871058
Directory /workspace/19.spi_device_alert_test/latest


Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1137976054
Short name T653
Test name
Test status
Simulation time 81639430 ps
CPU time 2.88 seconds
Started Jun 29 06:49:25 PM PDT 24
Finished Jun 29 06:49:28 PM PDT 24
Peak memory 232688 kb
Host smart-2b5da641-3b96-475e-9486-632ef5d4cd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137976054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1137976054
Directory /workspace/19.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/19.spi_device_csb_read.5952738
Short name T451
Test name
Test status
Simulation time 37700524 ps
CPU time 0.8 seconds
Started Jun 29 06:49:17 PM PDT 24
Finished Jun 29 06:49:19 PM PDT 24
Peak memory 206568 kb
Host smart-1b2eebe1-82af-4a88-8cf7-d240c96feb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5952738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.5952738
Directory /workspace/19.spi_device_csb_read/latest


Test location /workspace/coverage/default/19.spi_device_flash_all.3057115424
Short name T434
Test name
Test status
Simulation time 9651878333 ps
CPU time 56.83 seconds
Started Jun 29 06:49:27 PM PDT 24
Finished Jun 29 06:50:25 PM PDT 24
Peak memory 254420 kb
Host smart-b21911e4-79d5-4e96-8778-9f9d16ed6030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057115424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3057115424
Directory /workspace/19.spi_device_flash_all/latest


Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3062840049
Short name T441
Test name
Test status
Simulation time 7656909861 ps
CPU time 108.37 seconds
Started Jun 29 06:49:30 PM PDT 24
Finished Jun 29 06:51:19 PM PDT 24
Peak memory 257184 kb
Host smart-315d4c1f-8cfa-418b-a8a0-fed211a85b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062840049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3062840049
Directory /workspace/19.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1777232314
Short name T496
Test name
Test status
Simulation time 15221308576 ps
CPU time 25.78 seconds
Started Jun 29 06:49:29 PM PDT 24
Finished Jun 29 06:49:55 PM PDT 24
Peak memory 217464 kb
Host smart-28fdb48e-dff2-4aab-9ae6-ee341303b427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777232314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1777232314
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/19.spi_device_flash_mode.1590114499
Short name T1029
Test name
Test status
Simulation time 551452963 ps
CPU time 4.09 seconds
Started Jun 29 06:49:30 PM PDT 24
Finished Jun 29 06:49:35 PM PDT 24
Peak memory 232608 kb
Host smart-b8d0ff00-39ee-41d8-ae7c-cb8be9f2af0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590114499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1590114499
Directory /workspace/19.spi_device_flash_mode/latest


Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2275631867
Short name T181
Test name
Test status
Simulation time 63504260908 ps
CPU time 118.81 seconds
Started Jun 29 06:49:26 PM PDT 24
Finished Jun 29 06:51:25 PM PDT 24
Peak memory 254060 kb
Host smart-817b9e40-8a84-447c-8ee9-f644f1049a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275631867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2275631867
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/19.spi_device_intercept.3433039797
Short name T740
Test name
Test status
Simulation time 7771538009 ps
CPU time 16.14 seconds
Started Jun 29 06:49:21 PM PDT 24
Finished Jun 29 06:49:37 PM PDT 24
Peak memory 232796 kb
Host smart-de1fb837-a55a-4cef-af46-7ec5b8f741d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433039797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3433039797
Directory /workspace/19.spi_device_intercept/latest


Test location /workspace/coverage/default/19.spi_device_mailbox.4143699094
Short name T785
Test name
Test status
Simulation time 314900147 ps
CPU time 7.36 seconds
Started Jun 29 06:49:25 PM PDT 24
Finished Jun 29 06:49:32 PM PDT 24
Peak memory 235020 kb
Host smart-f9d7e77a-f8b9-44bb-a140-fb0f86760a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143699094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4143699094
Directory /workspace/19.spi_device_mailbox/latest


Test location /workspace/coverage/default/19.spi_device_mem_parity.1981062084
Short name T33
Test name
Test status
Simulation time 15979982 ps
CPU time 0.98 seconds
Started Jun 29 06:49:19 PM PDT 24
Finished Jun 29 06:49:21 PM PDT 24
Peak memory 216776 kb
Host smart-a050dbb5-3d83-4698-8d86-8e36ae9d3337
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981062084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1981062084
Directory /workspace/19.spi_device_mem_parity/latest


Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1119653300
Short name T756
Test name
Test status
Simulation time 247223898 ps
CPU time 4.25 seconds
Started Jun 29 06:49:19 PM PDT 24
Finished Jun 29 06:49:23 PM PDT 24
Peak memory 224408 kb
Host smart-e097fb26-1896-455d-8484-a2a8f07b7051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119653300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1119653300
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3378999171
Short name T444
Test name
Test status
Simulation time 5759600092 ps
CPU time 10.89 seconds
Started Jun 29 06:49:21 PM PDT 24
Finished Jun 29 06:49:32 PM PDT 24
Peak memory 232700 kb
Host smart-29c49192-addb-4f23-8b54-27334b1b4b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378999171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3378999171
Directory /workspace/19.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3249934747
Short name T866
Test name
Test status
Simulation time 2009563377 ps
CPU time 15.84 seconds
Started Jun 29 06:49:24 PM PDT 24
Finished Jun 29 06:49:40 PM PDT 24
Peak memory 222484 kb
Host smart-fd54c939-b0db-4fc3-bad7-675d7627207e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3249934747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3249934747
Directory /workspace/19.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/19.spi_device_stress_all.682256262
Short name T55
Test name
Test status
Simulation time 754708594776 ps
CPU time 1549.04 seconds
Started Jun 29 06:49:25 PM PDT 24
Finished Jun 29 07:15:15 PM PDT 24
Peak memory 300268 kb
Host smart-54900dcf-7f12-4246-abe6-f06d857bf2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682256262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.682256262
Directory /workspace/19.spi_device_stress_all/latest


Test location /workspace/coverage/default/19.spi_device_tpm_all.1975606651
Short name T1017
Test name
Test status
Simulation time 791799294 ps
CPU time 8.24 seconds
Started Jun 29 06:49:18 PM PDT 24
Finished Jun 29 06:49:27 PM PDT 24
Peak memory 216192 kb
Host smart-f133e00f-06fb-48ae-907f-95c59f83a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975606651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1975606651
Directory /workspace/19.spi_device_tpm_all/latest


Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3135392701
Short name T672
Test name
Test status
Simulation time 2364376325 ps
CPU time 9.18 seconds
Started Jun 29 06:49:20 PM PDT 24
Finished Jun 29 06:49:29 PM PDT 24
Peak memory 216344 kb
Host smart-ea0e6079-4553-40ce-bb0b-8f10492108b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135392701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3135392701
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/19.spi_device_tpm_rw.571815115
Short name T437
Test name
Test status
Simulation time 158136590 ps
CPU time 2.14 seconds
Started Jun 29 06:49:19 PM PDT 24
Finished Jun 29 06:49:22 PM PDT 24
Peak memory 216156 kb
Host smart-b639240b-2832-4e3a-a270-8c3b5af80a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571815115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.571815115
Directory /workspace/19.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.914332768
Short name T343
Test name
Test status
Simulation time 81910204 ps
CPU time 0.99 seconds
Started Jun 29 06:49:18 PM PDT 24
Finished Jun 29 06:49:19 PM PDT 24
Peak memory 206908 kb
Host smart-50f6bea1-b463-44db-8def-c2cff1a0f0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914332768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.914332768
Directory /workspace/19.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/19.spi_device_upload.1274759767
Short name T398
Test name
Test status
Simulation time 12634595946 ps
CPU time 20.4 seconds
Started Jun 29 06:49:26 PM PDT 24
Finished Jun 29 06:49:47 PM PDT 24
Peak memory 232748 kb
Host smart-362a3b8b-c2da-4e43-9a24-7eed0eb24afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274759767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1274759767
Directory /workspace/19.spi_device_upload/latest


Test location /workspace/coverage/default/2.spi_device_alert_test.812133813
Short name T631
Test name
Test status
Simulation time 40844650 ps
CPU time 0.73 seconds
Started Jun 29 06:48:16 PM PDT 24
Finished Jun 29 06:48:18 PM PDT 24
Peak memory 205344 kb
Host smart-e358f448-8cb1-4e37-8a5f-425e3218c8c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812133813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.812133813
Directory /workspace/2.spi_device_alert_test/latest


Test location /workspace/coverage/default/2.spi_device_cfg_cmd.256176332
Short name T720
Test name
Test status
Simulation time 4998284597 ps
CPU time 19.31 seconds
Started Jun 29 06:48:15 PM PDT 24
Finished Jun 29 06:48:35 PM PDT 24
Peak memory 232732 kb
Host smart-53a7cb87-53cd-433a-af2c-853593604348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256176332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.256176332
Directory /workspace/2.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/2.spi_device_csb_read.376784599
Short name T738
Test name
Test status
Simulation time 15357407 ps
CPU time 0.76 seconds
Started Jun 29 06:48:14 PM PDT 24
Finished Jun 29 06:48:15 PM PDT 24
Peak memory 205528 kb
Host smart-339f4cbc-ce0c-4ca8-8e05-ec586c620f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376784599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.376784599
Directory /workspace/2.spi_device_csb_read/latest


Test location /workspace/coverage/default/2.spi_device_flash_all.3690438398
Short name T772
Test name
Test status
Simulation time 13954507406 ps
CPU time 59.23 seconds
Started Jun 29 06:48:16 PM PDT 24
Finished Jun 29 06:49:16 PM PDT 24
Peak memory 257368 kb
Host smart-f98b91a3-2dc8-4d7c-8c31-7832fea95123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690438398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3690438398
Directory /workspace/2.spi_device_flash_all/latest


Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4190972102
Short name T53
Test name
Test status
Simulation time 51244896548 ps
CPU time 436.84 seconds
Started Jun 29 06:48:15 PM PDT 24
Finished Jun 29 06:55:33 PM PDT 24
Peak memory 249232 kb
Host smart-db40f404-94b5-4b33-8215-637ce6f8cfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190972102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4190972102
Directory /workspace/2.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/2.spi_device_flash_mode.655173191
Short name T551
Test name
Test status
Simulation time 374967736 ps
CPU time 3.39 seconds
Started Jun 29 06:48:11 PM PDT 24
Finished Jun 29 06:48:15 PM PDT 24
Peak memory 234252 kb
Host smart-8f766cbf-e3aa-4e21-ad45-1854f8f9023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655173191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.655173191
Directory /workspace/2.spi_device_flash_mode/latest


Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.4074179851
Short name T542
Test name
Test status
Simulation time 29053186028 ps
CPU time 195.79 seconds
Started Jun 29 06:48:11 PM PDT 24
Finished Jun 29 06:51:27 PM PDT 24
Peak memory 251144 kb
Host smart-2547dff4-4126-4d5e-bf91-c38a9a1e3b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074179851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.4074179851
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/2.spi_device_intercept.2165800477
Short name T498
Test name
Test status
Simulation time 2593357276 ps
CPU time 13.8 seconds
Started Jun 29 06:48:15 PM PDT 24
Finished Jun 29 06:48:30 PM PDT 24
Peak memory 224508 kb
Host smart-b0393420-10ac-416d-b822-807aba8d9c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165800477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2165800477
Directory /workspace/2.spi_device_intercept/latest


Test location /workspace/coverage/default/2.spi_device_mailbox.776613567
Short name T534
Test name
Test status
Simulation time 2393568376 ps
CPU time 9.83 seconds
Started Jun 29 06:48:13 PM PDT 24
Finished Jun 29 06:48:24 PM PDT 24
Peak memory 224624 kb
Host smart-bc510f37-3e0e-47ce-91e3-7a1551733dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776613567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.776613567
Directory /workspace/2.spi_device_mailbox/latest


Test location /workspace/coverage/default/2.spi_device_mem_parity.80311872
Short name T389
Test name
Test status
Simulation time 16223838 ps
CPU time 1.02 seconds
Started Jun 29 06:48:12 PM PDT 24
Finished Jun 29 06:48:14 PM PDT 24
Peak memory 216788 kb
Host smart-0eb2c69b-c84f-4ab8-91fa-cb5784ca803d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80311872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.80311872
Directory /workspace/2.spi_device_mem_parity/latest


Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.236237127
Short name T626
Test name
Test status
Simulation time 1254842633 ps
CPU time 6.51 seconds
Started Jun 29 06:48:15 PM PDT 24
Finished Jun 29 06:48:22 PM PDT 24
Peak memory 224408 kb
Host smart-235d7278-0c19-4832-be4b-311724ab0b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236237127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
236237127
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3586020047
Short name T907
Test name
Test status
Simulation time 17200921962 ps
CPU time 14.41 seconds
Started Jun 29 06:48:15 PM PDT 24
Finished Jun 29 06:48:30 PM PDT 24
Peak memory 240916 kb
Host smart-47326f36-380e-47dc-b8e3-e69643c52613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586020047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3586020047
Directory /workspace/2.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2460092670
Short name T983
Test name
Test status
Simulation time 909930186 ps
CPU time 10.18 seconds
Started Jun 29 06:48:13 PM PDT 24
Finished Jun 29 06:48:23 PM PDT 24
Peak memory 220340 kb
Host smart-db40209e-8282-4910-b30c-d642dbde04a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2460092670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2460092670
Directory /workspace/2.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/2.spi_device_sec_cm.4190557099
Short name T67
Test name
Test status
Simulation time 98626414 ps
CPU time 1.05 seconds
Started Jun 29 06:48:12 PM PDT 24
Finished Jun 29 06:48:13 PM PDT 24
Peak memory 235820 kb
Host smart-69689b20-7fa2-4060-9f38-03af8c075540
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190557099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4190557099
Directory /workspace/2.spi_device_sec_cm/latest


Test location /workspace/coverage/default/2.spi_device_stress_all.3383112411
Short name T523
Test name
Test status
Simulation time 525278037163 ps
CPU time 889.17 seconds
Started Jun 29 06:48:15 PM PDT 24
Finished Jun 29 07:03:05 PM PDT 24
Peak memory 273724 kb
Host smart-66eca9c8-7111-47fd-9df8-f08606ef6a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383112411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3383112411
Directory /workspace/2.spi_device_stress_all/latest


Test location /workspace/coverage/default/2.spi_device_tpm_all.2396838268
Short name T300
Test name
Test status
Simulation time 4451080197 ps
CPU time 13.94 seconds
Started Jun 29 06:48:15 PM PDT 24
Finished Jun 29 06:48:29 PM PDT 24
Peak memory 216232 kb
Host smart-7baf06b4-f99f-4b34-a40f-15a5eec66730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396838268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2396838268
Directory /workspace/2.spi_device_tpm_all/latest


Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1942176416
Short name T917
Test name
Test status
Simulation time 1117557028 ps
CPU time 1.25 seconds
Started Jun 29 06:48:14 PM PDT 24
Finished Jun 29 06:48:16 PM PDT 24
Peak memory 207856 kb
Host smart-004b46d8-bf80-41a6-a166-b3a85b34c3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942176416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1942176416
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/2.spi_device_tpm_rw.1878838467
Short name T752
Test name
Test status
Simulation time 796990056 ps
CPU time 4.67 seconds
Started Jun 29 06:48:18 PM PDT 24
Finished Jun 29 06:48:23 PM PDT 24
Peak memory 216252 kb
Host smart-6f3443ea-2450-4d85-874d-a603ef576592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878838467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1878838467
Directory /workspace/2.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.34589857
Short name T469
Test name
Test status
Simulation time 420960825 ps
CPU time 0.98 seconds
Started Jun 29 06:48:14 PM PDT 24
Finished Jun 29 06:48:15 PM PDT 24
Peak memory 206288 kb
Host smart-5917c3c4-07d2-4291-a331-479ca1de146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34589857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.34589857
Directory /workspace/2.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/2.spi_device_upload.861023069
Short name T751
Test name
Test status
Simulation time 858695516 ps
CPU time 7.51 seconds
Started Jun 29 06:48:13 PM PDT 24
Finished Jun 29 06:48:20 PM PDT 24
Peak memory 232604 kb
Host smart-ca1130a9-35e4-44df-bcd9-50ab9ce41851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861023069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.861023069
Directory /workspace/2.spi_device_upload/latest


Test location /workspace/coverage/default/20.spi_device_alert_test.1076853395
Short name T497
Test name
Test status
Simulation time 22546212 ps
CPU time 0.72 seconds
Started Jun 29 06:49:28 PM PDT 24
Finished Jun 29 06:49:29 PM PDT 24
Peak memory 205952 kb
Host smart-a4567c71-9949-4f0f-8f41-2ad8cc6f0e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076853395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1076853395
Directory /workspace/20.spi_device_alert_test/latest


Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1466493112
Short name T686
Test name
Test status
Simulation time 2324312799 ps
CPU time 3.55 seconds
Started Jun 29 06:49:23 PM PDT 24
Finished Jun 29 06:49:27 PM PDT 24
Peak memory 232744 kb
Host smart-16b18ed0-0fcd-456e-877a-35a0965a81f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466493112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1466493112
Directory /workspace/20.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/20.spi_device_csb_read.57008407
Short name T335
Test name
Test status
Simulation time 28031652 ps
CPU time 0.8 seconds
Started Jun 29 06:49:29 PM PDT 24
Finished Jun 29 06:49:31 PM PDT 24
Peak memory 206552 kb
Host smart-ab568332-ec8d-421c-b40f-072a862f69b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57008407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.57008407
Directory /workspace/20.spi_device_csb_read/latest


Test location /workspace/coverage/default/20.spi_device_flash_all.2575303370
Short name T462
Test name
Test status
Simulation time 1627975672 ps
CPU time 31.91 seconds
Started Jun 29 06:49:26 PM PDT 24
Finished Jun 29 06:49:58 PM PDT 24
Peak memory 249084 kb
Host smart-c3be6184-95d1-43af-90d2-e206f5117fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575303370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2575303370
Directory /workspace/20.spi_device_flash_all/latest


Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3425472425
Short name T35
Test name
Test status
Simulation time 16690746342 ps
CPU time 212.02 seconds
Started Jun 29 06:49:30 PM PDT 24
Finished Jun 29 06:53:03 PM PDT 24
Peak memory 254524 kb
Host smart-d8a01d8f-a3a4-4973-8eb6-207011b464c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425472425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3425472425
Directory /workspace/20.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2725362953
Short name T796
Test name
Test status
Simulation time 5359586063 ps
CPU time 76.57 seconds
Started Jun 29 06:49:25 PM PDT 24
Finished Jun 29 06:50:42 PM PDT 24
Peak memory 256640 kb
Host smart-69fcc160-7bcd-404d-932b-7a52b30a2856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725362953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2725362953
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/20.spi_device_flash_mode.2490754516
Short name T290
Test name
Test status
Simulation time 3496338311 ps
CPU time 8.73 seconds
Started Jun 29 06:49:27 PM PDT 24
Finished Jun 29 06:49:37 PM PDT 24
Peak memory 224600 kb
Host smart-e7572f01-2cf1-49b5-bfb2-c976ba732e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490754516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2490754516
Directory /workspace/20.spi_device_flash_mode/latest


Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1763278687
Short name T400
Test name
Test status
Simulation time 6097881681 ps
CPU time 22.27 seconds
Started Jun 29 06:49:30 PM PDT 24
Finished Jun 29 06:49:53 PM PDT 24
Peak memory 238444 kb
Host smart-29ab15de-391f-4cc8-9392-5f621e2e2ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763278687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1763278687
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/20.spi_device_intercept.2307685786
Short name T561
Test name
Test status
Simulation time 1258605051 ps
CPU time 13.28 seconds
Started Jun 29 06:49:25 PM PDT 24
Finished Jun 29 06:49:38 PM PDT 24
Peak memory 232596 kb
Host smart-c68abfa6-20d0-4045-9eda-d424e750160e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307685786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2307685786
Directory /workspace/20.spi_device_intercept/latest


Test location /workspace/coverage/default/20.spi_device_mailbox.3207333134
Short name T827
Test name
Test status
Simulation time 3374885043 ps
CPU time 15.53 seconds
Started Jun 29 06:49:30 PM PDT 24
Finished Jun 29 06:49:46 PM PDT 24
Peak memory 232764 kb
Host smart-880267ba-532c-41c8-adeb-748499f484f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207333134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3207333134
Directory /workspace/20.spi_device_mailbox/latest


Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2189918103
Short name T820
Test name
Test status
Simulation time 10592852675 ps
CPU time 16.34 seconds
Started Jun 29 06:49:30 PM PDT 24
Finished Jun 29 06:49:48 PM PDT 24
Peak memory 232720 kb
Host smart-9fc6d2e5-1008-4c0e-8581-46fa2b9461b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189918103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2189918103
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.727319482
Short name T889
Test name
Test status
Simulation time 373012812 ps
CPU time 2.79 seconds
Started Jun 29 06:49:26 PM PDT 24
Finished Jun 29 06:49:29 PM PDT 24
Peak memory 232612 kb
Host smart-0bb25810-0825-4666-8233-f66c87d929cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727319482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.727319482
Directory /workspace/20.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.332127044
Short name T724
Test name
Test status
Simulation time 2126396699 ps
CPU time 14.27 seconds
Started Jun 29 06:49:26 PM PDT 24
Finished Jun 29 06:49:41 PM PDT 24
Peak memory 222036 kb
Host smart-ecad1e27-93d9-497a-88cf-66b7f6470bf1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=332127044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.332127044
Directory /workspace/20.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/20.spi_device_stress_all.3778190744
Short name T670
Test name
Test status
Simulation time 93110068 ps
CPU time 1.02 seconds
Started Jun 29 06:49:27 PM PDT 24
Finished Jun 29 06:49:28 PM PDT 24
Peak memory 207476 kb
Host smart-b3bab70a-95b6-405e-88cc-cabf3f3b3834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778190744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3778190744
Directory /workspace/20.spi_device_stress_all/latest


Test location /workspace/coverage/default/20.spi_device_tpm_all.1375500804
Short name T45
Test name
Test status
Simulation time 5844238231 ps
CPU time 27.73 seconds
Started Jun 29 06:49:27 PM PDT 24
Finished Jun 29 06:49:55 PM PDT 24
Peak memory 216760 kb
Host smart-e2901b9f-cf91-44cc-a626-44c5b5982076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375500804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1375500804
Directory /workspace/20.spi_device_tpm_all/latest


Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1442577697
Short name T525
Test name
Test status
Simulation time 11701619227 ps
CPU time 5.02 seconds
Started Jun 29 06:49:30 PM PDT 24
Finished Jun 29 06:49:36 PM PDT 24
Peak memory 216324 kb
Host smart-e4872dc3-112f-42a1-911c-38070dae2882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442577697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1442577697
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/20.spi_device_tpm_rw.985921961
Short name T861
Test name
Test status
Simulation time 21845219 ps
CPU time 0.82 seconds
Started Jun 29 06:49:24 PM PDT 24
Finished Jun 29 06:49:25 PM PDT 24
Peak memory 206912 kb
Host smart-51e803d2-ca4e-4f7a-9d13-6506d5d742f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985921961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.985921961
Directory /workspace/20.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2732077755
Short name T709
Test name
Test status
Simulation time 38630820 ps
CPU time 0.8 seconds
Started Jun 29 06:49:26 PM PDT 24
Finished Jun 29 06:49:27 PM PDT 24
Peak memory 205840 kb
Host smart-04a9ba5a-6749-458f-b541-bdf0000ff83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732077755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2732077755
Directory /workspace/20.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/20.spi_device_upload.2151305730
Short name T231
Test name
Test status
Simulation time 516354845 ps
CPU time 2.8 seconds
Started Jun 29 06:49:30 PM PDT 24
Finished Jun 29 06:49:34 PM PDT 24
Peak memory 224504 kb
Host smart-a064d2b7-7057-4001-bd4e-dbaf6533be9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151305730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2151305730
Directory /workspace/20.spi_device_upload/latest


Test location /workspace/coverage/default/21.spi_device_alert_test.1638187577
Short name T949
Test name
Test status
Simulation time 11505622 ps
CPU time 0.69 seconds
Started Jun 29 06:49:25 PM PDT 24
Finished Jun 29 06:49:26 PM PDT 24
Peak memory 205412 kb
Host smart-70763493-4938-4528-b6f0-1aa393aeceb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638187577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1638187577
Directory /workspace/21.spi_device_alert_test/latest


Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3452505905
Short name T633
Test name
Test status
Simulation time 557145750 ps
CPU time 4.01 seconds
Started Jun 29 06:49:27 PM PDT 24
Finished Jun 29 06:49:31 PM PDT 24
Peak memory 224428 kb
Host smart-7c323281-0839-4ede-994c-56dffc8a2f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452505905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3452505905
Directory /workspace/21.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/21.spi_device_csb_read.2603864050
Short name T327
Test name
Test status
Simulation time 37767583 ps
CPU time 0.88 seconds
Started Jun 29 06:49:26 PM PDT 24
Finished Jun 29 06:49:28 PM PDT 24
Peak memory 206568 kb
Host smart-4b705f8d-a4d1-405e-8053-46517a28fa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603864050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2603864050
Directory /workspace/21.spi_device_csb_read/latest


Test location /workspace/coverage/default/21.spi_device_flash_all.3038491588
Short name T695
Test name
Test status
Simulation time 907416122 ps
CPU time 18.71 seconds
Started Jun 29 06:49:29 PM PDT 24
Finished Jun 29 06:49:48 PM PDT 24
Peak memory 232680 kb
Host smart-6ac82fcf-e140-477c-90ca-046c747dbba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038491588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3038491588
Directory /workspace/21.spi_device_flash_all/latest


Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2042397512
Short name T812
Test name
Test status
Simulation time 106145057758 ps
CPU time 120.2 seconds
Started Jun 29 06:49:27 PM PDT 24
Finished Jun 29 06:51:28 PM PDT 24
Peak memory 252132 kb
Host smart-8ad31e5e-621b-4792-8248-70cc4526c9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042397512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2042397512
Directory /workspace/21.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1539138414
Short name T911
Test name
Test status
Simulation time 58281347250 ps
CPU time 284.58 seconds
Started Jun 29 06:49:29 PM PDT 24
Finished Jun 29 06:54:14 PM PDT 24
Peak memory 250368 kb
Host smart-d1a3f11c-8e54-49b5-a450-f7b6f40ff3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539138414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1539138414
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/21.spi_device_flash_mode.3178178745
Short name T388
Test name
Test status
Simulation time 354083678 ps
CPU time 7.9 seconds
Started Jun 29 06:49:27 PM PDT 24
Finished Jun 29 06:49:36 PM PDT 24
Peak memory 224472 kb
Host smart-994b9320-406e-45f2-ba09-652f82b2df40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178178745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3178178745
Directory /workspace/21.spi_device_flash_mode/latest


Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1169915672
Short name T92
Test name
Test status
Simulation time 72529839172 ps
CPU time 183.51 seconds
Started Jun 29 06:49:29 PM PDT 24
Finished Jun 29 06:52:34 PM PDT 24
Peak memory 249180 kb
Host smart-e5635a27-5d2b-43e2-b054-ea62682cd68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169915672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1169915672
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/21.spi_device_intercept.696730189
Short name T93
Test name
Test status
Simulation time 356943302 ps
CPU time 4.96 seconds
Started Jun 29 06:49:24 PM PDT 24
Finished Jun 29 06:49:29 PM PDT 24
Peak memory 224444 kb
Host smart-33036f56-fc95-46a7-bc1d-88c1ca258f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696730189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.696730189
Directory /workspace/21.spi_device_intercept/latest


Test location /workspace/coverage/default/21.spi_device_mailbox.4052008726
Short name T613
Test name
Test status
Simulation time 40390739796 ps
CPU time 51.15 seconds
Started Jun 29 06:49:28 PM PDT 24
Finished Jun 29 06:50:20 PM PDT 24
Peak memory 232996 kb
Host smart-96af8092-5736-4f04-bf26-90db6878bc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052008726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4052008726
Directory /workspace/21.spi_device_mailbox/latest


Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2960142757
Short name T1003
Test name
Test status
Simulation time 35839858756 ps
CPU time 20.9 seconds
Started Jun 29 06:49:25 PM PDT 24
Finished Jun 29 06:49:46 PM PDT 24
Peak memory 232724 kb
Host smart-c348246c-8a2e-4da8-9699-deb17887fa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960142757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2960142757
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1698280950
Short name T454
Test name
Test status
Simulation time 479809689 ps
CPU time 3.98 seconds
Started Jun 29 06:49:30 PM PDT 24
Finished Jun 29 06:49:35 PM PDT 24
Peak memory 224452 kb
Host smart-263f3169-8752-4207-8115-e7e41ed31c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698280950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1698280950
Directory /workspace/21.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2419186101
Short name T603
Test name
Test status
Simulation time 150460310 ps
CPU time 3.91 seconds
Started Jun 29 06:49:27 PM PDT 24
Finished Jun 29 06:49:32 PM PDT 24
Peak memory 222436 kb
Host smart-2b3b9887-0d28-4a0a-9a4d-cd263c648e76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2419186101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2419186101
Directory /workspace/21.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/21.spi_device_stress_all.205476985
Short name T158
Test name
Test status
Simulation time 23974906760 ps
CPU time 73.04 seconds
Started Jun 29 06:49:31 PM PDT 24
Finished Jun 29 06:50:45 PM PDT 24
Peak memory 255628 kb
Host smart-36ba2596-6816-47df-9ec2-0cc9b4b04c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205476985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.205476985
Directory /workspace/21.spi_device_stress_all/latest


Test location /workspace/coverage/default/21.spi_device_tpm_all.2496241610
Short name T981
Test name
Test status
Simulation time 3636174139 ps
CPU time 18.66 seconds
Started Jun 29 06:49:25 PM PDT 24
Finished Jun 29 06:49:44 PM PDT 24
Peak memory 216348 kb
Host smart-61446944-feea-4f0f-b159-ed6deba78acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496241610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2496241610
Directory /workspace/21.spi_device_tpm_all/latest


Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2520911732
Short name T479
Test name
Test status
Simulation time 938291560 ps
CPU time 3.82 seconds
Started Jun 29 06:49:25 PM PDT 24
Finished Jun 29 06:49:29 PM PDT 24
Peak memory 216104 kb
Host smart-8042fc01-396f-4d25-8b64-b866bfc72aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520911732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2520911732
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/21.spi_device_tpm_rw.2748708825
Short name T628
Test name
Test status
Simulation time 93029703 ps
CPU time 3.49 seconds
Started Jun 29 06:49:29 PM PDT 24
Finished Jun 29 06:49:33 PM PDT 24
Peak memory 215748 kb
Host smart-b52fc44e-749a-4f3e-8c48-f87bb01856d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748708825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2748708825
Directory /workspace/21.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1965801933
Short name T489
Test name
Test status
Simulation time 1186528086 ps
CPU time 0.98 seconds
Started Jun 29 06:49:29 PM PDT 24
Finished Jun 29 06:49:31 PM PDT 24
Peak memory 206520 kb
Host smart-b7bea70b-a674-412c-a542-24847b0aad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965801933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1965801933
Directory /workspace/21.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/21.spi_device_upload.2299169931
Short name T427
Test name
Test status
Simulation time 1346174331 ps
CPU time 9.29 seconds
Started Jun 29 06:49:28 PM PDT 24
Finished Jun 29 06:49:39 PM PDT 24
Peak memory 232660 kb
Host smart-be61f9e4-5e1d-4e61-9de9-1e5b98b2f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299169931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2299169931
Directory /workspace/21.spi_device_upload/latest


Test location /workspace/coverage/default/22.spi_device_alert_test.717813650
Short name T520
Test name
Test status
Simulation time 69103323 ps
CPU time 0.75 seconds
Started Jun 29 06:49:35 PM PDT 24
Finished Jun 29 06:49:36 PM PDT 24
Peak memory 205440 kb
Host smart-96f0edf1-37a8-4b52-a26e-6d43755328e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717813650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.717813650
Directory /workspace/22.spi_device_alert_test/latest


Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1219289235
Short name T357
Test name
Test status
Simulation time 37686036 ps
CPU time 2.48 seconds
Started Jun 29 06:49:32 PM PDT 24
Finished Jun 29 06:49:36 PM PDT 24
Peak memory 232360 kb
Host smart-f9509584-6d54-4548-9734-d02cdf4ce843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219289235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1219289235
Directory /workspace/22.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/22.spi_device_csb_read.3608852093
Short name T637
Test name
Test status
Simulation time 49467276 ps
CPU time 0.82 seconds
Started Jun 29 06:49:30 PM PDT 24
Finished Jun 29 06:49:32 PM PDT 24
Peak memory 205824 kb
Host smart-8e74f15a-bd92-46b2-83c2-92da0acc30a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608852093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3608852093
Directory /workspace/22.spi_device_csb_read/latest


Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3792060080
Short name T852
Test name
Test status
Simulation time 44760649728 ps
CPU time 220.85 seconds
Started Jun 29 06:49:35 PM PDT 24
Finished Jun 29 06:53:16 PM PDT 24
Peak memory 249276 kb
Host smart-92f0f3cb-c765-4f04-83f9-0a0ad6a6e6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792060080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3792060080
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/22.spi_device_flash_mode.2501248932
Short name T826
Test name
Test status
Simulation time 41866530 ps
CPU time 2.72 seconds
Started Jun 29 06:49:33 PM PDT 24
Finished Jun 29 06:49:36 PM PDT 24
Peak memory 224444 kb
Host smart-220c0bc7-3140-4e38-b560-7f170a378af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501248932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2501248932
Directory /workspace/22.spi_device_flash_mode/latest


Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2507356364
Short name T180
Test name
Test status
Simulation time 1757680606 ps
CPU time 38.04 seconds
Started Jun 29 06:49:32 PM PDT 24
Finished Jun 29 06:50:10 PM PDT 24
Peak memory 253052 kb
Host smart-ee54668f-e3c5-48d5-a157-9e0629b5234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507356364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2507356364
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/22.spi_device_intercept.4099059302
Short name T1019
Test name
Test status
Simulation time 905084273 ps
CPU time 6.91 seconds
Started Jun 29 06:49:39 PM PDT 24
Finished Jun 29 06:49:46 PM PDT 24
Peak memory 232628 kb
Host smart-da82093c-7422-4a8a-9a54-b2e1a800f11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099059302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4099059302
Directory /workspace/22.spi_device_intercept/latest


Test location /workspace/coverage/default/22.spi_device_mailbox.1384534733
Short name T428
Test name
Test status
Simulation time 769317185 ps
CPU time 19.11 seconds
Started Jun 29 06:49:32 PM PDT 24
Finished Jun 29 06:49:52 PM PDT 24
Peak memory 252184 kb
Host smart-23705a19-ef06-4912-8876-5cde37d33551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384534733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1384534733
Directory /workspace/22.spi_device_mailbox/latest


Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1282979337
Short name T449
Test name
Test status
Simulation time 633800428 ps
CPU time 4.85 seconds
Started Jun 29 06:49:37 PM PDT 24
Finished Jun 29 06:49:43 PM PDT 24
Peak memory 234944 kb
Host smart-e613a70a-20f1-4211-b6cb-b192b2f4bea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282979337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1282979337
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2105012381
Short name T623
Test name
Test status
Simulation time 776199846 ps
CPU time 4.52 seconds
Started Jun 29 06:49:33 PM PDT 24
Finished Jun 29 06:49:38 PM PDT 24
Peak memory 232604 kb
Host smart-c75c16f3-c0fa-4fe5-9264-49d57ee445b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105012381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2105012381
Directory /workspace/22.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2992158929
Short name T467
Test name
Test status
Simulation time 75219892 ps
CPU time 3.39 seconds
Started Jun 29 06:49:33 PM PDT 24
Finished Jun 29 06:49:37 PM PDT 24
Peak memory 222364 kb
Host smart-2b8a04aa-a211-41f9-842c-37018e677f48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2992158929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2992158929
Directory /workspace/22.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/22.spi_device_stress_all.1816089338
Short name T649
Test name
Test status
Simulation time 514626264 ps
CPU time 1.06 seconds
Started Jun 29 06:49:39 PM PDT 24
Finished Jun 29 06:49:41 PM PDT 24
Peak memory 206744 kb
Host smart-6d9ec158-500a-4ec5-be75-03547aa6f1b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816089338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1816089338
Directory /workspace/22.spi_device_stress_all/latest


Test location /workspace/coverage/default/22.spi_device_tpm_all.3430741978
Short name T509
Test name
Test status
Simulation time 6059431071 ps
CPU time 15.89 seconds
Started Jun 29 06:49:35 PM PDT 24
Finished Jun 29 06:49:51 PM PDT 24
Peak memory 216292 kb
Host smart-808ce48f-1f46-48fe-9aac-7122b2aa235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430741978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3430741978
Directory /workspace/22.spi_device_tpm_all/latest


Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3702178200
Short name T308
Test name
Test status
Simulation time 3081733962 ps
CPU time 9.8 seconds
Started Jun 29 06:49:28 PM PDT 24
Finished Jun 29 06:49:39 PM PDT 24
Peak memory 216240 kb
Host smart-22615332-255c-41c5-bfb0-67bf3b0a7096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702178200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3702178200
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/22.spi_device_tpm_rw.2581663514
Short name T935
Test name
Test status
Simulation time 511265064 ps
CPU time 2.02 seconds
Started Jun 29 06:49:35 PM PDT 24
Finished Jun 29 06:49:37 PM PDT 24
Peak memory 216216 kb
Host smart-ca7b93ee-5328-4539-8263-474fdc22b652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581663514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2581663514
Directory /workspace/22.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2507867002
Short name T710
Test name
Test status
Simulation time 40505229 ps
CPU time 0.89 seconds
Started Jun 29 06:49:34 PM PDT 24
Finished Jun 29 06:49:36 PM PDT 24
Peak memory 206360 kb
Host smart-4547bc6d-5b19-420e-8bb8-da404706515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507867002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2507867002
Directory /workspace/22.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/22.spi_device_upload.1083550520
Short name T644
Test name
Test status
Simulation time 1182801718 ps
CPU time 5.35 seconds
Started Jun 29 06:49:34 PM PDT 24
Finished Jun 29 06:49:40 PM PDT 24
Peak memory 232664 kb
Host smart-b18d29a1-f5fd-437e-97dd-f99359aad402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083550520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1083550520
Directory /workspace/22.spi_device_upload/latest


Test location /workspace/coverage/default/23.spi_device_alert_test.3930230870
Short name T168
Test name
Test status
Simulation time 12673280 ps
CPU time 0.73 seconds
Started Jun 29 06:49:34 PM PDT 24
Finished Jun 29 06:49:35 PM PDT 24
Peak memory 205444 kb
Host smart-72337815-56bd-4f86-a15c-4afcf8cccc89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930230870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3930230870
Directory /workspace/23.spi_device_alert_test/latest


Test location /workspace/coverage/default/23.spi_device_cfg_cmd.273287919
Short name T924
Test name
Test status
Simulation time 5885147480 ps
CPU time 11.83 seconds
Started Jun 29 06:49:35 PM PDT 24
Finished Jun 29 06:49:48 PM PDT 24
Peak memory 232764 kb
Host smart-edde338b-088d-45d1-9f02-0436b7ed6450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273287919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.273287919
Directory /workspace/23.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/23.spi_device_csb_read.2988583959
Short name T14
Test name
Test status
Simulation time 53644630 ps
CPU time 0.75 seconds
Started Jun 29 06:49:33 PM PDT 24
Finished Jun 29 06:49:34 PM PDT 24
Peak memory 205864 kb
Host smart-d5502b39-bdea-44fc-93d3-e3c694c1d383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988583959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2988583959
Directory /workspace/23.spi_device_csb_read/latest


Test location /workspace/coverage/default/23.spi_device_flash_all.588333478
Short name T211
Test name
Test status
Simulation time 1378017864 ps
CPU time 9.41 seconds
Started Jun 29 06:49:37 PM PDT 24
Finished Jun 29 06:49:47 PM PDT 24
Peak memory 240896 kb
Host smart-b62bd9eb-6182-48be-8e51-0048edcb3b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588333478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.588333478
Directory /workspace/23.spi_device_flash_all/latest


Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1022904727
Short name T880
Test name
Test status
Simulation time 761370765 ps
CPU time 10.19 seconds
Started Jun 29 06:49:33 PM PDT 24
Finished Jun 29 06:49:44 PM PDT 24
Peak memory 221728 kb
Host smart-e8858624-5c15-41e8-85a8-ee4f88810a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022904727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1022904727
Directory /workspace/23.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/23.spi_device_flash_mode.1014775646
Short name T506
Test name
Test status
Simulation time 147077784 ps
CPU time 3.41 seconds
Started Jun 29 06:49:38 PM PDT 24
Finished Jun 29 06:49:42 PM PDT 24
Peak memory 232564 kb
Host smart-e962d5a0-62fa-43be-a5cf-4cf6af71dc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014775646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1014775646
Directory /workspace/23.spi_device_flash_mode/latest


Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3091202994
Short name T892
Test name
Test status
Simulation time 83044743872 ps
CPU time 146.44 seconds
Started Jun 29 06:49:31 PM PDT 24
Finished Jun 29 06:51:58 PM PDT 24
Peak memory 250192 kb
Host smart-642739a7-3730-4879-b497-1177da7cb5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091202994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3091202994
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/23.spi_device_intercept.2255937362
Short name T886
Test name
Test status
Simulation time 10391594825 ps
CPU time 7.26 seconds
Started Jun 29 06:49:37 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 232788 kb
Host smart-802757b6-7427-4cb7-87c8-92f1a89293c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255937362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2255937362
Directory /workspace/23.spi_device_intercept/latest


Test location /workspace/coverage/default/23.spi_device_mailbox.3051871761
Short name T359
Test name
Test status
Simulation time 4410070964 ps
CPU time 15.98 seconds
Started Jun 29 06:49:33 PM PDT 24
Finished Jun 29 06:49:50 PM PDT 24
Peak memory 237480 kb
Host smart-3590e5d5-a50c-452a-b306-29bc61c44bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051871761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3051871761
Directory /workspace/23.spi_device_mailbox/latest


Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3526132650
Short name T248
Test name
Test status
Simulation time 42119152742 ps
CPU time 19.15 seconds
Started Jun 29 06:49:32 PM PDT 24
Finished Jun 29 06:49:52 PM PDT 24
Peak memory 232752 kb
Host smart-8c08f433-fa09-4a43-b2da-8fd24baad1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526132650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3526132650
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2068776459
Short name T132
Test name
Test status
Simulation time 32569986 ps
CPU time 2.45 seconds
Started Jun 29 06:49:37 PM PDT 24
Finished Jun 29 06:49:40 PM PDT 24
Peak memory 232384 kb
Host smart-e33d3c53-6f7d-4080-9bcd-f4384dd1fc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068776459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2068776459
Directory /workspace/23.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2489090242
Short name T993
Test name
Test status
Simulation time 1547918533 ps
CPU time 16.24 seconds
Started Jun 29 06:49:32 PM PDT 24
Finished Jun 29 06:49:49 PM PDT 24
Peak memory 219248 kb
Host smart-4a0e2063-14a0-40bd-afb8-4816880b7489
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2489090242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2489090242
Directory /workspace/23.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/23.spi_device_stress_all.529745111
Short name T165
Test name
Test status
Simulation time 81593069855 ps
CPU time 404.44 seconds
Started Jun 29 06:49:32 PM PDT 24
Finished Jun 29 06:56:17 PM PDT 24
Peak memory 273468 kb
Host smart-21cf1bc2-01e0-4dd9-990d-c73789ba1364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529745111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.529745111
Directory /workspace/23.spi_device_stress_all/latest


Test location /workspace/coverage/default/23.spi_device_tpm_all.1610681307
Short name T459
Test name
Test status
Simulation time 1552493455 ps
CPU time 22.93 seconds
Started Jun 29 06:49:39 PM PDT 24
Finished Jun 29 06:50:02 PM PDT 24
Peak memory 218308 kb
Host smart-7877becf-fe20-4d1e-91e4-9bf5288a14c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610681307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1610681307
Directory /workspace/23.spi_device_tpm_all/latest


Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1239889624
Short name T358
Test name
Test status
Simulation time 495837226 ps
CPU time 2.86 seconds
Started Jun 29 06:49:36 PM PDT 24
Finished Jun 29 06:49:39 PM PDT 24
Peak memory 216160 kb
Host smart-53f0290a-4bc0-441f-a2ff-4217513e4fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239889624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1239889624
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/23.spi_device_tpm_rw.3049697512
Short name T417
Test name
Test status
Simulation time 41835341 ps
CPU time 1.01 seconds
Started Jun 29 06:49:32 PM PDT 24
Finished Jun 29 06:49:34 PM PDT 24
Peak memory 207716 kb
Host smart-c8885952-82d5-44e7-9152-12f64364fad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049697512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3049697512
Directory /workspace/23.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4052333208
Short name T1013
Test name
Test status
Simulation time 233852538 ps
CPU time 0.9 seconds
Started Jun 29 06:49:33 PM PDT 24
Finished Jun 29 06:49:35 PM PDT 24
Peak memory 206864 kb
Host smart-4b20ec8e-2876-4fd9-8cb6-4b9bc4517f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052333208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4052333208
Directory /workspace/23.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/23.spi_device_upload.2079025249
Short name T215
Test name
Test status
Simulation time 294271459 ps
CPU time 4.59 seconds
Started Jun 29 06:49:40 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 224448 kb
Host smart-9f5a0e92-f352-4b87-9977-91292442ca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079025249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2079025249
Directory /workspace/23.spi_device_upload/latest


Test location /workspace/coverage/default/24.spi_device_alert_test.1147304731
Short name T802
Test name
Test status
Simulation time 43031102 ps
CPU time 0.7 seconds
Started Jun 29 06:49:42 PM PDT 24
Finished Jun 29 06:49:44 PM PDT 24
Peak memory 204812 kb
Host smart-2b9eacfa-f488-4f9c-a6d7-20aa301e3e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147304731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1147304731
Directory /workspace/24.spi_device_alert_test/latest


Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3107402890
Short name T502
Test name
Test status
Simulation time 30312111 ps
CPU time 2.06 seconds
Started Jun 29 06:49:43 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 224408 kb
Host smart-38aec0cb-aed8-4452-8071-2b33a217ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107402890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3107402890
Directory /workspace/24.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/24.spi_device_csb_read.800856017
Short name T680
Test name
Test status
Simulation time 15922506 ps
CPU time 0.8 seconds
Started Jun 29 06:49:36 PM PDT 24
Finished Jun 29 06:49:37 PM PDT 24
Peak memory 205532 kb
Host smart-ce18aa4f-8fe4-46bb-a265-0defde936ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800856017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.800856017
Directory /workspace/24.spi_device_csb_read/latest


Test location /workspace/coverage/default/24.spi_device_flash_all.2677525606
Short name T203
Test name
Test status
Simulation time 42717687584 ps
CPU time 83.44 seconds
Started Jun 29 06:49:39 PM PDT 24
Finished Jun 29 06:51:03 PM PDT 24
Peak memory 254636 kb
Host smart-3db635a8-2c22-4efe-b545-d73a49da386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677525606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2677525606
Directory /workspace/24.spi_device_flash_all/latest


Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.295562227
Short name T263
Test name
Test status
Simulation time 126651371063 ps
CPU time 572.43 seconds
Started Jun 29 06:49:40 PM PDT 24
Finished Jun 29 06:59:13 PM PDT 24
Peak memory 254528 kb
Host smart-97f3d5c9-5762-4a15-80c1-05ce4c907847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295562227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.295562227
Directory /workspace/24.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2609764596
Short name T792
Test name
Test status
Simulation time 60981742621 ps
CPU time 131.35 seconds
Started Jun 29 06:49:40 PM PDT 24
Finished Jun 29 06:51:52 PM PDT 24
Peak memory 252116 kb
Host smart-c2a2c493-fe1b-4358-9c1e-84c1e9473099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609764596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2609764596
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/24.spi_device_flash_mode.3535838840
Short name T758
Test name
Test status
Simulation time 404979636 ps
CPU time 2.79 seconds
Started Jun 29 06:49:42 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 224436 kb
Host smart-f6637272-cf77-4916-b2f1-c4a99e107b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535838840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3535838840
Directory /workspace/24.spi_device_flash_mode/latest


Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1149072489
Short name T918
Test name
Test status
Simulation time 44169798755 ps
CPU time 153.18 seconds
Started Jun 29 06:49:41 PM PDT 24
Finished Jun 29 06:52:15 PM PDT 24
Peak memory 249116 kb
Host smart-ed5f01cd-7790-4806-b9f9-49645ac117ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149072489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1149072489
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/24.spi_device_intercept.1296076776
Short name T193
Test name
Test status
Simulation time 1030700981 ps
CPU time 8.26 seconds
Started Jun 29 06:49:41 PM PDT 24
Finished Jun 29 06:49:50 PM PDT 24
Peak memory 232640 kb
Host smart-9b602ff0-f673-44c7-b277-4a24158278f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296076776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1296076776
Directory /workspace/24.spi_device_intercept/latest


Test location /workspace/coverage/default/24.spi_device_mailbox.733177835
Short name T460
Test name
Test status
Simulation time 18597500616 ps
CPU time 37.47 seconds
Started Jun 29 06:49:40 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 232784 kb
Host smart-2df8e956-0571-4b58-8000-d815f818aaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733177835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.733177835
Directory /workspace/24.spi_device_mailbox/latest


Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4050083838
Short name T808
Test name
Test status
Simulation time 10175914992 ps
CPU time 9.19 seconds
Started Jun 29 06:49:39 PM PDT 24
Finished Jun 29 06:49:49 PM PDT 24
Peak memory 224548 kb
Host smart-ee4653ea-612d-4d8f-893d-4f63cda9c989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050083838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4050083838
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.937658286
Short name T558
Test name
Test status
Simulation time 37674432517 ps
CPU time 27.33 seconds
Started Jun 29 06:49:41 PM PDT 24
Finished Jun 29 06:50:09 PM PDT 24
Peak memory 232764 kb
Host smart-35a537f3-a363-463f-9e61-287cc828e92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937658286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.937658286
Directory /workspace/24.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1773653594
Short name T150
Test name
Test status
Simulation time 189989011 ps
CPU time 3.82 seconds
Started Jun 29 06:49:41 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 222612 kb
Host smart-3faf090a-3ad9-4e96-a646-6fbecc6c6cd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1773653594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1773653594
Directory /workspace/24.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/24.spi_device_stress_all.1573189677
Short name T164
Test name
Test status
Simulation time 32683660262 ps
CPU time 422.19 seconds
Started Jun 29 06:49:40 PM PDT 24
Finished Jun 29 06:56:44 PM PDT 24
Peak memory 270572 kb
Host smart-bd7f7308-48c9-44a4-ad0c-0a3d8551d346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573189677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1573189677
Directory /workspace/24.spi_device_stress_all/latest


Test location /workspace/coverage/default/24.spi_device_tpm_all.3411489623
Short name T566
Test name
Test status
Simulation time 1488341955 ps
CPU time 16.01 seconds
Started Jun 29 06:49:40 PM PDT 24
Finished Jun 29 06:49:57 PM PDT 24
Peak memory 216224 kb
Host smart-543a1034-4dd4-4749-b699-c0a77811b5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411489623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3411489623
Directory /workspace/24.spi_device_tpm_all/latest


Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.538164678
Short name T697
Test name
Test status
Simulation time 1216545196 ps
CPU time 4.23 seconds
Started Jun 29 06:49:40 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 216188 kb
Host smart-4092ce7b-4a2e-485f-b7fa-e2bb60b806de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538164678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.538164678
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/24.spi_device_tpm_rw.2587293744
Short name T629
Test name
Test status
Simulation time 105233241 ps
CPU time 1.43 seconds
Started Jun 29 06:49:43 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 216180 kb
Host smart-973080d0-e7a8-45e4-8318-bb3a74ca7902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587293744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2587293744
Directory /workspace/24.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/24.spi_device_upload.3283545805
Short name T651
Test name
Test status
Simulation time 13188947486 ps
CPU time 22.96 seconds
Started Jun 29 06:49:42 PM PDT 24
Finished Jun 29 06:50:05 PM PDT 24
Peak memory 232712 kb
Host smart-8dbc0c07-3c63-4947-bcaf-8a2aba6ae06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283545805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3283545805
Directory /workspace/24.spi_device_upload/latest


Test location /workspace/coverage/default/25.spi_device_alert_test.2730939672
Short name T562
Test name
Test status
Simulation time 41961976 ps
CPU time 0.72 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:49:51 PM PDT 24
Peak memory 205416 kb
Host smart-9be6a651-9a08-473e-bb4a-c8a6b0afecba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730939672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2730939672
Directory /workspace/25.spi_device_alert_test/latest


Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3398679666
Short name T228
Test name
Test status
Simulation time 296122568 ps
CPU time 3.48 seconds
Started Jun 29 06:49:40 PM PDT 24
Finished Jun 29 06:49:44 PM PDT 24
Peak memory 232620 kb
Host smart-1a16adc0-9504-42b8-83d6-f842a0d901ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398679666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3398679666
Directory /workspace/25.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/25.spi_device_csb_read.1905040375
Short name T396
Test name
Test status
Simulation time 15074226 ps
CPU time 0.75 seconds
Started Jun 29 06:49:39 PM PDT 24
Finished Jun 29 06:49:41 PM PDT 24
Peak memory 205864 kb
Host smart-067526c1-b6f1-46cb-a477-3bb2e3c7ffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905040375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1905040375
Directory /workspace/25.spi_device_csb_read/latest


Test location /workspace/coverage/default/25.spi_device_flash_all.2090149120
Short name T274
Test name
Test status
Simulation time 6011015787 ps
CPU time 59.03 seconds
Started Jun 29 06:49:50 PM PDT 24
Finished Jun 29 06:50:51 PM PDT 24
Peak memory 253116 kb
Host smart-bc63e2c7-8b10-4312-ac88-e0fe4658167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090149120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2090149120
Directory /workspace/25.spi_device_flash_all/latest


Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2509249965
Short name T424
Test name
Test status
Simulation time 1226688728 ps
CPU time 23.22 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:50:14 PM PDT 24
Peak memory 234008 kb
Host smart-ffa6fe37-928e-4306-a595-aee1257d7cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509249965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2509249965
Directory /workspace/25.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.292420050
Short name T602
Test name
Test status
Simulation time 4202726056 ps
CPU time 47.84 seconds
Started Jun 29 06:49:47 PM PDT 24
Finished Jun 29 06:50:36 PM PDT 24
Peak memory 249428 kb
Host smart-0da491ca-f109-4b58-8b36-44ac47846a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292420050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.292420050
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/25.spi_device_flash_mode.2482116599
Short name T879
Test name
Test status
Simulation time 17169031845 ps
CPU time 71.37 seconds
Started Jun 29 06:49:41 PM PDT 24
Finished Jun 29 06:50:53 PM PDT 24
Peak memory 249224 kb
Host smart-eb2e4ccd-a7bb-4056-9d9d-6e97ffd708d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482116599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2482116599
Directory /workspace/25.spi_device_flash_mode/latest


Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3988587399
Short name T196
Test name
Test status
Simulation time 8272254443 ps
CPU time 107.81 seconds
Started Jun 29 06:49:42 PM PDT 24
Finished Jun 29 06:51:30 PM PDT 24
Peak memory 257308 kb
Host smart-30187500-4811-4981-b45e-4d79e2e5eede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988587399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3988587399
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/25.spi_device_intercept.3781609768
Short name T611
Test name
Test status
Simulation time 3950709682 ps
CPU time 10.61 seconds
Started Jun 29 06:49:40 PM PDT 24
Finished Jun 29 06:49:52 PM PDT 24
Peak memory 224604 kb
Host smart-374939a7-c12b-49ad-9267-26d47a2a5028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781609768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3781609768
Directory /workspace/25.spi_device_intercept/latest


Test location /workspace/coverage/default/25.spi_device_mailbox.3327236347
Short name T876
Test name
Test status
Simulation time 1158109595 ps
CPU time 5.01 seconds
Started Jun 29 06:49:42 PM PDT 24
Finished Jun 29 06:49:48 PM PDT 24
Peak memory 232672 kb
Host smart-6790a70c-086e-44b8-a1f3-31078bd0747d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327236347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3327236347
Directory /workspace/25.spi_device_mailbox/latest


Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1636912291
Short name T409
Test name
Test status
Simulation time 24822787551 ps
CPU time 14.9 seconds
Started Jun 29 06:49:42 PM PDT 24
Finished Jun 29 06:49:58 PM PDT 24
Peak memory 232728 kb
Host smart-ebcd79c6-651f-4ea3-88c1-cd3a96c52dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636912291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1636912291
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3300021685
Short name T717
Test name
Test status
Simulation time 780460290 ps
CPU time 3.33 seconds
Started Jun 29 06:49:41 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 232640 kb
Host smart-5d5146e4-2c27-4c07-9261-ca428d6161ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300021685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3300021685
Directory /workspace/25.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4248477622
Short name T966
Test name
Test status
Simulation time 123838656 ps
CPU time 4.3 seconds
Started Jun 29 06:49:47 PM PDT 24
Finished Jun 29 06:49:52 PM PDT 24
Peak memory 222960 kb
Host smart-ec6f9c1a-aa5d-4358-91cd-fcd4f8ff6d64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4248477622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4248477622
Directory /workspace/25.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/25.spi_device_stress_all.2107409362
Short name T765
Test name
Test status
Simulation time 53378288337 ps
CPU time 385.6 seconds
Started Jun 29 06:49:48 PM PDT 24
Finished Jun 29 06:56:15 PM PDT 24
Peak memory 256740 kb
Host smart-95c392c7-6d86-4316-91e5-e29c3f669b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107409362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2107409362
Directory /workspace/25.spi_device_stress_all/latest


Test location /workspace/coverage/default/25.spi_device_tpm_all.1489874998
Short name T298
Test name
Test status
Simulation time 34700779781 ps
CPU time 32.23 seconds
Started Jun 29 06:49:40 PM PDT 24
Finished Jun 29 06:50:13 PM PDT 24
Peak memory 216348 kb
Host smart-b6ba5c75-3137-4e8e-924c-d4682055dab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489874998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1489874998
Directory /workspace/25.spi_device_tpm_all/latest


Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.889333628
Short name T507
Test name
Test status
Simulation time 5729822795 ps
CPU time 12.71 seconds
Started Jun 29 06:49:39 PM PDT 24
Finished Jun 29 06:49:52 PM PDT 24
Peak memory 216296 kb
Host smart-c38ff5c6-5b78-47c5-92f7-7e4a30b0ac5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889333628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.889333628
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/25.spi_device_tpm_rw.3704067376
Short name T301
Test name
Test status
Simulation time 55537446 ps
CPU time 1.41 seconds
Started Jun 29 06:49:39 PM PDT 24
Finished Jun 29 06:49:41 PM PDT 24
Peak memory 216184 kb
Host smart-f9e495b3-99a1-47d2-b5ab-f61894adc080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704067376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3704067376
Directory /workspace/25.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1623054569
Short name T6
Test name
Test status
Simulation time 192379002 ps
CPU time 1 seconds
Started Jun 29 06:49:39 PM PDT 24
Finished Jun 29 06:49:41 PM PDT 24
Peak memory 206104 kb
Host smart-d4c33a82-dd61-4bc7-8047-3b58288c323d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623054569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1623054569
Directory /workspace/25.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/25.spi_device_upload.1738236667
Short name T622
Test name
Test status
Simulation time 74859046 ps
CPU time 2.18 seconds
Started Jun 29 06:49:45 PM PDT 24
Finished Jun 29 06:49:47 PM PDT 24
Peak memory 236392 kb
Host smart-7a9c90a0-42e4-4417-82c2-73f2712d9fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738236667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1738236667
Directory /workspace/25.spi_device_upload/latest


Test location /workspace/coverage/default/26.spi_device_alert_test.4256172463
Short name T524
Test name
Test status
Simulation time 12980670 ps
CPU time 0.7 seconds
Started Jun 29 06:49:50 PM PDT 24
Finished Jun 29 06:49:52 PM PDT 24
Peak memory 205720 kb
Host smart-135df476-6c44-4530-8845-2c7e02d0b7b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256172463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4256172463
Directory /workspace/26.spi_device_alert_test/latest


Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2807709036
Short name T137
Test name
Test status
Simulation time 1451578412 ps
CPU time 6.1 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:49:57 PM PDT 24
Peak memory 224440 kb
Host smart-9f5659ea-ae40-4511-ba9d-69660651c38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807709036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2807709036
Directory /workspace/26.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/26.spi_device_csb_read.2884584487
Short name T713
Test name
Test status
Simulation time 43950463 ps
CPU time 0.83 seconds
Started Jun 29 06:49:47 PM PDT 24
Finished Jun 29 06:49:49 PM PDT 24
Peak memory 206568 kb
Host smart-e351c613-203f-4d3a-b768-45260018509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884584487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2884584487
Directory /workspace/26.spi_device_csb_read/latest


Test location /workspace/coverage/default/26.spi_device_flash_all.3615395772
Short name T365
Test name
Test status
Simulation time 164381017 ps
CPU time 0.8 seconds
Started Jun 29 06:49:48 PM PDT 24
Finished Jun 29 06:49:50 PM PDT 24
Peak memory 215852 kb
Host smart-e4d882ac-2ee5-408b-9850-0142d44c4d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615395772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3615395772
Directory /workspace/26.spi_device_flash_all/latest


Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.951790708
Short name T636
Test name
Test status
Simulation time 3824997236 ps
CPU time 35.5 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:50:26 PM PDT 24
Peak memory 249180 kb
Host smart-4c0944fc-a949-4d92-8813-33c08e722518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951790708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.951790708
Directory /workspace/26.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2142806530
Short name T488
Test name
Test status
Simulation time 167933398542 ps
CPU time 329.18 seconds
Started Jun 29 06:49:50 PM PDT 24
Finished Jun 29 06:55:21 PM PDT 24
Peak memory 253612 kb
Host smart-fdf4d33f-3b12-4fd0-b8a3-e0a9c5f915c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142806530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2142806530
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/26.spi_device_flash_mode.704519585
Short name T292
Test name
Test status
Simulation time 249362506 ps
CPU time 7.75 seconds
Started Jun 29 06:49:48 PM PDT 24
Finished Jun 29 06:49:57 PM PDT 24
Peak memory 224456 kb
Host smart-c5a47c22-3f39-45ea-8c7e-38c447df4c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704519585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.704519585
Directory /workspace/26.spi_device_flash_mode/latest


Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.721189085
Short name T848
Test name
Test status
Simulation time 23213910 ps
CPU time 0.79 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:49:51 PM PDT 24
Peak memory 215880 kb
Host smart-b9a4f194-557a-4fa8-94ec-fa8bcd7dac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721189085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.721189085
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/26.spi_device_intercept.2014369715
Short name T787
Test name
Test status
Simulation time 5957716861 ps
CPU time 17.35 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:50:08 PM PDT 24
Peak memory 232692 kb
Host smart-cac2566d-4876-49e9-b113-005898eb81bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014369715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2014369715
Directory /workspace/26.spi_device_intercept/latest


Test location /workspace/coverage/default/26.spi_device_mailbox.2480712456
Short name T694
Test name
Test status
Simulation time 34111802 ps
CPU time 2.21 seconds
Started Jun 29 06:49:47 PM PDT 24
Finished Jun 29 06:49:51 PM PDT 24
Peak memory 226848 kb
Host smart-273120d6-cc8d-4642-aa9d-9306a2254905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480712456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2480712456
Directory /workspace/26.spi_device_mailbox/latest


Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.687890302
Short name T598
Test name
Test status
Simulation time 18670321903 ps
CPU time 14.94 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:50:05 PM PDT 24
Peak memory 232780 kb
Host smart-67704c4b-097a-442b-8157-23308dab9a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687890302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.687890302
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.921511093
Short name T571
Test name
Test status
Simulation time 1035043269 ps
CPU time 10.32 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:50:00 PM PDT 24
Peak memory 232708 kb
Host smart-d258da60-c717-475c-9f37-338f9a118178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921511093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.921511093
Directory /workspace/26.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1501841141
Short name T715
Test name
Test status
Simulation time 4084963141 ps
CPU time 10.06 seconds
Started Jun 29 06:49:48 PM PDT 24
Finished Jun 29 06:49:59 PM PDT 24
Peak memory 222000 kb
Host smart-7f16c0b4-0094-4a47-b3bf-27111ed2e960
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1501841141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1501841141
Directory /workspace/26.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/26.spi_device_stress_all.1775168657
Short name T617
Test name
Test status
Simulation time 26060490358 ps
CPU time 179.36 seconds
Started Jun 29 06:49:48 PM PDT 24
Finished Jun 29 06:52:48 PM PDT 24
Peak memory 273084 kb
Host smart-ad6994a1-a4da-4a8c-a136-a9f2a1722ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775168657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1775168657
Directory /workspace/26.spi_device_stress_all/latest


Test location /workspace/coverage/default/26.spi_device_tpm_all.3640468314
Short name T1014
Test name
Test status
Simulation time 23547865031 ps
CPU time 33.07 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:50:24 PM PDT 24
Peak memory 216348 kb
Host smart-45dcc112-f6e3-4013-b543-16a12f24caa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640468314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3640468314
Directory /workspace/26.spi_device_tpm_all/latest


Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1834009187
Short name T940
Test name
Test status
Simulation time 4236614803 ps
CPU time 12.12 seconds
Started Jun 29 06:49:50 PM PDT 24
Finished Jun 29 06:50:03 PM PDT 24
Peak memory 216268 kb
Host smart-4f885341-fafc-4521-9ba3-cddc4bcb50af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834009187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1834009187
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/26.spi_device_tpm_rw.1866471865
Short name T527
Test name
Test status
Simulation time 30425767 ps
CPU time 0.84 seconds
Started Jun 29 06:49:51 PM PDT 24
Finished Jun 29 06:49:53 PM PDT 24
Peak memory 206444 kb
Host smart-627921f8-582f-4a7f-a0f4-b33fbff73ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866471865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1866471865
Directory /workspace/26.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1382217185
Short name T84
Test name
Test status
Simulation time 40899010 ps
CPU time 0.72 seconds
Started Jun 29 06:49:47 PM PDT 24
Finished Jun 29 06:49:48 PM PDT 24
Peak memory 205884 kb
Host smart-c494e1f4-d56b-4504-bd7c-5e499ab26837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382217185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1382217185
Directory /workspace/26.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/26.spi_device_upload.584455436
Short name T254
Test name
Test status
Simulation time 276036376 ps
CPU time 4.06 seconds
Started Jun 29 06:49:50 PM PDT 24
Finished Jun 29 06:49:55 PM PDT 24
Peak memory 224436 kb
Host smart-1b2e860b-f576-4c40-a8ba-b45ebb4bfe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584455436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.584455436
Directory /workspace/26.spi_device_upload/latest


Test location /workspace/coverage/default/27.spi_device_alert_test.3006109810
Short name T586
Test name
Test status
Simulation time 18184205 ps
CPU time 0.75 seconds
Started Jun 29 06:49:55 PM PDT 24
Finished Jun 29 06:49:56 PM PDT 24
Peak memory 204844 kb
Host smart-5e607fef-98f7-48e4-9f56-3f97aad1932c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006109810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3006109810
Directory /workspace/27.spi_device_alert_test/latest


Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3913988
Short name T656
Test name
Test status
Simulation time 169038580 ps
CPU time 3.3 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:49:54 PM PDT 24
Peak memory 224440 kb
Host smart-c730fdcb-1aa5-4468-b1f1-0960d561e31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3913988
Directory /workspace/27.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/27.spi_device_csb_read.1294089240
Short name T316
Test name
Test status
Simulation time 16288554 ps
CPU time 0.78 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:49:51 PM PDT 24
Peak memory 206836 kb
Host smart-4c438f65-a4f8-49bf-875f-58a9fedc040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294089240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1294089240
Directory /workspace/27.spi_device_csb_read/latest


Test location /workspace/coverage/default/27.spi_device_flash_all.4150475491
Short name T255
Test name
Test status
Simulation time 38828853818 ps
CPU time 149.96 seconds
Started Jun 29 06:49:48 PM PDT 24
Finished Jun 29 06:52:20 PM PDT 24
Peak memory 249192 kb
Host smart-69e68d13-477e-4aba-b4f6-fbc36103e247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150475491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.4150475491
Directory /workspace/27.spi_device_flash_all/latest


Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.4129981176
Short name T232
Test name
Test status
Simulation time 7082630715 ps
CPU time 30.33 seconds
Started Jun 29 06:49:47 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 240224 kb
Host smart-fe6f8aee-bc55-4e17-9627-a2d2725d410b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129981176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4129981176
Directory /workspace/27.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3686467690
Short name T888
Test name
Test status
Simulation time 8000604725 ps
CPU time 109.29 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:51:39 PM PDT 24
Peak memory 256072 kb
Host smart-658d64ba-b85d-4db7-b76c-353afb4524b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686467690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3686467690
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/27.spi_device_flash_mode.2997225490
Short name T877
Test name
Test status
Simulation time 44406914 ps
CPU time 3.07 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:49:54 PM PDT 24
Peak memory 232616 kb
Host smart-8e68dec8-3f02-48a5-868c-8c05bfee942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997225490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2997225490
Directory /workspace/27.spi_device_flash_mode/latest


Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3713038250
Short name T465
Test name
Test status
Simulation time 63116019225 ps
CPU time 123.5 seconds
Started Jun 29 06:49:47 PM PDT 24
Finished Jun 29 06:51:51 PM PDT 24
Peak memory 257356 kb
Host smart-7503b4f9-1905-40fa-bfc6-9ec0c5ade495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713038250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3713038250
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/27.spi_device_intercept.2452536099
Short name T225
Test name
Test status
Simulation time 862463338 ps
CPU time 4.42 seconds
Started Jun 29 06:49:51 PM PDT 24
Finished Jun 29 06:49:56 PM PDT 24
Peak memory 232612 kb
Host smart-f688b193-42cb-4f3a-8d4d-b167dee4a4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452536099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2452536099
Directory /workspace/27.spi_device_intercept/latest


Test location /workspace/coverage/default/27.spi_device_mailbox.2851524489
Short name T776
Test name
Test status
Simulation time 608460824 ps
CPU time 11.79 seconds
Started Jun 29 06:49:48 PM PDT 24
Finished Jun 29 06:50:01 PM PDT 24
Peak memory 232604 kb
Host smart-54238390-7a29-4f6c-8336-e8c7c4962f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851524489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2851524489
Directory /workspace/27.spi_device_mailbox/latest


Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.669452379
Short name T247
Test name
Test status
Simulation time 753404360 ps
CPU time 8.67 seconds
Started Jun 29 06:49:50 PM PDT 24
Finished Jun 29 06:50:00 PM PDT 24
Peak memory 232632 kb
Host smart-8449783f-9a45-4a75-ad03-986c63922a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669452379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.669452379
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1445890735
Short name T377
Test name
Test status
Simulation time 1213317800 ps
CPU time 5.34 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:49:56 PM PDT 24
Peak memory 240680 kb
Host smart-ee1ae5f6-1bf5-45f7-94fc-a41ac2c42d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445890735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1445890735
Directory /workspace/27.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.948156798
Short name T664
Test name
Test status
Simulation time 855597190 ps
CPU time 6.27 seconds
Started Jun 29 06:49:50 PM PDT 24
Finished Jun 29 06:49:58 PM PDT 24
Peak memory 222084 kb
Host smart-32839ad1-6f3c-48a7-858a-9cb607f5ee57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=948156798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.948156798
Directory /workspace/27.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/27.spi_device_stress_all.367254510
Short name T912
Test name
Test status
Simulation time 163928748952 ps
CPU time 742.91 seconds
Started Jun 29 06:49:47 PM PDT 24
Finished Jun 29 07:02:11 PM PDT 24
Peak memory 264772 kb
Host smart-2fd716d3-baca-41aa-8e47-3bae8b44d3af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367254510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.367254510
Directory /workspace/27.spi_device_stress_all/latest


Test location /workspace/coverage/default/27.spi_device_tpm_all.4174830446
Short name T391
Test name
Test status
Simulation time 93375766 ps
CPU time 0.71 seconds
Started Jun 29 06:49:52 PM PDT 24
Finished Jun 29 06:49:53 PM PDT 24
Peak memory 205612 kb
Host smart-a2a7d0db-4c2a-43fc-86cf-cff0649a8f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174830446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4174830446
Directory /workspace/27.spi_device_tpm_all/latest


Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4213578351
Short name T582
Test name
Test status
Simulation time 81222877 ps
CPU time 0.71 seconds
Started Jun 29 06:49:48 PM PDT 24
Finished Jun 29 06:49:50 PM PDT 24
Peak memory 205664 kb
Host smart-06bd1e7a-2968-4972-984d-f0ad84a5659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213578351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4213578351
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/27.spi_device_tpm_rw.3920440302
Short name T383
Test name
Test status
Simulation time 131111448 ps
CPU time 1.29 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:49:52 PM PDT 24
Peak memory 216116 kb
Host smart-ad97a111-8c69-465c-83c2-91af66ee0834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920440302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3920440302
Directory /workspace/27.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.632686960
Short name T897
Test name
Test status
Simulation time 136868708 ps
CPU time 0.85 seconds
Started Jun 29 06:49:47 PM PDT 24
Finished Jun 29 06:49:50 PM PDT 24
Peak memory 205884 kb
Host smart-1d859272-7ccf-4e6c-b32a-02bd239ed9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632686960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.632686960
Directory /workspace/27.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/27.spi_device_upload.3286428351
Short name T961
Test name
Test status
Simulation time 1098727285 ps
CPU time 5.39 seconds
Started Jun 29 06:49:49 PM PDT 24
Finished Jun 29 06:49:55 PM PDT 24
Peak memory 232668 kb
Host smart-3a6608b0-e0bc-4733-84ab-ff3d7f614ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286428351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3286428351
Directory /workspace/27.spi_device_upload/latest


Test location /workspace/coverage/default/28.spi_device_alert_test.1739228949
Short name T704
Test name
Test status
Simulation time 33418336 ps
CPU time 0.73 seconds
Started Jun 29 06:49:58 PM PDT 24
Finished Jun 29 06:49:59 PM PDT 24
Peak memory 205776 kb
Host smart-bb759dd8-fa68-42c3-9d77-e22f1994014f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739228949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1739228949
Directory /workspace/28.spi_device_alert_test/latest


Test location /workspace/coverage/default/28.spi_device_cfg_cmd.4276276130
Short name T655
Test name
Test status
Simulation time 74440514 ps
CPU time 3.51 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:50:07 PM PDT 24
Peak memory 232656 kb
Host smart-199cd550-1291-4707-981a-a4cfea751ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276276130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4276276130
Directory /workspace/28.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/28.spi_device_csb_read.525287078
Short name T313
Test name
Test status
Simulation time 166087194 ps
CPU time 0.78 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:49:58 PM PDT 24
Peak memory 206532 kb
Host smart-e5180b1e-9781-4f23-a566-28d2478d5234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525287078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.525287078
Directory /workspace/28.spi_device_csb_read/latest


Test location /workspace/coverage/default/28.spi_device_flash_all.2513538548
Short name T839
Test name
Test status
Simulation time 3419690560 ps
CPU time 44.84 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:50:41 PM PDT 24
Peak memory 250276 kb
Host smart-71357ef1-7ab8-4a8a-8829-c73df264cd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513538548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2513538548
Directory /workspace/28.spi_device_flash_all/latest


Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1225095627
Short name T448
Test name
Test status
Simulation time 26732442633 ps
CPU time 64.77 seconds
Started Jun 29 06:49:54 PM PDT 24
Finished Jun 29 06:50:59 PM PDT 24
Peak memory 235064 kb
Host smart-1f2f2fc6-52b0-4046-9793-ff152e4ab486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225095627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1225095627
Directory /workspace/28.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1217587075
Short name T262
Test name
Test status
Simulation time 22441279533 ps
CPU time 116.79 seconds
Started Jun 29 06:49:58 PM PDT 24
Finished Jun 29 06:51:55 PM PDT 24
Peak memory 269228 kb
Host smart-89462c8b-f921-4234-ad36-4c12b4a8bc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217587075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1217587075
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/28.spi_device_flash_mode.2081846809
Short name T286
Test name
Test status
Simulation time 184044907 ps
CPU time 6.07 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:50:09 PM PDT 24
Peak memory 232680 kb
Host smart-aa879676-692a-4eda-967b-e3bc5c2afac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081846809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2081846809
Directory /workspace/28.spi_device_flash_mode/latest


Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.4038156387
Short name T152
Test name
Test status
Simulation time 101024742 ps
CPU time 0.96 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:49:58 PM PDT 24
Peak memory 215940 kb
Host smart-1a5a2efb-ce52-4daa-98aa-099c2573cfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038156387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.4038156387
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/28.spi_device_intercept.1722136734
Short name T195
Test name
Test status
Simulation time 215394619 ps
CPU time 5.24 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:50:02 PM PDT 24
Peak memory 232636 kb
Host smart-603398b8-437d-496d-b7c5-a46186b95c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722136734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1722136734
Directory /workspace/28.spi_device_intercept/latest


Test location /workspace/coverage/default/28.spi_device_mailbox.1956458417
Short name T495
Test name
Test status
Simulation time 13739075822 ps
CPU time 34.97 seconds
Started Jun 29 06:49:55 PM PDT 24
Finished Jun 29 06:50:31 PM PDT 24
Peak memory 238920 kb
Host smart-0c6a11ab-88dc-4069-a1d1-cfba9b69cc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956458417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1956458417
Directory /workspace/28.spi_device_mailbox/latest


Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3480208409
Short name T788
Test name
Test status
Simulation time 1028602536 ps
CPU time 5.08 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:50:02 PM PDT 24
Peak memory 232632 kb
Host smart-7c8efaef-6319-4304-a54c-731e2c52e06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480208409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3480208409
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3795075737
Short name T652
Test name
Test status
Simulation time 14449813477 ps
CPU time 5.67 seconds
Started Jun 29 06:49:55 PM PDT 24
Finished Jun 29 06:50:01 PM PDT 24
Peak memory 224560 kb
Host smart-3e281290-f4d0-4d99-bd63-37db768d4f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795075737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3795075737
Directory /workspace/28.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1946631360
Short name T415
Test name
Test status
Simulation time 1325218387 ps
CPU time 7.62 seconds
Started Jun 29 06:49:54 PM PDT 24
Finished Jun 29 06:50:02 PM PDT 24
Peak memory 221952 kb
Host smart-77c2e640-205e-4667-8a94-2cbc14f6e802
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1946631360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1946631360
Directory /workspace/28.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/28.spi_device_stress_all.3348790532
Short name T19
Test name
Test status
Simulation time 4565899578 ps
CPU time 66.01 seconds
Started Jun 29 06:49:57 PM PDT 24
Finished Jun 29 06:51:03 PM PDT 24
Peak memory 249304 kb
Host smart-8954d022-5d97-4504-8ff8-c18a24f6ea83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348790532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3348790532
Directory /workspace/28.spi_device_stress_all/latest


Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1229639174
Short name T712
Test name
Test status
Simulation time 16949165 ps
CPU time 0.7 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:49:58 PM PDT 24
Peak memory 205636 kb
Host smart-6c9dd942-40f4-4164-84c6-22c86ee6ae0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229639174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1229639174
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/28.spi_device_tpm_rw.2583104527
Short name T641
Test name
Test status
Simulation time 183757493 ps
CPU time 1.52 seconds
Started Jun 29 06:49:57 PM PDT 24
Finished Jun 29 06:49:59 PM PDT 24
Peak memory 216184 kb
Host smart-7a38ba95-f486-4a0c-a9b5-0e646775f52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583104527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2583104527
Directory /workspace/28.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2910875837
Short name T526
Test name
Test status
Simulation time 23369645 ps
CPU time 0.8 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:49:57 PM PDT 24
Peak memory 205884 kb
Host smart-e93cab46-5140-43e9-aad2-12f90f7b5936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910875837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2910875837
Directory /workspace/28.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/28.spi_device_upload.2303288429
Short name T666
Test name
Test status
Simulation time 115865381 ps
CPU time 2.1 seconds
Started Jun 29 06:49:55 PM PDT 24
Finished Jun 29 06:49:58 PM PDT 24
Peak memory 224176 kb
Host smart-f0898a81-cf15-4f1f-b442-1f0d6e307d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303288429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2303288429
Directory /workspace/28.spi_device_upload/latest


Test location /workspace/coverage/default/29.spi_device_alert_test.392427484
Short name T909
Test name
Test status
Simulation time 14576158 ps
CPU time 0.76 seconds
Started Jun 29 06:50:05 PM PDT 24
Finished Jun 29 06:50:06 PM PDT 24
Peak memory 205420 kb
Host smart-8b295419-1429-41aa-b059-8f805dc1312b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392427484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.392427484
Directory /workspace/29.spi_device_alert_test/latest


Test location /workspace/coverage/default/29.spi_device_cfg_cmd.376474288
Short name T374
Test name
Test status
Simulation time 193575126 ps
CPU time 3.03 seconds
Started Jun 29 06:49:54 PM PDT 24
Finished Jun 29 06:49:58 PM PDT 24
Peak memory 224408 kb
Host smart-00701ae4-aa4d-4cef-b58c-d58e860e6156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376474288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.376474288
Directory /workspace/29.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/29.spi_device_csb_read.1693913183
Short name T638
Test name
Test status
Simulation time 22009248 ps
CPU time 0.75 seconds
Started Jun 29 06:49:57 PM PDT 24
Finished Jun 29 06:49:59 PM PDT 24
Peak memory 206892 kb
Host smart-d1e45861-6b14-49eb-9e19-29c96dab014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693913183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1693913183
Directory /workspace/29.spi_device_csb_read/latest


Test location /workspace/coverage/default/29.spi_device_flash_all.1979370587
Short name T936
Test name
Test status
Simulation time 1350344801 ps
CPU time 19.47 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:50:17 PM PDT 24
Peak memory 237016 kb
Host smart-d95b3488-9681-44a8-85b9-cdc52f54c329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979370587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1979370587
Directory /workspace/29.spi_device_flash_all/latest


Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.459657619
Short name T829
Test name
Test status
Simulation time 1417717461 ps
CPU time 20.08 seconds
Started Jun 29 06:50:04 PM PDT 24
Finished Jun 29 06:50:25 PM PDT 24
Peak memory 237524 kb
Host smart-798890eb-6609-4672-8218-b2f8fb5e19a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459657619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.459657619
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/29.spi_device_flash_mode.3898938460
Short name T969
Test name
Test status
Simulation time 213958697 ps
CPU time 3.6 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:50:00 PM PDT 24
Peak memory 232684 kb
Host smart-0e8ddfdc-2147-4426-92b8-79152f6ae9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898938460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3898938460
Directory /workspace/29.spi_device_flash_mode/latest


Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3454061414
Short name T473
Test name
Test status
Simulation time 7218925976 ps
CPU time 28.51 seconds
Started Jun 29 06:49:54 PM PDT 24
Finished Jun 29 06:50:22 PM PDT 24
Peak memory 224580 kb
Host smart-1fc58636-4cda-496b-ba6c-1b0aef467de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454061414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3454061414
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/29.spi_device_intercept.3471299250
Short name T960
Test name
Test status
Simulation time 7279395503 ps
CPU time 6.44 seconds
Started Jun 29 06:49:53 PM PDT 24
Finished Jun 29 06:50:00 PM PDT 24
Peak memory 232748 kb
Host smart-334936ed-7917-42e5-81bc-d6e7fb9aeddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471299250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3471299250
Directory /workspace/29.spi_device_intercept/latest


Test location /workspace/coverage/default/29.spi_device_mailbox.4080986331
Short name T253
Test name
Test status
Simulation time 1304843128 ps
CPU time 21.88 seconds
Started Jun 29 06:49:57 PM PDT 24
Finished Jun 29 06:50:20 PM PDT 24
Peak memory 224416 kb
Host smart-f299d65c-0f10-4d49-b941-ddf0c0e13d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080986331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4080986331
Directory /workspace/29.spi_device_mailbox/latest


Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4024728444
Short name T387
Test name
Test status
Simulation time 377339985 ps
CPU time 2.91 seconds
Started Jun 29 06:49:55 PM PDT 24
Finished Jun 29 06:49:58 PM PDT 24
Peak memory 224388 kb
Host smart-a771f436-65ee-4bb0-aa0f-e4e4d3e41382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024728444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4024728444
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3518687142
Short name T229
Test name
Test status
Simulation time 5014559870 ps
CPU time 8.25 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:50:10 PM PDT 24
Peak memory 232800 kb
Host smart-f48afdcb-cf28-4be0-b52c-b6ad5d488cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518687142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3518687142
Directory /workspace/29.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1526834268
Short name T763
Test name
Test status
Simulation time 301516933 ps
CPU time 4.08 seconds
Started Jun 29 06:49:54 PM PDT 24
Finished Jun 29 06:49:58 PM PDT 24
Peak memory 220920 kb
Host smart-d5b1aafc-7f0b-4e53-9a47-6e413b6fb87c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1526834268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1526834268
Directory /workspace/29.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/29.spi_device_stress_all.3328360506
Short name T159
Test name
Test status
Simulation time 267683045495 ps
CPU time 521.49 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:58:44 PM PDT 24
Peak memory 252296 kb
Host smart-aa5e66a1-9e4b-4846-b572-13a8533213f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328360506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3328360506
Directory /workspace/29.spi_device_stress_all/latest


Test location /workspace/coverage/default/29.spi_device_tpm_all.3212319399
Short name T24
Test name
Test status
Simulation time 3523187789 ps
CPU time 27.01 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:50:23 PM PDT 24
Peak memory 216352 kb
Host smart-47f8375d-a543-427e-bf4a-0b03ca269cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212319399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3212319399
Directory /workspace/29.spi_device_tpm_all/latest


Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2541396115
Short name T511
Test name
Test status
Simulation time 4656139500 ps
CPU time 15.45 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 216344 kb
Host smart-d4d4bfb1-0713-423c-84b0-6d32fd79bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541396115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2541396115
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/29.spi_device_tpm_rw.3341447921
Short name T133
Test name
Test status
Simulation time 76546143 ps
CPU time 3.87 seconds
Started Jun 29 06:49:57 PM PDT 24
Finished Jun 29 06:50:02 PM PDT 24
Peak memory 216148 kb
Host smart-e6a7ef61-7ff2-4078-a288-27ca49414133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341447921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3341447921
Directory /workspace/29.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1600407194
Short name T658
Test name
Test status
Simulation time 57872085 ps
CPU time 0.83 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:50:03 PM PDT 24
Peak memory 205884 kb
Host smart-5ba17bf3-8fea-4713-8080-234fdd9f4de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600407194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1600407194
Directory /workspace/29.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/29.spi_device_upload.810698115
Short name T463
Test name
Test status
Simulation time 90011038 ps
CPU time 2.65 seconds
Started Jun 29 06:49:56 PM PDT 24
Finished Jun 29 06:49:59 PM PDT 24
Peak memory 232648 kb
Host smart-d8cc7f1b-6156-4d92-8629-7ab3350706d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810698115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.810698115
Directory /workspace/29.spi_device_upload/latest


Test location /workspace/coverage/default/3.spi_device_alert_test.2759588647
Short name T458
Test name
Test status
Simulation time 10827958 ps
CPU time 0.73 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:26 PM PDT 24
Peak memory 204840 kb
Host smart-7f97fde7-1497-4233-8be7-c6522cd3509f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759588647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
759588647
Directory /workspace/3.spi_device_alert_test/latest


Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3721779069
Short name T351
Test name
Test status
Simulation time 6128291142 ps
CPU time 13.11 seconds
Started Jun 29 06:48:24 PM PDT 24
Finished Jun 29 06:48:38 PM PDT 24
Peak memory 224588 kb
Host smart-c177a347-ddc4-4f6f-a749-1fcb4a8eaf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721779069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3721779069
Directory /workspace/3.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/3.spi_device_csb_read.3191407834
Short name T1002
Test name
Test status
Simulation time 16370378 ps
CPU time 0.75 seconds
Started Jun 29 06:48:15 PM PDT 24
Finished Jun 29 06:48:16 PM PDT 24
Peak memory 206504 kb
Host smart-0d4ed56a-dff3-4ea4-9213-ae157301c4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191407834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3191407834
Directory /workspace/3.spi_device_csb_read/latest


Test location /workspace/coverage/default/3.spi_device_flash_all.343734793
Short name T1008
Test name
Test status
Simulation time 217033074745 ps
CPU time 84.61 seconds
Started Jun 29 06:48:20 PM PDT 24
Finished Jun 29 06:49:45 PM PDT 24
Peak memory 249188 kb
Host smart-a4b9b1ab-71eb-4650-b806-18efc1ea2804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343734793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.343734793
Directory /workspace/3.spi_device_flash_all/latest


Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2257072911
Short name T128
Test name
Test status
Simulation time 13371355089 ps
CPU time 123.31 seconds
Started Jun 29 06:48:24 PM PDT 24
Finished Jun 29 06:50:28 PM PDT 24
Peak memory 265632 kb
Host smart-955b5e24-5fe1-4258-828c-58a9ddc0c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257072911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2257072911
Directory /workspace/3.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3558507124
Short name T306
Test name
Test status
Simulation time 65970465820 ps
CPU time 342.8 seconds
Started Jun 29 06:48:21 PM PDT 24
Finished Jun 29 06:54:04 PM PDT 24
Peak memory 273500 kb
Host smart-37e7c087-4bf1-4bb3-a7bd-b8b65f92abbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558507124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3558507124
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/3.spi_device_flash_mode.2602310483
Short name T716
Test name
Test status
Simulation time 418789041 ps
CPU time 3.73 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:29 PM PDT 24
Peak memory 224472 kb
Host smart-311bdba0-93a8-4b48-ac7a-4cd6a6c056ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602310483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2602310483
Directory /workspace/3.spi_device_flash_mode/latest


Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.589046687
Short name T217
Test name
Test status
Simulation time 34615858519 ps
CPU time 59.48 seconds
Started Jun 29 06:48:23 PM PDT 24
Finished Jun 29 06:49:23 PM PDT 24
Peak memory 254040 kb
Host smart-e119fb8d-5401-43dc-ad6a-566fb0010840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589046687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
589046687
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/3.spi_device_intercept.2215041791
Short name T810
Test name
Test status
Simulation time 2654437454 ps
CPU time 7.56 seconds
Started Jun 29 06:48:22 PM PDT 24
Finished Jun 29 06:48:30 PM PDT 24
Peak memory 224544 kb
Host smart-1f670bbb-14a1-4304-bda9-a795dde1b726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215041791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2215041791
Directory /workspace/3.spi_device_intercept/latest


Test location /workspace/coverage/default/3.spi_device_mailbox.26994678
Short name T204
Test name
Test status
Simulation time 2894062364 ps
CPU time 13.14 seconds
Started Jun 29 06:48:23 PM PDT 24
Finished Jun 29 06:48:36 PM PDT 24
Peak memory 232764 kb
Host smart-9c27fead-d934-4631-9c6b-2ccbf57754d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26994678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.26994678
Directory /workspace/3.spi_device_mailbox/latest


Test location /workspace/coverage/default/3.spi_device_mem_parity.3617053879
Short name T630
Test name
Test status
Simulation time 14894726 ps
CPU time 1.13 seconds
Started Jun 29 06:48:16 PM PDT 24
Finished Jun 29 06:48:18 PM PDT 24
Peak memory 216776 kb
Host smart-7a7b5af8-c2be-4d37-aea4-3148d4224a40
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617053879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3617053879
Directory /workspace/3.spi_device_mem_parity/latest


Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.4130576008
Short name T499
Test name
Test status
Simulation time 58314105 ps
CPU time 2.33 seconds
Started Jun 29 06:48:23 PM PDT 24
Finished Jun 29 06:48:26 PM PDT 24
Peak memory 232356 kb
Host smart-84afed69-06bf-4566-8d33-cf1185ea8997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130576008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.4130576008
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2041147398
Short name T320
Test name
Test status
Simulation time 240848795 ps
CPU time 2.17 seconds
Started Jun 29 06:48:21 PM PDT 24
Finished Jun 29 06:48:23 PM PDT 24
Peak memory 223932 kb
Host smart-555fc64f-7084-49cc-bfd2-670b6b7e4024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041147398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2041147398
Directory /workspace/3.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.761128078
Short name T531
Test name
Test status
Simulation time 399916749 ps
CPU time 4.18 seconds
Started Jun 29 06:48:23 PM PDT 24
Finished Jun 29 06:48:28 PM PDT 24
Peak memory 222532 kb
Host smart-a49be39b-9482-4b50-bb0e-4a3f6951bff0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=761128078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.761128078
Directory /workspace/3.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/3.spi_device_sec_cm.261791392
Short name T64
Test name
Test status
Simulation time 33441716 ps
CPU time 0.91 seconds
Started Jun 29 06:48:26 PM PDT 24
Finished Jun 29 06:48:27 PM PDT 24
Peak memory 235520 kb
Host smart-069ea385-0a86-46cf-bc53-566c77ab7c69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261791392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.261791392
Directory /workspace/3.spi_device_sec_cm/latest


Test location /workspace/coverage/default/3.spi_device_stress_all.2916822127
Short name T18
Test name
Test status
Simulation time 45277492 ps
CPU time 0.98 seconds
Started Jun 29 06:48:23 PM PDT 24
Finished Jun 29 06:48:24 PM PDT 24
Peak memory 206984 kb
Host smart-7f2ae40f-d441-4c81-a7c5-01688a14cf23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916822127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2916822127
Directory /workspace/3.spi_device_stress_all/latest


Test location /workspace/coverage/default/3.spi_device_tpm_all.3621046276
Short name T982
Test name
Test status
Simulation time 2243762448 ps
CPU time 9.41 seconds
Started Jun 29 06:48:16 PM PDT 24
Finished Jun 29 06:48:26 PM PDT 24
Peak memory 216244 kb
Host smart-bc570f8d-002f-40e3-899f-97e09a64b2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621046276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3621046276
Directory /workspace/3.spi_device_tpm_all/latest


Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1025096098
Short name T732
Test name
Test status
Simulation time 2801608225 ps
CPU time 11.37 seconds
Started Jun 29 06:48:16 PM PDT 24
Finished Jun 29 06:48:28 PM PDT 24
Peak memory 216248 kb
Host smart-415fff26-275a-4093-8ce1-138bc8ed7f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025096098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1025096098
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/3.spi_device_tpm_rw.3768556872
Short name T445
Test name
Test status
Simulation time 130855508 ps
CPU time 4.52 seconds
Started Jun 29 06:48:19 PM PDT 24
Finished Jun 29 06:48:24 PM PDT 24
Peak memory 216132 kb
Host smart-ee99d5f9-21ff-4fa1-a0dd-b814b0207cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768556872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3768556872
Directory /workspace/3.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.362492772
Short name T1026
Test name
Test status
Simulation time 76776573 ps
CPU time 0.92 seconds
Started Jun 29 06:48:17 PM PDT 24
Finished Jun 29 06:48:19 PM PDT 24
Peak memory 205832 kb
Host smart-a44f1eed-683c-47ef-a793-fa392997656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362492772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.362492772
Directory /workspace/3.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/3.spi_device_upload.2483626008
Short name T970
Test name
Test status
Simulation time 200373878 ps
CPU time 4.25 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:30 PM PDT 24
Peak memory 240556 kb
Host smart-e5b7b420-c5c8-43e6-a2db-5a385a79aa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483626008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2483626008
Directory /workspace/3.spi_device_upload/latest


Test location /workspace/coverage/default/30.spi_device_alert_test.1716069123
Short name T620
Test name
Test status
Simulation time 145190282 ps
CPU time 0.74 seconds
Started Jun 29 06:50:04 PM PDT 24
Finished Jun 29 06:50:06 PM PDT 24
Peak memory 205416 kb
Host smart-9989d21f-21a2-4efa-a156-bddfd910db1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716069123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1716069123
Directory /workspace/30.spi_device_alert_test/latest


Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2701759569
Short name T998
Test name
Test status
Simulation time 128258208 ps
CPU time 3.48 seconds
Started Jun 29 06:50:05 PM PDT 24
Finished Jun 29 06:50:09 PM PDT 24
Peak memory 232916 kb
Host smart-7f00b3b2-56c5-4f1e-8ba7-29efd9fb13f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701759569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2701759569
Directory /workspace/30.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/30.spi_device_csb_read.1534156565
Short name T378
Test name
Test status
Simulation time 13059587 ps
CPU time 0.76 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:50:02 PM PDT 24
Peak memory 206520 kb
Host smart-ea61acbc-55fb-4698-9e46-020a6a473132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534156565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1534156565
Directory /workspace/30.spi_device_csb_read/latest


Test location /workspace/coverage/default/30.spi_device_flash_all.2772379
Short name T136
Test name
Test status
Simulation time 2254620484 ps
CPU time 15.07 seconds
Started Jun 29 06:50:05 PM PDT 24
Finished Jun 29 06:50:21 PM PDT 24
Peak memory 224484 kb
Host smart-a51cc8b5-6638-441f-8378-a7e4e8d9d5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2772379
Directory /workspace/30.spi_device_flash_all/latest


Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4077008770
Short name T207
Test name
Test status
Simulation time 25563293207 ps
CPU time 315.79 seconds
Started Jun 29 06:50:05 PM PDT 24
Finished Jun 29 06:55:22 PM PDT 24
Peak memory 264420 kb
Host smart-e2d00d7a-8a7a-49be-a988-6ee5b1d987df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077008770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4077008770
Directory /workspace/30.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.783531394
Short name T170
Test name
Test status
Simulation time 106067933475 ps
CPU time 283 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:54:47 PM PDT 24
Peak memory 268416 kb
Host smart-55da2530-5beb-4776-8c79-f993782bd039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783531394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.783531394
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/30.spi_device_flash_mode.1904873912
Short name T285
Test name
Test status
Simulation time 5117671453 ps
CPU time 15.11 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 232916 kb
Host smart-5852b085-b5ba-419d-a0ea-3963b98cf883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904873912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1904873912
Directory /workspace/30.spi_device_flash_mode/latest


Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2736930629
Short name T265
Test name
Test status
Simulation time 3599122280 ps
CPU time 81.11 seconds
Started Jun 29 06:50:03 PM PDT 24
Finished Jun 29 06:51:25 PM PDT 24
Peak memory 259912 kb
Host smart-236feb7c-81b9-48c4-b9e2-86a198d5b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736930629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2736930629
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/30.spi_device_intercept.2321662072
Short name T222
Test name
Test status
Simulation time 57155328 ps
CPU time 2.74 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:50:05 PM PDT 24
Peak memory 232668 kb
Host smart-9887de78-11c7-4f0b-99ca-d1abb4b81e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321662072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2321662072
Directory /workspace/30.spi_device_intercept/latest


Test location /workspace/coverage/default/30.spi_device_mailbox.1128786641
Short name T242
Test name
Test status
Simulation time 16196548359 ps
CPU time 84.93 seconds
Started Jun 29 06:50:03 PM PDT 24
Finished Jun 29 06:51:29 PM PDT 24
Peak memory 239472 kb
Host smart-bf702400-a417-4e32-82e8-a431a4efde7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128786641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1128786641
Directory /workspace/30.spi_device_mailbox/latest


Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.833592671
Short name T401
Test name
Test status
Simulation time 450356827 ps
CPU time 2.3 seconds
Started Jun 29 06:50:04 PM PDT 24
Finished Jun 29 06:50:07 PM PDT 24
Peak memory 224400 kb
Host smart-41a85e6b-06af-47b5-8a71-3fcfe862152b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833592671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.833592671
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1359838332
Short name T976
Test name
Test status
Simulation time 1069982481 ps
CPU time 6.18 seconds
Started Jun 29 06:50:03 PM PDT 24
Finished Jun 29 06:50:10 PM PDT 24
Peak memory 240544 kb
Host smart-1e96fa50-a204-48b2-82e9-927f0733afb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359838332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1359838332
Directory /workspace/30.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4277056254
Short name T71
Test name
Test status
Simulation time 25649029809 ps
CPU time 24.4 seconds
Started Jun 29 06:50:05 PM PDT 24
Finished Jun 29 06:50:30 PM PDT 24
Peak memory 220464 kb
Host smart-27a4b554-a017-4f7d-a7fd-3e229dd2954a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4277056254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4277056254
Directory /workspace/30.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/30.spi_device_stress_all.2668166779
Short name T769
Test name
Test status
Simulation time 4666980228 ps
CPU time 82.54 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:51:26 PM PDT 24
Peak memory 265520 kb
Host smart-d783bab2-29e3-4e7c-b99f-be67c9ac591a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668166779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2668166779
Directory /workspace/30.spi_device_stress_all/latest


Test location /workspace/coverage/default/30.spi_device_tpm_all.4110783600
Short name T587
Test name
Test status
Simulation time 2056147668 ps
CPU time 16.99 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:50:20 PM PDT 24
Peak memory 216224 kb
Host smart-b3b4e406-7f17-4087-8a77-a55e970aa416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110783600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4110783600
Directory /workspace/30.spi_device_tpm_all/latest


Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2237360188
Short name T379
Test name
Test status
Simulation time 20203223758 ps
CPU time 14.91 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 216312 kb
Host smart-80c7398c-ae39-42a6-8f9a-fa2125b092b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237360188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2237360188
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/30.spi_device_tpm_rw.1122988535
Short name T865
Test name
Test status
Simulation time 34894879 ps
CPU time 1 seconds
Started Jun 29 06:50:04 PM PDT 24
Finished Jun 29 06:50:05 PM PDT 24
Peak memory 206972 kb
Host smart-c44e7f48-b514-4238-abac-ab5dde322f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122988535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1122988535
Directory /workspace/30.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3128642974
Short name T755
Test name
Test status
Simulation time 126187731 ps
CPU time 1.01 seconds
Started Jun 29 06:50:03 PM PDT 24
Finished Jun 29 06:50:05 PM PDT 24
Peak memory 206264 kb
Host smart-da5cc792-3c76-463a-8d77-8772efd83b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128642974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3128642974
Directory /workspace/30.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/30.spi_device_upload.1874471453
Short name T721
Test name
Test status
Simulation time 322672772 ps
CPU time 5.52 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:50:07 PM PDT 24
Peak memory 232640 kb
Host smart-582f2624-9f0f-4c73-bbd3-af7cab68648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874471453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1874471453
Directory /workspace/30.spi_device_upload/latest


Test location /workspace/coverage/default/31.spi_device_alert_test.3220952154
Short name T76
Test name
Test status
Simulation time 15303938 ps
CPU time 0.72 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:50:13 PM PDT 24
Peak memory 204788 kb
Host smart-83cc7a4c-35f9-44de-8c28-0f00f59426d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220952154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3220952154
Directory /workspace/31.spi_device_alert_test/latest


Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3504324540
Short name T689
Test name
Test status
Simulation time 412355279 ps
CPU time 2.52 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:50:06 PM PDT 24
Peak memory 232620 kb
Host smart-4fee2ed9-5937-4122-9592-a3ae2fb79ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504324540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3504324540
Directory /workspace/31.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/31.spi_device_csb_read.2765190366
Short name T691
Test name
Test status
Simulation time 50355796 ps
CPU time 0.75 seconds
Started Jun 29 06:50:03 PM PDT 24
Finished Jun 29 06:50:05 PM PDT 24
Peak memory 205556 kb
Host smart-00b491ef-1f63-4eb9-8813-7cacbbbfd566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765190366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2765190366
Directory /workspace/31.spi_device_csb_read/latest


Test location /workspace/coverage/default/31.spi_device_flash_all.2896608797
Short name T875
Test name
Test status
Simulation time 17285559543 ps
CPU time 27.76 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:50:40 PM PDT 24
Peak memory 235216 kb
Host smart-11810928-ab72-4f30-8780-e884487aafb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896608797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2896608797
Directory /workspace/31.spi_device_flash_all/latest


Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.623664853
Short name T809
Test name
Test status
Simulation time 3510586539 ps
CPU time 79.88 seconds
Started Jun 29 06:50:11 PM PDT 24
Finished Jun 29 06:51:31 PM PDT 24
Peak memory 254608 kb
Host smart-b7860b57-ca9d-44a4-9ed1-3a4896f67a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623664853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.623664853
Directory /workspace/31.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1632093484
Short name T258
Test name
Test status
Simulation time 36357913893 ps
CPU time 183.88 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:53:16 PM PDT 24
Peak memory 249232 kb
Host smart-1ca8cfee-b324-4710-80b8-5745638cdff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632093484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1632093484
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/31.spi_device_flash_mode.338880691
Short name T962
Test name
Test status
Simulation time 1226840759 ps
CPU time 10.74 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:50:14 PM PDT 24
Peak memory 224476 kb
Host smart-228e8b1c-3291-440a-a69e-c0d07bdd64ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338880691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.338880691
Directory /workspace/31.spi_device_flash_mode/latest


Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2230721394
Short name T219
Test name
Test status
Simulation time 21260386418 ps
CPU time 72.58 seconds
Started Jun 29 06:50:03 PM PDT 24
Finished Jun 29 06:51:17 PM PDT 24
Peak memory 255332 kb
Host smart-f46c7fc6-10e8-45c8-bd7f-86bdf1f9b58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230721394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2230721394
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/31.spi_device_intercept.3976100672
Short name T942
Test name
Test status
Simulation time 220575900 ps
CPU time 5 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:50:08 PM PDT 24
Peak memory 218788 kb
Host smart-11b57aea-d480-4819-97a8-26cc5977f118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976100672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3976100672
Directory /workspace/31.spi_device_intercept/latest


Test location /workspace/coverage/default/31.spi_device_mailbox.1336085204
Short name T800
Test name
Test status
Simulation time 483161927 ps
CPU time 12.09 seconds
Started Jun 29 06:50:03 PM PDT 24
Finished Jun 29 06:50:16 PM PDT 24
Peak memory 232632 kb
Host smart-381a406a-3b0e-4a2e-8979-045effd4c993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336085204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1336085204
Directory /workspace/31.spi_device_mailbox/latest


Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2665777420
Short name T543
Test name
Test status
Simulation time 8123452899 ps
CPU time 8.46 seconds
Started Jun 29 06:50:01 PM PDT 24
Finished Jun 29 06:50:11 PM PDT 24
Peak memory 232724 kb
Host smart-4fcc167b-3323-4f43-be83-a5d869034c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665777420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2665777420
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2585221519
Short name T857
Test name
Test status
Simulation time 2901525802 ps
CPU time 6.12 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:50:09 PM PDT 24
Peak memory 240604 kb
Host smart-86cfc6f3-1836-4d87-8350-eedb5b9d94bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585221519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2585221519
Directory /workspace/31.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2106150598
Short name T956
Test name
Test status
Simulation time 124899438 ps
CPU time 4.15 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:50:16 PM PDT 24
Peak memory 218880 kb
Host smart-42823c07-ba90-4e3c-bc85-2fef3a05ea6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2106150598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2106150598
Directory /workspace/31.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/31.spi_device_stress_all.536131313
Short name T272
Test name
Test status
Simulation time 91652677769 ps
CPU time 824.24 seconds
Started Jun 29 06:50:15 PM PDT 24
Finished Jun 29 07:04:00 PM PDT 24
Peak memory 259768 kb
Host smart-81538e09-f33b-4ea0-a087-45137f1fcb87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536131313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.536131313
Directory /workspace/31.spi_device_stress_all/latest


Test location /workspace/coverage/default/31.spi_device_tpm_all.1668377985
Short name T608
Test name
Test status
Simulation time 44648673 ps
CPU time 0.73 seconds
Started Jun 29 06:50:04 PM PDT 24
Finished Jun 29 06:50:05 PM PDT 24
Peak memory 205700 kb
Host smart-c75f15f2-438c-4e19-94fc-a294acbcec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668377985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1668377985
Directory /workspace/31.spi_device_tpm_all/latest


Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.670539356
Short name T405
Test name
Test status
Simulation time 1230935989 ps
CPU time 1.65 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:50:05 PM PDT 24
Peak memory 207852 kb
Host smart-725166f6-2af2-473f-9717-c0215ce1a70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670539356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.670539356
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/31.spi_device_tpm_rw.3084861622
Short name T881
Test name
Test status
Simulation time 308677376 ps
CPU time 1.34 seconds
Started Jun 29 06:50:05 PM PDT 24
Finished Jun 29 06:50:07 PM PDT 24
Peak memory 216192 kb
Host smart-08aa158a-94aa-471e-8653-81e4573197f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084861622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3084861622
Directory /workspace/31.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3625833531
Short name T781
Test name
Test status
Simulation time 13393260 ps
CPU time 0.73 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:50:04 PM PDT 24
Peak memory 205876 kb
Host smart-80758dac-7b9c-4999-bee3-eeec03f680e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625833531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3625833531
Directory /workspace/31.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/31.spi_device_upload.3341466800
Short name T430
Test name
Test status
Simulation time 10992895033 ps
CPU time 15.43 seconds
Started Jun 29 06:50:02 PM PDT 24
Finished Jun 29 06:50:19 PM PDT 24
Peak memory 232796 kb
Host smart-f8c7b3d1-3849-4cd6-98c5-2c3aeacf2040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341466800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3341466800
Directory /workspace/31.spi_device_upload/latest


Test location /workspace/coverage/default/32.spi_device_alert_test.3062895301
Short name T708
Test name
Test status
Simulation time 22763485 ps
CPU time 0.69 seconds
Started Jun 29 06:50:14 PM PDT 24
Finished Jun 29 06:50:15 PM PDT 24
Peak memory 204780 kb
Host smart-900246ba-7c17-4b94-8ffb-749226d857aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062895301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3062895301
Directory /workspace/32.spi_device_alert_test/latest


Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1629173192
Short name T410
Test name
Test status
Simulation time 5047720326 ps
CPU time 6.59 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:20 PM PDT 24
Peak memory 224636 kb
Host smart-33b9ce40-0cca-4e28-93be-c1e13f178162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629173192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1629173192
Directory /workspace/32.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/32.spi_device_csb_read.1232243711
Short name T353
Test name
Test status
Simulation time 78470990 ps
CPU time 0.86 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:50:14 PM PDT 24
Peak memory 206568 kb
Host smart-569f7d44-104d-4649-b363-5db6765cb372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232243711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1232243711
Directory /workspace/32.spi_device_csb_read/latest


Test location /workspace/coverage/default/32.spi_device_flash_all.3458419500
Short name T908
Test name
Test status
Simulation time 2160249303 ps
CPU time 15.62 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:29 PM PDT 24
Peak memory 234612 kb
Host smart-951b6385-3d93-4872-acec-6bd110787a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458419500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3458419500
Directory /workspace/32.spi_device_flash_all/latest


Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1870897298
Short name T260
Test name
Test status
Simulation time 39477828013 ps
CPU time 68.59 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:51:22 PM PDT 24
Peak memory 232856 kb
Host smart-a28f2f26-a3e1-4ba9-8885-29b15d949720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870897298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1870897298
Directory /workspace/32.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2337382673
Short name T452
Test name
Test status
Simulation time 15842569022 ps
CPU time 129.45 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:52:23 PM PDT 24
Peak memory 264724 kb
Host smart-ea548b7b-ab10-4f9a-afe2-557745466745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337382673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2337382673
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/32.spi_device_flash_mode.3685170440
Short name T284
Test name
Test status
Simulation time 10143436081 ps
CPU time 35.65 seconds
Started Jun 29 06:50:11 PM PDT 24
Finished Jun 29 06:50:47 PM PDT 24
Peak memory 232796 kb
Host smart-92fd06ea-fc55-4611-91c7-fc4d27db3870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685170440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3685170440
Directory /workspace/32.spi_device_flash_mode/latest


Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1089003228
Short name T1025
Test name
Test status
Simulation time 27100417793 ps
CPU time 210.82 seconds
Started Jun 29 06:50:14 PM PDT 24
Finished Jun 29 06:53:45 PM PDT 24
Peak memory 249392 kb
Host smart-376b3873-48f4-4a02-b391-907e2d901a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089003228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1089003228
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/32.spi_device_intercept.2939450353
Short name T834
Test name
Test status
Simulation time 106471434 ps
CPU time 2.05 seconds
Started Jun 29 06:50:15 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 223892 kb
Host smart-c6b13860-9b7e-4714-b9f5-067d92445eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939450353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2939450353
Directory /workspace/32.spi_device_intercept/latest


Test location /workspace/coverage/default/32.spi_device_mailbox.3127094443
Short name T811
Test name
Test status
Simulation time 1846159848 ps
CPU time 5.23 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:20 PM PDT 24
Peak memory 236996 kb
Host smart-ca92483d-46a3-4914-bba4-65285bea753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127094443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3127094443
Directory /workspace/32.spi_device_mailbox/latest


Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3252962379
Short name T412
Test name
Test status
Simulation time 66951826161 ps
CPU time 26.55 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:41 PM PDT 24
Peak memory 232760 kb
Host smart-bc5e1755-785c-4a6e-808e-b611694a609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252962379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3252962379
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4217033085
Short name T220
Test name
Test status
Simulation time 579995025 ps
CPU time 3.41 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 224444 kb
Host smart-4a83411c-18e1-425f-bdb7-18b77dc1d375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217033085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4217033085
Directory /workspace/32.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4171141814
Short name T564
Test name
Test status
Simulation time 1286631598 ps
CPU time 4.16 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 220192 kb
Host smart-0aa3da56-8f0d-4817-ac66-60a91b3e74ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4171141814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4171141814
Directory /workspace/32.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/32.spi_device_stress_all.2463608149
Short name T718
Test name
Test status
Simulation time 119020022531 ps
CPU time 139.63 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:52:33 PM PDT 24
Peak memory 249268 kb
Host smart-787cbef9-1dc4-4937-a525-c99cddcb7fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463608149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2463608149
Directory /workspace/32.spi_device_stress_all/latest


Test location /workspace/coverage/default/32.spi_device_tpm_all.2281167651
Short name T395
Test name
Test status
Simulation time 6056589590 ps
CPU time 33.68 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:50:46 PM PDT 24
Peak memory 216304 kb
Host smart-320ea3e7-b53c-4cd6-b4dd-0aa45236132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281167651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2281167651
Directory /workspace/32.spi_device_tpm_all/latest


Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.935455189
Short name T416
Test name
Test status
Simulation time 1047912879 ps
CPU time 6.79 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:50:19 PM PDT 24
Peak memory 216128 kb
Host smart-40d777bc-c635-4063-a903-a1d5346a4845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935455189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.935455189
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/32.spi_device_tpm_rw.2327419131
Short name T560
Test name
Test status
Simulation time 260582625 ps
CPU time 2.32 seconds
Started Jun 29 06:50:15 PM PDT 24
Finished Jun 29 06:50:17 PM PDT 24
Peak memory 216208 kb
Host smart-20e1bcf9-3bb1-475f-8bed-f341e5bd573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327419131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2327419131
Directory /workspace/32.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.137635879
Short name T774
Test name
Test status
Simulation time 321847524 ps
CPU time 0.91 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:50:13 PM PDT 24
Peak memory 205880 kb
Host smart-15015002-9c4e-4831-aaa2-b86aafb08239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137635879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.137635879
Directory /workspace/32.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/32.spi_device_upload.1841018416
Short name T533
Test name
Test status
Simulation time 12171350975 ps
CPU time 13.09 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:27 PM PDT 24
Peak memory 232800 kb
Host smart-abe9107b-6e62-44ee-baa5-32ecbaf8d00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841018416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1841018416
Directory /workspace/32.spi_device_upload/latest


Test location /workspace/coverage/default/33.spi_device_alert_test.2524900930
Short name T901
Test name
Test status
Simulation time 23397399 ps
CPU time 0.71 seconds
Started Jun 29 06:50:18 PM PDT 24
Finished Jun 29 06:50:19 PM PDT 24
Peak memory 204840 kb
Host smart-98bc9fa1-d816-4648-adbf-3da9b35227d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524900930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2524900930
Directory /workspace/33.spi_device_alert_test/latest


Test location /workspace/coverage/default/33.spi_device_cfg_cmd.706575062
Short name T915
Test name
Test status
Simulation time 227159208 ps
CPU time 3.81 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:17 PM PDT 24
Peak memory 224444 kb
Host smart-8c12beea-6791-443d-801d-2f0fc37d235d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706575062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.706575062
Directory /workspace/33.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/33.spi_device_csb_read.821413864
Short name T346
Test name
Test status
Simulation time 57274752 ps
CPU time 0.78 seconds
Started Jun 29 06:50:14 PM PDT 24
Finished Jun 29 06:50:15 PM PDT 24
Peak memory 206544 kb
Host smart-c94597d4-a5fc-435a-b5c5-cc8aacee6344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821413864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.821413864
Directory /workspace/33.spi_device_csb_read/latest


Test location /workspace/coverage/default/33.spi_device_flash_all.3110071250
Short name T828
Test name
Test status
Simulation time 285674687812 ps
CPU time 263.31 seconds
Started Jun 29 06:50:20 PM PDT 24
Finished Jun 29 06:54:44 PM PDT 24
Peak memory 249576 kb
Host smart-e9b684e1-d831-45f5-b6ab-13ae4fa5ef23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110071250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3110071250
Directory /workspace/33.spi_device_flash_all/latest


Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1710944132
Short name T730
Test name
Test status
Simulation time 21476166539 ps
CPU time 99.64 seconds
Started Jun 29 06:50:24 PM PDT 24
Finished Jun 29 06:52:04 PM PDT 24
Peak memory 257216 kb
Host smart-a4b8b79f-6176-4b7e-9997-649496d9f977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710944132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1710944132
Directory /workspace/33.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3496004520
Short name T199
Test name
Test status
Simulation time 48981154772 ps
CPU time 203.92 seconds
Started Jun 29 06:50:24 PM PDT 24
Finished Jun 29 06:53:49 PM PDT 24
Peak memory 266408 kb
Host smart-97a78e0e-abbf-40e5-84c4-58fe093956c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496004520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3496004520
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/33.spi_device_flash_mode.3992579208
Short name T443
Test name
Test status
Simulation time 117072360 ps
CPU time 2.99 seconds
Started Jun 29 06:50:15 PM PDT 24
Finished Jun 29 06:50:18 PM PDT 24
Peak memory 232676 kb
Host smart-20e4d862-d09a-44c4-a0af-831c6fd9148a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992579208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3992579208
Directory /workspace/33.spi_device_flash_mode/latest


Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.4229607056
Short name T1010
Test name
Test status
Simulation time 11840240757 ps
CPU time 106.98 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:52:01 PM PDT 24
Peak memory 251196 kb
Host smart-2da7bb8d-8599-4b8f-80b0-5fdd00576126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229607056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.4229607056
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/33.spi_device_intercept.4176526792
Short name T361
Test name
Test status
Simulation time 32601608 ps
CPU time 2.36 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:16 PM PDT 24
Peak memory 232388 kb
Host smart-67329a03-3938-49cb-b4dc-aaadb72879c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176526792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4176526792
Directory /workspace/33.spi_device_intercept/latest


Test location /workspace/coverage/default/33.spi_device_mailbox.232168660
Short name T256
Test name
Test status
Simulation time 11163963554 ps
CPU time 30.79 seconds
Started Jun 29 06:50:10 PM PDT 24
Finished Jun 29 06:50:42 PM PDT 24
Peak memory 233780 kb
Host smart-421632be-a30c-4223-a744-c9b0ffef3d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232168660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.232168660
Directory /workspace/33.spi_device_mailbox/latest


Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1695790535
Short name T932
Test name
Test status
Simulation time 418872294 ps
CPU time 5.8 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:50:19 PM PDT 24
Peak memory 232636 kb
Host smart-bebce688-feda-4a2f-8d10-9a63bcc7d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695790535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1695790535
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.162386863
Short name T455
Test name
Test status
Simulation time 2208487650 ps
CPU time 7.41 seconds
Started Jun 29 06:50:14 PM PDT 24
Finished Jun 29 06:50:22 PM PDT 24
Peak memory 224508 kb
Host smart-9bc1bf33-2579-470c-81c5-d6577009163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162386863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.162386863
Directory /workspace/33.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2672586785
Short name T838
Test name
Test status
Simulation time 1541270516 ps
CPU time 5.5 seconds
Started Jun 29 06:50:25 PM PDT 24
Finished Jun 29 06:50:31 PM PDT 24
Peak memory 219464 kb
Host smart-7b0b21c2-8b1c-4219-96b0-23f074771601
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2672586785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2672586785
Directory /workspace/33.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/33.spi_device_tpm_all.2732965825
Short name T307
Test name
Test status
Simulation time 460367651 ps
CPU time 2.54 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:16 PM PDT 24
Peak memory 216400 kb
Host smart-d545b7c6-7b65-4a10-b0b4-f738d16042f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732965825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2732965825
Directory /workspace/33.spi_device_tpm_all/latest


Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1907507065
Short name T529
Test name
Test status
Simulation time 13488715769 ps
CPU time 8.75 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:22 PM PDT 24
Peak memory 217464 kb
Host smart-ee0e945d-0a26-46d1-9970-b707edadb69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907507065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1907507065
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/33.spi_device_tpm_rw.2065129319
Short name T47
Test name
Test status
Simulation time 60152500 ps
CPU time 1.36 seconds
Started Jun 29 06:50:10 PM PDT 24
Finished Jun 29 06:50:12 PM PDT 24
Peak memory 216180 kb
Host smart-07c4310c-590b-4d5b-975c-c7e3153a709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065129319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2065129319
Directory /workspace/33.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2409701838
Short name T554
Test name
Test status
Simulation time 98777405 ps
CPU time 0.79 seconds
Started Jun 29 06:50:13 PM PDT 24
Finished Jun 29 06:50:15 PM PDT 24
Peak memory 205816 kb
Host smart-b19484fc-21ff-40c1-bb09-0c96e2a8c2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409701838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2409701838
Directory /workspace/33.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/33.spi_device_upload.2516528137
Short name T131
Test name
Test status
Simulation time 3931084247 ps
CPU time 11.89 seconds
Started Jun 29 06:50:12 PM PDT 24
Finished Jun 29 06:50:24 PM PDT 24
Peak memory 224588 kb
Host smart-256cc6ae-e4ef-471a-89d7-3c7da849944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516528137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2516528137
Directory /workspace/33.spi_device_upload/latest


Test location /workspace/coverage/default/34.spi_device_alert_test.4031214330
Short name T477
Test name
Test status
Simulation time 17931431 ps
CPU time 0.71 seconds
Started Jun 29 06:50:19 PM PDT 24
Finished Jun 29 06:50:21 PM PDT 24
Peak memory 205372 kb
Host smart-d748774f-ae57-4188-95f0-907c457d5eac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031214330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4031214330
Directory /workspace/34.spi_device_alert_test/latest


Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2041640765
Short name T661
Test name
Test status
Simulation time 174055157 ps
CPU time 2.61 seconds
Started Jun 29 06:50:20 PM PDT 24
Finished Jun 29 06:50:23 PM PDT 24
Peak memory 232616 kb
Host smart-b1fd3b98-894d-4e66-a413-696ccbf71500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041640765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2041640765
Directory /workspace/34.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/34.spi_device_csb_read.4290142289
Short name T819
Test name
Test status
Simulation time 14231687 ps
CPU time 0.77 seconds
Started Jun 29 06:50:21 PM PDT 24
Finished Jun 29 06:50:23 PM PDT 24
Peak memory 206556 kb
Host smart-7f249078-c6de-4ecc-b582-dd68b51e3811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290142289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4290142289
Directory /workspace/34.spi_device_csb_read/latest


Test location /workspace/coverage/default/34.spi_device_flash_all.1047312844
Short name T830
Test name
Test status
Simulation time 2009404187 ps
CPU time 44.64 seconds
Started Jun 29 06:50:25 PM PDT 24
Finished Jun 29 06:51:10 PM PDT 24
Peak memory 240924 kb
Host smart-5731494b-ca44-4660-89e3-ddec824fe6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047312844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1047312844
Directory /workspace/34.spi_device_flash_all/latest


Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2660136133
Short name T130
Test name
Test status
Simulation time 273219048382 ps
CPU time 628.01 seconds
Started Jun 29 06:50:24 PM PDT 24
Finished Jun 29 07:00:53 PM PDT 24
Peak memory 264292 kb
Host smart-7222a37a-735c-4aa9-86fc-ecaaa22a912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660136133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2660136133
Directory /workspace/34.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2579970291
Short name T367
Test name
Test status
Simulation time 8316807080 ps
CPU time 44.64 seconds
Started Jun 29 06:50:19 PM PDT 24
Finished Jun 29 06:51:04 PM PDT 24
Peak memory 237940 kb
Host smart-6b968a08-7241-441d-9879-5b0bfa01060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579970291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2579970291
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/34.spi_device_flash_mode.1194649003
Short name T580
Test name
Test status
Simulation time 657657731 ps
CPU time 7.95 seconds
Started Jun 29 06:50:19 PM PDT 24
Finished Jun 29 06:50:27 PM PDT 24
Peak memory 240868 kb
Host smart-672ffd1b-6afa-45b9-8039-0ad8880b58da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194649003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1194649003
Directory /workspace/34.spi_device_flash_mode/latest


Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.4249995648
Short name T821
Test name
Test status
Simulation time 798342664 ps
CPU time 11.92 seconds
Started Jun 29 06:50:22 PM PDT 24
Finished Jun 29 06:50:34 PM PDT 24
Peak memory 248520 kb
Host smart-32b8c3d3-6305-4d65-bfd6-3943fbe812d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249995648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.4249995648
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/34.spi_device_intercept.4087027250
Short name T86
Test name
Test status
Simulation time 2246124191 ps
CPU time 7.14 seconds
Started Jun 29 06:50:21 PM PDT 24
Finished Jun 29 06:50:28 PM PDT 24
Peak memory 224484 kb
Host smart-f84d8b85-94d9-4aef-b328-aafe17a90374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087027250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4087027250
Directory /workspace/34.spi_device_intercept/latest


Test location /workspace/coverage/default/34.spi_device_mailbox.15670407
Short name T435
Test name
Test status
Simulation time 9793107806 ps
CPU time 26 seconds
Started Jun 29 06:50:21 PM PDT 24
Finished Jun 29 06:50:48 PM PDT 24
Peak memory 249768 kb
Host smart-4ac41978-638d-46ed-809f-8e93cdba7733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15670407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.15670407
Directory /workspace/34.spi_device_mailbox/latest


Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2734064582
Short name T385
Test name
Test status
Simulation time 3219540831 ps
CPU time 15.19 seconds
Started Jun 29 06:50:21 PM PDT 24
Finished Jun 29 06:50:37 PM PDT 24
Peak memory 232824 kb
Host smart-f71a5362-eda7-4272-b181-9633c569a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734064582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2734064582
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2929997718
Short name T963
Test name
Test status
Simulation time 1027372416 ps
CPU time 4.59 seconds
Started Jun 29 06:50:23 PM PDT 24
Finished Jun 29 06:50:28 PM PDT 24
Peak memory 224452 kb
Host smart-8610ab80-7f82-4fbd-81a4-1c710874f223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929997718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2929997718
Directory /workspace/34.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.726983994
Short name T364
Test name
Test status
Simulation time 1117723359 ps
CPU time 12.12 seconds
Started Jun 29 06:50:21 PM PDT 24
Finished Jun 29 06:50:33 PM PDT 24
Peak memory 222052 kb
Host smart-b8e19e72-5635-4413-ba83-f47a4ad94ee5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=726983994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.726983994
Directory /workspace/34.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/34.spi_device_stress_all.360502192
Short name T693
Test name
Test status
Simulation time 2480023094 ps
CPU time 59.37 seconds
Started Jun 29 06:50:22 PM PDT 24
Finished Jun 29 06:51:22 PM PDT 24
Peak memory 249252 kb
Host smart-7f161a29-aa53-4f5f-a24d-ee47defff8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360502192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.360502192
Directory /workspace/34.spi_device_stress_all/latest


Test location /workspace/coverage/default/34.spi_device_tpm_all.1850551162
Short name T926
Test name
Test status
Simulation time 3219439913 ps
CPU time 11.76 seconds
Started Jun 29 06:50:23 PM PDT 24
Finished Jun 29 06:50:35 PM PDT 24
Peak memory 216316 kb
Host smart-f940d8de-b896-4ef0-92ac-cf09a3c7e089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850551162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1850551162
Directory /workspace/34.spi_device_tpm_all/latest


Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.375428554
Short name T26
Test name
Test status
Simulation time 3740285289 ps
CPU time 3.41 seconds
Started Jun 29 06:50:19 PM PDT 24
Finished Jun 29 06:50:23 PM PDT 24
Peak memory 216344 kb
Host smart-355e69df-c17e-4a54-8ac8-72a30f20a868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375428554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.375428554
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/34.spi_device_tpm_rw.4214799617
Short name T304
Test name
Test status
Simulation time 116865537 ps
CPU time 1.62 seconds
Started Jun 29 06:50:20 PM PDT 24
Finished Jun 29 06:50:22 PM PDT 24
Peak memory 216216 kb
Host smart-75436356-646a-4e43-9576-7c18bcaab55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214799617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4214799617
Directory /workspace/34.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1620954793
Short name T798
Test name
Test status
Simulation time 79786942 ps
CPU time 0.88 seconds
Started Jun 29 06:50:23 PM PDT 24
Finished Jun 29 06:50:24 PM PDT 24
Peak memory 205884 kb
Host smart-bc7fdf10-aa38-43c1-b451-00a55c08bc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620954793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1620954793
Directory /workspace/34.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/34.spi_device_upload.104729420
Short name T510
Test name
Test status
Simulation time 17586989586 ps
CPU time 29.83 seconds
Started Jun 29 06:50:23 PM PDT 24
Finished Jun 29 06:50:54 PM PDT 24
Peak memory 232712 kb
Host smart-e82e442b-c296-4146-8cfd-7c107464f6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104729420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.104729420
Directory /workspace/34.spi_device_upload/latest


Test location /workspace/coverage/default/35.spi_device_alert_test.518928989
Short name T786
Test name
Test status
Simulation time 70799663 ps
CPU time 0.71 seconds
Started Jun 29 06:50:21 PM PDT 24
Finished Jun 29 06:50:22 PM PDT 24
Peak memory 205396 kb
Host smart-7c3b1430-8bd9-4176-ad14-48c6a6706a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518928989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.518928989
Directory /workspace/35.spi_device_alert_test/latest


Test location /workspace/coverage/default/35.spi_device_cfg_cmd.646046842
Short name T546
Test name
Test status
Simulation time 4139386558 ps
CPU time 4.32 seconds
Started Jun 29 06:50:25 PM PDT 24
Finished Jun 29 06:50:30 PM PDT 24
Peak memory 224044 kb
Host smart-4894c73b-0200-4e2c-8716-4e3fa4f66637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646046842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.646046842
Directory /workspace/35.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/35.spi_device_csb_read.4015479196
Short name T349
Test name
Test status
Simulation time 44429035 ps
CPU time 0.77 seconds
Started Jun 29 06:50:19 PM PDT 24
Finished Jun 29 06:50:20 PM PDT 24
Peak memory 206564 kb
Host smart-cebf0169-077b-4739-9ac9-b54c5d5ea5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015479196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4015479196
Directory /workspace/35.spi_device_csb_read/latest


Test location /workspace/coverage/default/35.spi_device_flash_all.3759575712
Short name T952
Test name
Test status
Simulation time 2518553882 ps
CPU time 59.12 seconds
Started Jun 29 06:50:21 PM PDT 24
Finished Jun 29 06:51:20 PM PDT 24
Peak memory 271972 kb
Host smart-1b943708-b970-42b5-b6fa-4881b1aa1f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759575712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3759575712
Directory /workspace/35.spi_device_flash_all/latest


Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3802173751
Short name T484
Test name
Test status
Simulation time 1492886789 ps
CPU time 36.93 seconds
Started Jun 29 06:50:20 PM PDT 24
Finished Jun 29 06:50:58 PM PDT 24
Peak memory 249212 kb
Host smart-f086bff9-6393-421a-a6a2-07a47f81d749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802173751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3802173751
Directory /workspace/35.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4007265573
Short name T870
Test name
Test status
Simulation time 25896046732 ps
CPU time 138.12 seconds
Started Jun 29 06:50:24 PM PDT 24
Finished Jun 29 06:52:43 PM PDT 24
Peak memory 255708 kb
Host smart-0faf2bb1-722f-46ca-ba85-e3e2e6df5a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007265573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4007265573
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1850754246
Short name T984
Test name
Test status
Simulation time 3654205518 ps
CPU time 31.82 seconds
Started Jun 29 06:50:21 PM PDT 24
Finished Jun 29 06:50:53 PM PDT 24
Peak memory 233108 kb
Host smart-a61f6ac6-0a8a-45c3-a0e6-824fbbf5ca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850754246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1850754246
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/35.spi_device_intercept.2822691675
Short name T584
Test name
Test status
Simulation time 1721552517 ps
CPU time 9.35 seconds
Started Jun 29 06:50:19 PM PDT 24
Finished Jun 29 06:50:29 PM PDT 24
Peak memory 224440 kb
Host smart-6283a1d4-2075-481f-bbd3-0f64a71ac511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822691675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2822691675
Directory /workspace/35.spi_device_intercept/latest


Test location /workspace/coverage/default/35.spi_device_mailbox.919225394
Short name T991
Test name
Test status
Simulation time 28689823309 ps
CPU time 41.34 seconds
Started Jun 29 06:50:18 PM PDT 24
Finished Jun 29 06:51:00 PM PDT 24
Peak memory 232720 kb
Host smart-23d58bc9-f37d-40b2-8add-540f27db7c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919225394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.919225394
Directory /workspace/35.spi_device_mailbox/latest


Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.233038721
Short name T855
Test name
Test status
Simulation time 1937127218 ps
CPU time 2.47 seconds
Started Jun 29 06:50:18 PM PDT 24
Finished Jun 29 06:50:21 PM PDT 24
Peak memory 224436 kb
Host smart-ecd1cd5c-8c06-4fc1-b5b3-ceb22658ffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233038721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.233038721
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3506791647
Short name T189
Test name
Test status
Simulation time 1197181985 ps
CPU time 4.05 seconds
Started Jun 29 06:50:23 PM PDT 24
Finished Jun 29 06:50:28 PM PDT 24
Peak memory 232632 kb
Host smart-ca96d11d-de5f-4f62-a662-604cb8ba94b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506791647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3506791647
Directory /workspace/35.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3908371975
Short name T483
Test name
Test status
Simulation time 25978420311 ps
CPU time 13.76 seconds
Started Jun 29 06:50:23 PM PDT 24
Finished Jun 29 06:50:38 PM PDT 24
Peak memory 222976 kb
Host smart-408e2a91-f31e-482e-916b-fcc81066f70d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3908371975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3908371975
Directory /workspace/35.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/35.spi_device_tpm_all.4194622346
Short name T739
Test name
Test status
Simulation time 725543920 ps
CPU time 2.55 seconds
Started Jun 29 06:50:20 PM PDT 24
Finished Jun 29 06:50:23 PM PDT 24
Peak memory 216192 kb
Host smart-f9cc1864-0d7d-43ef-b129-7c7d95894f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194622346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4194622346
Directory /workspace/35.spi_device_tpm_all/latest


Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.676115997
Short name T621
Test name
Test status
Simulation time 4216059695 ps
CPU time 6.94 seconds
Started Jun 29 06:50:22 PM PDT 24
Finished Jun 29 06:50:30 PM PDT 24
Peak memory 216316 kb
Host smart-943e7d18-94ee-493b-87ba-3526997cad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676115997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.676115997
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/35.spi_device_tpm_rw.782557349
Short name T851
Test name
Test status
Simulation time 209968061 ps
CPU time 1.02 seconds
Started Jun 29 06:50:25 PM PDT 24
Finished Jun 29 06:50:26 PM PDT 24
Peak memory 207040 kb
Host smart-bf099ba3-4a1f-4c7d-a023-bac292532af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782557349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.782557349
Directory /workspace/35.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2993101122
Short name T868
Test name
Test status
Simulation time 13602788 ps
CPU time 0.7 seconds
Started Jun 29 06:50:22 PM PDT 24
Finished Jun 29 06:50:23 PM PDT 24
Peak memory 205560 kb
Host smart-a3d9a62f-ec0d-4406-b003-eb2f7c0aad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993101122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2993101122
Directory /workspace/35.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/35.spi_device_upload.2952169023
Short name T999
Test name
Test status
Simulation time 2897736481 ps
CPU time 16.33 seconds
Started Jun 29 06:50:24 PM PDT 24
Finished Jun 29 06:50:41 PM PDT 24
Peak memory 224580 kb
Host smart-1fd2cf1b-e69f-4da6-9a33-396ea9404d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952169023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2952169023
Directory /workspace/35.spi_device_upload/latest


Test location /workspace/coverage/default/36.spi_device_alert_test.1636325636
Short name T687
Test name
Test status
Simulation time 13266886 ps
CPU time 0.7 seconds
Started Jun 29 06:50:29 PM PDT 24
Finished Jun 29 06:50:31 PM PDT 24
Peak memory 205412 kb
Host smart-378a529e-5c65-4d04-934f-fb662dead94e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636325636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1636325636
Directory /workspace/36.spi_device_alert_test/latest


Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3913863523
Short name T539
Test name
Test status
Simulation time 482845830 ps
CPU time 3.74 seconds
Started Jun 29 06:50:28 PM PDT 24
Finished Jun 29 06:50:32 PM PDT 24
Peak memory 224444 kb
Host smart-7f74093f-6ca7-4833-9b09-13b05b673eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913863523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3913863523
Directory /workspace/36.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/36.spi_device_csb_read.1242078285
Short name T1000
Test name
Test status
Simulation time 26153944 ps
CPU time 0.82 seconds
Started Jun 29 06:50:25 PM PDT 24
Finished Jun 29 06:50:26 PM PDT 24
Peak memory 206564 kb
Host smart-b7155ea8-18db-4f82-ab0a-d74f59a35612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242078285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1242078285
Directory /workspace/36.spi_device_csb_read/latest


Test location /workspace/coverage/default/36.spi_device_flash_all.3299357248
Short name T44
Test name
Test status
Simulation time 111953781416 ps
CPU time 230.19 seconds
Started Jun 29 06:50:29 PM PDT 24
Finished Jun 29 06:54:20 PM PDT 24
Peak memory 264108 kb
Host smart-86265341-c6ef-4de6-beef-d122aaed8077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299357248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3299357248
Directory /workspace/36.spi_device_flash_all/latest


Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1383176065
Short name T297
Test name
Test status
Simulation time 29209671475 ps
CPU time 113.05 seconds
Started Jun 29 06:50:28 PM PDT 24
Finished Jun 29 06:52:22 PM PDT 24
Peak memory 253536 kb
Host smart-0f118289-40f9-4ece-bf91-5c36c95f2f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383176065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1383176065
Directory /workspace/36.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4173367627
Short name T78
Test name
Test status
Simulation time 25739104733 ps
CPU time 108.41 seconds
Started Jun 29 06:50:33 PM PDT 24
Finished Jun 29 06:52:22 PM PDT 24
Peak memory 253352 kb
Host smart-78b65fcf-4191-4b6c-a586-19acd8fe4c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173367627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4173367627
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/36.spi_device_flash_mode.3986334241
Short name T329
Test name
Test status
Simulation time 605159054 ps
CPU time 4.32 seconds
Started Jun 29 06:50:28 PM PDT 24
Finished Jun 29 06:50:33 PM PDT 24
Peak memory 224484 kb
Host smart-1a3b54f7-844f-4255-958f-a6ab297e07ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986334241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3986334241
Directory /workspace/36.spi_device_flash_mode/latest


Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1033720626
Short name T230
Test name
Test status
Simulation time 17006316311 ps
CPU time 119.69 seconds
Started Jun 29 06:50:28 PM PDT 24
Finished Jun 29 06:52:29 PM PDT 24
Peak memory 249500 kb
Host smart-9e2647f9-edaa-40c9-bcd1-fc9e17293efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033720626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1033720626
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/36.spi_device_intercept.663511847
Short name T103
Test name
Test status
Simulation time 113780356 ps
CPU time 2.15 seconds
Started Jun 29 06:50:32 PM PDT 24
Finished Jun 29 06:50:34 PM PDT 24
Peak memory 232416 kb
Host smart-97ee5f69-5afd-424b-9178-9ea19eb24cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663511847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.663511847
Directory /workspace/36.spi_device_intercept/latest


Test location /workspace/coverage/default/36.spi_device_mailbox.3316522838
Short name T799
Test name
Test status
Simulation time 660271356 ps
CPU time 5.06 seconds
Started Jun 29 06:50:29 PM PDT 24
Finished Jun 29 06:50:35 PM PDT 24
Peak memory 232672 kb
Host smart-85dce1e6-19b5-45a8-a3e7-bbf25a11f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316522838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3316522838
Directory /workspace/36.spi_device_mailbox/latest


Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2472222356
Short name T859
Test name
Test status
Simulation time 3182530542 ps
CPU time 6.32 seconds
Started Jun 29 06:50:32 PM PDT 24
Finished Jun 29 06:50:39 PM PDT 24
Peak memory 233860 kb
Host smart-7aab3cd8-abec-4871-a5c4-af8d1f1287e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472222356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2472222356
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.625466494
Short name T167
Test name
Test status
Simulation time 23575564596 ps
CPU time 17.94 seconds
Started Jun 29 06:50:33 PM PDT 24
Finished Jun 29 06:50:52 PM PDT 24
Peak memory 224592 kb
Host smart-3c0146d2-5e08-495f-ad5d-d284b73ac39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625466494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.625466494
Directory /workspace/36.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.866535120
Short name T145
Test name
Test status
Simulation time 1331314968 ps
CPU time 18.25 seconds
Started Jun 29 06:50:29 PM PDT 24
Finished Jun 29 06:50:47 PM PDT 24
Peak memory 220368 kb
Host smart-e8f72d61-a51d-44cb-976f-a18303cfe8d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=866535120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.866535120
Directory /workspace/36.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/36.spi_device_stress_all.2221616806
Short name T885
Test name
Test status
Simulation time 113702309 ps
CPU time 1 seconds
Started Jun 29 06:50:30 PM PDT 24
Finished Jun 29 06:50:31 PM PDT 24
Peak memory 206680 kb
Host smart-50805a2a-37df-46a2-be2d-28ebc1f7ef1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221616806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2221616806
Directory /workspace/36.spi_device_stress_all/latest


Test location /workspace/coverage/default/36.spi_device_tpm_all.2714848307
Short name T625
Test name
Test status
Simulation time 2306948999 ps
CPU time 9 seconds
Started Jun 29 06:50:27 PM PDT 24
Finished Jun 29 06:50:36 PM PDT 24
Peak memory 216348 kb
Host smart-ab4b2169-d60a-49cd-b223-8a19b54064fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714848307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2714848307
Directory /workspace/36.spi_device_tpm_all/latest


Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3656613017
Short name T782
Test name
Test status
Simulation time 14846624760 ps
CPU time 18.85 seconds
Started Jun 29 06:50:21 PM PDT 24
Finished Jun 29 06:50:40 PM PDT 24
Peak memory 216284 kb
Host smart-e68a6e34-0590-4287-b994-68878744a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656613017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3656613017
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/36.spi_device_tpm_rw.1097029531
Short name T676
Test name
Test status
Simulation time 2791757952 ps
CPU time 5.13 seconds
Started Jun 29 06:50:29 PM PDT 24
Finished Jun 29 06:50:35 PM PDT 24
Peak memory 216260 kb
Host smart-6f18f851-fe6b-411d-834c-7b2259c349a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097029531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1097029531
Directory /workspace/36.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1202791298
Short name T845
Test name
Test status
Simulation time 212707904 ps
CPU time 0.9 seconds
Started Jun 29 06:50:28 PM PDT 24
Finished Jun 29 06:50:29 PM PDT 24
Peak memory 206908 kb
Host smart-17efba72-9c38-4335-99c1-395cb1c1608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202791298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1202791298
Directory /workspace/36.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/36.spi_device_upload.982620424
Short name T945
Test name
Test status
Simulation time 720243162 ps
CPU time 4.49 seconds
Started Jun 29 06:50:29 PM PDT 24
Finished Jun 29 06:50:34 PM PDT 24
Peak memory 232648 kb
Host smart-a8416d46-62a0-401f-8347-fe8cca4764e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982620424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.982620424
Directory /workspace/36.spi_device_upload/latest


Test location /workspace/coverage/default/37.spi_device_alert_test.796431335
Short name T1018
Test name
Test status
Simulation time 44545972 ps
CPU time 0.68 seconds
Started Jun 29 06:50:33 PM PDT 24
Finished Jun 29 06:50:34 PM PDT 24
Peak memory 204840 kb
Host smart-d15dfcda-284e-4714-b5e5-25091bde922b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796431335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.796431335
Directory /workspace/37.spi_device_alert_test/latest


Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2414123383
Short name T681
Test name
Test status
Simulation time 92522219 ps
CPU time 3.38 seconds
Started Jun 29 06:50:30 PM PDT 24
Finished Jun 29 06:50:34 PM PDT 24
Peak memory 232632 kb
Host smart-6ef58084-d5e8-48fe-920f-4070f9135b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414123383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2414123383
Directory /workspace/37.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/37.spi_device_csb_read.528606855
Short name T947
Test name
Test status
Simulation time 25729567 ps
CPU time 0.75 seconds
Started Jun 29 06:50:30 PM PDT 24
Finished Jun 29 06:50:31 PM PDT 24
Peak memory 206568 kb
Host smart-3de8b986-028f-4e34-8bd2-d6b4c8812aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528606855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.528606855
Directory /workspace/37.spi_device_csb_read/latest


Test location /workspace/coverage/default/37.spi_device_flash_all.405491805
Short name T73
Test name
Test status
Simulation time 103532482544 ps
CPU time 178.64 seconds
Started Jun 29 06:50:32 PM PDT 24
Finished Jun 29 06:53:31 PM PDT 24
Peak memory 257340 kb
Host smart-532f4a0b-f09d-43c3-9839-a5bb55ba7043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405491805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.405491805
Directory /workspace/37.spi_device_flash_all/latest


Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1052995446
Short name T269
Test name
Test status
Simulation time 46909295152 ps
CPU time 141.28 seconds
Started Jun 29 06:50:28 PM PDT 24
Finished Jun 29 06:52:50 PM PDT 24
Peak memory 267108 kb
Host smart-0e3ef923-1524-48de-90dd-ee0c5e633ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052995446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1052995446
Directory /workspace/37.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4138326861
Short name T900
Test name
Test status
Simulation time 108734769885 ps
CPU time 309.22 seconds
Started Jun 29 06:50:29 PM PDT 24
Finished Jun 29 06:55:39 PM PDT 24
Peak memory 264584 kb
Host smart-7f6dddf2-2574-4680-ab77-656fad4518ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138326861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4138326861
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/37.spi_device_flash_mode.1041571489
Short name T1016
Test name
Test status
Simulation time 1205745347 ps
CPU time 5.83 seconds
Started Jun 29 06:50:27 PM PDT 24
Finished Jun 29 06:50:33 PM PDT 24
Peak memory 224508 kb
Host smart-97bbe8d8-1d92-45c2-985d-b05803aaa4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041571489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1041571489
Directory /workspace/37.spi_device_flash_mode/latest


Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2385460346
Short name T369
Test name
Test status
Simulation time 4688196725 ps
CPU time 60.51 seconds
Started Jun 29 06:50:32 PM PDT 24
Finished Jun 29 06:51:33 PM PDT 24
Peak memory 253252 kb
Host smart-e2d8998b-e192-419b-8fa2-ac9a63d67e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385460346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2385460346
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/37.spi_device_intercept.2948228643
Short name T90
Test name
Test status
Simulation time 899024104 ps
CPU time 3.15 seconds
Started Jun 29 06:50:30 PM PDT 24
Finished Jun 29 06:50:33 PM PDT 24
Peak memory 224444 kb
Host smart-5257ecda-cd25-4a43-81ea-ef87282e4bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948228643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2948228643
Directory /workspace/37.spi_device_intercept/latest


Test location /workspace/coverage/default/37.spi_device_mailbox.1448622796
Short name T91
Test name
Test status
Simulation time 49058231235 ps
CPU time 42.09 seconds
Started Jun 29 06:50:31 PM PDT 24
Finished Jun 29 06:51:13 PM PDT 24
Peak memory 232752 kb
Host smart-c884fbdc-a456-4a0d-a4e8-efe38b9a148a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448622796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1448622796
Directory /workspace/37.spi_device_mailbox/latest


Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1165309670
Short name T209
Test name
Test status
Simulation time 1301578720 ps
CPU time 6.13 seconds
Started Jun 29 06:50:30 PM PDT 24
Finished Jun 29 06:50:37 PM PDT 24
Peak memory 224428 kb
Host smart-ecfc666a-6618-412e-98ed-0bf98243e00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165309670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1165309670
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.903600692
Short name T393
Test name
Test status
Simulation time 8134546612 ps
CPU time 13.38 seconds
Started Jun 29 06:50:33 PM PDT 24
Finished Jun 29 06:50:47 PM PDT 24
Peak memory 224504 kb
Host smart-db9515f4-31fd-474b-8a29-15dc67854672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903600692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.903600692
Directory /workspace/37.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2352419004
Short name T619
Test name
Test status
Simulation time 3359898786 ps
CPU time 17.28 seconds
Started Jun 29 06:50:32 PM PDT 24
Finished Jun 29 06:50:50 PM PDT 24
Peak memory 222128 kb
Host smart-4427229c-63dd-471e-88be-caf6779724dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2352419004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2352419004
Directory /workspace/37.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/37.spi_device_stress_all.2558674622
Short name T134
Test name
Test status
Simulation time 75669403 ps
CPU time 1.21 seconds
Started Jun 29 06:50:29 PM PDT 24
Finished Jun 29 06:50:31 PM PDT 24
Peak memory 206860 kb
Host smart-c2d05388-45a4-45d1-97ef-0f8a0ee2b8fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558674622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2558674622
Directory /workspace/37.spi_device_stress_all/latest


Test location /workspace/coverage/default/37.spi_device_tpm_all.749572125
Short name T348
Test name
Test status
Simulation time 469557704 ps
CPU time 2.59 seconds
Started Jun 29 06:50:27 PM PDT 24
Finished Jun 29 06:50:30 PM PDT 24
Peak memory 216360 kb
Host smart-db5827d7-e9d2-46d4-b7a5-ab47d4d2fdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749572125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.749572125
Directory /workspace/37.spi_device_tpm_all/latest


Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2157450080
Short name T380
Test name
Test status
Simulation time 1954719630 ps
CPU time 3.54 seconds
Started Jun 29 06:50:30 PM PDT 24
Finished Jun 29 06:50:34 PM PDT 24
Peak memory 216144 kb
Host smart-6d62f8e9-707b-405c-bf81-5d7c43509cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157450080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2157450080
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/37.spi_device_tpm_rw.3865271988
Short name T330
Test name
Test status
Simulation time 30014846 ps
CPU time 0.81 seconds
Started Jun 29 06:50:33 PM PDT 24
Finished Jun 29 06:50:35 PM PDT 24
Peak memory 205888 kb
Host smart-0477aa5b-08ab-4d13-bf37-1233a79e68ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865271988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3865271988
Directory /workspace/37.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1493855947
Short name T318
Test name
Test status
Simulation time 219198468 ps
CPU time 1.04 seconds
Started Jun 29 06:50:28 PM PDT 24
Finished Jun 29 06:50:30 PM PDT 24
Peak memory 206908 kb
Host smart-d38efed8-8001-47bb-9d85-b5f6238a3915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493855947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1493855947
Directory /workspace/37.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/37.spi_device_upload.992413743
Short name T336
Test name
Test status
Simulation time 8935237951 ps
CPU time 15.89 seconds
Started Jun 29 06:50:28 PM PDT 24
Finished Jun 29 06:50:45 PM PDT 24
Peak memory 232800 kb
Host smart-df892ec4-019b-4d9e-a441-a99121e5b854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992413743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.992413743
Directory /workspace/37.spi_device_upload/latest


Test location /workspace/coverage/default/38.spi_device_alert_test.1863275286
Short name T784
Test name
Test status
Simulation time 45840149 ps
CPU time 0.68 seconds
Started Jun 29 06:50:42 PM PDT 24
Finished Jun 29 06:50:43 PM PDT 24
Peak memory 204836 kb
Host smart-e6a6f683-01f9-481f-b427-4d880e257075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863275286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1863275286
Directory /workspace/38.spi_device_alert_test/latest


Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4089261443
Short name T184
Test name
Test status
Simulation time 122573517 ps
CPU time 3.38 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:50:45 PM PDT 24
Peak memory 232688 kb
Host smart-bf95106c-ccd2-4f4d-8e0a-ffb9fe7baeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089261443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4089261443
Directory /workspace/38.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/38.spi_device_csb_read.2823929103
Short name T481
Test name
Test status
Simulation time 16298010 ps
CPU time 0.81 seconds
Started Jun 29 06:50:28 PM PDT 24
Finished Jun 29 06:50:30 PM PDT 24
Peak memory 206800 kb
Host smart-94ce1aa6-7139-4a3b-b499-a4b0430e17f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823929103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2823929103
Directory /workspace/38.spi_device_csb_read/latest


Test location /workspace/coverage/default/38.spi_device_flash_all.1448147428
Short name T212
Test name
Test status
Simulation time 721702961 ps
CPU time 13.9 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:50:56 PM PDT 24
Peak memory 235744 kb
Host smart-8664a989-fda5-46a3-aadc-bfd366c8ff27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448147428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1448147428
Directory /workspace/38.spi_device_flash_all/latest


Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1581043544
Short name T519
Test name
Test status
Simulation time 2669326447 ps
CPU time 14.54 seconds
Started Jun 29 06:50:43 PM PDT 24
Finished Jun 29 06:50:58 PM PDT 24
Peak memory 217628 kb
Host smart-20a7052c-df4c-4f66-9690-c020deb9b314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581043544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1581043544
Directory /workspace/38.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.986195424
Short name T68
Test name
Test status
Simulation time 16610692728 ps
CPU time 138.12 seconds
Started Jun 29 06:50:39 PM PDT 24
Finished Jun 29 06:52:57 PM PDT 24
Peak memory 240980 kb
Host smart-203ecc6b-0296-4854-ab21-f3b2dcdccb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986195424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.986195424
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/38.spi_device_flash_mode.820138248
Short name T293
Test name
Test status
Simulation time 3029076806 ps
CPU time 39.59 seconds
Started Jun 29 06:50:40 PM PDT 24
Finished Jun 29 06:51:20 PM PDT 24
Peak memory 249016 kb
Host smart-d747ce9b-2c31-4f60-8e05-447006c06ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820138248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.820138248
Directory /workspace/38.spi_device_flash_mode/latest


Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2879793108
Short name T42
Test name
Test status
Simulation time 48769893719 ps
CPU time 85.1 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:52:07 PM PDT 24
Peak memory 255320 kb
Host smart-34b01457-9b14-45b7-a7d4-073addf51b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879793108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2879793108
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/38.spi_device_intercept.383851739
Short name T440
Test name
Test status
Simulation time 8620747909 ps
CPU time 21.91 seconds
Started Jun 29 06:50:32 PM PDT 24
Finished Jun 29 06:50:54 PM PDT 24
Peak memory 224596 kb
Host smart-8fa91994-7a8c-4c92-8569-a5a9b08d7b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383851739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.383851739
Directory /workspace/38.spi_device_intercept/latest


Test location /workspace/coverage/default/38.spi_device_mailbox.4194015376
Short name T807
Test name
Test status
Simulation time 170976910 ps
CPU time 4.78 seconds
Started Jun 29 06:50:33 PM PDT 24
Finished Jun 29 06:50:39 PM PDT 24
Peak memory 224476 kb
Host smart-93484fde-a92d-4701-be96-c3d6220002c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194015376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4194015376
Directory /workspace/38.spi_device_mailbox/latest


Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1805415575
Short name T355
Test name
Test status
Simulation time 198059719 ps
CPU time 4.9 seconds
Started Jun 29 06:50:33 PM PDT 24
Finished Jun 29 06:50:38 PM PDT 24
Peak memory 240516 kb
Host smart-edc38757-426d-4931-b24a-bd7596c11fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805415575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1805415575
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2047909236
Short name T252
Test name
Test status
Simulation time 4710919356 ps
CPU time 6.83 seconds
Started Jun 29 06:50:32 PM PDT 24
Finished Jun 29 06:50:39 PM PDT 24
Peak memory 224600 kb
Host smart-2b64200f-22de-45fc-b087-fbdf6b186872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047909236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2047909236
Directory /workspace/38.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1892316813
Short name T990
Test name
Test status
Simulation time 1386544930 ps
CPU time 5.79 seconds
Started Jun 29 06:50:46 PM PDT 24
Finished Jun 29 06:50:52 PM PDT 24
Peak memory 218728 kb
Host smart-8534a86f-c6e4-4781-b755-b888c7b7667f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1892316813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1892316813
Directory /workspace/38.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/38.spi_device_tpm_all.2945264073
Short name T726
Test name
Test status
Simulation time 567946923 ps
CPU time 5.14 seconds
Started Jun 29 06:50:33 PM PDT 24
Finished Jun 29 06:50:39 PM PDT 24
Peak memory 216184 kb
Host smart-c93641c7-b2c3-46f7-9fa0-4349cca9521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945264073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2945264073
Directory /workspace/38.spi_device_tpm_all/latest


Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3873869343
Short name T916
Test name
Test status
Simulation time 4922830349 ps
CPU time 9.6 seconds
Started Jun 29 06:50:27 PM PDT 24
Finished Jun 29 06:50:36 PM PDT 24
Peak memory 216264 kb
Host smart-625547e1-6969-42a7-ab06-eff363c142df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873869343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3873869343
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/38.spi_device_tpm_rw.3631175903
Short name T930
Test name
Test status
Simulation time 179156318 ps
CPU time 1.51 seconds
Started Jun 29 06:50:28 PM PDT 24
Finished Jun 29 06:50:30 PM PDT 24
Peak memory 216216 kb
Host smart-7e04d84d-36a6-4c5c-875c-82980561e74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631175903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3631175903
Directory /workspace/38.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3127489311
Short name T688
Test name
Test status
Simulation time 103689127 ps
CPU time 0.88 seconds
Started Jun 29 06:50:30 PM PDT 24
Finished Jun 29 06:50:31 PM PDT 24
Peak memory 206848 kb
Host smart-ac3999b0-f09a-4650-8446-7cf5801dd495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127489311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3127489311
Directory /workspace/38.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/38.spi_device_upload.1425643026
Short name T610
Test name
Test status
Simulation time 318003220 ps
CPU time 2.24 seconds
Started Jun 29 06:50:30 PM PDT 24
Finished Jun 29 06:50:32 PM PDT 24
Peak memory 224400 kb
Host smart-0e87fa22-501e-4e87-9a59-9c03346cd071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425643026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1425643026
Directory /workspace/38.spi_device_upload/latest


Test location /workspace/coverage/default/39.spi_device_alert_test.2534161261
Short name T806
Test name
Test status
Simulation time 23065691 ps
CPU time 0.71 seconds
Started Jun 29 06:50:43 PM PDT 24
Finished Jun 29 06:50:44 PM PDT 24
Peak memory 205768 kb
Host smart-67b6f9e5-0746-4bea-9315-8ce33e53f1bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534161261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2534161261
Directory /workspace/39.spi_device_alert_test/latest


Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1852495591
Short name T714
Test name
Test status
Simulation time 1245307846 ps
CPU time 2.22 seconds
Started Jun 29 06:50:46 PM PDT 24
Finished Jun 29 06:50:48 PM PDT 24
Peak memory 224424 kb
Host smart-fc2ba5d8-dbea-4461-81e1-ff8329a9e49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852495591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1852495591
Directory /workspace/39.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/39.spi_device_csb_read.2619709476
Short name T518
Test name
Test status
Simulation time 20835208 ps
CPU time 0.79 seconds
Started Jun 29 06:50:40 PM PDT 24
Finished Jun 29 06:50:42 PM PDT 24
Peak memory 206568 kb
Host smart-fdee045b-c96a-407a-8094-c30f464ba5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619709476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2619709476
Directory /workspace/39.spi_device_csb_read/latest


Test location /workspace/coverage/default/39.spi_device_flash_all.3462076915
Short name T567
Test name
Test status
Simulation time 5983310332 ps
CPU time 17.12 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:50:59 PM PDT 24
Peak memory 249112 kb
Host smart-4fca01c9-1915-4884-bdab-7af86d639b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462076915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3462076915
Directory /workspace/39.spi_device_flash_all/latest


Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3822365659
Short name T447
Test name
Test status
Simulation time 44366419957 ps
CPU time 84.91 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:52:07 PM PDT 24
Peak memory 263036 kb
Host smart-6a57cc81-06a8-4786-8b72-219fd5b5626e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822365659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3822365659
Directory /workspace/39.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2057495359
Short name T224
Test name
Test status
Simulation time 51896646445 ps
CPU time 110.14 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:52:32 PM PDT 24
Peak memory 248644 kb
Host smart-befcfb20-3c48-4ea4-b0a4-2f879c88b6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057495359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2057495359
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/39.spi_device_flash_mode.1651397663
Short name T148
Test name
Test status
Simulation time 672393570 ps
CPU time 3.85 seconds
Started Jun 29 06:50:43 PM PDT 24
Finished Jun 29 06:50:47 PM PDT 24
Peak memory 224428 kb
Host smart-6b036987-4e3d-4939-95a5-8a27ac9dddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651397663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1651397663
Directory /workspace/39.spi_device_flash_mode/latest


Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1033568652
Short name T703
Test name
Test status
Simulation time 75006451020 ps
CPU time 73.11 seconds
Started Jun 29 06:50:42 PM PDT 24
Finished Jun 29 06:51:56 PM PDT 24
Peak memory 249080 kb
Host smart-aa518f4a-cb48-4bcb-b5af-e68e4ea1bd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033568652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1033568652
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/39.spi_device_intercept.167255807
Short name T778
Test name
Test status
Simulation time 1443661566 ps
CPU time 13.38 seconds
Started Jun 29 06:50:40 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 228424 kb
Host smart-80b806e3-3b47-4fb1-ab33-09cf9e4b6427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167255807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.167255807
Directory /workspace/39.spi_device_intercept/latest


Test location /workspace/coverage/default/39.spi_device_mailbox.3834015716
Short name T540
Test name
Test status
Simulation time 33789395 ps
CPU time 2.25 seconds
Started Jun 29 06:50:43 PM PDT 24
Finished Jun 29 06:50:46 PM PDT 24
Peak memory 232336 kb
Host smart-bea54b9c-3590-4e56-8c92-ad52365f0477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834015716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3834015716
Directory /workspace/39.spi_device_mailbox/latest


Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1309724872
Short name T604
Test name
Test status
Simulation time 216206932 ps
CPU time 4.12 seconds
Started Jun 29 06:50:45 PM PDT 24
Finished Jun 29 06:50:49 PM PDT 24
Peak memory 236876 kb
Host smart-f92a72c4-cdc6-47e0-b77f-d9ce4e29f6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309724872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1309724872
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2270816527
Short name T1023
Test name
Test status
Simulation time 2241654567 ps
CPU time 9.59 seconds
Started Jun 29 06:50:42 PM PDT 24
Finished Jun 29 06:50:53 PM PDT 24
Peak memory 248876 kb
Host smart-538dd389-ce2f-4f48-a592-bdb727f50cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270816527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2270816527
Directory /workspace/39.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.491490144
Short name T37
Test name
Test status
Simulation time 743129728 ps
CPU time 3.65 seconds
Started Jun 29 06:50:39 PM PDT 24
Finished Jun 29 06:50:43 PM PDT 24
Peak memory 219852 kb
Host smart-5baf84bd-703f-41df-a08f-857163adfaab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=491490144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.491490144
Directory /workspace/39.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/39.spi_device_tpm_all.805016161
Short name T295
Test name
Test status
Simulation time 18363888740 ps
CPU time 30.37 seconds
Started Jun 29 06:50:42 PM PDT 24
Finished Jun 29 06:51:13 PM PDT 24
Peak memory 216540 kb
Host smart-c45df7a8-67d7-44e0-9b88-4c5c832b59a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805016161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.805016161
Directory /workspace/39.spi_device_tpm_all/latest


Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.808579837
Short name T522
Test name
Test status
Simulation time 1218245021 ps
CPU time 4.29 seconds
Started Jun 29 06:50:43 PM PDT 24
Finished Jun 29 06:50:48 PM PDT 24
Peak memory 216192 kb
Host smart-8928f5b5-cf5a-4405-9a6f-6e5848860888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808579837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.808579837
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/39.spi_device_tpm_rw.3639271861
Short name T75
Test name
Test status
Simulation time 19125821 ps
CPU time 0.69 seconds
Started Jun 29 06:50:40 PM PDT 24
Finished Jun 29 06:50:41 PM PDT 24
Peak memory 205616 kb
Host smart-b4bb53e3-5c74-4cb4-9a6c-1e3938cefa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639271861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3639271861
Directory /workspace/39.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3355252088
Short name T446
Test name
Test status
Simulation time 157783119 ps
CPU time 0.88 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:50:42 PM PDT 24
Peak memory 206384 kb
Host smart-74042cc7-7fca-4f2c-a1d4-562a2c94b2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355252088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3355252088
Directory /workspace/39.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/39.spi_device_upload.3115849722
Short name T590
Test name
Test status
Simulation time 9384313698 ps
CPU time 17.81 seconds
Started Jun 29 06:50:39 PM PDT 24
Finished Jun 29 06:50:57 PM PDT 24
Peak memory 240980 kb
Host smart-73d0319c-e684-4235-a74a-a8d8bcd65e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115849722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3115849722
Directory /workspace/39.spi_device_upload/latest


Test location /workspace/coverage/default/4.spi_device_alert_test.2736265780
Short name T62
Test name
Test status
Simulation time 23681737 ps
CPU time 0.71 seconds
Started Jun 29 06:48:20 PM PDT 24
Finished Jun 29 06:48:21 PM PDT 24
Peak memory 205804 kb
Host smart-539d5e68-30e7-4a5e-bdbe-51e38e927192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736265780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
736265780
Directory /workspace/4.spi_device_alert_test/latest


Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3746606015
Short name T1012
Test name
Test status
Simulation time 7522736902 ps
CPU time 11.83 seconds
Started Jun 29 06:48:23 PM PDT 24
Finished Jun 29 06:48:35 PM PDT 24
Peak memory 224556 kb
Host smart-748734ca-3805-4d2d-9c32-8be7a912b7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746606015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3746606015
Directory /workspace/4.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/4.spi_device_csb_read.2457020219
Short name T59
Test name
Test status
Simulation time 12921711 ps
CPU time 0.76 seconds
Started Jun 29 06:48:23 PM PDT 24
Finished Jun 29 06:48:24 PM PDT 24
Peak memory 205528 kb
Host smart-570951f1-d59a-4364-a697-22aa37e3db48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457020219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2457020219
Directory /workspace/4.spi_device_csb_read/latest


Test location /workspace/coverage/default/4.spi_device_flash_all.4038780796
Short name T249
Test name
Test status
Simulation time 4416489761 ps
CPU time 61.44 seconds
Started Jun 29 06:48:24 PM PDT 24
Finished Jun 29 06:49:26 PM PDT 24
Peak memory 252660 kb
Host smart-1e73f51f-72a5-4a5f-a953-ae3861ad1ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038780796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4038780796
Directory /workspace/4.spi_device_flash_all/latest


Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1703466821
Short name T862
Test name
Test status
Simulation time 17885102369 ps
CPU time 44.12 seconds
Started Jun 29 06:48:22 PM PDT 24
Finished Jun 29 06:49:06 PM PDT 24
Peak memory 249216 kb
Host smart-d16dacbf-7b24-4c69-9818-85a7ec9b0f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703466821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1703466821
Directory /workspace/4.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.278059151
Short name T257
Test name
Test status
Simulation time 236146618477 ps
CPU time 538.46 seconds
Started Jun 29 06:48:20 PM PDT 24
Finished Jun 29 06:57:19 PM PDT 24
Peak memory 249532 kb
Host smart-aa7bc038-c3d8-403e-a9f3-6ca8c4099c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278059151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
278059151
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/4.spi_device_flash_mode.1918991703
Short name T339
Test name
Test status
Simulation time 166167606 ps
CPU time 3.78 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:30 PM PDT 24
Peak memory 224472 kb
Host smart-91e288f2-4b27-42d4-99d6-e9255749dc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918991703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1918991703
Directory /workspace/4.spi_device_flash_mode/latest


Test location /workspace/coverage/default/4.spi_device_intercept.4257576741
Short name T902
Test name
Test status
Simulation time 2497722188 ps
CPU time 23.78 seconds
Started Jun 29 06:48:20 PM PDT 24
Finished Jun 29 06:48:45 PM PDT 24
Peak memory 224604 kb
Host smart-b7ae8d36-e2c2-4101-ba56-6a49350ad4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257576741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4257576741
Directory /workspace/4.spi_device_intercept/latest


Test location /workspace/coverage/default/4.spi_device_mailbox.2501161912
Short name T370
Test name
Test status
Simulation time 23996295206 ps
CPU time 33.33 seconds
Started Jun 29 06:48:29 PM PDT 24
Finished Jun 29 06:49:03 PM PDT 24
Peak memory 239952 kb
Host smart-5655893b-1d55-4459-aedc-1058db4ba44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501161912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2501161912
Directory /workspace/4.spi_device_mailbox/latest


Test location /workspace/coverage/default/4.spi_device_mem_parity.13704571
Short name T1006
Test name
Test status
Simulation time 32495358 ps
CPU time 1.07 seconds
Started Jun 29 06:48:20 PM PDT 24
Finished Jun 29 06:48:22 PM PDT 24
Peak memory 216788 kb
Host smart-764f1e3f-1bdc-4c9f-a70d-6702f7f655a1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13704571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.13704571
Directory /workspace/4.spi_device_mem_parity/latest


Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3458327059
Short name T677
Test name
Test status
Simulation time 8218929296 ps
CPU time 4.28 seconds
Started Jun 29 06:48:20 PM PDT 24
Finished Jun 29 06:48:25 PM PDT 24
Peak memory 224592 kb
Host smart-19d3b63d-9345-44d2-b447-592716a812d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458327059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3458327059
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4205707576
Short name T674
Test name
Test status
Simulation time 7759033939 ps
CPU time 11.03 seconds
Started Jun 29 06:48:21 PM PDT 24
Finished Jun 29 06:48:33 PM PDT 24
Peak memory 232764 kb
Host smart-6cc412c3-2f6f-4afe-82f4-827fdbc1bb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205707576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4205707576
Directory /workspace/4.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.287277504
Short name T853
Test name
Test status
Simulation time 14958284482 ps
CPU time 12.11 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:38 PM PDT 24
Peak memory 219036 kb
Host smart-11f9a0bf-bdf3-45b3-8371-39d9fba77e53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=287277504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.287277504
Directory /workspace/4.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/4.spi_device_sec_cm.4178250328
Short name T65
Test name
Test status
Simulation time 58209441 ps
CPU time 1.06 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:27 PM PDT 24
Peak memory 235404 kb
Host smart-9ba0c0df-2262-4d38-8c6e-6a9f6b5a2c3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178250328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4178250328
Directory /workspace/4.spi_device_sec_cm/latest


Test location /workspace/coverage/default/4.spi_device_tpm_all.4265990455
Short name T965
Test name
Test status
Simulation time 3834967015 ps
CPU time 20.54 seconds
Started Jun 29 06:48:26 PM PDT 24
Finished Jun 29 06:48:47 PM PDT 24
Peak memory 216256 kb
Host smart-360c3983-62d1-4734-8eb9-d1d6ab03be09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265990455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4265990455
Directory /workspace/4.spi_device_tpm_all/latest


Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2645674905
Short name T532
Test name
Test status
Simulation time 582207784 ps
CPU time 3.39 seconds
Started Jun 29 06:48:21 PM PDT 24
Finished Jun 29 06:48:25 PM PDT 24
Peak memory 216152 kb
Host smart-2ac819f1-702d-4735-8a74-cd3c0737acee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645674905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2645674905
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/4.spi_device_tpm_rw.3711197529
Short name T773
Test name
Test status
Simulation time 1623970106 ps
CPU time 2.37 seconds
Started Jun 29 06:48:22 PM PDT 24
Finished Jun 29 06:48:25 PM PDT 24
Peak memory 216256 kb
Host smart-6b6ad61b-b74a-4b73-96e8-06f42572705d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711197529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3711197529
Directory /workspace/4.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1463399086
Short name T563
Test name
Test status
Simulation time 129737500 ps
CPU time 0.82 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:27 PM PDT 24
Peak memory 205876 kb
Host smart-7811bb51-10fa-4564-9743-ee8671025a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463399086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1463399086
Directory /workspace/4.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/4.spi_device_upload.4177289028
Short name T722
Test name
Test status
Simulation time 121808252 ps
CPU time 2.54 seconds
Started Jun 29 06:48:22 PM PDT 24
Finished Jun 29 06:48:25 PM PDT 24
Peak memory 232668 kb
Host smart-b69ff547-b12c-4bc5-9884-16c5b9df0c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177289028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4177289028
Directory /workspace/4.spi_device_upload/latest


Test location /workspace/coverage/default/40.spi_device_alert_test.2274069834
Short name T61
Test name
Test status
Simulation time 38368907 ps
CPU time 0.68 seconds
Started Jun 29 06:50:40 PM PDT 24
Finished Jun 29 06:50:41 PM PDT 24
Peak memory 205740 kb
Host smart-199d1dcd-ce05-483c-847c-b506c76a9362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274069834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2274069834
Directory /workspace/40.spi_device_alert_test/latest


Test location /workspace/coverage/default/40.spi_device_cfg_cmd.788796177
Short name T957
Test name
Test status
Simulation time 386994882 ps
CPU time 3.54 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:50:45 PM PDT 24
Peak memory 232644 kb
Host smart-de5f17d3-c339-4986-9ff5-57199ab0ca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788796177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.788796177
Directory /workspace/40.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/40.spi_device_csb_read.2578218048
Short name T331
Test name
Test status
Simulation time 88155266 ps
CPU time 0.76 seconds
Started Jun 29 06:50:44 PM PDT 24
Finished Jun 29 06:50:45 PM PDT 24
Peak memory 205476 kb
Host smart-5891b9ff-a5dc-4bf5-8970-a338a87d3abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578218048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2578218048
Directory /workspace/40.spi_device_csb_read/latest


Test location /workspace/coverage/default/40.spi_device_flash_all.4038038361
Short name T206
Test name
Test status
Simulation time 3230539288 ps
CPU time 44.29 seconds
Started Jun 29 06:50:40 PM PDT 24
Finished Jun 29 06:51:25 PM PDT 24
Peak memory 253204 kb
Host smart-6092da1e-00c6-4698-b2f7-aa59b8f732ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038038361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.4038038361
Directory /workspace/40.spi_device_flash_all/latest


Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4094182567
Short name T303
Test name
Test status
Simulation time 3296271392 ps
CPU time 56.32 seconds
Started Jun 29 06:50:40 PM PDT 24
Finished Jun 29 06:51:37 PM PDT 24
Peak memory 232788 kb
Host smart-2a821381-6c44-4694-8e8e-55fcbb4cabed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094182567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4094182567
Directory /workspace/40.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/40.spi_device_flash_mode.634344713
Short name T601
Test name
Test status
Simulation time 46926290 ps
CPU time 3.08 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:50:45 PM PDT 24
Peak memory 232672 kb
Host smart-b5c588af-c258-4377-a113-2f376fed9159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634344713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.634344713
Directory /workspace/40.spi_device_flash_mode/latest


Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2544971626
Short name T597
Test name
Test status
Simulation time 2115697230 ps
CPU time 49.41 seconds
Started Jun 29 06:50:46 PM PDT 24
Finished Jun 29 06:51:36 PM PDT 24
Peak memory 249332 kb
Host smart-ebbc0373-2da4-4801-81fc-649c80b00d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544971626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2544971626
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/40.spi_device_intercept.1284230522
Short name T337
Test name
Test status
Simulation time 5485566891 ps
CPU time 24.19 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:51:07 PM PDT 24
Peak memory 232800 kb
Host smart-1caae733-a29a-4fc9-8774-49374564f404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284230522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1284230522
Directory /workspace/40.spi_device_intercept/latest


Test location /workspace/coverage/default/40.spi_device_mailbox.1324564956
Short name T996
Test name
Test status
Simulation time 11141195674 ps
CPU time 132.41 seconds
Started Jun 29 06:50:42 PM PDT 24
Finished Jun 29 06:52:55 PM PDT 24
Peak memory 233752 kb
Host smart-1af3d670-2c65-4bbf-be50-274840e911d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324564956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1324564956
Directory /workspace/40.spi_device_mailbox/latest


Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.250740338
Short name T925
Test name
Test status
Simulation time 4436396073 ps
CPU time 13.17 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:50:54 PM PDT 24
Peak memory 232740 kb
Host smart-d16008fc-33e5-4141-9de8-82dfc7399e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250740338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.250740338
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3565343544
Short name T240
Test name
Test status
Simulation time 201184751 ps
CPU time 4.69 seconds
Started Jun 29 06:50:39 PM PDT 24
Finished Jun 29 06:50:44 PM PDT 24
Peak memory 239636 kb
Host smart-d25f6364-0a55-4d01-8b9e-3b81829e23f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565343544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3565343544
Directory /workspace/40.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2705386121
Short name T599
Test name
Test status
Simulation time 4455047317 ps
CPU time 13.05 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 223084 kb
Host smart-33cf8be7-a134-43ce-a3c2-47a632424093
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2705386121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2705386121
Directory /workspace/40.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/40.spi_device_stress_all.502145597
Short name T994
Test name
Test status
Simulation time 15178448240 ps
CPU time 52.91 seconds
Started Jun 29 06:50:40 PM PDT 24
Finished Jun 29 06:51:33 PM PDT 24
Peak memory 252824 kb
Host smart-79b807b7-a85a-44fa-a0e4-b3a7e80d9a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502145597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.502145597
Directory /workspace/40.spi_device_stress_all/latest


Test location /workspace/coverage/default/40.spi_device_tpm_all.313998311
Short name T310
Test name
Test status
Simulation time 49469339 ps
CPU time 0.7 seconds
Started Jun 29 06:50:40 PM PDT 24
Finished Jun 29 06:50:42 PM PDT 24
Peak memory 205672 kb
Host smart-01f54722-4ba4-42b2-a377-8ff87f68f25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313998311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.313998311
Directory /workspace/40.spi_device_tpm_all/latest


Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.567913096
Short name T741
Test name
Test status
Simulation time 3460755430 ps
CPU time 8.14 seconds
Started Jun 29 06:50:40 PM PDT 24
Finished Jun 29 06:50:49 PM PDT 24
Peak memory 216356 kb
Host smart-b34f734e-6391-44f4-b6d5-eddcc7c1adfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567913096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.567913096
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/40.spi_device_tpm_rw.2230820151
Short name T342
Test name
Test status
Simulation time 253260334 ps
CPU time 2.55 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:50:45 PM PDT 24
Peak memory 216224 kb
Host smart-36b43b32-40d7-4020-a763-2225ce16eec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230820151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2230820151
Directory /workspace/40.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.690352411
Short name T941
Test name
Test status
Simulation time 154000828 ps
CPU time 0.78 seconds
Started Jun 29 06:50:39 PM PDT 24
Finished Jun 29 06:50:40 PM PDT 24
Peak memory 205884 kb
Host smart-2421b29e-bcc2-49cf-9708-e819033f57a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690352411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.690352411
Directory /workspace/40.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/40.spi_device_upload.879502732
Short name T244
Test name
Test status
Simulation time 34373767599 ps
CPU time 13.07 seconds
Started Jun 29 06:50:42 PM PDT 24
Finished Jun 29 06:50:56 PM PDT 24
Peak memory 232740 kb
Host smart-3ae0941f-97af-47b0-965d-5734afff4d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879502732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.879502732
Directory /workspace/40.spi_device_upload/latest


Test location /workspace/coverage/default/41.spi_device_alert_test.4244155198
Short name T589
Test name
Test status
Simulation time 15239891 ps
CPU time 0.74 seconds
Started Jun 29 06:50:48 PM PDT 24
Finished Jun 29 06:50:49 PM PDT 24
Peak memory 205420 kb
Host smart-07ef5a90-30ca-46f4-a4d5-9991624becbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244155198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4244155198
Directory /workspace/41.spi_device_alert_test/latest


Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1879444391
Short name T813
Test name
Test status
Simulation time 226287584 ps
CPU time 2.59 seconds
Started Jun 29 06:50:51 PM PDT 24
Finished Jun 29 06:50:54 PM PDT 24
Peak memory 224440 kb
Host smart-61a164b9-f1f9-47d0-95e2-c50a994b2e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879444391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1879444391
Directory /workspace/41.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/41.spi_device_csb_read.1445281811
Short name T696
Test name
Test status
Simulation time 33168056 ps
CPU time 0.79 seconds
Started Jun 29 06:50:41 PM PDT 24
Finished Jun 29 06:50:42 PM PDT 24
Peak memory 206504 kb
Host smart-293e0798-d87d-4547-8e70-48630b2bbf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445281811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1445281811
Directory /workspace/41.spi_device_csb_read/latest


Test location /workspace/coverage/default/41.spi_device_flash_all.2452931449
Short name T1001
Test name
Test status
Simulation time 1160329855 ps
CPU time 10.52 seconds
Started Jun 29 06:50:54 PM PDT 24
Finished Jun 29 06:51:05 PM PDT 24
Peak memory 224536 kb
Host smart-8a811503-43e9-420b-b906-211a530fc40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452931449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2452931449
Directory /workspace/41.spi_device_flash_all/latest


Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.665469224
Short name T139
Test name
Test status
Simulation time 418373147492 ps
CPU time 324.84 seconds
Started Jun 29 06:50:51 PM PDT 24
Finished Jun 29 06:56:16 PM PDT 24
Peak memory 254400 kb
Host smart-6966518a-4c7e-4073-9f89-1d31d57dce5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665469224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.665469224
Directory /workspace/41.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.4093554713
Short name T436
Test name
Test status
Simulation time 127906384416 ps
CPU time 294.45 seconds
Started Jun 29 06:50:52 PM PDT 24
Finished Jun 29 06:55:47 PM PDT 24
Peak memory 249192 kb
Host smart-c8159ac4-2651-4b3e-b0fc-4e042530c504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093554713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.4093554713
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/41.spi_device_flash_mode.3909411932
Short name T605
Test name
Test status
Simulation time 486861498 ps
CPU time 9.54 seconds
Started Jun 29 06:50:50 PM PDT 24
Finished Jun 29 06:51:00 PM PDT 24
Peak memory 232684 kb
Host smart-c8223ca8-eb19-4897-a7b3-54c04f31ee3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909411932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3909411932
Directory /workspace/41.spi_device_flash_mode/latest


Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2376349713
Short name T382
Test name
Test status
Simulation time 4886775207 ps
CPU time 5.79 seconds
Started Jun 29 06:50:47 PM PDT 24
Finished Jun 29 06:50:53 PM PDT 24
Peak memory 233844 kb
Host smart-02a91db0-8f9e-40a2-a975-fff69979d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376349713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2376349713
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/41.spi_device_intercept.2315468505
Short name T192
Test name
Test status
Simulation time 510861259 ps
CPU time 4.73 seconds
Started Jun 29 06:50:50 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 224372 kb
Host smart-40efab40-49b7-408d-a5de-7c59b40d58e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315468505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2315468505
Directory /workspace/41.spi_device_intercept/latest


Test location /workspace/coverage/default/41.spi_device_mailbox.3996133814
Short name T989
Test name
Test status
Simulation time 1279358760 ps
CPU time 8.81 seconds
Started Jun 29 06:50:52 PM PDT 24
Finished Jun 29 06:51:02 PM PDT 24
Peak memory 232644 kb
Host smart-3df56f4c-0901-4b90-a105-5c0c50a1f851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996133814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3996133814
Directory /workspace/41.spi_device_mailbox/latest


Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2183792452
Short name T205
Test name
Test status
Simulation time 73733136 ps
CPU time 2.64 seconds
Started Jun 29 06:50:47 PM PDT 24
Finished Jun 29 06:50:49 PM PDT 24
Peak memory 232628 kb
Host smart-98c01cb1-effc-4eb1-abc3-91ead58826ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183792452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2183792452
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.336331851
Short name T893
Test name
Test status
Simulation time 2677774130 ps
CPU time 8.57 seconds
Started Jun 29 06:50:47 PM PDT 24
Finished Jun 29 06:50:56 PM PDT 24
Peak memory 240804 kb
Host smart-89a6ca02-e03f-48f5-8859-8bc2e5a71d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336331851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.336331851
Directory /workspace/41.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4112218470
Short name T11
Test name
Test status
Simulation time 3456780624 ps
CPU time 5.34 seconds
Started Jun 29 06:50:51 PM PDT 24
Finished Jun 29 06:50:56 PM PDT 24
Peak memory 219984 kb
Host smart-cdb4c131-dfce-431f-9031-276c5d7b2f26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4112218470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4112218470
Directory /workspace/41.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/41.spi_device_stress_all.3168314368
Short name T470
Test name
Test status
Simulation time 174485100 ps
CPU time 1.18 seconds
Started Jun 29 06:50:47 PM PDT 24
Finished Jun 29 06:50:48 PM PDT 24
Peak memory 206784 kb
Host smart-5f741ecc-0d25-4725-89eb-71948625617d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168314368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3168314368
Directory /workspace/41.spi_device_stress_all/latest


Test location /workspace/coverage/default/41.spi_device_tpm_all.3120519667
Short name T549
Test name
Test status
Simulation time 5503892523 ps
CPU time 26.34 seconds
Started Jun 29 06:50:48 PM PDT 24
Finished Jun 29 06:51:14 PM PDT 24
Peak memory 216352 kb
Host smart-cfc89e3d-5d33-418a-adc1-cd14bf2e03ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120519667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3120519667
Directory /workspace/41.spi_device_tpm_all/latest


Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2601789511
Short name T804
Test name
Test status
Simulation time 3057734064 ps
CPU time 8.87 seconds
Started Jun 29 06:50:51 PM PDT 24
Finished Jun 29 06:51:00 PM PDT 24
Peak memory 216308 kb
Host smart-acca3479-bd2c-4f46-a64c-746a7caa2136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601789511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2601789511
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/41.spi_device_tpm_rw.405264431
Short name T472
Test name
Test status
Simulation time 50142639 ps
CPU time 1.17 seconds
Started Jun 29 06:50:48 PM PDT 24
Finished Jun 29 06:50:50 PM PDT 24
Peak memory 207872 kb
Host smart-5491f410-940d-4f18-8206-02b7d695f0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405264431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.405264431
Directory /workspace/41.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.885599549
Short name T729
Test name
Test status
Simulation time 59681799 ps
CPU time 0.75 seconds
Started Jun 29 06:50:56 PM PDT 24
Finished Jun 29 06:50:57 PM PDT 24
Peak memory 205880 kb
Host smart-f6d50fe5-01b0-4b75-a2d0-df546f183d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885599549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.885599549
Directory /workspace/41.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/41.spi_device_upload.1677738093
Short name T581
Test name
Test status
Simulation time 557680491 ps
CPU time 8.31 seconds
Started Jun 29 06:50:46 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 232672 kb
Host smart-30cee1c0-1ca8-4650-a39c-36cad8b95b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677738093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1677738093
Directory /workspace/41.spi_device_upload/latest


Test location /workspace/coverage/default/42.spi_device_alert_test.2391574589
Short name T731
Test name
Test status
Simulation time 19708100 ps
CPU time 0.75 seconds
Started Jun 29 06:50:54 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 204840 kb
Host smart-dfd8d233-9c19-42d2-9bdc-b82237ad6b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391574589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2391574589
Directory /workspace/42.spi_device_alert_test/latest


Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2927227002
Short name T1004
Test name
Test status
Simulation time 107759674 ps
CPU time 2.33 seconds
Started Jun 29 06:50:52 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 224488 kb
Host smart-65449b35-88e4-452f-825c-0b47c6a6c5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927227002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2927227002
Directory /workspace/42.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/42.spi_device_csb_read.451604602
Short name T368
Test name
Test status
Simulation time 20272724 ps
CPU time 0.8 seconds
Started Jun 29 06:50:47 PM PDT 24
Finished Jun 29 06:50:48 PM PDT 24
Peak memory 206556 kb
Host smart-830c7fe9-de11-4382-8110-21dfc228c419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451604602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.451604602
Directory /workspace/42.spi_device_csb_read/latest


Test location /workspace/coverage/default/42.spi_device_flash_all.3417864511
Short name T992
Test name
Test status
Simulation time 109288218325 ps
CPU time 182.72 seconds
Started Jun 29 06:50:51 PM PDT 24
Finished Jun 29 06:53:54 PM PDT 24
Peak memory 250136 kb
Host smart-d11ff8f3-0d67-48c5-81e4-f630b01cd1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417864511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3417864511
Directory /workspace/42.spi_device_flash_all/latest


Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2888626704
Short name T995
Test name
Test status
Simulation time 66209694797 ps
CPU time 620.64 seconds
Started Jun 29 06:50:48 PM PDT 24
Finished Jun 29 07:01:09 PM PDT 24
Peak memory 251428 kb
Host smart-ded4516b-872f-4f0f-8208-e26da086de0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888626704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2888626704
Directory /workspace/42.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2304832545
Short name T791
Test name
Test status
Simulation time 13527950728 ps
CPU time 14.16 seconds
Started Jun 29 06:50:52 PM PDT 24
Finished Jun 29 06:51:07 PM PDT 24
Peak memory 219100 kb
Host smart-04470227-3438-44d0-bbe2-568701850e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304832545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2304832545
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/42.spi_device_flash_mode.3184146811
Short name T149
Test name
Test status
Simulation time 2740777736 ps
CPU time 27.23 seconds
Started Jun 29 06:50:50 PM PDT 24
Finished Jun 29 06:51:18 PM PDT 24
Peak memory 224516 kb
Host smart-e660a587-652d-4d07-8a85-74a9741c6d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184146811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3184146811
Directory /workspace/42.spi_device_flash_mode/latest


Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.4236528513
Short name T88
Test name
Test status
Simulation time 236146336154 ps
CPU time 455.88 seconds
Started Jun 29 06:50:52 PM PDT 24
Finished Jun 29 06:58:29 PM PDT 24
Peak memory 272976 kb
Host smart-e05b8056-04cf-4f0b-923c-eb746ee3da13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236528513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.4236528513
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/42.spi_device_intercept.126853065
Short name T371
Test name
Test status
Simulation time 133739486 ps
CPU time 3.43 seconds
Started Jun 29 06:50:49 PM PDT 24
Finished Jun 29 06:50:52 PM PDT 24
Peak memory 232888 kb
Host smart-6e481fae-f020-41e9-b320-cb773500bbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126853065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.126853065
Directory /workspace/42.spi_device_intercept/latest


Test location /workspace/coverage/default/42.spi_device_mailbox.1402013081
Short name T237
Test name
Test status
Simulation time 372390616 ps
CPU time 4.05 seconds
Started Jun 29 06:50:49 PM PDT 24
Finished Jun 29 06:50:54 PM PDT 24
Peak memory 232620 kb
Host smart-bf27a950-00fc-4023-be75-ff26238e8fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402013081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1402013081
Directory /workspace/42.spi_device_mailbox/latest


Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1621033250
Short name T837
Test name
Test status
Simulation time 107120102 ps
CPU time 2.7 seconds
Started Jun 29 06:50:50 PM PDT 24
Finished Jun 29 06:50:53 PM PDT 24
Peak memory 232376 kb
Host smart-44e911a1-2293-48ff-bb40-ed54b256d56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621033250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1621033250
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.433533927
Short name T927
Test name
Test status
Simulation time 293532361 ps
CPU time 3.78 seconds
Started Jun 29 06:50:46 PM PDT 24
Finished Jun 29 06:50:50 PM PDT 24
Peak memory 224464 kb
Host smart-23a226bc-03e3-42c0-834e-ea4d8e64d352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433533927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.433533927
Directory /workspace/42.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3782533151
Short name T650
Test name
Test status
Simulation time 330043101 ps
CPU time 5.61 seconds
Started Jun 29 06:50:52 PM PDT 24
Finished Jun 29 06:50:58 PM PDT 24
Peak memory 219328 kb
Host smart-1cc9c4f3-1204-461d-8781-6714b0fbe602
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3782533151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3782533151
Directory /workspace/42.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/42.spi_device_stress_all.3596827040
Short name T559
Test name
Test status
Simulation time 185564678 ps
CPU time 1.06 seconds
Started Jun 29 06:50:48 PM PDT 24
Finished Jun 29 06:50:49 PM PDT 24
Peak memory 206772 kb
Host smart-c4ef58b3-d322-417f-83cc-7f3f5dfbf206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596827040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3596827040
Directory /workspace/42.spi_device_stress_all/latest


Test location /workspace/coverage/default/42.spi_device_tpm_all.2288982466
Short name T406
Test name
Test status
Simulation time 25212061558 ps
CPU time 18.51 seconds
Started Jun 29 06:50:52 PM PDT 24
Finished Jun 29 06:51:10 PM PDT 24
Peak memory 216304 kb
Host smart-af62a416-e9f1-4fb0-9b81-8f28b6fade2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288982466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2288982466
Directory /workspace/42.spi_device_tpm_all/latest


Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3936958058
Short name T419
Test name
Test status
Simulation time 257784480 ps
CPU time 2.67 seconds
Started Jun 29 06:50:48 PM PDT 24
Finished Jun 29 06:50:51 PM PDT 24
Peak memory 216128 kb
Host smart-e87fb3ca-248f-437c-bfdb-f04a69117a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936958058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3936958058
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/42.spi_device_tpm_rw.541199146
Short name T591
Test name
Test status
Simulation time 406365934 ps
CPU time 2.72 seconds
Started Jun 29 06:50:51 PM PDT 24
Finished Jun 29 06:50:54 PM PDT 24
Peak memory 216100 kb
Host smart-a8b3cd2b-503d-4196-9cba-17906edaf997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541199146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.541199146
Directory /workspace/42.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3980347428
Short name T457
Test name
Test status
Simulation time 17140479 ps
CPU time 0.68 seconds
Started Jun 29 06:50:54 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 205588 kb
Host smart-3f7f304a-f1b2-4c4d-a3d7-ece165ae3973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980347428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3980347428
Directory /workspace/42.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/42.spi_device_upload.2725196652
Short name T373
Test name
Test status
Simulation time 1400815917 ps
CPU time 8.65 seconds
Started Jun 29 06:50:54 PM PDT 24
Finished Jun 29 06:51:03 PM PDT 24
Peak memory 224504 kb
Host smart-d0813190-f876-4bc8-8fe2-a945d3baa957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725196652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2725196652
Directory /workspace/42.spi_device_upload/latest


Test location /workspace/coverage/default/43.spi_device_alert_test.2722378118
Short name T411
Test name
Test status
Simulation time 13133142 ps
CPU time 0.73 seconds
Started Jun 29 06:51:03 PM PDT 24
Finished Jun 29 06:51:04 PM PDT 24
Peak memory 205400 kb
Host smart-54ebb5a8-434a-442a-a31c-154d3f486846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722378118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2722378118
Directory /workspace/43.spi_device_alert_test/latest


Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2694445753
Short name T734
Test name
Test status
Simulation time 1663465791 ps
CPU time 9.69 seconds
Started Jun 29 06:51:00 PM PDT 24
Finished Jun 29 06:51:10 PM PDT 24
Peak memory 232628 kb
Host smart-bbd30c66-990f-4f2b-baf6-db7f4f8dce9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694445753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2694445753
Directory /workspace/43.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/43.spi_device_csb_read.4200376658
Short name T683
Test name
Test status
Simulation time 16473134 ps
CPU time 0.76 seconds
Started Jun 29 06:50:54 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 206564 kb
Host smart-d3ec9a8c-e66d-47dd-bade-e31ea2e153f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200376658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4200376658
Directory /workspace/43.spi_device_csb_read/latest


Test location /workspace/coverage/default/43.spi_device_flash_all.560928136
Short name T267
Test name
Test status
Simulation time 80150628794 ps
CPU time 160.4 seconds
Started Jun 29 06:51:08 PM PDT 24
Finished Jun 29 06:53:49 PM PDT 24
Peak memory 254532 kb
Host smart-3e3ca66a-7b08-43c6-bf64-66edcbb5a5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560928136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.560928136
Directory /workspace/43.spi_device_flash_all/latest


Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.603356798
Short name T183
Test name
Test status
Simulation time 4589196858 ps
CPU time 87.75 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:52:40 PM PDT 24
Peak memory 254824 kb
Host smart-1ba3649c-aa15-4c88-8312-3b144b6106c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603356798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.603356798
Directory /workspace/43.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2936525946
Short name T1028
Test name
Test status
Simulation time 38964248364 ps
CPU time 48.72 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:59 PM PDT 24
Peak memory 241040 kb
Host smart-682264e4-744a-4bbd-85f1-553bb5091e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936525946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2936525946
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/43.spi_device_flash_mode.4174081367
Short name T287
Test name
Test status
Simulation time 810161284 ps
CPU time 8.29 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:22 PM PDT 24
Peak memory 232652 kb
Host smart-ff0b0878-aed5-4019-8303-0aaeacaa060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174081367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4174081367
Directory /workspace/43.spi_device_flash_mode/latest


Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1410891538
Short name T645
Test name
Test status
Simulation time 3781720817 ps
CPU time 25.06 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:39 PM PDT 24
Peak memory 249180 kb
Host smart-4fb9d3a4-a80e-4f37-8c9b-7849a8f0a21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410891538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1410891538
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/43.spi_device_intercept.3127537704
Short name T238
Test name
Test status
Simulation time 1288317030 ps
CPU time 3.29 seconds
Started Jun 29 06:50:51 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 224484 kb
Host smart-88909e8d-2eda-4ad3-99d0-6819287ab86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127537704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3127537704
Directory /workspace/43.spi_device_intercept/latest


Test location /workspace/coverage/default/43.spi_device_mailbox.1532934674
Short name T234
Test name
Test status
Simulation time 862009789 ps
CPU time 14.03 seconds
Started Jun 29 06:50:51 PM PDT 24
Finished Jun 29 06:51:05 PM PDT 24
Peak memory 240568 kb
Host smart-822477e0-db8e-47e2-a11e-79d081d12a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532934674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1532934674
Directory /workspace/43.spi_device_mailbox/latest


Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3752102249
Short name T43
Test name
Test status
Simulation time 374928241 ps
CPU time 4.81 seconds
Started Jun 29 06:50:50 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 232656 kb
Host smart-ca9d4c6b-d3c0-49ac-ad5e-8ffed23be544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752102249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3752102249
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1577138955
Short name T951
Test name
Test status
Simulation time 699293535 ps
CPU time 8.63 seconds
Started Jun 29 06:50:53 PM PDT 24
Finished Jun 29 06:51:02 PM PDT 24
Peak memory 232676 kb
Host smart-79952ad6-ceb4-449e-963f-282111283418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577138955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1577138955
Directory /workspace/43.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3417545835
Short name T501
Test name
Test status
Simulation time 363939096 ps
CPU time 5.51 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:18 PM PDT 24
Peak memory 219184 kb
Host smart-eb7e1b2b-9e29-49d9-bfab-1e1e83c331cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3417545835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3417545835
Directory /workspace/43.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/43.spi_device_stress_all.3425840101
Short name T163
Test name
Test status
Simulation time 26950122966 ps
CPU time 103.17 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:52:57 PM PDT 24
Peak memory 257460 kb
Host smart-d6201867-2aa0-4be7-8ff7-2fa49659a4cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425840101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3425840101
Directory /workspace/43.spi_device_stress_all/latest


Test location /workspace/coverage/default/43.spi_device_tpm_all.1598295729
Short name T699
Test name
Test status
Simulation time 9173313895 ps
CPU time 15.05 seconds
Started Jun 29 06:50:51 PM PDT 24
Finished Jun 29 06:51:06 PM PDT 24
Peak memory 216312 kb
Host smart-99aa507d-b5ea-429d-abb3-0c8aadb1c722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598295729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1598295729
Directory /workspace/43.spi_device_tpm_all/latest


Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1595026184
Short name T906
Test name
Test status
Simulation time 20739268 ps
CPU time 0.77 seconds
Started Jun 29 06:50:49 PM PDT 24
Finished Jun 29 06:50:50 PM PDT 24
Peak memory 205660 kb
Host smart-3bf9a04a-8018-43a7-91c2-2ad5bae911a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595026184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1595026184
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/43.spi_device_tpm_rw.2654486730
Short name T341
Test name
Test status
Simulation time 183171775 ps
CPU time 0.82 seconds
Started Jun 29 06:50:54 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 206604 kb
Host smart-b8dbbd9d-28bc-4460-8b4d-278696c3e1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654486730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2654486730
Directory /workspace/43.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1333017860
Short name T794
Test name
Test status
Simulation time 485377090 ps
CPU time 0.89 seconds
Started Jun 29 06:50:52 PM PDT 24
Finished Jun 29 06:50:53 PM PDT 24
Peak memory 206872 kb
Host smart-0d85d505-fb52-4147-a7aa-e628ce34c48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333017860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1333017860
Directory /workspace/43.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/43.spi_device_upload.237080983
Short name T505
Test name
Test status
Simulation time 565242808 ps
CPU time 5.8 seconds
Started Jun 29 06:50:54 PM PDT 24
Finished Jun 29 06:51:00 PM PDT 24
Peak memory 232704 kb
Host smart-87102ffe-1335-400c-90c1-d75884bec2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237080983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.237080983
Directory /workspace/43.spi_device_upload/latest


Test location /workspace/coverage/default/44.spi_device_alert_test.964023109
Short name T461
Test name
Test status
Simulation time 22676162 ps
CPU time 0.72 seconds
Started Jun 29 06:50:59 PM PDT 24
Finished Jun 29 06:51:00 PM PDT 24
Peak memory 204752 kb
Host smart-f8d7d5b4-6fd5-415f-a6de-ed85a0f5a2e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964023109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.964023109
Directory /workspace/44.spi_device_alert_test/latest


Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3103631237
Short name T375
Test name
Test status
Simulation time 4878887979 ps
CPU time 12.64 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:27 PM PDT 24
Peak memory 232776 kb
Host smart-574f5439-fadf-4588-9767-fff57469c0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103631237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3103631237
Directory /workspace/44.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/44.spi_device_csb_read.1656121058
Short name T345
Test name
Test status
Simulation time 179078064 ps
CPU time 0.76 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:14 PM PDT 24
Peak memory 206892 kb
Host smart-9c54cce5-9599-45c1-bca0-08c073031405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656121058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1656121058
Directory /workspace/44.spi_device_csb_read/latest


Test location /workspace/coverage/default/44.spi_device_flash_all.2255119404
Short name T556
Test name
Test status
Simulation time 200650794 ps
CPU time 0.86 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:51:12 PM PDT 24
Peak memory 215976 kb
Host smart-c8609036-cd18-4eae-814b-e418822c7898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255119404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2255119404
Directory /workspace/44.spi_device_flash_all/latest


Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1127947390
Short name T538
Test name
Test status
Simulation time 25837301951 ps
CPU time 263.65 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:55:36 PM PDT 24
Peak memory 257424 kb
Host smart-8a74a2b3-1b26-44c5-922f-23e7237b8374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127947390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1127947390
Directory /workspace/44.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.871930887
Short name T550
Test name
Test status
Simulation time 55842408118 ps
CPU time 281.66 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:55:56 PM PDT 24
Peak memory 250252 kb
Host smart-e1ad696d-cd08-408f-bd28-8dd71599f89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871930887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.871930887
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/44.spi_device_flash_mode.193571757
Short name T873
Test name
Test status
Simulation time 9154607633 ps
CPU time 34.48 seconds
Started Jun 29 06:50:59 PM PDT 24
Finished Jun 29 06:51:34 PM PDT 24
Peak memory 232736 kb
Host smart-d038cf73-d84f-4c1a-b4c4-1340ec45e338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193571757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.193571757
Directory /workspace/44.spi_device_flash_mode/latest


Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2769010551
Short name T414
Test name
Test status
Simulation time 30244855724 ps
CPU time 72.73 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:52:25 PM PDT 24
Peak memory 252120 kb
Host smart-068914ab-9e31-4454-be7f-df146cd1f35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769010551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2769010551
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/44.spi_device_intercept.1051219101
Short name T574
Test name
Test status
Simulation time 164099375 ps
CPU time 3.81 seconds
Started Jun 29 06:51:09 PM PDT 24
Finished Jun 29 06:51:13 PM PDT 24
Peak memory 224448 kb
Host smart-f70c8d3a-1b8a-4d72-bb65-dbd4e76a162a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051219101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1051219101
Directory /workspace/44.spi_device_intercept/latest


Test location /workspace/coverage/default/44.spi_device_mailbox.133145409
Short name T317
Test name
Test status
Simulation time 132748187 ps
CPU time 2.39 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:14 PM PDT 24
Peak memory 232372 kb
Host smart-037d0238-760d-463b-bdba-3005f1d01e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133145409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.133145409
Directory /workspace/44.spi_device_mailbox/latest


Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.578908719
Short name T7
Test name
Test status
Simulation time 186981774 ps
CPU time 2.75 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:13 PM PDT 24
Peak memory 232664 kb
Host smart-eefc51ff-3510-4eab-96dc-9959e07662bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578908719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.578908719
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3014010668
Short name T701
Test name
Test status
Simulation time 1556544949 ps
CPU time 12.35 seconds
Started Jun 29 06:50:59 PM PDT 24
Finished Jun 29 06:51:11 PM PDT 24
Peak memory 240680 kb
Host smart-c150c766-7770-4714-9c5e-f4a17821d108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014010668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3014010668
Directory /workspace/44.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3160348599
Short name T931
Test name
Test status
Simulation time 2281588227 ps
CPU time 13 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:26 PM PDT 24
Peak memory 222452 kb
Host smart-a7c4e724-038c-4b9d-924a-77d8a4106e47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3160348599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3160348599
Directory /workspace/44.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/44.spi_device_stress_all.3091441258
Short name T867
Test name
Test status
Simulation time 193569715 ps
CPU time 1.1 seconds
Started Jun 29 06:51:15 PM PDT 24
Finished Jun 29 06:51:17 PM PDT 24
Peak memory 207096 kb
Host smart-cfea4080-9af2-4b71-b9b9-dfaa8fe51582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091441258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3091441258
Directory /workspace/44.spi_device_stress_all/latest


Test location /workspace/coverage/default/44.spi_device_tpm_all.2683238676
Short name T305
Test name
Test status
Simulation time 14826729775 ps
CPU time 13.91 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:28 PM PDT 24
Peak memory 216312 kb
Host smart-b53606a8-df75-42e9-bb41-c89cab3e43a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683238676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2683238676
Directory /workspace/44.spi_device_tpm_all/latest


Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3313714819
Short name T903
Test name
Test status
Simulation time 13996675543 ps
CPU time 10.44 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:24 PM PDT 24
Peak memory 216304 kb
Host smart-05b9f083-388e-4a63-83dc-57077a7b7627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313714819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3313714819
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/44.spi_device_tpm_rw.811182801
Short name T46
Test name
Test status
Simulation time 758688319 ps
CPU time 2.24 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:51:19 PM PDT 24
Peak memory 216184 kb
Host smart-8d2fa28c-01d5-4040-bd4a-0b33ed5cb5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811182801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.811182801
Directory /workspace/44.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2645918292
Short name T321
Test name
Test status
Simulation time 35358734 ps
CPU time 0.9 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:12 PM PDT 24
Peak memory 206884 kb
Host smart-6e5c330c-2587-43d2-878f-f83016c84ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645918292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2645918292
Directory /workspace/44.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/44.spi_device_upload.2084231361
Short name T347
Test name
Test status
Simulation time 2815192104 ps
CPU time 10.73 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:24 PM PDT 24
Peak memory 232764 kb
Host smart-5df503e1-128c-4011-8140-557d42762949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084231361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2084231361
Directory /workspace/44.spi_device_upload/latest


Test location /workspace/coverage/default/45.spi_device_alert_test.3184295661
Short name T642
Test name
Test status
Simulation time 39302689 ps
CPU time 0.71 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:14 PM PDT 24
Peak memory 205396 kb
Host smart-15522b40-1d2a-4ec6-81e3-babe8cf5238f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184295661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3184295661
Directory /workspace/45.spi_device_alert_test/latest


Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3691405747
Short name T831
Test name
Test status
Simulation time 34771087 ps
CPU time 2.2 seconds
Started Jun 29 06:50:58 PM PDT 24
Finished Jun 29 06:51:01 PM PDT 24
Peak memory 224416 kb
Host smart-755cba19-87cc-4c93-9693-30707f5e5631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691405747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3691405747
Directory /workspace/45.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/45.spi_device_csb_read.2793492600
Short name T789
Test name
Test status
Simulation time 45978628 ps
CPU time 0.75 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:11 PM PDT 24
Peak memory 206564 kb
Host smart-b4c2ac25-964d-4498-9c1b-3ceb4a14f267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793492600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2793492600
Directory /workspace/45.spi_device_csb_read/latest


Test location /workspace/coverage/default/45.spi_device_flash_all.1256796186
Short name T210
Test name
Test status
Simulation time 31595441640 ps
CPU time 107.48 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:52:59 PM PDT 24
Peak memory 255444 kb
Host smart-48801e6d-07be-4b83-b6fe-6e5d66fb13c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256796186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1256796186
Directory /workspace/45.spi_device_flash_all/latest


Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1440912494
Short name T654
Test name
Test status
Simulation time 8245212348 ps
CPU time 57.72 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:52:11 PM PDT 24
Peak memory 257428 kb
Host smart-a484a2fb-0444-4988-bc80-a71054aff9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440912494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1440912494
Directory /workspace/45.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2810325419
Short name T823
Test name
Test status
Simulation time 30923870575 ps
CPU time 195.57 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:54:32 PM PDT 24
Peak memory 240968 kb
Host smart-686da003-4573-4e1e-b170-8fbe5790ecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810325419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2810325419
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/45.spi_device_flash_mode.4244752349
Short name T1011
Test name
Test status
Simulation time 3650118017 ps
CPU time 15.65 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:30 PM PDT 24
Peak memory 224608 kb
Host smart-f71a0ade-c4f3-42dd-8364-a4f1cb409b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244752349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4244752349
Directory /workspace/45.spi_device_flash_mode/latest


Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2590784656
Short name T987
Test name
Test status
Simulation time 4239924549 ps
CPU time 20.09 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:30 PM PDT 24
Peak memory 238316 kb
Host smart-98535c41-d4b3-4f60-9a2a-c11f1cbbfaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590784656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2590784656
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/45.spi_device_intercept.2700883832
Short name T208
Test name
Test status
Simulation time 747601859 ps
CPU time 9.72 seconds
Started Jun 29 06:51:08 PM PDT 24
Finished Jun 29 06:51:18 PM PDT 24
Peak memory 224448 kb
Host smart-f0acf57b-f148-44a2-ba39-d7d45ddb5f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700883832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2700883832
Directory /workspace/45.spi_device_intercept/latest


Test location /workspace/coverage/default/45.spi_device_mailbox.1320968487
Short name T226
Test name
Test status
Simulation time 3931438087 ps
CPU time 15.6 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:30 PM PDT 24
Peak memory 224508 kb
Host smart-cbc2b628-7036-4e43-a6fc-3f4497b1aa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320968487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1320968487
Directory /workspace/45.spi_device_mailbox/latest


Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2606377059
Short name T570
Test name
Test status
Simulation time 65393853 ps
CPU time 2.6 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:14 PM PDT 24
Peak memory 232636 kb
Host smart-b87a55b7-3995-46dc-b2d6-651fc899aca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606377059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2606377059
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.746944487
Short name T746
Test name
Test status
Simulation time 13456851721 ps
CPU time 23.66 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:51:36 PM PDT 24
Peak memory 240652 kb
Host smart-906c602d-97fa-43ac-a0d1-5f36dab90700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746944487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.746944487
Directory /workspace/45.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3408141394
Short name T745
Test name
Test status
Simulation time 92769878 ps
CPU time 3.86 seconds
Started Jun 29 06:51:15 PM PDT 24
Finished Jun 29 06:51:20 PM PDT 24
Peak memory 222920 kb
Host smart-75a27aae-c13c-4e20-8562-042df0999b64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3408141394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3408141394
Directory /workspace/45.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/45.spi_device_stress_all.1041603083
Short name T850
Test name
Test status
Simulation time 244564049505 ps
CPU time 474.79 seconds
Started Jun 29 06:51:01 PM PDT 24
Finished Jun 29 06:58:56 PM PDT 24
Peak memory 282140 kb
Host smart-8502b468-a0b4-4019-9cd8-a31b853582a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041603083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1041603083
Directory /workspace/45.spi_device_stress_all/latest


Test location /workspace/coverage/default/45.spi_device_tpm_all.727704698
Short name T296
Test name
Test status
Simulation time 1054925914 ps
CPU time 10.2 seconds
Started Jun 29 06:50:59 PM PDT 24
Finished Jun 29 06:51:09 PM PDT 24
Peak memory 216276 kb
Host smart-817423e3-175a-4c75-b72b-ab0163354d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727704698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.727704698
Directory /workspace/45.spi_device_tpm_all/latest


Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.981995869
Short name T833
Test name
Test status
Simulation time 3675870776 ps
CPU time 5.87 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:20 PM PDT 24
Peak memory 216276 kb
Host smart-9e1c2425-958c-4c68-b24d-8a8e2ca9a9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981995869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.981995869
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/45.spi_device_tpm_rw.3190983310
Short name T376
Test name
Test status
Simulation time 750039749 ps
CPU time 3.48 seconds
Started Jun 29 06:51:15 PM PDT 24
Finished Jun 29 06:51:19 PM PDT 24
Peak memory 216156 kb
Host smart-fdbb4331-18d7-4e23-8eaa-080db09803e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190983310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3190983310
Directory /workspace/45.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3849636736
Short name T849
Test name
Test status
Simulation time 48575578 ps
CPU time 0.81 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:15 PM PDT 24
Peak memory 205884 kb
Host smart-b7c42771-9a43-40e4-8a27-7519ab02ec79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849636736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3849636736
Directory /workspace/45.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/45.spi_device_upload.3308881479
Short name T16
Test name
Test status
Simulation time 1157545278 ps
CPU time 6.04 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:17 PM PDT 24
Peak memory 232636 kb
Host smart-c432d91a-1bba-4d48-ba79-8e73107444a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308881479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3308881479
Directory /workspace/45.spi_device_upload/latest


Test location /workspace/coverage/default/46.spi_device_alert_test.3700091228
Short name T60
Test name
Test status
Simulation time 40771804 ps
CPU time 0.73 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:14 PM PDT 24
Peak memory 205412 kb
Host smart-d698db0d-11ae-4d45-9195-df688cd1e5ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700091228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3700091228
Directory /workspace/46.spi_device_alert_test/latest


Test location /workspace/coverage/default/46.spi_device_cfg_cmd.724719451
Short name T967
Test name
Test status
Simulation time 878281746 ps
CPU time 5.71 seconds
Started Jun 29 06:51:15 PM PDT 24
Finished Jun 29 06:51:21 PM PDT 24
Peak memory 224440 kb
Host smart-5ba60a81-17e1-44c6-8a89-9baab3b77614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724719451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.724719451
Directory /workspace/46.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/46.spi_device_csb_read.4174557821
Short name T169
Test name
Test status
Simulation time 72968007 ps
CPU time 0.78 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:14 PM PDT 24
Peak memory 206536 kb
Host smart-befd070d-ab26-4a07-9b2c-6a0e8c6d3165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174557821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4174557821
Directory /workspace/46.spi_device_csb_read/latest


Test location /workspace/coverage/default/46.spi_device_flash_all.3730516632
Short name T185
Test name
Test status
Simulation time 9134553583 ps
CPU time 14.53 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:28 PM PDT 24
Peak memory 224604 kb
Host smart-aba785e9-4e6f-4529-99f9-f200164c77fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730516632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3730516632
Directory /workspace/46.spi_device_flash_all/latest


Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.791684775
Short name T491
Test name
Test status
Simulation time 17376751931 ps
CPU time 105.09 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:52:55 PM PDT 24
Peak memory 237308 kb
Host smart-53e89235-e70b-4612-b87f-74f687396880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791684775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.791684775
Directory /workspace/46.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.751369573
Short name T835
Test name
Test status
Simulation time 101111668022 ps
CPU time 286.48 seconds
Started Jun 29 06:51:09 PM PDT 24
Finished Jun 29 06:55:56 PM PDT 24
Peak memory 273092 kb
Host smart-dbfc5441-5736-4a02-b874-ffdee8b36cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751369573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.751369573
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/46.spi_device_flash_mode.1658845396
Short name T291
Test name
Test status
Simulation time 117209253 ps
CPU time 6.44 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:20 PM PDT 24
Peak memory 238368 kb
Host smart-03448acf-2906-43af-bcec-be84f950b474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658845396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1658845396
Directory /workspace/46.spi_device_flash_mode/latest


Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3245579899
Short name T270
Test name
Test status
Simulation time 5003659782 ps
CPU time 41.16 seconds
Started Jun 29 06:51:08 PM PDT 24
Finished Jun 29 06:51:50 PM PDT 24
Peak memory 240964 kb
Host smart-fd2af982-3488-40c9-8bc4-b66177250e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245579899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3245579899
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/46.spi_device_intercept.540753536
Short name T58
Test name
Test status
Simulation time 2920499646 ps
CPU time 10.05 seconds
Started Jun 29 06:51:09 PM PDT 24
Finished Jun 29 06:51:20 PM PDT 24
Peak memory 224564 kb
Host smart-e6d6ce22-20ca-46cc-81ac-102aa9c9b4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540753536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.540753536
Directory /workspace/46.spi_device_intercept/latest


Test location /workspace/coverage/default/46.spi_device_mailbox.4181913354
Short name T706
Test name
Test status
Simulation time 3177334538 ps
CPU time 29.04 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:40 PM PDT 24
Peak memory 232792 kb
Host smart-b0807067-db17-4127-aa14-1123c6427454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181913354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4181913354
Directory /workspace/46.spi_device_mailbox/latest


Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3236543060
Short name T213
Test name
Test status
Simulation time 26412114680 ps
CPU time 35.03 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:51:47 PM PDT 24
Peak memory 235792 kb
Host smart-dd1c9ec3-f2e4-47c7-a9fb-3d6a8c1081e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236543060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3236543060
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1146909084
Short name T545
Test name
Test status
Simulation time 1389266340 ps
CPU time 8.94 seconds
Started Jun 29 06:51:15 PM PDT 24
Finished Jun 29 06:51:25 PM PDT 24
Peak memory 224408 kb
Host smart-ca49ee5f-b136-4560-8c5e-16722582f4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146909084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1146909084
Directory /workspace/46.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.398693582
Short name T147
Test name
Test status
Simulation time 132348421 ps
CPU time 3.98 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:51:16 PM PDT 24
Peak memory 222692 kb
Host smart-6d6b1974-9dd8-46fa-86fd-38f9ab06bfbb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=398693582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.398693582
Directory /workspace/46.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/46.spi_device_stress_all.2242908476
Short name T52
Test name
Test status
Simulation time 14416335680 ps
CPU time 152.41 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:53:47 PM PDT 24
Peak memory 252828 kb
Host smart-90906d56-e5fd-4b2e-ada8-c05583dd5d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242908476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2242908476
Directory /workspace/46.spi_device_stress_all/latest


Test location /workspace/coverage/default/46.spi_device_tpm_all.2743912202
Short name T421
Test name
Test status
Simulation time 5144197139 ps
CPU time 29.83 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:44 PM PDT 24
Peak memory 220132 kb
Host smart-5c508681-7150-4b33-b9a0-aa64fde2c393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743912202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2743912202
Directory /workspace/46.spi_device_tpm_all/latest


Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2429904688
Short name T882
Test name
Test status
Simulation time 122494161 ps
CPU time 1.52 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:16 PM PDT 24
Peak memory 207852 kb
Host smart-f6907a39-f5d3-4bb8-b148-b24fff21a9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429904688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2429904688
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/46.spi_device_tpm_rw.2930806938
Short name T923
Test name
Test status
Simulation time 644819971 ps
CPU time 2.05 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:51:18 PM PDT 24
Peak memory 216188 kb
Host smart-21502114-63a3-4f18-8ed5-a88cbd10402f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930806938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2930806938
Directory /workspace/46.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3057753202
Short name T780
Test name
Test status
Simulation time 117417229 ps
CPU time 0.82 seconds
Started Jun 29 06:51:14 PM PDT 24
Finished Jun 29 06:51:15 PM PDT 24
Peak memory 205832 kb
Host smart-e8ae64a1-b4d9-4628-86fa-1d21ad08f33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057753202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3057753202
Directory /workspace/46.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/46.spi_device_upload.1085651364
Short name T241
Test name
Test status
Simulation time 798588118 ps
CPU time 5.01 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:51:17 PM PDT 24
Peak memory 236252 kb
Host smart-03a74d82-4bc2-41bf-8ec0-3a5d37a9793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085651364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1085651364
Directory /workspace/46.spi_device_upload/latest


Test location /workspace/coverage/default/47.spi_device_alert_test.61422511
Short name T747
Test name
Test status
Simulation time 26172096 ps
CPU time 0.76 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:12 PM PDT 24
Peak memory 204844 kb
Host smart-f9282d6d-a060-4668-9a7d-e0a5c494de7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61422511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.61422511
Directory /workspace/47.spi_device_alert_test/latest


Test location /workspace/coverage/default/47.spi_device_cfg_cmd.294575813
Short name T890
Test name
Test status
Simulation time 338467995 ps
CPU time 4.4 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:19 PM PDT 24
Peak memory 232680 kb
Host smart-4b44f0ff-4537-4a23-97a7-34fdf18079e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294575813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.294575813
Directory /workspace/47.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/47.spi_device_csb_read.2562699628
Short name T700
Test name
Test status
Simulation time 35350183 ps
CPU time 0.79 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:12 PM PDT 24
Peak memory 206892 kb
Host smart-328d0fa7-fca2-4fe5-9c04-30a616d0f2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562699628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2562699628
Directory /workspace/47.spi_device_csb_read/latest


Test location /workspace/coverage/default/47.spi_device_flash_all.2826538539
Short name T278
Test name
Test status
Simulation time 9675282546 ps
CPU time 121.3 seconds
Started Jun 29 06:51:09 PM PDT 24
Finished Jun 29 06:53:11 PM PDT 24
Peak memory 249220 kb
Host smart-d43cd59f-f61c-41d2-8ee8-5782a628157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826538539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2826538539
Directory /workspace/47.spi_device_flash_all/latest


Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3905957841
Short name T797
Test name
Test status
Simulation time 40221348098 ps
CPU time 82.33 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:52:36 PM PDT 24
Peak memory 249484 kb
Host smart-7fd3edae-3b22-483b-97ca-75f5ae84115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905957841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3905957841
Directory /workspace/47.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3181930084
Short name T280
Test name
Test status
Simulation time 385528464889 ps
CPU time 191 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:54:23 PM PDT 24
Peak memory 254840 kb
Host smart-dcefbecb-8741-4374-9783-a181bc9171b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181930084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3181930084
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/47.spi_device_intercept.3505468493
Short name T475
Test name
Test status
Simulation time 1348509927 ps
CPU time 13.12 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:26 PM PDT 24
Peak memory 232680 kb
Host smart-196678bf-a7a3-4e77-973b-4c0541268a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505468493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3505468493
Directory /workspace/47.spi_device_intercept/latest


Test location /workspace/coverage/default/47.spi_device_mailbox.3474173023
Short name T1009
Test name
Test status
Simulation time 2372794444 ps
CPU time 27.36 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:51:44 PM PDT 24
Peak memory 249184 kb
Host smart-2823a189-df96-4a97-a793-32e46634c19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474173023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3474173023
Directory /workspace/47.spi_device_mailbox/latest


Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4117171210
Short name T261
Test name
Test status
Simulation time 8471706753 ps
CPU time 17.67 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:51:35 PM PDT 24
Peak memory 239808 kb
Host smart-3ef96dbb-ad4c-4d18-8be8-b0b30b8922be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117171210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4117171210
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2175073716
Short name T471
Test name
Test status
Simulation time 49051308519 ps
CPU time 28.39 seconds
Started Jun 29 06:51:09 PM PDT 24
Finished Jun 29 06:51:38 PM PDT 24
Peak memory 232736 kb
Host smart-4d4008fb-2a62-4ef7-9e20-2024c448daec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175073716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2175073716
Directory /workspace/47.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.873776583
Short name T530
Test name
Test status
Simulation time 2493266195 ps
CPU time 7.33 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:51:24 PM PDT 24
Peak memory 222404 kb
Host smart-98125551-4696-407b-98b1-5f6dd9354693
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=873776583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.873776583
Directory /workspace/47.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/47.spi_device_stress_all.1372600134
Short name T162
Test name
Test status
Simulation time 47632360 ps
CPU time 1.06 seconds
Started Jun 29 06:51:19 PM PDT 24
Finished Jun 29 06:51:22 PM PDT 24
Peak memory 206976 kb
Host smart-7ee0efa7-f468-41be-add5-691855deb569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372600134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1372600134
Directory /workspace/47.spi_device_stress_all/latest


Test location /workspace/coverage/default/47.spi_device_tpm_all.3421827669
Short name T135
Test name
Test status
Simulation time 2635760294 ps
CPU time 7.79 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:18 PM PDT 24
Peak memory 219212 kb
Host smart-245f4664-698d-4208-8e8f-0063fd52e6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421827669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3421827669
Directory /workspace/47.spi_device_tpm_all/latest


Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4218471752
Short name T363
Test name
Test status
Simulation time 3445754321 ps
CPU time 12.69 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:26 PM PDT 24
Peak memory 216216 kb
Host smart-e043cb91-8af0-4e88-ae3c-5383dd423965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218471752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4218471752
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/47.spi_device_tpm_rw.1742907378
Short name T891
Test name
Test status
Simulation time 263242195 ps
CPU time 9.75 seconds
Started Jun 29 06:51:19 PM PDT 24
Finished Jun 29 06:51:30 PM PDT 24
Peak memory 216448 kb
Host smart-d4594ae8-58ca-47dd-bb2d-978da82f975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742907378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1742907378
Directory /workspace/47.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2784429414
Short name T896
Test name
Test status
Simulation time 70671217 ps
CPU time 0.73 seconds
Started Jun 29 06:51:10 PM PDT 24
Finished Jun 29 06:51:12 PM PDT 24
Peak memory 205892 kb
Host smart-414c7c5d-7f9c-4373-a2e9-f4b0efb4b0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784429414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2784429414
Directory /workspace/47.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/47.spi_device_upload.4002328552
Short name T914
Test name
Test status
Simulation time 9166550855 ps
CPU time 28.08 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:51:44 PM PDT 24
Peak memory 239784 kb
Host smart-4f739478-f2cb-4660-9510-f875798af14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002328552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4002328552
Directory /workspace/47.spi_device_upload/latest


Test location /workspace/coverage/default/48.spi_device_alert_test.1328361051
Short name T426
Test name
Test status
Simulation time 13662723 ps
CPU time 0.76 seconds
Started Jun 29 06:51:18 PM PDT 24
Finished Jun 29 06:51:19 PM PDT 24
Peak memory 205392 kb
Host smart-d98eaa80-526a-498f-b23e-a8338a95d756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328361051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1328361051
Directory /workspace/48.spi_device_alert_test/latest


Test location /workspace/coverage/default/48.spi_device_cfg_cmd.769711763
Short name T793
Test name
Test status
Simulation time 581795866 ps
CPU time 2.56 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:16 PM PDT 24
Peak memory 224468 kb
Host smart-33a0384e-ca51-47a6-bffc-f338f599ff5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769711763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.769711763
Directory /workspace/48.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/48.spi_device_csb_read.2096014138
Short name T614
Test name
Test status
Simulation time 13997472 ps
CPU time 0.76 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:51:17 PM PDT 24
Peak memory 205540 kb
Host smart-94e88e30-c17a-4575-9d51-137559683256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096014138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2096014138
Directory /workspace/48.spi_device_csb_read/latest


Test location /workspace/coverage/default/48.spi_device_flash_all.2254732435
Short name T418
Test name
Test status
Simulation time 6786441886 ps
CPU time 47.64 seconds
Started Jun 29 06:51:18 PM PDT 24
Finished Jun 29 06:52:07 PM PDT 24
Peak memory 255372 kb
Host smart-615a66a4-33b7-42da-a0b2-8cce62aab789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254732435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2254732435
Directory /workspace/48.spi_device_flash_all/latest


Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.341537627
Short name T1021
Test name
Test status
Simulation time 912843368 ps
CPU time 20.86 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:51:37 PM PDT 24
Peak memory 254624 kb
Host smart-76228051-99f6-49df-b13c-6552b3952038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341537627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.341537627
Directory /workspace/48.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3713273435
Short name T668
Test name
Test status
Simulation time 23319019352 ps
CPU time 47.27 seconds
Started Jun 29 06:51:18 PM PDT 24
Finished Jun 29 06:52:06 PM PDT 24
Peak memory 251672 kb
Host smart-9f5deee2-b257-4709-9641-ccaeda2b0c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713273435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3713273435
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/48.spi_device_flash_mode.1384688967
Short name T615
Test name
Test status
Simulation time 1104930703 ps
CPU time 4.91 seconds
Started Jun 29 06:51:17 PM PDT 24
Finished Jun 29 06:51:22 PM PDT 24
Peak memory 232672 kb
Host smart-c960d0ca-a71a-48e1-8dba-faf290b52bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384688967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1384688967
Directory /workspace/48.spi_device_flash_mode/latest


Test location /workspace/coverage/default/48.spi_device_intercept.2621054393
Short name T233
Test name
Test status
Simulation time 174885449 ps
CPU time 3.74 seconds
Started Jun 29 06:51:17 PM PDT 24
Finished Jun 29 06:51:22 PM PDT 24
Peak memory 232620 kb
Host smart-9e65824d-168d-40e9-b396-9abea55b1575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621054393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2621054393
Directory /workspace/48.spi_device_intercept/latest


Test location /workspace/coverage/default/48.spi_device_mailbox.1779095697
Short name T988
Test name
Test status
Simulation time 1215717530 ps
CPU time 9.65 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:51:26 PM PDT 24
Peak memory 232656 kb
Host smart-7e4036ad-cb8f-41a9-a83e-eb56b4cd07d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779095697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1779095697
Directory /workspace/48.spi_device_mailbox/latest


Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3526186443
Short name T188
Test name
Test status
Simulation time 2891355834 ps
CPU time 4.5 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:51:17 PM PDT 24
Peak memory 232624 kb
Host smart-bc3671d3-1932-42b2-b9dc-575c166644a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526186443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3526186443
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1870083430
Short name T596
Test name
Test status
Simulation time 172227411 ps
CPU time 3.44 seconds
Started Jun 29 06:51:13 PM PDT 24
Finished Jun 29 06:51:18 PM PDT 24
Peak memory 224408 kb
Host smart-04bff0b0-cdf6-466e-bea3-5954425ad0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870083430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1870083430
Directory /workspace/48.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3338944099
Short name T478
Test name
Test status
Simulation time 1603055432 ps
CPU time 7.76 seconds
Started Jun 29 06:51:19 PM PDT 24
Finished Jun 29 06:51:27 PM PDT 24
Peak memory 221892 kb
Host smart-ff3b8777-3b1f-420b-bfa5-b88199227c66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3338944099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3338944099
Directory /workspace/48.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/48.spi_device_stress_all.4207460085
Short name T259
Test name
Test status
Simulation time 24254531847 ps
CPU time 320.14 seconds
Started Jun 29 06:51:19 PM PDT 24
Finished Jun 29 06:56:41 PM PDT 24
Peak memory 286044 kb
Host smart-6e6d9bf1-707b-4b74-9d82-552ff25b04cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207460085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4207460085
Directory /workspace/48.spi_device_stress_all/latest


Test location /workspace/coverage/default/48.spi_device_tpm_all.299728444
Short name T74
Test name
Test status
Simulation time 5080817031 ps
CPU time 31.99 seconds
Started Jun 29 06:51:11 PM PDT 24
Finished Jun 29 06:51:43 PM PDT 24
Peak memory 220908 kb
Host smart-c0ae43d3-e49b-4298-816d-85c74a082e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299728444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.299728444
Directory /workspace/48.spi_device_tpm_all/latest


Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2933980522
Short name T762
Test name
Test status
Simulation time 31659679570 ps
CPU time 9.94 seconds
Started Jun 29 06:51:19 PM PDT 24
Finished Jun 29 06:51:30 PM PDT 24
Peak memory 216564 kb
Host smart-fe6047e8-36bf-4283-8c89-8166dc5172f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933980522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2933980522
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/48.spi_device_tpm_rw.3308396028
Short name T466
Test name
Test status
Simulation time 199756378 ps
CPU time 5.43 seconds
Started Jun 29 06:51:17 PM PDT 24
Finished Jun 29 06:51:23 PM PDT 24
Peak memory 216156 kb
Host smart-c5886d6e-a134-49c9-bef6-a1c7b33b7ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308396028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3308396028
Directory /workspace/48.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3248525312
Short name T678
Test name
Test status
Simulation time 87701276 ps
CPU time 0.87 seconds
Started Jun 29 06:51:12 PM PDT 24
Finished Jun 29 06:51:14 PM PDT 24
Peak memory 205876 kb
Host smart-ecd1ca43-3b7c-47f3-9541-65f2d95f5060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248525312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3248525312
Directory /workspace/48.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/48.spi_device_upload.1606982097
Short name T872
Test name
Test status
Simulation time 861346061 ps
CPU time 4.47 seconds
Started Jun 29 06:51:16 PM PDT 24
Finished Jun 29 06:51:21 PM PDT 24
Peak memory 224468 kb
Host smart-3ababd6f-6bc7-432c-83fa-4cc28babfa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606982097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1606982097
Directory /workspace/48.spi_device_upload/latest


Test location /workspace/coverage/default/49.spi_device_alert_test.307294014
Short name T955
Test name
Test status
Simulation time 13975585 ps
CPU time 0.72 seconds
Started Jun 29 06:51:23 PM PDT 24
Finished Jun 29 06:51:24 PM PDT 24
Peak memory 205396 kb
Host smart-f893939b-072b-4c0a-af12-2931f9608636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307294014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.307294014
Directory /workspace/49.spi_device_alert_test/latest


Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3402356518
Short name T315
Test name
Test status
Simulation time 84900038 ps
CPU time 2.52 seconds
Started Jun 29 06:51:19 PM PDT 24
Finished Jun 29 06:51:23 PM PDT 24
Peak memory 232636 kb
Host smart-103d5a79-0553-4e74-945c-34b15a4a0aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402356518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3402356518
Directory /workspace/49.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/49.spi_device_csb_read.3870201331
Short name T512
Test name
Test status
Simulation time 17122911 ps
CPU time 0.73 seconds
Started Jun 29 06:51:17 PM PDT 24
Finished Jun 29 06:51:18 PM PDT 24
Peak memory 205840 kb
Host smart-e9eba0aa-6b98-4054-b862-5d727434ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870201331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3870201331
Directory /workspace/49.spi_device_csb_read/latest


Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3986885800
Short name T236
Test name
Test status
Simulation time 5115169132 ps
CPU time 34.1 seconds
Started Jun 29 06:51:18 PM PDT 24
Finished Jun 29 06:51:53 PM PDT 24
Peak memory 254480 kb
Host smart-14d9f1f9-27c2-4804-abf4-b7bdf247de37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986885800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3986885800
Directory /workspace/49.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.140299837
Short name T536
Test name
Test status
Simulation time 18896286938 ps
CPU time 159.88 seconds
Started Jun 29 06:51:19 PM PDT 24
Finished Jun 29 06:53:59 PM PDT 24
Peak memory 255352 kb
Host smart-a58966ce-8068-49d7-9fc7-1d13d9b4eb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140299837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.140299837
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/49.spi_device_flash_mode.1851884415
Short name T1015
Test name
Test status
Simulation time 5392953274 ps
CPU time 22.72 seconds
Started Jun 29 06:51:24 PM PDT 24
Finished Jun 29 06:51:47 PM PDT 24
Peak memory 233348 kb
Host smart-c8b8da0e-5abd-48e1-8bc3-865748f5eb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851884415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1851884415
Directory /workspace/49.spi_device_flash_mode/latest


Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1620842490
Short name T282
Test name
Test status
Simulation time 4484251522 ps
CPU time 26.26 seconds
Started Jun 29 06:51:18 PM PDT 24
Finished Jun 29 06:51:45 PM PDT 24
Peak memory 239412 kb
Host smart-11dc173f-7f21-49f1-867d-681cfce3b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620842490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1620842490
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/49.spi_device_intercept.1773522866
Short name T322
Test name
Test status
Simulation time 40356575 ps
CPU time 2.05 seconds
Started Jun 29 06:51:19 PM PDT 24
Finished Jun 29 06:51:22 PM PDT 24
Peak memory 223916 kb
Host smart-6d862447-648e-40bf-9fd7-e4fb349e0e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773522866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1773522866
Directory /workspace/49.spi_device_intercept/latest


Test location /workspace/coverage/default/49.spi_device_mailbox.446801815
Short name T227
Test name
Test status
Simulation time 764721170 ps
CPU time 10.22 seconds
Started Jun 29 06:51:20 PM PDT 24
Finished Jun 29 06:51:31 PM PDT 24
Peak memory 232664 kb
Host smart-9797f24b-9bf1-4bba-90d4-1aa8dd4b8d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446801815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.446801815
Directory /workspace/49.spi_device_mailbox/latest


Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1752076627
Short name T684
Test name
Test status
Simulation time 57216523379 ps
CPU time 12.37 seconds
Started Jun 29 06:51:20 PM PDT 24
Finished Jun 29 06:51:33 PM PDT 24
Peak memory 232764 kb
Host smart-e32ff76e-75e8-4685-8fbd-9457a65046b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752076627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1752076627
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2490137299
Short name T894
Test name
Test status
Simulation time 899888548 ps
CPU time 2.51 seconds
Started Jun 29 06:51:23 PM PDT 24
Finished Jun 29 06:51:26 PM PDT 24
Peak memory 224468 kb
Host smart-6fcacd31-8db0-44d2-9769-737754e0a04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490137299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2490137299
Directory /workspace/49.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.736634963
Short name T431
Test name
Test status
Simulation time 583821234 ps
CPU time 7.81 seconds
Started Jun 29 06:51:14 PM PDT 24
Finished Jun 29 06:51:23 PM PDT 24
Peak memory 222988 kb
Host smart-01e3b533-53bf-41ba-93bf-25c163679451
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=736634963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.736634963
Directory /workspace/49.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/49.spi_device_stress_all.3309894104
Short name T407
Test name
Test status
Simulation time 78579402110 ps
CPU time 143.29 seconds
Started Jun 29 06:51:20 PM PDT 24
Finished Jun 29 06:53:44 PM PDT 24
Peak memory 249288 kb
Host smart-112b9946-6f30-4af2-9245-75053dc05e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309894104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3309894104
Directory /workspace/49.spi_device_stress_all/latest


Test location /workspace/coverage/default/49.spi_device_tpm_all.1642065649
Short name T356
Test name
Test status
Simulation time 8457229984 ps
CPU time 43.97 seconds
Started Jun 29 06:51:19 PM PDT 24
Finished Jun 29 06:52:04 PM PDT 24
Peak memory 216348 kb
Host smart-f6206047-1662-4c18-8471-f22ae15c8648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642065649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1642065649
Directory /workspace/49.spi_device_tpm_all/latest


Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2521451585
Short name T760
Test name
Test status
Simulation time 480730010 ps
CPU time 1.58 seconds
Started Jun 29 06:51:18 PM PDT 24
Finished Jun 29 06:51:20 PM PDT 24
Peak memory 207884 kb
Host smart-2ece0000-6271-47c2-8485-4ab1e7805a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521451585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2521451585
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/49.spi_device_tpm_rw.2261162598
Short name T898
Test name
Test status
Simulation time 770018279 ps
CPU time 2.42 seconds
Started Jun 29 06:51:17 PM PDT 24
Finished Jun 29 06:51:21 PM PDT 24
Peak memory 216144 kb
Host smart-238dd693-f404-42c5-8490-80fd6d70ff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261162598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2261162598
Directory /workspace/49.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4045159456
Short name T937
Test name
Test status
Simulation time 201821441 ps
CPU time 0.9 seconds
Started Jun 29 06:51:19 PM PDT 24
Finished Jun 29 06:51:21 PM PDT 24
Peak memory 205884 kb
Host smart-0ad4a3b0-f018-4428-9576-ea7306db52aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045159456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4045159456
Directory /workspace/49.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/49.spi_device_upload.862846210
Short name T878
Test name
Test status
Simulation time 5824584742 ps
CPU time 6.63 seconds
Started Jun 29 06:51:18 PM PDT 24
Finished Jun 29 06:51:26 PM PDT 24
Peak memory 224556 kb
Host smart-dee725a6-5fc9-4749-b897-d6e3a74e2428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862846210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.862846210
Directory /workspace/49.spi_device_upload/latest


Test location /workspace/coverage/default/5.spi_device_alert_test.4220777421
Short name T362
Test name
Test status
Simulation time 22454410 ps
CPU time 0.69 seconds
Started Jun 29 06:48:33 PM PDT 24
Finished Jun 29 06:48:34 PM PDT 24
Peak memory 205044 kb
Host smart-40d90f1b-814a-430a-9fd6-c823832473bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220777421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
220777421
Directory /workspace/5.spi_device_alert_test/latest


Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2779821598
Short name T186
Test name
Test status
Simulation time 234799425 ps
CPU time 3.44 seconds
Started Jun 29 06:48:29 PM PDT 24
Finished Jun 29 06:48:33 PM PDT 24
Peak memory 224476 kb
Host smart-39ce62ab-f190-4d39-bb35-4a14993913b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779821598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2779821598
Directory /workspace/5.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/5.spi_device_csb_read.1403910233
Short name T514
Test name
Test status
Simulation time 42896291 ps
CPU time 0.75 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:26 PM PDT 24
Peak memory 206036 kb
Host smart-33f744ef-1ac0-463c-8902-2e802aaefdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403910233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1403910233
Directory /workspace/5.spi_device_csb_read/latest


Test location /workspace/coverage/default/5.spi_device_flash_all.2730897594
Short name T790
Test name
Test status
Simulation time 28637943984 ps
CPU time 68.04 seconds
Started Jun 29 06:48:34 PM PDT 24
Finished Jun 29 06:49:42 PM PDT 24
Peak memory 257168 kb
Host smart-cffd7fd0-e4f0-4abc-903a-fc48d41f6114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730897594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2730897594
Directory /workspace/5.spi_device_flash_all/latest


Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3039593022
Short name T49
Test name
Test status
Simulation time 4310894666 ps
CPU time 63.69 seconds
Started Jun 29 06:48:32 PM PDT 24
Finished Jun 29 06:49:36 PM PDT 24
Peak memory 252272 kb
Host smart-17df610e-a16d-4d6d-9849-378c18e6030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039593022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3039593022
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/5.spi_device_flash_mode.790528221
Short name T578
Test name
Test status
Simulation time 348414731 ps
CPU time 6.57 seconds
Started Jun 29 06:48:29 PM PDT 24
Finished Jun 29 06:48:36 PM PDT 24
Peak memory 239788 kb
Host smart-85ac1098-7c8a-4e9e-98cc-0a8150894ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790528221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.790528221
Directory /workspace/5.spi_device_flash_mode/latest


Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3971273728
Short name T283
Test name
Test status
Simulation time 2067085225 ps
CPU time 23.7 seconds
Started Jun 29 06:48:23 PM PDT 24
Finished Jun 29 06:48:47 PM PDT 24
Peak memory 257240 kb
Host smart-5851d96a-d8a4-4295-91b4-526c8d408f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971273728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3971273728
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/5.spi_device_intercept.600512212
Short name T647
Test name
Test status
Simulation time 1560514175 ps
CPU time 5.24 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:31 PM PDT 24
Peak memory 224420 kb
Host smart-16162eb6-7c87-467e-805f-0bb4d147df66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600512212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.600512212
Directory /workspace/5.spi_device_intercept/latest


Test location /workspace/coverage/default/5.spi_device_mailbox.4238299183
Short name T690
Test name
Test status
Simulation time 3571447609 ps
CPU time 16.75 seconds
Started Jun 29 06:48:29 PM PDT 24
Finished Jun 29 06:48:46 PM PDT 24
Peak memory 249152 kb
Host smart-871ac6cd-2c18-49d5-b851-2dc67c0e6b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238299183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4238299183
Directory /workspace/5.spi_device_mailbox/latest


Test location /workspace/coverage/default/5.spi_device_mem_parity.1038955859
Short name T429
Test name
Test status
Simulation time 14880247 ps
CPU time 0.98 seconds
Started Jun 29 06:48:19 PM PDT 24
Finished Jun 29 06:48:20 PM PDT 24
Peak memory 216776 kb
Host smart-b11c49f1-2da9-4e5a-9526-3aa315944204
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038955859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1038955859
Directory /workspace/5.spi_device_mem_parity/latest


Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1728296740
Short name T767
Test name
Test status
Simulation time 9615785007 ps
CPU time 10.27 seconds
Started Jun 29 06:48:21 PM PDT 24
Finished Jun 29 06:48:32 PM PDT 24
Peak memory 240940 kb
Host smart-2ad2cfe1-ba19-4f40-aa35-1c32ac2dc195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728296740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1728296740
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3591625734
Short name T733
Test name
Test status
Simulation time 2195678180 ps
CPU time 3.47 seconds
Started Jun 29 06:48:24 PM PDT 24
Finished Jun 29 06:48:28 PM PDT 24
Peak memory 224420 kb
Host smart-ad702010-8ced-45e4-960f-13d1657ab26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591625734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3591625734
Directory /workspace/5.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4229441698
Short name T386
Test name
Test status
Simulation time 256780311 ps
CPU time 3.5 seconds
Started Jun 29 06:48:31 PM PDT 24
Finished Jun 29 06:48:35 PM PDT 24
Peak memory 220280 kb
Host smart-35884303-715a-4cb3-8947-570586390efc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4229441698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4229441698
Directory /workspace/5.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/5.spi_device_stress_all.3030003802
Short name T129
Test name
Test status
Simulation time 5971667903 ps
CPU time 57.39 seconds
Started Jun 29 06:48:32 PM PDT 24
Finished Jun 29 06:49:30 PM PDT 24
Peak memory 249212 kb
Host smart-b20b47ef-7cd2-4baa-b303-26324c37c39e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030003802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3030003802
Directory /workspace/5.spi_device_stress_all/latest


Test location /workspace/coverage/default/5.spi_device_tpm_all.776018594
Short name T754
Test name
Test status
Simulation time 9528283767 ps
CPU time 22.76 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:49 PM PDT 24
Peak memory 216280 kb
Host smart-c001a3ee-c824-4898-bc1e-ec1d2aa941dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776018594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.776018594
Directory /workspace/5.spi_device_tpm_all/latest


Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3190646599
Short name T744
Test name
Test status
Simulation time 295073327 ps
CPU time 1.47 seconds
Started Jun 29 06:48:24 PM PDT 24
Finished Jun 29 06:48:26 PM PDT 24
Peak memory 207828 kb
Host smart-83d94153-2c42-4166-a293-f1e50e1fa96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190646599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3190646599
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/5.spi_device_tpm_rw.1191244758
Short name T899
Test name
Test status
Simulation time 137961639 ps
CPU time 1.65 seconds
Started Jun 29 06:48:23 PM PDT 24
Finished Jun 29 06:48:25 PM PDT 24
Peak memory 216188 kb
Host smart-5f41316a-a804-4126-95e8-9598e6e3ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191244758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1191244758
Directory /workspace/5.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1577599197
Short name T323
Test name
Test status
Simulation time 116087539 ps
CPU time 0.96 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:26 PM PDT 24
Peak memory 205812 kb
Host smart-faaedfb7-55c6-4432-b542-c93431a51dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577599197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1577599197
Directory /workspace/5.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/5.spi_device_upload.400037715
Short name T314
Test name
Test status
Simulation time 483506033 ps
CPU time 2.18 seconds
Started Jun 29 06:48:25 PM PDT 24
Finished Jun 29 06:48:27 PM PDT 24
Peak memory 223788 kb
Host smart-7977e1ec-7848-47e9-92df-fd8ea1027be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400037715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.400037715
Directory /workspace/5.spi_device_upload/latest


Test location /workspace/coverage/default/6.spi_device_alert_test.1163857734
Short name T413
Test name
Test status
Simulation time 40218260 ps
CPU time 0.71 seconds
Started Jun 29 06:48:38 PM PDT 24
Finished Jun 29 06:48:39 PM PDT 24
Peak memory 205396 kb
Host smart-8eaa6505-62c4-4124-820d-5ff4021c6cf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163857734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
163857734
Directory /workspace/6.spi_device_alert_test/latest


Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3228682956
Short name T665
Test name
Test status
Simulation time 144331638 ps
CPU time 2.36 seconds
Started Jun 29 06:48:36 PM PDT 24
Finished Jun 29 06:48:39 PM PDT 24
Peak memory 223448 kb
Host smart-afbb07ef-49b2-4e10-b7d3-09341d84fd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228682956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3228682956
Directory /workspace/6.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/6.spi_device_csb_read.1255849633
Short name T72
Test name
Test status
Simulation time 17258647 ps
CPU time 0.76 seconds
Started Jun 29 06:48:34 PM PDT 24
Finished Jun 29 06:48:35 PM PDT 24
Peak memory 205856 kb
Host smart-b1771155-c6f7-4110-8b91-cdd79cfc9a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255849633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1255849633
Directory /workspace/6.spi_device_csb_read/latest


Test location /workspace/coverage/default/6.spi_device_flash_all.125461373
Short name T759
Test name
Test status
Simulation time 61763451701 ps
CPU time 228.77 seconds
Started Jun 29 06:48:31 PM PDT 24
Finished Jun 29 06:52:20 PM PDT 24
Peak memory 252188 kb
Host smart-cf551349-2bd7-4b9e-9a74-c66e3836d399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125461373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.125461373
Directory /workspace/6.spi_device_flash_all/latest


Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3930469078
Short name T575
Test name
Test status
Simulation time 39930262102 ps
CPU time 378.93 seconds
Started Jun 29 06:48:31 PM PDT 24
Finished Jun 29 06:54:50 PM PDT 24
Peak memory 253188 kb
Host smart-64849948-d69d-4ede-81f3-d15e53e1070b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930469078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3930469078
Directory /workspace/6.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3432358467
Short name T299
Test name
Test status
Simulation time 23564557944 ps
CPU time 33.49 seconds
Started Jun 29 06:48:31 PM PDT 24
Finished Jun 29 06:49:05 PM PDT 24
Peak memory 217656 kb
Host smart-46f2970f-4dc8-40c5-88a8-b88d811f2851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432358467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3432358467
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/6.spi_device_flash_mode.1600878522
Short name T294
Test name
Test status
Simulation time 445851758 ps
CPU time 7.8 seconds
Started Jun 29 06:48:34 PM PDT 24
Finished Jun 29 06:48:42 PM PDT 24
Peak memory 224504 kb
Host smart-1526ae16-1401-48f2-8bd8-bb81443c95b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600878522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1600878522
Directory /workspace/6.spi_device_flash_mode/latest


Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1784018295
Short name T182
Test name
Test status
Simulation time 38264774414 ps
CPU time 56.88 seconds
Started Jun 29 06:48:32 PM PDT 24
Finished Jun 29 06:49:29 PM PDT 24
Peak memory 238136 kb
Host smart-8832c156-5a6d-497b-bc4a-b306b46d00aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784018295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1784018295
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/6.spi_device_intercept.1211802034
Short name T577
Test name
Test status
Simulation time 189986008 ps
CPU time 5.93 seconds
Started Jun 29 06:48:31 PM PDT 24
Finished Jun 29 06:48:37 PM PDT 24
Peak memory 232636 kb
Host smart-df515841-ffe0-4dea-80d3-22498f0c46a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211802034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1211802034
Directory /workspace/6.spi_device_intercept/latest


Test location /workspace/coverage/default/6.spi_device_mailbox.2602257085
Short name T913
Test name
Test status
Simulation time 14961904993 ps
CPU time 41.58 seconds
Started Jun 29 06:48:31 PM PDT 24
Finished Jun 29 06:49:13 PM PDT 24
Peak memory 240464 kb
Host smart-66c2ede1-56de-4824-8805-24998fa03e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602257085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2602257085
Directory /workspace/6.spi_device_mailbox/latest


Test location /workspace/coverage/default/6.spi_device_mem_parity.1423952490
Short name T32
Test name
Test status
Simulation time 24472627 ps
CPU time 1.03 seconds
Started Jun 29 06:48:34 PM PDT 24
Finished Jun 29 06:48:36 PM PDT 24
Peak memory 216776 kb
Host smart-c27c36b0-ed4b-43be-9090-94ec074265ca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423952490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1423952490
Directory /workspace/6.spi_device_mem_parity/latest


Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2604156447
Short name T883
Test name
Test status
Simulation time 60799005 ps
CPU time 2.54 seconds
Started Jun 29 06:48:32 PM PDT 24
Finished Jun 29 06:48:35 PM PDT 24
Peak memory 232384 kb
Host smart-5a62970a-7aba-43ce-be21-300beb9ef5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604156447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2604156447
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3907480393
Short name T326
Test name
Test status
Simulation time 55536852 ps
CPU time 2.1 seconds
Started Jun 29 06:48:33 PM PDT 24
Finished Jun 29 06:48:36 PM PDT 24
Peak memory 224356 kb
Host smart-2b7f6ec1-9db6-4a33-92ad-cf4313d40790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907480393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3907480393
Directory /workspace/6.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2118989835
Short name T750
Test name
Test status
Simulation time 1026705219 ps
CPU time 11.15 seconds
Started Jun 29 06:48:32 PM PDT 24
Finished Jun 29 06:48:44 PM PDT 24
Peak memory 220544 kb
Host smart-b7b30c9e-7708-48c0-b445-33d51437c503
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2118989835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2118989835
Directory /workspace/6.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/6.spi_device_stress_all.2922104299
Short name T22
Test name
Test status
Simulation time 6543680437 ps
CPU time 88.88 seconds
Started Jun 29 06:48:30 PM PDT 24
Finished Jun 29 06:49:59 PM PDT 24
Peak memory 267296 kb
Host smart-1d43c041-5332-4be5-b8f1-9604eb6051ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922104299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2922104299
Directory /workspace/6.spi_device_stress_all/latest


Test location /workspace/coverage/default/6.spi_device_tpm_all.734213808
Short name T594
Test name
Test status
Simulation time 13491674878 ps
CPU time 39.87 seconds
Started Jun 29 06:48:29 PM PDT 24
Finished Jun 29 06:49:10 PM PDT 24
Peak memory 216348 kb
Host smart-c593606d-7f3a-41a9-9828-fa01c8a83390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734213808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.734213808
Directory /workspace/6.spi_device_tpm_all/latest


Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2624862462
Short name T500
Test name
Test status
Simulation time 4110517673 ps
CPU time 6.67 seconds
Started Jun 29 06:48:37 PM PDT 24
Finished Jun 29 06:48:44 PM PDT 24
Peak memory 216308 kb
Host smart-46b66e46-c872-4993-a5ae-aac22db59312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624862462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2624862462
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/6.spi_device_tpm_rw.3953454222
Short name T344
Test name
Test status
Simulation time 19820201 ps
CPU time 0.94 seconds
Started Jun 29 06:48:34 PM PDT 24
Finished Jun 29 06:48:35 PM PDT 24
Peak memory 207304 kb
Host smart-3a097b40-1aa6-4033-b35a-dafdbdca07fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953454222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3953454222
Directory /workspace/6.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3461576923
Short name T438
Test name
Test status
Simulation time 71138406 ps
CPU time 0.73 seconds
Started Jun 29 06:48:32 PM PDT 24
Finished Jun 29 06:48:33 PM PDT 24
Peak memory 205884 kb
Host smart-c17e60ea-9ecf-4247-b9ed-899c426d00c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461576923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3461576923
Directory /workspace/6.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/6.spi_device_upload.2876483883
Short name T985
Test name
Test status
Simulation time 17374513155 ps
CPU time 16.27 seconds
Started Jun 29 06:48:31 PM PDT 24
Finished Jun 29 06:48:47 PM PDT 24
Peak memory 232764 kb
Host smart-bf9e064c-fb73-4dc4-af0d-22ccef5ab2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876483883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2876483883
Directory /workspace/6.spi_device_upload/latest


Test location /workspace/coverage/default/7.spi_device_alert_test.1270593538
Short name T662
Test name
Test status
Simulation time 24131860 ps
CPU time 0.74 seconds
Started Jun 29 06:48:32 PM PDT 24
Finished Jun 29 06:48:33 PM PDT 24
Peak memory 205740 kb
Host smart-d204224b-0637-44e8-95ad-d5a87959079f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270593538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
270593538
Directory /workspace/7.spi_device_alert_test/latest


Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2414364268
Short name T858
Test name
Test status
Simulation time 249859438 ps
CPU time 5 seconds
Started Jun 29 06:48:33 PM PDT 24
Finished Jun 29 06:48:38 PM PDT 24
Peak memory 224436 kb
Host smart-f6deceb2-45df-4515-b8a3-9f1b800bf9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414364268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2414364268
Directory /workspace/7.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/7.spi_device_csb_read.1939988303
Short name T338
Test name
Test status
Simulation time 13129853 ps
CPU time 0.85 seconds
Started Jun 29 06:48:38 PM PDT 24
Finished Jun 29 06:48:39 PM PDT 24
Peak memory 205736 kb
Host smart-24fe5731-7549-458e-bdf1-106b22960053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939988303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1939988303
Directory /workspace/7.spi_device_csb_read/latest


Test location /workspace/coverage/default/7.spi_device_flash_all.2175270935
Short name T468
Test name
Test status
Simulation time 2403762970 ps
CPU time 31.01 seconds
Started Jun 29 06:48:38 PM PDT 24
Finished Jun 29 06:49:09 PM PDT 24
Peak memory 236604 kb
Host smart-258c688c-69e3-4cb5-8e8c-8b928fc9e782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175270935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2175270935
Directory /workspace/7.spi_device_flash_all/latest


Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3616123939
Short name T895
Test name
Test status
Simulation time 4858703296 ps
CPU time 49.2 seconds
Started Jun 29 06:48:32 PM PDT 24
Finished Jun 29 06:49:22 PM PDT 24
Peak memory 239376 kb
Host smart-79d448dd-73d7-4da4-8abe-195b79c6d110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616123939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3616123939
Directory /workspace/7.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.4214468909
Short name T727
Test name
Test status
Simulation time 18763913210 ps
CPU time 76.19 seconds
Started Jun 29 06:48:38 PM PDT 24
Finished Jun 29 06:49:55 PM PDT 24
Peak memory 254164 kb
Host smart-1cc4fff4-a1f0-4302-99d9-8380c6aed580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214468909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.4214468909
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/7.spi_device_flash_mode.1278877446
Short name T146
Test name
Test status
Simulation time 12946949886 ps
CPU time 28.26 seconds
Started Jun 29 06:48:33 PM PDT 24
Finished Jun 29 06:49:02 PM PDT 24
Peak memory 224588 kb
Host smart-798ded65-4863-44e0-bee3-2111a67456bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278877446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1278877446
Directory /workspace/7.spi_device_flash_mode/latest


Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4273265466
Short name T975
Test name
Test status
Simulation time 590557362602 ps
CPU time 338.32 seconds
Started Jun 29 06:48:30 PM PDT 24
Finished Jun 29 06:54:09 PM PDT 24
Peak memory 251952 kb
Host smart-262dbe11-f49b-4cec-9611-5916dfe4ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273265466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4273265466
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/7.spi_device_intercept.3282534450
Short name T725
Test name
Test status
Simulation time 744138288 ps
CPU time 7.99 seconds
Started Jun 29 06:48:33 PM PDT 24
Finished Jun 29 06:48:41 PM PDT 24
Peak memory 224436 kb
Host smart-2fbfa2cc-2e6e-4826-82d7-0666ccf98ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282534450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3282534450
Directory /workspace/7.spi_device_intercept/latest


Test location /workspace/coverage/default/7.spi_device_mailbox.1733785665
Short name T569
Test name
Test status
Simulation time 32237299 ps
CPU time 2.43 seconds
Started Jun 29 06:48:33 PM PDT 24
Finished Jun 29 06:48:36 PM PDT 24
Peak memory 232412 kb
Host smart-e564c357-84ea-4f95-9044-c823dc6b9502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733785665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1733785665
Directory /workspace/7.spi_device_mailbox/latest


Test location /workspace/coverage/default/7.spi_device_mem_parity.2734319125
Short name T480
Test name
Test status
Simulation time 33793305 ps
CPU time 1.03 seconds
Started Jun 29 06:48:31 PM PDT 24
Finished Jun 29 06:48:32 PM PDT 24
Peak memory 216740 kb
Host smart-09778abf-0bdb-43a5-aa62-00e1caef593b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734319125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2734319125
Directory /workspace/7.spi_device_mem_parity/latest


Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2476302206
Short name T517
Test name
Test status
Simulation time 121971823 ps
CPU time 2.55 seconds
Started Jun 29 06:48:37 PM PDT 24
Finished Jun 29 06:48:40 PM PDT 24
Peak memory 232380 kb
Host smart-da5af5d4-4764-4cb5-8d16-57e4d8ebf3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476302206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2476302206
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.948082300
Short name T841
Test name
Test status
Simulation time 30724038216 ps
CPU time 19.9 seconds
Started Jun 29 06:48:34 PM PDT 24
Finished Jun 29 06:48:54 PM PDT 24
Peak memory 240380 kb
Host smart-fd67dc90-6650-4431-a3af-b146f59653aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948082300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.948082300
Directory /workspace/7.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2333679124
Short name T144
Test name
Test status
Simulation time 5561750454 ps
CPU time 14.25 seconds
Started Jun 29 06:48:37 PM PDT 24
Finished Jun 29 06:48:52 PM PDT 24
Peak memory 220852 kb
Host smart-89f299fd-dc1b-4d98-ac81-2f2b1d0533d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2333679124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2333679124
Directory /workspace/7.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/7.spi_device_stress_all.1989109291
Short name T513
Test name
Test status
Simulation time 8273914501 ps
CPU time 58.69 seconds
Started Jun 29 06:48:33 PM PDT 24
Finished Jun 29 06:49:32 PM PDT 24
Peak memory 253184 kb
Host smart-78a486f2-31ea-4a20-85e1-e8567528d9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989109291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1989109291
Directory /workspace/7.spi_device_stress_all/latest


Test location /workspace/coverage/default/7.spi_device_tpm_all.4161832829
Short name T736
Test name
Test status
Simulation time 5812806765 ps
CPU time 30.89 seconds
Started Jun 29 06:48:37 PM PDT 24
Finished Jun 29 06:49:08 PM PDT 24
Peak memory 216348 kb
Host smart-bcba2bf2-859b-4bb2-969c-23a04baa07cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161832829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4161832829
Directory /workspace/7.spi_device_tpm_all/latest


Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4171295428
Short name T328
Test name
Test status
Simulation time 552322640 ps
CPU time 3.17 seconds
Started Jun 29 06:48:32 PM PDT 24
Finished Jun 29 06:48:36 PM PDT 24
Peak memory 216252 kb
Host smart-86f26ba4-fb52-46f9-9092-3756e449a75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171295428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4171295428
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/7.spi_device_tpm_rw.682605658
Short name T504
Test name
Test status
Simulation time 154266880 ps
CPU time 0.93 seconds
Started Jun 29 06:48:31 PM PDT 24
Finished Jun 29 06:48:32 PM PDT 24
Peak memory 205904 kb
Host smart-5b0c8e49-0c75-4ce9-84c6-c8aa6d7f501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682605658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.682605658
Directory /workspace/7.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2971729125
Short name T166
Test name
Test status
Simulation time 12816194 ps
CPU time 0.71 seconds
Started Jun 29 06:48:34 PM PDT 24
Finished Jun 29 06:48:35 PM PDT 24
Peak memory 205884 kb
Host smart-e62e0439-0bc0-43ef-91a9-59636575e821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971729125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2971729125
Directory /workspace/7.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/7.spi_device_upload.1018280758
Short name T768
Test name
Test status
Simulation time 9597599072 ps
CPU time 16.33 seconds
Started Jun 29 06:48:32 PM PDT 24
Finished Jun 29 06:48:49 PM PDT 24
Peak memory 232772 kb
Host smart-73f0d3a6-b9a1-4559-9cc0-b8e4d5fcbee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018280758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1018280758
Directory /workspace/7.spi_device_upload/latest


Test location /workspace/coverage/default/8.spi_device_alert_test.3320508065
Short name T801
Test name
Test status
Simulation time 71842941 ps
CPU time 0.75 seconds
Started Jun 29 06:48:42 PM PDT 24
Finished Jun 29 06:48:43 PM PDT 24
Peak memory 205416 kb
Host smart-dc3c729b-1cca-4b77-a09f-44788b8390e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320508065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
320508065
Directory /workspace/8.spi_device_alert_test/latest


Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2009452294
Short name T944
Test name
Test status
Simulation time 573534187 ps
CPU time 2.2 seconds
Started Jun 29 06:48:40 PM PDT 24
Finished Jun 29 06:48:43 PM PDT 24
Peak memory 224152 kb
Host smart-4473312b-6895-4a41-8ad1-b70e3877d6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009452294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2009452294
Directory /workspace/8.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/8.spi_device_csb_read.2844458013
Short name T311
Test name
Test status
Simulation time 48695748 ps
CPU time 0.78 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 06:48:48 PM PDT 24
Peak memory 206488 kb
Host smart-5f56f476-6c00-4b5f-aec2-cde937112c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844458013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2844458013
Directory /workspace/8.spi_device_csb_read/latest


Test location /workspace/coverage/default/8.spi_device_flash_all.3762826733
Short name T197
Test name
Test status
Simulation time 40145127287 ps
CPU time 80.09 seconds
Started Jun 29 06:48:43 PM PDT 24
Finished Jun 29 06:50:04 PM PDT 24
Peak memory 249128 kb
Host smart-830eaa2f-adbc-4df6-9ecc-d0b71fca24b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762826733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3762826733
Directory /workspace/8.spi_device_flash_all/latest


Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1616238769
Short name T579
Test name
Test status
Simulation time 2078825035 ps
CPU time 40 seconds
Started Jun 29 06:48:38 PM PDT 24
Finished Jun 29 06:49:19 PM PDT 24
Peak memory 252656 kb
Host smart-de473bd2-d36b-44bb-afc7-5fdc2fea79f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616238769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1616238769
Directory /workspace/8.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2946196356
Short name T973
Test name
Test status
Simulation time 5047636487 ps
CPU time 106.03 seconds
Started Jun 29 06:48:40 PM PDT 24
Finished Jun 29 06:50:27 PM PDT 24
Peak memory 255800 kb
Host smart-606af0ef-d720-420a-8d07-a99f25e4323f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946196356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2946196356
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/8.spi_device_flash_mode.480877723
Short name T289
Test name
Test status
Simulation time 1847449367 ps
CPU time 20.35 seconds
Started Jun 29 06:48:42 PM PDT 24
Finished Jun 29 06:49:03 PM PDT 24
Peak memory 240900 kb
Host smart-d4d4dd7c-0327-4415-9d44-34a9d659795c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480877723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.480877723
Directory /workspace/8.spi_device_flash_mode/latest


Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2537003220
Short name T779
Test name
Test status
Simulation time 36447722368 ps
CPU time 177.91 seconds
Started Jun 29 06:48:40 PM PDT 24
Finished Jun 29 06:51:39 PM PDT 24
Peak memory 255556 kb
Host smart-404cbfcb-93b5-457d-a941-4b5d375146cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537003220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2537003220
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/8.spi_device_intercept.3775052741
Short name T979
Test name
Test status
Simulation time 496570763 ps
CPU time 3.76 seconds
Started Jun 29 06:48:38 PM PDT 24
Finished Jun 29 06:48:43 PM PDT 24
Peak memory 232616 kb
Host smart-7d708d42-0a0b-42e1-b2a0-339dd80aab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775052741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3775052741
Directory /workspace/8.spi_device_intercept/latest


Test location /workspace/coverage/default/8.spi_device_mailbox.850929124
Short name T334
Test name
Test status
Simulation time 104455769 ps
CPU time 2.11 seconds
Started Jun 29 06:48:40 PM PDT 24
Finished Jun 29 06:48:43 PM PDT 24
Peak memory 223952 kb
Host smart-be6aef43-9870-4287-b388-fec59d2c246c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850929124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.850929124
Directory /workspace/8.spi_device_mailbox/latest


Test location /workspace/coverage/default/8.spi_device_mem_parity.1110864483
Short name T737
Test name
Test status
Simulation time 51650221 ps
CPU time 1.01 seconds
Started Jun 29 06:48:39 PM PDT 24
Finished Jun 29 06:48:40 PM PDT 24
Peak memory 218012 kb
Host smart-a6429df5-13f9-466f-91a5-50ca7a6b2425
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110864483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1110864483
Directory /workspace/8.spi_device_mem_parity/latest


Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1495289386
Short name T948
Test name
Test status
Simulation time 1325084857 ps
CPU time 5.78 seconds
Started Jun 29 06:48:39 PM PDT 24
Finished Jun 29 06:48:45 PM PDT 24
Peak memory 232660 kb
Host smart-c9867e88-99e7-4fd2-be06-d97f5ae6a19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495289386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1495289386
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3309392513
Short name T943
Test name
Test status
Simulation time 40381353584 ps
CPU time 28.69 seconds
Started Jun 29 06:48:48 PM PDT 24
Finished Jun 29 06:49:17 PM PDT 24
Peak memory 232792 kb
Host smart-a9713aa1-9e0c-4868-bf3e-3522e3da0bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309392513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3309392513
Directory /workspace/8.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1311191795
Short name T535
Test name
Test status
Simulation time 3075219525 ps
CPU time 6.13 seconds
Started Jun 29 06:48:39 PM PDT 24
Finished Jun 29 06:48:46 PM PDT 24
Peak memory 223328 kb
Host smart-def2a040-a448-4c58-9750-dbd157670387
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1311191795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1311191795
Directory /workspace/8.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/8.spi_device_stress_all.3331806491
Short name T953
Test name
Test status
Simulation time 9340540027 ps
CPU time 110.2 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 06:50:37 PM PDT 24
Peak memory 252684 kb
Host smart-17fac133-36ba-48d5-bc3e-0f9042f6bfee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331806491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3331806491
Directory /workspace/8.spi_device_stress_all/latest


Test location /workspace/coverage/default/8.spi_device_tpm_all.3156558613
Short name T711
Test name
Test status
Simulation time 1815672465 ps
CPU time 20.45 seconds
Started Jun 29 06:48:39 PM PDT 24
Finished Jun 29 06:49:00 PM PDT 24
Peak memory 216352 kb
Host smart-3e59b335-1479-4386-b25c-4db9891acdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156558613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3156558613
Directory /workspace/8.spi_device_tpm_all/latest


Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.496085982
Short name T390
Test name
Test status
Simulation time 264113129 ps
CPU time 2.38 seconds
Started Jun 29 06:48:40 PM PDT 24
Finished Jun 29 06:48:44 PM PDT 24
Peak memory 216256 kb
Host smart-210c19ad-1468-4978-87e9-fc2517a06dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496085982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.496085982
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/8.spi_device_tpm_rw.1528911306
Short name T904
Test name
Test status
Simulation time 139137204 ps
CPU time 4.68 seconds
Started Jun 29 06:48:44 PM PDT 24
Finished Jun 29 06:48:49 PM PDT 24
Peak memory 216188 kb
Host smart-70e8d15a-64b0-4285-8fb6-3608d6b16ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528911306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1528911306
Directory /workspace/8.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1081975180
Short name T607
Test name
Test status
Simulation time 136963304 ps
CPU time 1.04 seconds
Started Jun 29 06:48:47 PM PDT 24
Finished Jun 29 06:48:49 PM PDT 24
Peak memory 205892 kb
Host smart-3a442ed7-2a3c-4dff-9179-290f02c1fe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081975180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1081975180
Directory /workspace/8.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/8.spi_device_upload.2454563962
Short name T557
Test name
Test status
Simulation time 348184393 ps
CPU time 5.96 seconds
Started Jun 29 06:48:37 PM PDT 24
Finished Jun 29 06:48:44 PM PDT 24
Peak memory 232696 kb
Host smart-146d17f3-1868-4bfb-a347-ca65fa53be59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454563962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2454563962
Directory /workspace/8.spi_device_upload/latest


Test location /workspace/coverage/default/9.spi_device_alert_test.876070017
Short name T777
Test name
Test status
Simulation time 15586204 ps
CPU time 0.74 seconds
Started Jun 29 06:48:47 PM PDT 24
Finished Jun 29 06:48:48 PM PDT 24
Peak memory 205400 kb
Host smart-8b0417f9-6c6e-44f5-9325-1293b02fd259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876070017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.876070017
Directory /workspace/9.spi_device_alert_test/latest


Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2612423115
Short name T493
Test name
Test status
Simulation time 709684447 ps
CPU time 6.25 seconds
Started Jun 29 06:48:41 PM PDT 24
Finished Jun 29 06:48:48 PM PDT 24
Peak memory 224440 kb
Host smart-82ccff2c-ef8c-4af9-af57-abfefc614539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612423115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2612423115
Directory /workspace/9.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/9.spi_device_csb_read.1483923509
Short name T646
Test name
Test status
Simulation time 18330794 ps
CPU time 0.79 seconds
Started Jun 29 06:48:39 PM PDT 24
Finished Jun 29 06:48:40 PM PDT 24
Peak memory 205504 kb
Host smart-b87a4c78-22a3-4114-a755-ce7b727174e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483923509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1483923509
Directory /workspace/9.spi_device_csb_read/latest


Test location /workspace/coverage/default/9.spi_device_flash_all.1333869521
Short name T667
Test name
Test status
Simulation time 50513611 ps
CPU time 0.81 seconds
Started Jun 29 06:48:39 PM PDT 24
Finished Jun 29 06:48:40 PM PDT 24
Peak memory 215852 kb
Host smart-3d430e95-c447-44ef-98a6-724b36eaacd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333869521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1333869521
Directory /workspace/9.spi_device_flash_all/latest


Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3218612146
Short name T187
Test name
Test status
Simulation time 33759829202 ps
CPU time 274.77 seconds
Started Jun 29 06:48:43 PM PDT 24
Finished Jun 29 06:53:19 PM PDT 24
Peak memory 254228 kb
Host smart-cb6ce416-742d-410d-babd-f55de2d32381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218612146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3218612146
Directory /workspace/9.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.906530554
Short name T202
Test name
Test status
Simulation time 50927144639 ps
CPU time 188.94 seconds
Started Jun 29 06:48:38 PM PDT 24
Finished Jun 29 06:51:47 PM PDT 24
Peak memory 268416 kb
Host smart-a34d0167-db2d-41f2-a28b-23ecfa866b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906530554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
906530554
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/9.spi_device_flash_mode.986224187
Short name T934
Test name
Test status
Simulation time 759477603 ps
CPU time 6.46 seconds
Started Jun 29 06:48:41 PM PDT 24
Finished Jun 29 06:48:48 PM PDT 24
Peak memory 240888 kb
Host smart-d2bcef94-037e-4a9f-aeba-350806d587c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986224187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.986224187
Directory /workspace/9.spi_device_flash_mode/latest


Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3836414535
Short name T856
Test name
Test status
Simulation time 4426782529 ps
CPU time 46.18 seconds
Started Jun 29 06:48:48 PM PDT 24
Finished Jun 29 06:49:35 PM PDT 24
Peak memory 241012 kb
Host smart-71929e3c-c042-494e-a4fb-5b713fd01eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836414535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3836414535
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/9.spi_device_intercept.2604108616
Short name T634
Test name
Test status
Simulation time 568918374 ps
CPU time 3.31 seconds
Started Jun 29 06:48:42 PM PDT 24
Finished Jun 29 06:48:47 PM PDT 24
Peak memory 224440 kb
Host smart-fe4d9cef-3f38-48df-8b8a-4a84e7c7e38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604108616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2604108616
Directory /workspace/9.spi_device_intercept/latest


Test location /workspace/coverage/default/9.spi_device_mailbox.3438702877
Short name T905
Test name
Test status
Simulation time 461976826 ps
CPU time 2.36 seconds
Started Jun 29 06:48:40 PM PDT 24
Finished Jun 29 06:48:44 PM PDT 24
Peak memory 223880 kb
Host smart-1d3e6397-959d-4460-8b07-a860206343bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438702877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3438702877
Directory /workspace/9.spi_device_mailbox/latest


Test location /workspace/coverage/default/9.spi_device_mem_parity.4145009459
Short name T805
Test name
Test status
Simulation time 44878441 ps
CPU time 1.02 seconds
Started Jun 29 06:48:43 PM PDT 24
Finished Jun 29 06:48:45 PM PDT 24
Peak memory 217928 kb
Host smart-968c38be-f2b5-4da7-89e6-02a07dc7a312
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145009459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4145009459
Directory /workspace/9.spi_device_mem_parity/latest


Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2792283192
Short name T476
Test name
Test status
Simulation time 1794664689 ps
CPU time 6.09 seconds
Started Jun 29 06:48:42 PM PDT 24
Finished Jun 29 06:48:50 PM PDT 24
Peak memory 232596 kb
Host smart-6d232978-4fde-4f75-8409-d9e50ade96b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792283192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2792283192
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.186178866
Short name T243
Test name
Test status
Simulation time 3155086692 ps
CPU time 10.24 seconds
Started Jun 29 06:48:44 PM PDT 24
Finished Jun 29 06:48:55 PM PDT 24
Peak memory 224596 kb
Host smart-41773f24-86ba-4095-bc11-c035382bc45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186178866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.186178866
Directory /workspace/9.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4281312708
Short name T997
Test name
Test status
Simulation time 9370396519 ps
CPU time 7.74 seconds
Started Jun 29 06:48:44 PM PDT 24
Finished Jun 29 06:48:53 PM PDT 24
Peak memory 221576 kb
Host smart-fd49bb29-099d-48bc-bb99-57b466ce22de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4281312708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4281312708
Directory /workspace/9.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/9.spi_device_stress_all.3226853625
Short name T679
Test name
Test status
Simulation time 845895272 ps
CPU time 1.02 seconds
Started Jun 29 06:48:40 PM PDT 24
Finished Jun 29 06:48:42 PM PDT 24
Peak memory 206956 kb
Host smart-1a06c558-d8f0-481a-844e-67bd8153f79e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226853625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3226853625
Directory /workspace/9.spi_device_stress_all/latest


Test location /workspace/coverage/default/9.spi_device_tpm_all.396155744
Short name T673
Test name
Test status
Simulation time 655028068 ps
CPU time 2.3 seconds
Started Jun 29 06:48:46 PM PDT 24
Finished Jun 29 06:48:49 PM PDT 24
Peak memory 216356 kb
Host smart-ccaf6b13-0fd2-49a9-8d8f-0a7423e0fc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396155744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.396155744
Directory /workspace/9.spi_device_tpm_all/latest


Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1047788057
Short name T946
Test name
Test status
Simulation time 4468380979 ps
CPU time 15.33 seconds
Started Jun 29 06:48:40 PM PDT 24
Finished Jun 29 06:48:57 PM PDT 24
Peak memory 216324 kb
Host smart-0183b813-0d04-45b6-a68c-ac2f8df8bfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047788057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1047788057
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/9.spi_device_tpm_rw.1014921846
Short name T832
Test name
Test status
Simulation time 22184469 ps
CPU time 1.22 seconds
Started Jun 29 06:48:41 PM PDT 24
Finished Jun 29 06:48:43 PM PDT 24
Peak memory 207944 kb
Host smart-06fc667e-47a2-43ac-b5be-7cbc3695ad76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014921846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1014921846
Directory /workspace/9.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2674840362
Short name T85
Test name
Test status
Simulation time 80169967 ps
CPU time 0.76 seconds
Started Jun 29 06:48:42 PM PDT 24
Finished Jun 29 06:48:44 PM PDT 24
Peak memory 205880 kb
Host smart-adc3b7ed-ccb0-4ab4-8e35-d69c1afb9434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674840362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2674840362
Directory /workspace/9.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/9.spi_device_upload.1199297400
Short name T766
Test name
Test status
Simulation time 2549614458 ps
CPU time 10.01 seconds
Started Jun 29 06:48:41 PM PDT 24
Finished Jun 29 06:48:52 PM PDT 24
Peak memory 224560 kb
Host smart-fee1b21c-6a33-44f7-befc-ca9b10d924fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199297400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1199297400
Directory /workspace/9.spi_device_upload/latest
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