Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2429570	1			T1	1		T2	44		T3	228
all_values[1]	2429570	1			T1	1		T2	44		T3	228
all_values[2]	2429570	1			T1	1		T2	44		T3	228
all_values[3]	2429570	1			T1	1		T2	44		T3	228
all_values[4]	2429570	1			T1	1		T2	44		T3	228
all_values[5]	2429570	1			T1	1		T2	44		T3	228
all_values[6]	2429570	1			T1	1		T2	44		T3	228
all_values[7]	2429570	1			T1	1		T2	44		T3	228

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19049954

1

T1

8

T2

352

T3

1824

auto[1]

386606

1

T14

17

T15

16

T17

18118

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19409878

1

T1

8

T2

352

T3

1824

auto[1]

26682

1

T9

102

T11

25

T13

382

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2365730	1			T1	1		T2	44		T3	228
all_values[0]	auto[0]	auto[1]	11530	1			T9	87		T11	25		T13	226
all_values[0]	auto[1]	auto[0]	51642	1			T14	1		T15	1		T17	4
all_values[0]	auto[1]	auto[1]	668	1			T17	1		T62	92		T18	86
all_values[1]	auto[0]	auto[0]	2346462	1			T1	1		T2	44		T3	228
all_values[1]	auto[0]	auto[1]	8148	1			T9	15		T13	127		T14	66
all_values[1]	auto[1]	auto[0]	74373	1			T15	3		T17	4495		T62	4420
all_values[1]	auto[1]	auto[1]	587	1			T14	1		T17	33		T62	89
all_values[2]	auto[0]	auto[0]	2394984	1			T1	1		T2	44		T3	228
all_values[2]	auto[0]	auto[1]	3840	1			T13	29		T14	16		T15	11
all_values[2]	auto[1]	auto[0]	30558	1			T14	5		T15	1		T17	3
all_values[2]	auto[1]	auto[1]	188	1			T15	3		T17	2		T62	10
all_values[3]	auto[0]	auto[0]	2393146	1			T1	1		T2	44		T3	228
all_values[3]	auto[0]	auto[1]	166	1			T14	1		T17	2		T62	1
all_values[3]	auto[1]	auto[0]	36082	1			T14	3		T17	4522		T62	4508
all_values[3]	auto[1]	auto[1]	176	1			T17	3		T18	4		T19	6
all_values[4]	auto[0]	auto[0]	2397039	1			T1	1		T2	44		T3	228
all_values[4]	auto[0]	auto[1]	174	1			T14	2		T17	4		T18	4
all_values[4]	auto[1]	auto[0]	32154	1			T15	1		T17	4521		T62	4508
all_values[4]	auto[1]	auto[1]	203	1			T14	1		T17	2		T62	2
all_values[5]	auto[0]	auto[0]	2372397	1			T1	1		T2	44		T3	228
all_values[5]	auto[0]	auto[1]	151	1			T14	1		T17	1		T62	1
all_values[5]	auto[1]	auto[0]	56864	1			T14	4		T17	4524		T62	4507
all_values[5]	auto[1]	auto[1]	158	1			T15	2		T17	1		T62	1
all_values[6]	auto[0]	auto[0]	2394031	1			T1	1		T2	44		T3	228
all_values[6]	auto[0]	auto[1]	170	1			T17	4		T62	2		T18	6
all_values[6]	auto[1]	auto[0]	35202	1			T14	1		T15	1		T17	1
all_values[6]	auto[1]	auto[1]	167	1			T14	1		T15	3		T17	1
all_values[7]	auto[0]	auto[0]	2361808	1			T1	1		T2	44		T3	228
all_values[7]	auto[0]	auto[1]	178	1			T14	1		T15	2		T17	3
all_values[7]	auto[1]	auto[0]	67406	1			T15	1		T17	5		T62	4508
all_values[7]	auto[1]	auto[1]	178	1			T62	1		T18	3		T21	2