Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35183	1			T2	2		T5	4		T6	4
auto[SpiFlashAddrCfg]	7908	1			T9	35		T11	51		T13	45
auto[SpiFlashAddr3b]	9527	1			T2	2		T4	1		T9	54
auto[SpiFlashAddr4b]	7737	1			T2	8		T9	61		T11	45

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33558

1

T2

12

T4

1

T5

4

auto[1]

26797

1

T9

247

T11

156

T13

176

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32652

1

T2

4

T5

2

T6

4

auto[1]

27703

1

T2

8

T4

1

T5

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39774	1			T2	2		T5	4		T6	4
values[1]	1088	1			T2	2		T9	6		T11	5
values[2]	1471	1			T2	4		T9	10		T11	8
values[3]	1519	1			T9	8		T11	11		T13	6
values[4]	1592	1			T9	9		T11	4		T13	13
values[5]	1579	1			T2	2		T4	1		T9	5
values[6]	1542	1			T9	14		T11	7		T13	8
values[7]	1549	1			T2	2		T9	10		T11	17
values[8]	10241	1			T9	67		T11	60		T13	46

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35175

1

T2

12

T5

4

T6

4

auto[1]

25180

1

T4

1

T13

367

T14

493

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57094

1

T2

12

T4

1

T5

4

write

3261

1

T9

11

T11

7

T13

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19677

1

T2

8

T4

1

T6

4

valids[0x1]

40678

1

T2

4

T5

4

T9

270

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1570	1			T5	2		T9	7		T11	6
internal_process_ops[0x5a]	1608	1			T9	7		T11	5		T13	6
internal_process_ops[0x05]	21457	1			T5	2		T9	171		T11	80
internal_process_ops[0x35]	1480	1			T9	4		T11	7		T13	5
internal_process_ops[0x15]	1635	1			T2	2		T9	7		T11	4
internal_process_ops[0x03]	1143	1			T9	9		T11	10		T13	4
internal_process_ops[0x0b]	1139	1			T9	7		T11	8		T13	4
internal_process_ops[0x3b]	1144	1			T2	2		T4	1		T9	7
internal_process_ops[0x6b]	1167	1			T9	11		T11	6		T13	3
internal_process_ops[0xbb]	1114	1			T9	6		T11	7		T13	2
internal_process_ops[0xeb]	1156	1			T9	8		T11	12		T13	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58806

1

T2

12

T4

1

T5

4

auto[1]

1549

1

T9

7

T11

2

T13

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58023

1

T2

12

T4

1

T5

4

auto[1]

2332

1

T9

10

T11

8

T13

16

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12261

1

T2

2

T5

4

T6

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6984

1

T9

162

T11

78

T15

22

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2238

1

T9

14

T11

15

T23

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2130

1

T9

18

T11

35

T15

18

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2838

1

T2

2

T9

22

T11

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2552

1

T9

28

T11

23

T15

17

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2278

1

T2

8

T9

28

T11

29

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2068

1

T9

30

T11

15

T15

17

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T11

2

T45

1

T42

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

102

1

T31

1

T42

2

T43

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

133

1

T9

1

T11

2

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

144

1

T11

1

T28

2

T42

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

147

1

T31

2

T37

1

T45

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

78

1

T9

1

T15

1

T40

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

115

1

T11

1

T15

1

T31

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

97

1

T9

2

T31

1

T40

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

127

1

T9

1

T31

1

T43

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

94

1

T37

1

T40

1

T43

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

100

1

T9

2

T28

3

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

117

1

T9

1

T37

3

T42

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

146

1

T31

1

T37

1

T28

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

87

1

T31

1

T43

1

T82

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

120

1

T31

2

T37

5

T82

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

109

1

T9

3

T11

1

T27

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7955

1

T13

119

T14

185

T22

18

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7150

1

T13

124

T14

152

T22

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1395

1

T13

26

T14

20

T25

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1320

1

T13

17

T14

25

T22

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1682

1

T4

1

T13

17

T14

29

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1644

1

T13

13

T14

24

T22

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1318

1

T13

24

T14

21

T22

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1281

1

T13

19

T14

19

T22

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

99

1

T14

4

T18

3

T171

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

82

1

T13

2

T14

1

T62

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

77

1

T14

3

T16

2

T62

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

86

1

T78

2

T171

1

T141

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

92

1

T14

1

T16

3

T17

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

103

1

T16

3

T78

1

T171

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

97

1

T13

1

T17

2

T78

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

96

1

T13

1

T22

1

T172

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

69

1

T13

1

T14

1

T16

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

104

1

T13

2

T14

1

T18

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

107

1

T13

1

T14

2

T78

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

93

1

T17

1

T172

6

T138

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

78

1

T14

1

T16

1

T62

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

75

1

T14

3

T78

1

T139

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

95

1

T22

1

T16

1

T17

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

82

1

T14

1

T171

2

T172

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4115	1			T6	4		T9	33		T11	49
auto[0]	values[0]	valids[0x1]	18277	1			T2	2		T5	4		T9	221
auto[0]	values[1]	valids[0x1]	624	1			T2	2		T9	6		T11	5
auto[0]	values[2]	valids[0x0]	663	1			T2	4		T9	8		T11	7
auto[0]	values[2]	valids[0x1]	279	1			T9	2		T11	1		T15	1
auto[0]	values[3]	valids[0x0]	598	1			T9	7		T11	7		T15	3
auto[0]	values[3]	valids[0x1]	327	1			T9	1		T11	4		T15	1
auto[0]	values[4]	valids[0x0]	648	1			T9	7		T11	3		T31	8
auto[0]	values[4]	valids[0x1]	379	1			T9	2		T11	1		T15	1
auto[0]	values[5]	valids[0x0]	642	1			T2	2		T9	3		T11	4
auto[0]	values[5]	valids[0x1]	325	1			T9	2		T15	1		T31	5
auto[0]	values[6]	valids[0x0]	616	1			T9	9		T11	7		T31	6
auto[0]	values[6]	valids[0x1]	340	1			T9	5		T15	5		T31	2
auto[0]	values[7]	valids[0x0]	617	1			T2	2		T9	8		T11	11
auto[0]	values[7]	valids[0x1]	334	1			T9	2		T11	6		T23	2
auto[0]	values[8]	valids[0x0]	3989	1			T9	38		T11	36		T23	6
auto[0]	values[8]	valids[0x1]	2402	1			T9	29		T11	24		T15	19
auto[1]	values[0]	valids[0x0]	3389	1			T13	49		T14	56		T22	11
auto[1]	values[0]	valids[0x1]	13993	1			T13	215		T14	318		T22	16
auto[1]	values[1]	valids[0x1]	464	1			T13	1		T14	5		T16	2
auto[1]	values[2]	valids[0x0]	303	1			T13	2		T14	4		T16	2
auto[1]	values[2]	valids[0x1]	226	1			T13	9		T14	2		T22	1
auto[1]	values[3]	valids[0x0]	376	1			T13	6		T14	10		T16	1
auto[1]	values[3]	valids[0x1]	218	1			T14	8		T22	1		T18	3
auto[1]	values[4]	valids[0x0]	343	1			T13	10		T14	8		T22	4
auto[1]	values[4]	valids[0x1]	222	1			T13	3		T14	5		T22	1
auto[1]	values[5]	valids[0x0]	373	1			T4	1		T13	5		T14	1
auto[1]	values[5]	valids[0x1]	239	1			T13	6		T16	2		T17	2
auto[1]	values[6]	valids[0x0]	335	1			T13	3		T14	6		T22	1
auto[1]	values[6]	valids[0x1]	251	1			T13	5		T14	7		T22	3
auto[1]	values[7]	valids[0x0]	353	1			T13	7		T14	3		T22	3
auto[1]	values[7]	valids[0x1]	245	1			T14	15		T22	2		T62	1
auto[1]	values[8]	valids[0x0]	2317	1			T13	24		T14	27		T22	12
auto[1]	values[8]	valids[0x1]	1533	1			T13	22		T14	18		T22	4