Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3547025

1

T2

5553

T4

264

T5

12022

auto[1]

32504

1

T9

163

T11

73

T13

167

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1009346

1

T2

1

T4

264

T5

6024

auto[1]

2570183

1

T2

5552

T5

5998

T9

22278

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	773025	1			T2	5553		T4	35		T5	1158
auto[524288:1048575]	402629	1			T5	4061		T9	260		T11	520
auto[1048576:1572863]	376363	1			T4	4		T5	4550		T11	33
auto[1572864:2097151]	434976	1			T5	10		T9	9579		T11	528
auto[2097152:2621439]	380773	1			T5	863		T6	72		T9	2859
auto[2621440:3145727]	374977	1			T9	257		T11	3276		T12	180
auto[3145728:3670015]	412472	1			T9	513		T11	12		T12	1
auto[3670016:4194303]	424314	1			T4	225		T5	1380		T9	8708

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2605254

1

T2

5553

T4

10

T5

6017

auto[1]

974275

1

T4

254

T5

6005

T6

562

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3074640

1

T2

5553

T4

264

T5

12022

auto[1]

504889

1

T9

261

T11

34

T12

250

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	260256	1			T2	1		T4	35		T5	1158
auto[0]	auto[0]	auto[0:524287]	auto[1]	424470	1			T2	5552		T9	138		T11	258
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	111153	1			T5	1062		T9	1		T11	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	246582	1			T5	2999		T11	514		T13	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	88450	1			T4	4		T5	1575		T13	7
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	234799	1			T5	2975		T11	33		T13	6
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	128426	1			T5	10		T9	24		T11	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	236777	1			T9	9431		T11	519		T13	539
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	92373	1			T5	863		T6	72		T9	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	236674	1			T9	2854		T11	4272		T13	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	95699	1			T9	1		T11	8		T13	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	199393	1			T9	256		T11	3224		T13	513
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	118255	1			T11	3		T13	8		T14	13
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	214444	1			T9	512		T11	5		T13	841
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	101150	1			T4	225		T5	1356		T9	9
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	259501	1			T5	24		T9	8678		T11	2906
auto[0]	auto[1]	auto[0:524287]	auto[0]	1084	1			T9	1		T12	1		T14	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	81990	1			T13	354		T14	2		T37	2485
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	767	1			T9	3		T11	4		T12	64
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	40543	1			T9	256		T15	4		T28	1342
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1047	1			T12	3		T13	2		T14	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	46875	1			T13	2		T14	512		T15	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	782	1			T11	1		T14	1		T31	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	64649	1			T31	1290		T37	653		T16	513
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	979	1			T13	1		T15	4		T31	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	48084	1			T15	516		T40	512		T18	512
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	840	1			T11	3		T12	180		T13	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	76478	1			T11	1		T13	1		T14	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2043	1			T9	1		T11	1		T12	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	74437	1			T14	53		T22	256		T31	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2138	1			T12	1		T13	1		T14	12
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	55887	1			T13	1470		T14	257		T37	2521
auto[1]	auto[0]	auto[0:524287]	auto[0]	564	1			T9	2		T11	2		T13	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3848	1			T9	16		T11	15		T13	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	348	1			T13	2		T14	3		T31	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2861	1			T13	40		T14	27		T31	30
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	371	1			T13	2		T22	5		T15	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2632	1			T13	15		T15	2		T31	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	424	1			T9	5		T11	1		T13	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3283	1			T9	119		T11	2		T13	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	339	1			T13	1		T37	3		T28	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1801	1			T13	8		T28	4		T16	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	348	1			T11	1		T13	1		T14	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1609	1			T11	15		T13	10		T14	9
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	360	1			T11	2		T13	1		T14	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2220	1			T11	1		T13	14		T14	84
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	381	1			T9	3		T11	1		T13	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	4849	1			T9	18		T11	9		T13	53
auto[1]	auto[1]	auto[0:524287]	auto[0]	77	1			T14	2		T17	1		T42	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	736	1			T14	79		T17	6		T42	8
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	57	1			T16	1		T195	1		T46	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	318	1			T195	10		T163	10		T79	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	131	1			T13	1		T31	1		T42	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	2058	1			T31	10		T42	9		T43	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	88	1			T16	1		T42	1		T82	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	547	1			T42	1		T82	39		T138	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	104	1			T15	2		T37	3		T78	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	419	1			T15	2		T78	29		T82	118
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	102	1			T11	1		T13	1		T31	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	508	1			T11	23		T13	1		T31	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	146	1			T22	4		T37	14		T62	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	567	1			T62	25		T171	21		T201	10
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	64	1			T14	1		T138	2		T179	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	344	1			T138	4		T179	5		T196	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2078594	1			T2	5553		T4	10		T5	6017
auto[0]	auto[0]	auto[1]	969808	1			T4	254		T5	6005		T6	562
auto[0]	auto[1]	auto[0]	494799	1			T9	261		T11	10		T12	250
auto[0]	auto[1]	auto[1]	3824	1			T14	1		T31	1		T42	2
auto[1]	auto[0]	auto[0]	25717	1			T9	163		T11	45		T13	164
auto[1]	auto[0]	auto[1]	521	1			T11	4		T14	1		T22	2
auto[1]	auto[1]	auto[0]	6144	1			T11	23		T13	3		T14	81
auto[1]	auto[1]	auto[1]	122	1			T11	1		T14	1		T37	1