Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2429570	1			T1	1		T2	44		T3	228
all_pins[1]	2429570	1			T1	1		T2	44		T3	228
all_pins[2]	2429570	1			T1	1		T2	44		T3	228
all_pins[3]	2429570	1			T1	1		T2	44		T3	228
all_pins[4]	2429570	1			T1	1		T2	44		T3	228
all_pins[5]	2429570	1			T1	1		T2	44		T3	228
all_pins[6]	2429570	1			T1	1		T2	44		T3	228
all_pins[7]	2429570	1			T1	1		T2	44		T3	228

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19396506	1			T1	8		T2	352		T3	1824
values[0x1]	40054	1			T14	3		T15	8		T17	577
transitions[0x0=>0x1]	38280	1			T14	3		T15	7		T17	575
transitions[0x1=>0x0]	38291	1			T14	3		T15	7		T17	575

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2428849	1			T1	1		T2	44		T3	228
all_pins[0]	values[0x1]	721	1			T17	1		T62	99		T18	92
all_pins[0]	transitions[0x0=>0x1]	301	1			T17	1		T62	5		T18	19
all_pins[0]	transitions[0x1=>0x0]	214	1			T14	1		T17	35		T18	2
all_pins[1]	values[0x0]	2428936	1			T1	1		T2	44		T3	228
all_pins[1]	values[0x1]	634	1			T14	1		T17	35		T62	94
all_pins[1]	transitions[0x0=>0x1]	565	1			T14	1		T17	34		T62	82
all_pins[1]	transitions[0x1=>0x0]	126	1			T15	3		T17	1		T18	1
all_pins[2]	values[0x0]	2429375	1			T1	1		T2	44		T3	228
all_pins[2]	values[0x1]	195	1			T15	3		T17	2		T62	12
all_pins[2]	transitions[0x0=>0x1]	151	1			T15	3		T17	1		T62	12
all_pins[2]	transitions[0x1=>0x0]	132	1			T17	2		T18	4		T19	4
all_pins[3]	values[0x0]	2429394	1			T1	1		T2	44		T3	228
all_pins[3]	values[0x1]	176	1			T17	3		T18	4		T19	6
all_pins[3]	transitions[0x0=>0x1]	121	1			T17	3		T18	3		T19	5
all_pins[3]	transitions[0x1=>0x0]	148	1			T14	1		T17	2		T62	2
all_pins[4]	values[0x0]	2429367	1			T1	1		T2	44		T3	228
all_pins[4]	values[0x1]	203	1			T14	1		T17	2		T62	2
all_pins[4]	transitions[0x0=>0x1]	161	1			T14	1		T17	2		T62	2
all_pins[4]	transitions[0x1=>0x0]	2893	1			T15	2		T17	533		T62	444
all_pins[5]	values[0x0]	2426635	1			T1	1		T2	44		T3	228
all_pins[5]	values[0x1]	2935	1			T15	2		T17	533		T62	444
all_pins[5]	transitions[0x0=>0x1]	1878	1			T15	1		T17	533		T62	2
all_pins[5]	transitions[0x1=>0x0]	33955	1			T14	1		T15	2		T17	1
all_pins[6]	values[0x0]	2394558	1			T1	1		T2	44		T3	228
all_pins[6]	values[0x1]	35012	1			T14	1		T15	3		T17	1
all_pins[6]	transitions[0x0=>0x1]	34974	1			T14	1		T15	3		T17	1
all_pins[6]	transitions[0x1=>0x0]	140	1			T62	1		T18	3		T21	1
all_pins[7]	values[0x0]	2429392	1			T1	1		T2	44		T3	228
all_pins[7]	values[0x1]	178	1			T62	1		T18	3		T21	2
all_pins[7]	transitions[0x0=>0x1]	129	1			T18	1		T21	2		T29	2
all_pins[7]	transitions[0x1=>0x0]	683	1			T17	1		T62	99		T18	90