Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20506

1

T2

12

T5

4

T6

4

auto[1]

14669

1

T9

247

T11

156

T15

75

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3672	1			T9	35		T15	44		T31	72
values[1]	4208	1			T9	40		T15	22		T31	87
values[2]	4289	1			T11	115		T15	22		T31	20
values[3]	4344	1			T6	4		T9	20		T11	41
values[4]	4283	1			T9	42		T11	76		T12	16
values[5]	4906	1			T9	179		T15	43		T27	28
values[6]	4684	1			T5	4		T9	67		T11	20
values[7]	4789	1			T2	12		T11	41		T24	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3858	1			T9	55		T15	46		T31	99
values[1]	4554	1			T11	20		T24	12		T15	43
values[2]	3895	1			T9	70		T11	76		T31	185
values[3]	4180	1			T9	42		T11	23		T23	12
values[4]	4525	1			T2	12		T6	4		T9	20
values[5]	4621	1			T9	131		T11	61		T31	20
values[6]	4627	1			T9	40		T37	80		T45	31
values[7]	4915	1			T5	4		T9	25		T11	41

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	323	1			T9	26		T184	2		T40	28
auto[0]	values[0]	values[1]	297	1			T15	10		T28	15		T196	11
auto[0]	values[0]	values[2]	312	1			T31	53		T231	6		T33	5
auto[0]	values[0]	values[3]	196	1			T15	10		T42	5		T209	24
auto[0]	values[0]	values[4]	112	1			T202	10		T232	23		T233	5
auto[0]	values[0]	values[5]	188	1			T220	8		T180	12		T234	12
auto[0]	values[0]	values[6]	256	1			T37	9		T42	18		T198	10
auto[0]	values[0]	values[7]	452	1			T42	10		T43	14		T189	15
auto[0]	values[1]	values[0]	245	1			T230	5		T21	13		T235	8
auto[0]	values[1]	values[1]	263	1			T40	15		T33	12		T20	8
auto[0]	values[1]	values[2]	286	1			T31	79		T210	16		T218	10
auto[0]	values[1]	values[3]	461	1			T15	9		T43	12		T82	35
auto[0]	values[1]	values[4]	431	1			T9	8		T43	25		T82	35
auto[0]	values[1]	values[5]	232	1			T28	17		T104	2		T40	12
auto[0]	values[1]	values[6]	313	1			T9	4		T45	15		T136	2
auto[0]	values[1]	values[7]	246	1			T45	40		T43	17		T57	11
auto[0]	values[2]	values[0]	114	1			T31	9		T37	8		T82	24
auto[0]	values[2]	values[1]	276	1			T37	12		T28	9		T40	13
auto[0]	values[2]	values[2]	225	1			T11	6		T94	10		T189	13
auto[0]	values[2]	values[3]	538	1			T11	10		T38	38		T82	212
auto[0]	values[2]	values[4]	260	1			T11	26		T37	9		T28	22
auto[0]	values[2]	values[5]	247	1			T236	12		T189	25		T201	6
auto[0]	values[2]	values[6]	265	1			T42	8		T21	8		T30	10
auto[0]	values[2]	values[7]	401	1			T15	6		T32	4		T226	12
auto[0]	values[3]	values[0]	254	1			T31	13		T37	9		T28	6
auto[0]	values[3]	values[1]	315	1			T37	6		T82	22		T237	6
auto[0]	values[3]	values[2]	304	1			T31	9		T28	17		T40	12
auto[0]	values[3]	values[3]	294	1			T23	12		T37	7		T238	12
auto[0]	values[3]	values[4]	222	1			T6	4		T40	9		T194	4
auto[0]	values[3]	values[5]	361	1			T11	27		T230	7		T202	171
auto[0]	values[3]	values[6]	219	1			T9	14		T37	10		T40	12
auto[0]	values[3]	values[7]	393	1			T40	38		T21	13		T201	15
auto[0]	values[4]	values[0]	401	1			T40	14		T239	18		T34	20
auto[0]	values[4]	values[1]	263	1			T40	22		T21	14		T240	12
auto[0]	values[4]	values[2]	291	1			T9	12		T11	10		T37	13
auto[0]	values[4]	values[3]	484	1			T43	18		T82	7		T33	9
auto[0]	values[4]	values[4]	369	1			T11	11		T43	9		T186	20
auto[0]	values[4]	values[5]	214	1			T11	14		T96	10		T197	10
auto[0]	values[4]	values[6]	283	1			T37	10		T82	15		T94	6
auto[0]	values[4]	values[7]	279	1			T12	16		T40	13		T82	12
auto[0]	values[5]	values[0]	294	1			T9	10		T15	18		T91	20
auto[0]	values[5]	values[1]	349	1			T15	13		T224	16		T45	14
auto[0]	values[5]	values[2]	340	1			T9	13		T42	74		T241	2
auto[0]	values[5]	values[3]	240	1			T185	10		T40	14		T33	11
auto[0]	values[5]	values[4]	297	1			T37	15		T20	30		T163	11
auto[0]	values[5]	values[5]	439	1			T9	14		T31	11		T220	13
auto[0]	values[5]	values[6]	433	1			T187	8		T43	10		T33	36
auto[0]	values[5]	values[7]	572	1			T20	65		T201	12		T30	124
auto[0]	values[6]	values[0]	252	1			T15	16		T31	51		T43	8
auto[0]	values[6]	values[1]	628	1			T11	13		T42	38		T33	5
auto[0]	values[6]	values[2]	222	1			T37	12		T94	10		T164	44
auto[0]	values[6]	values[3]	200	1			T9	24		T19	24		T221	12
auto[0]	values[6]	values[4]	419	1			T94	13		T196	10		T202	81
auto[0]	values[6]	values[5]	312	1			T230	8		T33	9		T20	8
auto[0]	values[6]	values[6]	298	1			T79	11		T205	62		T242	18
auto[0]	values[6]	values[7]	349	1			T5	4		T9	11		T31	8
auto[0]	values[7]	values[0]	331	1			T134	6		T82	14		T20	7
auto[0]	values[7]	values[1]	321	1			T24	12		T38	5		T30	6
auto[0]	values[7]	values[2]	341	1			T43	13		T243	16		T201	38
auto[0]	values[7]	values[3]	469	1			T82	22		T201	11		T225	11
auto[0]	values[7]	values[4]	477	1			T2	12		T31	29		T82	35
auto[0]	values[7]	values[5]	432	1			T43	10		T20	10		T94	9
auto[0]	values[7]	values[6]	231	1			T37	17		T43	17		T82	10
auto[0]	values[7]	values[7]	375	1			T11	20		T42	12		T82	76
auto[1]	values[0]	values[0]	184	1			T9	9		T40	12		T94	18
auto[1]	values[0]	values[1]	243	1			T15	10		T28	5		T196	15
auto[1]	values[0]	values[2]	207	1			T31	19		T33	15		T142	15
auto[1]	values[0]	values[3]	138	1			T15	14		T42	15		T43	15
auto[1]	values[0]	values[4]	118	1			T202	10		T232	19		T233	15
auto[1]	values[0]	values[5]	135	1			T220	12		T242	5		T222	25
auto[1]	values[0]	values[6]	326	1			T37	11		T42	2		T21	14
auto[1]	values[0]	values[7]	185	1			T42	22		T43	9		T189	5
auto[1]	values[1]	values[0]	217	1			T230	15		T21	7		T244	35
auto[1]	values[1]	values[1]	181	1			T40	12		T33	8		T20	12
auto[1]	values[1]	values[2]	194	1			T31	8		T218	18		T245	6
auto[1]	values[1]	values[3]	242	1			T15	13		T43	8		T82	4
auto[1]	values[1]	values[4]	256	1			T9	12		T43	24		T82	9
auto[1]	values[1]	values[5]	157	1			T28	10		T40	8		T196	7
auto[1]	values[1]	values[6]	360	1			T9	16		T45	16		T21	7
auto[1]	values[1]	values[7]	124	1			T45	13		T43	9		T57	13
auto[1]	values[2]	values[0]	194	1			T31	11		T37	12		T82	14
auto[1]	values[2]	values[1]	195	1			T37	8		T28	12		T40	7
auto[1]	values[2]	values[2]	156	1			T11	50		T94	10		T189	7
auto[1]	values[2]	values[3]	205	1			T11	13		T38	2		T82	17
auto[1]	values[2]	values[4]	275	1			T11	10		T37	11		T28	20
auto[1]	values[2]	values[5]	362	1			T189	8		T201	14		T30	25
auto[1]	values[2]	values[6]	372	1			T42	84		T21	14		T30	28
auto[1]	values[2]	values[7]	204	1			T15	16		T20	9		T21	15
auto[1]	values[3]	values[0]	178	1			T31	7		T37	11		T28	14
auto[1]	values[3]	values[1]	187	1			T37	14		T82	11		T164	6
auto[1]	values[3]	values[2]	229	1			T31	17		T28	3		T40	51
auto[1]	values[3]	values[3]	183	1			T37	13		T230	5		T220	11
auto[1]	values[3]	values[4]	449	1			T40	34		T42	41		T38	39
auto[1]	values[3]	values[5]	316	1			T11	14		T230	17		T202	10
auto[1]	values[3]	values[6]	286	1			T9	6		T37	10		T40	8
auto[1]	values[3]	values[7]	154	1			T40	8		T21	7		T201	6
auto[1]	values[4]	values[0]	214	1			T40	10		T34	11		T47	12
auto[1]	values[4]	values[1]	369	1			T40	8		T21	6		T246	12
auto[1]	values[4]	values[2]	169	1			T9	30		T11	10		T37	7
auto[1]	values[4]	values[3]	122	1			T43	2		T82	13		T33	11
auto[1]	values[4]	values[4]	264	1			T11	25		T43	35		T196	54
auto[1]	values[4]	values[5]	204	1			T11	6		T43	34		T47	21
auto[1]	values[4]	values[6]	167	1			T37	10		T82	5		T94	14
auto[1]	values[4]	values[7]	190	1			T40	7		T82	8		T33	10
auto[1]	values[5]	values[0]	215	1			T9	10		T15	2		T82	7
auto[1]	values[5]	values[1]	253	1			T15	10		T45	6		T201	62
auto[1]	values[5]	values[2]	160	1			T9	15		T42	19		T189	7
auto[1]	values[5]	values[3]	124	1			T40	6		T33	13		T227	9
auto[1]	values[5]	values[4]	164	1			T27	28		T37	5		T20	11
auto[1]	values[5]	values[5]	409	1			T9	117		T31	9		T41	28
auto[1]	values[5]	values[6]	353	1			T43	12		T33	13		T220	14
auto[1]	values[5]	values[7]	264	1			T20	9		T201	52		T30	6
auto[1]	values[6]	values[0]	147	1			T15	10		T31	8		T43	12
auto[1]	values[6]	values[1]	220	1			T11	7		T42	6		T33	15
auto[1]	values[6]	values[2]	250	1			T37	8		T94	10		T164	6
auto[1]	values[6]	values[3]	118	1			T9	18		T204	22		T19	18
auto[1]	values[6]	values[4]	276	1			T94	7		T196	10		T202	13
auto[1]	values[6]	values[5]	360	1			T230	26		T33	12		T20	12
auto[1]	values[6]	values[6]	215	1			T79	15		T205	6		T242	3
auto[1]	values[6]	values[7]	418	1			T9	14		T31	12		T20	16
auto[1]	values[7]	values[0]	295	1			T82	6		T20	19		T21	16
auto[1]	values[7]	values[1]	194	1			T38	15		T30	14		T225	11
auto[1]	values[7]	values[2]	209	1			T43	13		T201	8		T142	9
auto[1]	values[7]	values[3]	166	1			T82	11		T201	9		T225	33
auto[1]	values[7]	values[4]	136	1			T31	8		T82	10		T33	10
auto[1]	values[7]	values[5]	253	1			T43	10		T20	10		T94	11
auto[1]	values[7]	values[6]	250	1			T37	3		T43	3		T82	10
auto[1]	values[7]	values[7]	309	1			T11	21		T42	8		T82	7