Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	436	1			T9	3		T11	2		T24	4
auto[ReadAddrCrossIntoMailbox]	371	1			T9	4		T11	2		T24	4
auto[ReadAddrCrossOutOfMailbox]	326	1			T9	3		T11	3		T24	2
auto[ReadAddrCrossAllMailbox]	254	1			T9	4		T11	1		T15	3
auto[ReadAddrOutsideMailbox]	3950	1			T2	2		T9	34		T11	38

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2630

1

T2

1

T9

24

T11

22

auto[1]

2707

1

T2

1

T9

24

T11

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	895	1			T9	9		T11	10		T15	10
read_ops[0x0b]	897	1			T9	7		T11	8		T15	7
read_ops[0x3b]	889	1			T2	2		T9	7		T11	3
read_ops[0x6b]	891	1			T9	11		T11	6		T24	4
read_ops[0xbb]	865	1			T9	6		T11	7		T24	4
read_ops[0xeb]	900	1			T9	8		T11	12		T24	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T37	1		T28	1		T94	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T9	1		T31	2		T40	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T15	1		T37	3		T202	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T9	1		T31	1		T42	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T15	2		T82	1		T202	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T9	1		T31	3		T40	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T15	1		T28	1		T40	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T9	1		T40	1		T42	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	320	1			T9	4		T11	3		T15	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	331	1			T9	1		T11	7		T15	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T31	1		T38	1		T33	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T11	1		T31	1		T40	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T9	1		T28	1		T43	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	40	1			T11	1		T31	1		T37	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T21	1		T189	1		T30	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T33	1		T20	1		T79	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T15	1		T31	1		T43	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T82	1		T79	1		T247	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	341	1			T9	4		T11	2		T15	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	340	1			T9	2		T11	4		T15	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T40	1		T91	1		T43	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T31	2		T28	1		T91	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T24	1		T15	1		T37	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T24	1		T37	1		T43	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T28	1		T38	1		T82	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T15	1		T31	1		T94	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T9	1		T28	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T9	1		T231	1		T82	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	341	1			T2	1		T9	4		T11	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T2	1		T9	1		T31	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T24	1		T15	1		T37	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T9	2		T24	1		T38	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T24	1		T31	1		T42	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T9	1		T24	1		T15	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T9	1		T15	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T9	1		T82	1		T230	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T31	1		T28	1		T94	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T30	1		T163	1		T242	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	336	1			T9	3		T11	5		T15	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T9	3		T11	1		T15	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T24	1		T40	2		T82	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T11	1		T24	1		T40	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T38	1		T223	3		T94	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T9	1		T15	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T15	1		T40	1		T42	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T11	1		T15	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T15	1		T37	1		T201	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	31	1			T31	1		T43	1		T82	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	320	1			T9	3		T11	4		T24	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	310	1			T9	2		T11	1		T24	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T185	1		T82	1		T20	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T15	1		T37	1		T185	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T11	1		T15	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T28	2		T45	1		T40	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T11	2		T24	1		T15	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T24	1		T15	1		T31	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T40	1		T42	1		T220	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T9	1		T11	1		T37	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	322	1			T9	3		T11	2		T31	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	354	1			T9	4		T11	6		T224	2