Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4812	1			T9	80		T11	20		T15	20
values[1]	4583	1			T11	77		T15	43		T31	46
values[2]	4116	1			T9	20		T11	40		T15	46
values[3]	4119	1			T5	4		T9	42		T11	21
values[4]	4430	1			T9	70		T11	56		T15	22
values[5]	4059	1			T6	4		T9	131		T24	12
values[6]	5022	1			T2	12		T9	20		T11	56
values[7]	4034	1			T9	20		T11	23		T23	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3761	1			T9	151		T11	56		T31	40
values[1]	3944	1			T9	62		T11	20		T15	44
values[2]	4912	1			T5	4		T9	25		T11	40
values[3]	4193	1			T9	20		T24	12		T15	40
values[4]	4383	1			T6	4		T9	20		T15	24
values[5]	4061	1			T2	12		T9	22		T11	77
values[6]	4755	1			T9	48		T11	44		T15	26
values[7]	5166	1			T9	35		T11	56		T23	12

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34347

1

T2

12

T5

4

T6

4

auto[1]

828

1

T9

7

T11

2

T15

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	289	1			T230	44		T227	20		T80	47
auto[0]	values[0]	values[1]	528	1			T9	18		T197	10		T134	6
auto[0]	values[0]	values[2]	706	1			T9	23		T37	20		T21	20
auto[0]	values[0]	values[3]	434	1			T15	20		T28	45		T82	20
auto[0]	values[0]	values[4]	828	1			T42	54		T43	41		T20	20
auto[0]	values[0]	values[5]	490	1			T31	87		T104	2		T19	21
auto[0]	values[0]	values[6]	785	1			T40	42		T230	19		T19	21
auto[0]	values[0]	values[7]	625	1			T9	35		T11	20		T40	20
auto[0]	values[1]	values[0]	804	1			T11	36		T31	19		T199	19
auto[0]	values[1]	values[1]	556	1			T20	20		T21	20		T189	41
auto[0]	values[1]	values[2]	380	1			T11	20		T184	2		T248	12
auto[0]	values[1]	values[3]	384	1			T15	20		T30	20		T218	20
auto[0]	values[1]	values[4]	386	1			T21	27		T249	2		T202	25
auto[0]	values[1]	values[5]	321	1			T15	22		T182	24		T47	22
auto[0]	values[1]	values[6]	582	1			T11	21		T31	26		T226	12
auto[0]	values[1]	values[7]	1063	1			T231	6		T43	63		T20	41
auto[0]	values[2]	values[0]	479	1			T28	22		T94	40		T225	51
auto[0]	values[2]	values[1]	435	1			T11	20		T15	22		T236	12
auto[0]	values[2]	values[2]	446	1			T11	19		T91	20		T43	21
auto[0]	values[2]	values[3]	643	1			T9	20		T28	40		T42	46
auto[0]	values[2]	values[4]	365	1			T15	24		T37	20		T202	20
auto[0]	values[2]	values[5]	438	1			T31	19		T82	20		T136	2
auto[0]	values[2]	values[6]	411	1			T33	44		T189	55		T163	20
auto[0]	values[2]	values[7]	793	1			T31	95		T43	23		T241	2
auto[0]	values[3]	values[0]	436	1			T201	21		T142	19		T79	26
auto[0]	values[3]	values[1]	435	1			T9	42		T37	20		T47	23
auto[0]	values[3]	values[2]	822	1			T5	4		T12	16		T45	28
auto[0]	values[3]	values[3]	404	1			T28	21		T21	20		T250	6
auto[0]	values[3]	values[4]	678	1			T40	46		T82	38		T20	25
auto[0]	values[3]	values[5]	475	1			T11	21		T194	4		T43	39
auto[0]	values[3]	values[6]	479	1			T15	26		T33	42		T94	20
auto[0]	values[3]	values[7]	299	1			T37	20		T220	20		T21	20
auto[0]	values[4]	values[0]	358	1			T9	20		T11	20		T31	20
auto[0]	values[4]	values[1]	527	1			T15	22		T209	24		T43	20
auto[0]	values[4]	values[2]	519	1			T43	25		T82	45		T33	19
auto[0]	values[4]	values[3]	424	1			T40	24		T187	8		T94	20
auto[0]	values[4]	values[4]	456	1			T82	39		T33	28		T20	26
auto[0]	values[4]	values[5]	703	1			T9	22		T28	20		T96	10
auto[0]	values[4]	values[6]	671	1			T9	28		T31	25		T37	18
auto[0]	values[4]	values[7]	671	1			T11	36		T45	31		T42	35
auto[0]	values[5]	values[0]	510	1			T9	128		T21	21		T225	44
auto[0]	values[5]	values[1]	360	1			T201	77		T142	20		T233	20
auto[0]	values[5]	values[2]	540	1			T37	20		T40	62		T133	14
auto[0]	values[5]	values[3]	415	1			T24	12		T40	20		T42	20
auto[0]	values[5]	values[4]	373	1			T6	4		T40	20		T42	20
auto[0]	values[5]	values[5]	491	1			T30	32		T218	28		T244	20
auto[0]	values[5]	values[6]	789	1			T45	20		T40	20		T230	24
auto[0]	values[5]	values[7]	489	1			T45	25		T251	4		T252	8
auto[0]	values[6]	values[0]	283	1			T40	27		T79	20		T227	38
auto[0]	values[6]	values[1]	692	1			T37	20		T189	20		T201	29
auto[0]	values[6]	values[2]	839	1			T82	19		T94	20		T196	20
auto[0]	values[6]	values[3]	747	1			T37	20		T82	248		T33	19
auto[0]	values[6]	values[4]	663	1			T40	20		T20	17		T21	27
auto[0]	values[6]	values[5]	640	1			T2	12		T11	55		T37	18
auto[0]	values[6]	values[6]	402	1			T9	20		T37	20		T82	32
auto[0]	values[6]	values[7]	640	1			T42	20		T30	93		T142	20
auto[0]	values[7]	values[0]	511	1			T224	16		T38	18		T238	12
auto[0]	values[7]	values[1]	333	1			T185	10		T198	10		T220	19
auto[0]	values[7]	values[2]	530	1			T43	19		T196	20		T188	22
auto[0]	values[7]	values[3]	648	1			T27	26		T31	47		T42	44
auto[0]	values[7]	values[4]	530	1			T9	20		T31	20		T40	20
auto[0]	values[7]	values[5]	395	1			T37	20		T41	24		T42	59
auto[0]	values[7]	values[6]	524	1			T11	23		T37	18		T21	19
auto[0]	values[7]	values[7]	475	1			T23	12		T32	4		T37	19
auto[1]	values[0]	values[0]	8	1			T80	1		T253	4		T254	1
auto[1]	values[0]	values[1]	10	1			T9	2		T20	2		T57	1
auto[1]	values[0]	values[2]	23	1			T9	2		T163	2		T79	2
auto[1]	values[0]	values[3]	11	1			T28	2		T30	2		T79	2
auto[1]	values[0]	values[4]	21	1			T42	4		T43	3		T202	3
auto[1]	values[0]	values[5]	11	1			T189	3		T222	4		T206	1
auto[1]	values[0]	values[6]	23	1			T40	1		T230	1		T189	3
auto[1]	values[0]	values[7]	20	1			T42	1		T230	2		T30	2
auto[1]	values[1]	values[0]	22	1			T31	1		T199	1		T80	5
auto[1]	values[1]	values[1]	14	1			T189	2		T201	1		T255	3
auto[1]	values[1]	values[2]	12	1			T192	1		T233	3		T256	2
auto[1]	values[1]	values[3]	2	1			T257	1		T256	1		-	-
auto[1]	values[1]	values[4]	9	1			T164	1		T258	2		T208	1
auto[1]	values[1]	values[5]	13	1			T15	1		T259	1		T260	1
auto[1]	values[1]	values[6]	14	1			T29	1		T163	2		T218	1
auto[1]	values[1]	values[7]	21	1			T43	2		T142	3		T227	1
auto[1]	values[2]	values[0]	18	1			T225	3		T192	1		T34	2
auto[1]	values[2]	values[1]	10	1			T222	2		T261	1		T259	1
auto[1]	values[2]	values[2]	6	1			T11	1		T43	1		T20	1
auto[1]	values[2]	values[3]	23	1			T42	2		T43	1		T94	5
auto[1]	values[2]	values[4]	5	1			T260	1		T262	4		-	-
auto[1]	values[2]	values[5]	20	1			T31	1		T257	1		T207	2
auto[1]	values[2]	values[6]	10	1			T33	1		T189	1		T47	2
auto[1]	values[2]	values[7]	14	1			T31	1		T189	1		T166	2
auto[1]	values[3]	values[0]	7	1			T142	1		T245	2		T34	3
auto[1]	values[3]	values[1]	7	1			T47	2		T143	1		T263	1
auto[1]	values[3]	values[2]	24	1			T82	1		T21	3		T225	1
auto[1]	values[3]	values[3]	8	1			T258	1		T264	2		T265	2
auto[1]	values[3]	values[4]	17	1			T20	1		T220	1		T166	1
auto[1]	values[3]	values[5]	16	1			T43	1		T94	4		T21	1
auto[1]	values[3]	values[6]	11	1			T33	1		T79	2		T244	2
auto[1]	values[3]	values[7]	1	1			T258	1		-	-		-	-
auto[1]	values[4]	values[0]	11	1			T189	2		T266	1		T267	3
auto[1]	values[4]	values[1]	13	1			T94	3		T196	2		T30	1
auto[1]	values[4]	values[2]	14	1			T43	1		T33	1		T215	4
auto[1]	values[4]	values[3]	14	1			T201	2		T164	1		T242	3
auto[1]	values[4]	values[4]	4	1			T33	1		T268	1		T269	2
auto[1]	values[4]	values[5]	12	1			T20	1		T30	2		T163	1
auto[1]	values[4]	values[6]	14	1			T37	2		T201	2		T57	2
auto[1]	values[4]	values[7]	19	1			T142	1		T192	1		T242	1
auto[1]	values[5]	values[0]	13	1			T9	3		T21	1		T232	1
auto[1]	values[5]	values[1]	3	1			T201	2		T270	1		-	-
auto[1]	values[5]	values[2]	18	1			T40	1		T227	3		T215	6
auto[1]	values[5]	values[3]	7	1			T258	4		T271	1		T272	2
auto[1]	values[5]	values[4]	11	1			T43	2		T230	3		T33	2
auto[1]	values[5]	values[5]	12	1			T205	1		T242	4		T259	1
auto[1]	values[5]	values[6]	18	1			T201	1		T245	2		T215	4
auto[1]	values[5]	values[7]	10	1			T80	1		T261	1		T47	1
auto[1]	values[6]	values[0]	1	1			T273	1		-	-		-	-
auto[1]	values[6]	values[1]	15	1			T201	1		T225	1		T274	1
auto[1]	values[6]	values[2]	23	1			T82	1		T189	3		T79	3
auto[1]	values[6]	values[3]	11	1			T82	1		T33	1		T21	1
auto[1]	values[6]	values[4]	27	1			T20	3		T21	4		T189	1
auto[1]	values[6]	values[5]	18	1			T11	1		T37	2		T82	2
auto[1]	values[6]	values[6]	11	1			T82	1		T21	1		T233	2
auto[1]	values[6]	values[7]	10	1			T30	1		T164	3		T266	2
auto[1]	values[7]	values[0]	11	1			T38	2		T220	1		T196	1
auto[1]	values[7]	values[1]	6	1			T220	1		T232	1		T266	1
auto[1]	values[7]	values[2]	10	1			T43	1		T215	4		T275	2
auto[1]	values[7]	values[3]	18	1			T27	2		T43	1		T217	1
auto[1]	values[7]	values[4]	10	1			T38	1		T276	1		T255	3
auto[1]	values[7]	values[5]	6	1			T41	4		T94	2		-	-
auto[1]	values[7]	values[6]	11	1			T37	2		T21	1		T261	1
auto[1]	values[7]	values[7]	16	1			T37	1		T40	2		T82	1