Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	716	1			T14	4		T15	4		T17	8
all_values[1]	716	1			T14	4		T15	4		T17	8
all_values[2]	716	1			T14	4		T15	4		T17	8
all_values[3]	716	1			T14	4		T15	4		T17	8
all_values[4]	716	1			T14	4		T15	4		T17	8
all_values[5]	716	1			T14	4		T15	4		T17	8
all_values[6]	716	1			T14	4		T15	4		T17	8
all_values[7]	716	1			T14	4		T15	4		T17	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3013

1

T14

22

T15

23

T17

33

auto[1]

2715

1

T14

10

T15

9

T17

31

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2247

1

T14

16

T15

15

T17

29

auto[1]

3481

1

T14

16

T15

17

T17

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3295

1

T14

22

T15

21

T17

44

auto[1]

2433

1

T14

10

T15

11

T17

20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	122	1			T14	3		T15	4		T17	2
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T17	1		T18	2		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	129	1			T14	1		T17	2		T18	3
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T17	1		T62	1		T18	2
all_values[0]	auto[1]	auto[0]	auto[1]	164	1			T17	1		T62	1		T18	4
all_values[0]	auto[1]	auto[1]	auto[1]	144	1			T17	1		T18	3		T19	2
all_values[1]	auto[0]	auto[0]	auto[0]	150	1			T17	1		T62	1		T18	3
all_values[1]	auto[0]	auto[0]	auto[1]	69	1			T14	2		T15	1		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T15	2		T17	3		T18	2
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T17	2		T62	1		T18	2
all_values[1]	auto[1]	auto[0]	auto[1]	136	1			T14	2		T15	1		T62	1
all_values[1]	auto[1]	auto[1]	auto[1]	138	1			T17	2		T62	1		T18	3
all_values[2]	auto[0]	auto[0]	auto[0]	147	1			T14	1		T17	2		T18	6
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T17	1		T62	2		T29	1
all_values[2]	auto[0]	auto[1]	auto[0]	120	1			T14	3		T17	1		T18	4
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T15	2		T17	1		T62	1
all_values[2]	auto[1]	auto[0]	auto[1]	175	1			T15	1		T17	2		T62	1
all_values[2]	auto[1]	auto[1]	auto[1]	133	1			T15	1		T17	1		T18	1
all_values[3]	auto[0]	auto[0]	auto[0]	134	1			T15	2		T17	2		T62	1
all_values[3]	auto[0]	auto[0]	auto[1]	64	1			T14	1		T62	1		T18	1
all_values[3]	auto[0]	auto[1]	auto[0]	127	1			T14	1		T17	1		T62	1
all_values[3]	auto[0]	auto[1]	auto[1]	79	1			T17	1		T18	2		T19	2
all_values[3]	auto[1]	auto[0]	auto[1]	165	1			T14	1		T15	2		T17	4
all_values[3]	auto[1]	auto[1]	auto[1]	147	1			T14	1		T18	1		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	121	1			T15	3		T17	1		T18	2
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T14	1		T17	1		T18	2
all_values[4]	auto[0]	auto[1]	auto[0]	114	1			T17	1		T62	2		T18	2
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T17	3		T62	1		T163	1
all_values[4]	auto[1]	auto[0]	auto[1]	174	1			T14	3		T15	1		T17	1
all_values[4]	auto[1]	auto[1]	auto[1]	149	1			T17	1		T18	1		T19	1
all_values[5]	auto[0]	auto[0]	auto[0]	218	1			T15	2		T17	3		T62	1
all_values[5]	auto[0]	auto[1]	auto[0]	189	1			T14	3		T17	3		T62	1
all_values[5]	auto[1]	auto[0]	auto[1]	176	1			T14	1		T15	1		T17	2
all_values[5]	auto[1]	auto[1]	auto[1]	133	1			T15	1		T18	3		T19	1
all_values[6]	auto[0]	auto[0]	auto[0]	152	1			T14	2		T17	1		T62	1
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T17	2		T62	1		T18	3
all_values[6]	auto[0]	auto[1]	auto[0]	134	1			T17	2		T62	1		T18	2
all_values[6]	auto[0]	auto[1]	auto[1]	62	1			T14	1		T15	2		T17	1
all_values[6]	auto[1]	auto[0]	auto[1]	152	1			T14	1		T15	2		T17	1
all_values[6]	auto[1]	auto[1]	auto[1]	140	1			T17	1		T18	2		T20	1
all_values[7]	auto[0]	auto[0]	auto[0]	144	1			T14	2		T15	1		T17	1
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T14	1		T15	1		T17	1
all_values[7]	auto[0]	auto[1]	auto[0]	113	1			T15	1		T17	3		T62	1
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T18	1		T21	2		T29	2
all_values[7]	auto[1]	auto[0]	auto[1]	174	1			T14	1		T15	1		T17	3
all_values[7]	auto[1]	auto[1]	auto[1]	133	1			T62	1		T18	4		T21	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal