Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1831

1

T3

2

T7

4

T9

5

auto[1]

1768

1

T1

6

T7

4

T9

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2049

1

T3

2

T9

5

T11

2

auto[1]

1550

1

T1

6

T7

8

T9

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2805

1

T1

6

T3

2

T7

8

auto[1]

794

1

T11

1

T13

7

T14

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	691	1			T7	1		T9	2		T13	8
valid[1]	743	1			T1	1		T9	2		T11	1
valid[2]	713	1			T1	1		T7	2		T9	1
valid[3]	729	1			T1	2		T7	2		T9	4
valid[4]	723	1			T1	2		T3	2		T7	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	106	1			T13	1		T14	1		T28	1
auto[0]	auto[0]	valid[0]	auto[1]	151	1			T9	1		T88	2		T89	5
auto[0]	auto[0]	valid[1]	auto[0]	131	1			T13	1		T44	1		T16	1
auto[0]	auto[0]	valid[1]	auto[1]	155	1			T88	1		T89	2		T294	3
auto[0]	auto[0]	valid[2]	auto[0]	137	1			T28	1		T292	1		T18	1
auto[0]	auto[0]	valid[2]	auto[1]	157	1			T13	4		T15	2		T89	4
auto[0]	auto[0]	valid[3]	auto[0]	142	1			T9	1		T13	2		T28	3
auto[0]	auto[0]	valid[3]	auto[1]	146	1			T7	1		T9	1		T89	4
auto[0]	auto[0]	valid[4]	auto[0]	140	1			T3	2		T9	1		T13	1
auto[0]	auto[0]	valid[4]	auto[1]	161	1			T7	3		T9	1		T89	5
auto[0]	auto[1]	valid[0]	auto[0]	121	1			T13	3		T14	1		T17	4
auto[0]	auto[1]	valid[0]	auto[1]	154	1			T7	1		T9	1		T13	2
auto[0]	auto[1]	valid[1]	auto[0]	141	1			T9	2		T13	1		T14	1
auto[0]	auto[1]	valid[1]	auto[1]	166	1			T1	1		T13	1		T88	1
auto[0]	auto[1]	valid[2]	auto[0]	115	1			T11	1		T14	1		T28	1
auto[0]	auto[1]	valid[2]	auto[1]	162	1			T1	1		T7	2		T9	1
auto[0]	auto[1]	valid[3]	auto[0]	118	1			T9	1		T13	1		T14	3
auto[0]	auto[1]	valid[3]	auto[1]	157	1			T1	2		T7	1		T9	1
auto[0]	auto[1]	valid[4]	auto[0]	104	1			T28	1		T44	2		T17	1
auto[0]	auto[1]	valid[4]	auto[1]	141	1			T1	2		T88	1		T89	3
auto[1]	auto[0]	valid[0]	auto[0]	85	1			T13	1		T15	2		T28	1
auto[1]	auto[0]	valid[1]	auto[0]	76	1			T11	1		T44	1		T140	2
auto[1]	auto[0]	valid[2]	auto[0]	73	1			T13	2		T14	1		T28	2
auto[1]	auto[0]	valid[3]	auto[0]	84	1			T28	2		T44	1		T62	1
auto[1]	auto[0]	valid[4]	auto[0]	87	1			T13	1		T28	2		T44	1
auto[1]	auto[1]	valid[0]	auto[0]	74	1			T13	1		T17	1		T62	1
auto[1]	auto[1]	valid[1]	auto[0]	74	1			T13	1		T14	1		T15	1
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T14	1		T44	2		T292	1
auto[1]	auto[1]	valid[3]	auto[0]	82	1			T17	1		T292	1		T172	1
auto[1]	auto[1]	valid[4]	auto[0]	90	1			T13	1		T14	1		T28	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal