Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51516

1

T3

51

T8

6

T9

284

auto[1]

16006

1

T1

6

T7

122

T9

77

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48653

1

T1

6

T3

35

T7

122

auto[1]

18869

1

T3

16

T8

2

T9

111

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34643	1			T1	6		T3	28		T7	77
others[1]	5659	1			T3	3		T7	7		T8	2
others[2]	5602	1			T3	2		T7	9		T8	1
others[3]	6600	1			T3	7		T7	9		T9	34
interest[1]	3826	1			T3	5		T7	4		T8	1
interest[4]	22495	1			T1	6		T3	16		T7	55
interest[64]	11192	1			T3	6		T7	16		T8	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16693	1			T3	19		T9	90		T11	7
auto[0]	auto[0]	others[1]	2728	1			T3	3		T8	2		T9	16
auto[0]	auto[0]	others[2]	2700	1			T3	2		T8	1		T9	11
auto[0]	auto[0]	others[3]	3166	1			T3	3		T9	18		T11	2
auto[0]	auto[0]	interest[1]	1885	1			T3	3		T9	8		T11	1
auto[0]	auto[0]	interest[4]	10763	1			T3	12		T9	53		T11	4
auto[0]	auto[0]	interest[64]	5475	1			T3	5		T8	1		T9	30
auto[0]	auto[1]	others[0]	8398	1			T1	6		T7	77		T9	36
auto[0]	auto[1]	others[1]	1276	1			T7	7		T9	10		T11	2
auto[0]	auto[1]	others[2]	1276	1			T7	9		T9	4		T11	1
auto[0]	auto[1]	others[3]	1529	1			T7	9		T9	3		T11	2
auto[0]	auto[1]	interest[1]	874	1			T7	4		T9	10		T13	4
auto[0]	auto[1]	interest[4]	5568	1			T1	6		T7	55		T9	19
auto[0]	auto[1]	interest[64]	2653	1			T7	16		T9	14		T13	23
auto[1]	auto[0]	others[0]	9552	1			T3	9		T8	1		T9	61
auto[1]	auto[0]	others[1]	1655	1			T9	8		T13	15		T14	9
auto[1]	auto[0]	others[2]	1626	1			T9	9		T11	1		T13	17
auto[1]	auto[0]	others[3]	1905	1			T3	4		T9	13		T11	1
auto[1]	auto[0]	interest[1]	1067	1			T3	2		T8	1		T9	4
auto[1]	auto[0]	interest[4]	6164	1			T3	4		T9	42		T11	8
auto[1]	auto[0]	interest[64]	3064	1			T3	1		T9	16		T11	5

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal