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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T1039 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3680521742 Jun 30 05:27:54 PM PDT 24 Jun 30 05:27:56 PM PDT 24 153520264 ps
T1040 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2069403643 Jun 30 05:28:00 PM PDT 24 Jun 30 05:28:01 PM PDT 24 42258330 ps
T113 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.239562714 Jun 30 05:27:43 PM PDT 24 Jun 30 05:27:46 PM PDT 24 146839373 ps
T102 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1199812261 Jun 30 05:27:55 PM PDT 24 Jun 30 05:28:12 PM PDT 24 3506182060 ps
T1041 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2604209502 Jun 30 05:28:08 PM PDT 24 Jun 30 05:28:10 PM PDT 24 15000918 ps
T156 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2763164818 Jun 30 05:27:54 PM PDT 24 Jun 30 05:27:57 PM PDT 24 139422483 ps
T122 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2503168888 Jun 30 05:27:18 PM PDT 24 Jun 30 05:27:20 PM PDT 24 132809158 ps
T1042 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.534955816 Jun 30 05:27:56 PM PDT 24 Jun 30 05:27:57 PM PDT 24 20990786 ps
T1043 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2493194206 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:38 PM PDT 24 32600094 ps
T114 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1176836410 Jun 30 05:27:46 PM PDT 24 Jun 30 05:28:05 PM PDT 24 1236001011 ps
T116 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1615909454 Jun 30 05:27:25 PM PDT 24 Jun 30 05:27:32 PM PDT 24 106675438 ps
T105 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2622447595 Jun 30 05:27:45 PM PDT 24 Jun 30 05:27:49 PM PDT 24 112198921 ps
T115 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3987328039 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:57 PM PDT 24 301163533 ps
T123 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.473100826 Jun 30 05:27:36 PM PDT 24 Jun 30 05:27:39 PM PDT 24 123326887 ps
T174 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1689110120 Jun 30 05:28:08 PM PDT 24 Jun 30 05:28:17 PM PDT 24 5348409274 ps
T106 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2403666913 Jun 30 05:27:25 PM PDT 24 Jun 30 05:27:28 PM PDT 24 499639769 ps
T107 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1240473873 Jun 30 05:27:35 PM PDT 24 Jun 30 05:27:39 PM PDT 24 279993651 ps
T1044 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1070407137 Jun 30 05:27:57 PM PDT 24 Jun 30 05:27:59 PM PDT 24 45569500 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2823620533 Jun 30 05:27:13 PM PDT 24 Jun 30 05:27:16 PM PDT 24 69933459 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1111884962 Jun 30 05:27:21 PM PDT 24 Jun 30 05:27:22 PM PDT 24 23539468 ps
T1047 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1270231320 Jun 30 05:27:56 PM PDT 24 Jun 30 05:27:58 PM PDT 24 23535477 ps
T108 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2230123007 Jun 30 05:27:22 PM PDT 24 Jun 30 05:27:24 PM PDT 24 34221086 ps
T1048 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3907888258 Jun 30 05:28:02 PM PDT 24 Jun 30 05:28:03 PM PDT 24 18038000 ps
T111 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1919552435 Jun 30 05:27:26 PM PDT 24 Jun 30 05:27:29 PM PDT 24 776745473 ps
T1049 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.850990447 Jun 30 05:27:58 PM PDT 24 Jun 30 05:28:00 PM PDT 24 36541074 ps
T1050 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1771769763 Jun 30 05:27:20 PM PDT 24 Jun 30 05:27:21 PM PDT 24 13025023 ps
T1051 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1034833830 Jun 30 05:27:35 PM PDT 24 Jun 30 05:27:38 PM PDT 24 336540876 ps
T124 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4052141116 Jun 30 05:27:18 PM PDT 24 Jun 30 05:27:20 PM PDT 24 239082688 ps
T125 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.673486189 Jun 30 05:27:11 PM PDT 24 Jun 30 05:27:37 PM PDT 24 4296863859 ps
T1052 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.158692437 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:39 PM PDT 24 13498545 ps
T1053 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1102070286 Jun 30 05:27:55 PM PDT 24 Jun 30 05:27:56 PM PDT 24 11991528 ps
T1054 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1889800917 Jun 30 05:27:26 PM PDT 24 Jun 30 05:27:39 PM PDT 24 814229402 ps
T1055 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3732188342 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:40 PM PDT 24 227912695 ps
T1056 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3104791253 Jun 30 05:28:08 PM PDT 24 Jun 30 05:28:10 PM PDT 24 37328441 ps
T109 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1532482176 Jun 30 05:27:35 PM PDT 24 Jun 30 05:27:39 PM PDT 24 358088722 ps
T1057 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3001207683 Jun 30 05:27:38 PM PDT 24 Jun 30 05:27:42 PM PDT 24 224669712 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.493772135 Jun 30 05:27:21 PM PDT 24 Jun 30 05:27:23 PM PDT 24 35056450 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4032768554 Jun 30 05:27:25 PM PDT 24 Jun 30 05:27:28 PM PDT 24 71773193 ps
T157 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1998515224 Jun 30 05:27:35 PM PDT 24 Jun 30 05:27:39 PM PDT 24 125433694 ps
T110 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3765794490 Jun 30 05:28:05 PM PDT 24 Jun 30 05:28:10 PM PDT 24 232972542 ps
T158 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4098410072 Jun 30 05:27:34 PM PDT 24 Jun 30 05:27:38 PM PDT 24 143145109 ps
T1060 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2497360653 Jun 30 05:27:26 PM PDT 24 Jun 30 05:27:31 PM PDT 24 818548222 ps
T159 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.354027533 Jun 30 05:27:12 PM PDT 24 Jun 30 05:27:27 PM PDT 24 3251684684 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1870925295 Jun 30 05:27:25 PM PDT 24 Jun 30 05:28:01 PM PDT 24 15125686098 ps
T1062 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.720999259 Jun 30 05:27:36 PM PDT 24 Jun 30 05:27:38 PM PDT 24 19797918 ps
T1063 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3764291415 Jun 30 05:27:59 PM PDT 24 Jun 30 05:28:01 PM PDT 24 42493031 ps
T1064 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1805265059 Jun 30 05:27:57 PM PDT 24 Jun 30 05:27:59 PM PDT 24 52745226 ps
T1065 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2824339015 Jun 30 05:28:07 PM PDT 24 Jun 30 05:28:08 PM PDT 24 16587625 ps
T84 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1001577844 Jun 30 05:27:27 PM PDT 24 Jun 30 05:27:29 PM PDT 24 32441538 ps
T1066 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4207542211 Jun 30 05:27:55 PM PDT 24 Jun 30 05:27:59 PM PDT 24 207230458 ps
T1067 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3180316854 Jun 30 05:28:00 PM PDT 24 Jun 30 05:28:02 PM PDT 24 13212726 ps
T126 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4225338250 Jun 30 05:28:00 PM PDT 24 Jun 30 05:28:02 PM PDT 24 72257246 ps
T1068 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.167768226 Jun 30 05:27:59 PM PDT 24 Jun 30 05:28:01 PM PDT 24 43091446 ps
T161 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1280816571 Jun 30 05:27:27 PM PDT 24 Jun 30 05:27:32 PM PDT 24 329282887 ps
T1069 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1601788949 Jun 30 05:27:25 PM PDT 24 Jun 30 05:27:38 PM PDT 24 359479489 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.380827948 Jun 30 05:27:25 PM PDT 24 Jun 30 05:27:29 PM PDT 24 426385412 ps
T1071 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2191202693 Jun 30 05:27:35 PM PDT 24 Jun 30 05:27:40 PM PDT 24 178920838 ps
T1072 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3281523712 Jun 30 05:27:57 PM PDT 24 Jun 30 05:27:59 PM PDT 24 15957133 ps
T127 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.852995968 Jun 30 05:27:41 PM PDT 24 Jun 30 05:27:44 PM PDT 24 36556267 ps
T1073 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.752700262 Jun 30 05:27:27 PM PDT 24 Jun 30 05:27:35 PM PDT 24 912759422 ps
T128 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4036803909 Jun 30 05:27:54 PM PDT 24 Jun 30 05:27:56 PM PDT 24 226543781 ps
T85 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1751774026 Jun 30 05:27:18 PM PDT 24 Jun 30 05:27:20 PM PDT 24 35963521 ps
T1074 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2109398687 Jun 30 05:27:40 PM PDT 24 Jun 30 05:27:43 PM PDT 24 44884251 ps
T176 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2833732087 Jun 30 05:27:26 PM PDT 24 Jun 30 05:27:47 PM PDT 24 1172725581 ps
T160 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.974037323 Jun 30 05:27:35 PM PDT 24 Jun 30 05:27:39 PM PDT 24 214633672 ps
T1075 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1589796351 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:44 PM PDT 24 175813259 ps
T1076 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1730498954 Jun 30 05:27:58 PM PDT 24 Jun 30 05:28:00 PM PDT 24 14025592 ps
T1077 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.294754200 Jun 30 05:27:56 PM PDT 24 Jun 30 05:27:58 PM PDT 24 35012248 ps
T1078 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4034208340 Jun 30 05:27:36 PM PDT 24 Jun 30 05:27:37 PM PDT 24 30473654 ps
T130 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2788152752 Jun 30 05:27:11 PM PDT 24 Jun 30 05:27:12 PM PDT 24 72492533 ps
T129 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2045850145 Jun 30 05:27:36 PM PDT 24 Jun 30 05:27:38 PM PDT 24 85030143 ps
T1079 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2414577473 Jun 30 05:27:57 PM PDT 24 Jun 30 05:27:59 PM PDT 24 33685597 ps
T162 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.338850982 Jun 30 05:27:44 PM PDT 24 Jun 30 05:28:10 PM PDT 24 8584165670 ps
T1080 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3521190731 Jun 30 05:27:32 PM PDT 24 Jun 30 05:27:36 PM PDT 24 161078382 ps
T1081 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.21665324 Jun 30 05:27:28 PM PDT 24 Jun 30 05:27:29 PM PDT 24 11866973 ps
T1082 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3911657984 Jun 30 05:27:54 PM PDT 24 Jun 30 05:27:55 PM PDT 24 33265799 ps
T1083 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.110466827 Jun 30 05:27:42 PM PDT 24 Jun 30 05:27:43 PM PDT 24 20275925 ps
T1084 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1715580352 Jun 30 05:27:58 PM PDT 24 Jun 30 05:28:00 PM PDT 24 11507587 ps
T131 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4271984932 Jun 30 05:27:26 PM PDT 24 Jun 30 05:27:29 PM PDT 24 79970014 ps
T1085 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.122821359 Jun 30 05:27:27 PM PDT 24 Jun 30 05:27:33 PM PDT 24 160043656 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2368897175 Jun 30 05:27:11 PM PDT 24 Jun 30 05:27:13 PM PDT 24 22136182 ps
T1087 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.313112544 Jun 30 05:28:00 PM PDT 24 Jun 30 05:28:02 PM PDT 24 35220580 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.653194461 Jun 30 05:27:10 PM PDT 24 Jun 30 05:27:11 PM PDT 24 13553198 ps
T1089 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1634528009 Jun 30 05:27:36 PM PDT 24 Jun 30 05:27:43 PM PDT 24 110458186 ps
T86 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1939943278 Jun 30 05:27:25 PM PDT 24 Jun 30 05:27:27 PM PDT 24 44186420 ps
T1090 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2102433683 Jun 30 05:28:00 PM PDT 24 Jun 30 05:28:01 PM PDT 24 46734003 ps
T1091 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.624415897 Jun 30 05:28:08 PM PDT 24 Jun 30 05:28:12 PM PDT 24 41159790 ps
T1092 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.159943636 Jun 30 05:27:43 PM PDT 24 Jun 30 05:27:45 PM PDT 24 35352171 ps
T1093 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.648777125 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:42 PM PDT 24 193530624 ps
T1094 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2535952299 Jun 30 05:27:59 PM PDT 24 Jun 30 05:28:01 PM PDT 24 28657441 ps
T1095 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1077772825 Jun 30 05:27:43 PM PDT 24 Jun 30 05:27:46 PM PDT 24 95780396 ps
T1096 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2844751631 Jun 30 05:27:26 PM PDT 24 Jun 30 05:27:31 PM PDT 24 738157055 ps
T1097 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2747994639 Jun 30 05:27:56 PM PDT 24 Jun 30 05:27:58 PM PDT 24 141325728 ps
T132 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1041593557 Jun 30 05:27:13 PM PDT 24 Jun 30 05:27:16 PM PDT 24 28154155 ps
T1098 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1488696143 Jun 30 05:27:12 PM PDT 24 Jun 30 05:27:21 PM PDT 24 386947628 ps
T173 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1466488819 Jun 30 05:27:45 PM PDT 24 Jun 30 05:27:49 PM PDT 24 223641097 ps
T1099 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2682871931 Jun 30 05:27:25 PM PDT 24 Jun 30 05:27:27 PM PDT 24 14090691 ps
T1100 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3031991800 Jun 30 05:27:45 PM PDT 24 Jun 30 05:27:47 PM PDT 24 136597788 ps
T1101 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2374540419 Jun 30 05:27:44 PM PDT 24 Jun 30 05:27:48 PM PDT 24 128288999 ps
T1102 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.457849414 Jun 30 05:27:56 PM PDT 24 Jun 30 05:27:57 PM PDT 24 34029813 ps
T175 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1456606511 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:51 PM PDT 24 210606965 ps
T1103 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2872302976 Jun 30 05:27:42 PM PDT 24 Jun 30 05:27:43 PM PDT 24 38647134 ps
T1104 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1267874163 Jun 30 05:27:57 PM PDT 24 Jun 30 05:28:01 PM PDT 24 203559752 ps
T1105 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3279322432 Jun 30 05:27:43 PM PDT 24 Jun 30 05:27:47 PM PDT 24 448273134 ps
T1106 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2791511342 Jun 30 05:28:08 PM PDT 24 Jun 30 05:28:13 PM PDT 24 124609933 ps
T1107 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1489226698 Jun 30 05:27:56 PM PDT 24 Jun 30 05:28:13 PM PDT 24 1349895277 ps
T1108 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3594749269 Jun 30 05:27:25 PM PDT 24 Jun 30 05:27:27 PM PDT 24 34797979 ps
T1109 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.567763401 Jun 30 05:27:26 PM PDT 24 Jun 30 05:27:31 PM PDT 24 177521765 ps
T1110 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2791499529 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:40 PM PDT 24 55267338 ps
T1111 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3770704151 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:43 PM PDT 24 118371300 ps
T1112 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4094138263 Jun 30 05:27:35 PM PDT 24 Jun 30 05:28:01 PM PDT 24 1109832674 ps
T1113 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1456412309 Jun 30 05:27:20 PM PDT 24 Jun 30 05:27:23 PM PDT 24 91165962 ps
T1114 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.437388590 Jun 30 05:28:00 PM PDT 24 Jun 30 05:28:03 PM PDT 24 47760634 ps
T1115 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.224464127 Jun 30 05:28:05 PM PDT 24 Jun 30 05:28:09 PM PDT 24 131006156 ps
T1116 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.407884880 Jun 30 05:27:19 PM PDT 24 Jun 30 05:27:23 PM PDT 24 584738272 ps
T1117 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.632448426 Jun 30 05:27:34 PM PDT 24 Jun 30 05:27:37 PM PDT 24 115306335 ps
T1118 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3672392111 Jun 30 05:27:55 PM PDT 24 Jun 30 05:27:56 PM PDT 24 14967100 ps
T1119 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1265740746 Jun 30 05:27:57 PM PDT 24 Jun 30 05:27:59 PM PDT 24 14337090 ps
T1120 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3205162914 Jun 30 05:27:11 PM PDT 24 Jun 30 05:27:12 PM PDT 24 23344990 ps
T1121 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2005945704 Jun 30 05:27:35 PM PDT 24 Jun 30 05:27:38 PM PDT 24 56038067 ps
T1122 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3516126924 Jun 30 05:28:02 PM PDT 24 Jun 30 05:28:03 PM PDT 24 18326514 ps
T1123 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2864730731 Jun 30 05:27:27 PM PDT 24 Jun 30 05:27:29 PM PDT 24 82253081 ps
T1124 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2484077469 Jun 30 05:27:59 PM PDT 24 Jun 30 05:28:00 PM PDT 24 13185902 ps
T1125 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3816033178 Jun 30 05:27:35 PM PDT 24 Jun 30 05:27:40 PM PDT 24 592250970 ps
T1126 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4008768980 Jun 30 05:28:00 PM PDT 24 Jun 30 05:28:05 PM PDT 24 1167816453 ps
T1127 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3010151680 Jun 30 05:27:39 PM PDT 24 Jun 30 05:27:52 PM PDT 24 1850462561 ps
T1128 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1867756358 Jun 30 05:27:11 PM PDT 24 Jun 30 05:27:17 PM PDT 24 385801771 ps
T1129 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.486979761 Jun 30 05:27:43 PM PDT 24 Jun 30 05:27:46 PM PDT 24 165484528 ps
T1130 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2029408515 Jun 30 05:27:13 PM PDT 24 Jun 30 05:27:51 PM PDT 24 3069697500 ps
T1131 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4210085097 Jun 30 05:27:40 PM PDT 24 Jun 30 05:27:42 PM PDT 24 265454464 ps
T1132 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1287677581 Jun 30 05:27:25 PM PDT 24 Jun 30 05:27:27 PM PDT 24 14495637 ps
T1133 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1025611859 Jun 30 05:27:43 PM PDT 24 Jun 30 05:27:47 PM PDT 24 110798573 ps
T1134 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1942832728 Jun 30 05:27:44 PM PDT 24 Jun 30 05:27:45 PM PDT 24 33697112 ps
T1135 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3234285747 Jun 30 05:27:44 PM PDT 24 Jun 30 05:27:49 PM PDT 24 201632983 ps
T1136 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1919992783 Jun 30 05:28:07 PM PDT 24 Jun 30 05:28:09 PM PDT 24 54386210 ps
T1137 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1605107818 Jun 30 05:27:56 PM PDT 24 Jun 30 05:27:59 PM PDT 24 42512750 ps
T1138 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4162537953 Jun 30 05:27:21 PM PDT 24 Jun 30 05:27:43 PM PDT 24 311772803 ps
T1139 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1550395552 Jun 30 05:27:36 PM PDT 24 Jun 30 05:27:38 PM PDT 24 103878116 ps
T1140 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1722381502 Jun 30 05:27:57 PM PDT 24 Jun 30 05:27:58 PM PDT 24 100933200 ps
T1141 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3936253359 Jun 30 05:27:44 PM PDT 24 Jun 30 05:27:47 PM PDT 24 1405797942 ps
T1142 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.316247286 Jun 30 05:27:12 PM PDT 24 Jun 30 05:27:13 PM PDT 24 17265193 ps
T1143 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1181767680 Jun 30 05:27:11 PM PDT 24 Jun 30 05:27:34 PM PDT 24 1683397218 ps
T1144 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3562549610 Jun 30 05:27:21 PM PDT 24 Jun 30 05:27:37 PM PDT 24 2083718715 ps
T1145 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2361419499 Jun 30 05:27:12 PM PDT 24 Jun 30 05:27:16 PM PDT 24 464818719 ps
T1146 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.942992246 Jun 30 05:27:54 PM PDT 24 Jun 30 05:28:17 PM PDT 24 3408240659 ps
T1147 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1388932697 Jun 30 05:27:25 PM PDT 24 Jun 30 05:27:33 PM PDT 24 224775342 ps
T87 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1412099585 Jun 30 05:27:20 PM PDT 24 Jun 30 05:27:21 PM PDT 24 21594456 ps
T1148 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4081758953 Jun 30 05:27:56 PM PDT 24 Jun 30 05:27:57 PM PDT 24 20384991 ps
T1149 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2307278992 Jun 30 05:27:58 PM PDT 24 Jun 30 05:28:00 PM PDT 24 19195791 ps
T1150 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1922340655 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:39 PM PDT 24 11073549 ps
T1151 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1802060633 Jun 30 05:27:37 PM PDT 24 Jun 30 05:27:56 PM PDT 24 302019684 ps

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.4187963737
Short name T9
Test name
Test status
Simulation time 31007424377 ps
CPU time 112.15 seconds
Started Jun 30 07:01:16 PM PDT 24
Finished Jun 30 07:03:09 PM PDT 24
Peak memory 256464 kb
Host smart-b23aafa5-3b76-49ab-81d5-c5de76796e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187963737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.4187963737
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1067070988
Short name T17
Test name
Test status
Simulation time 4837117480 ps
CPU time 62.43 seconds
Started Jun 30 06:59:17 PM PDT 24
Finished Jun 30 07:00:22 PM PDT 24
Peak memory 241012 kb
Host smart-5dca5a2d-4d65-4278-871e-517d8efde874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067070988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1067070988
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.873003201
Short name T30
Test name
Test status
Simulation time 142247054429 ps
CPU time 415.98 seconds
Started Jun 30 07:00:06 PM PDT 24
Finished Jun 30 07:07:08 PM PDT 24
Peak memory 289740 kb
Host smart-c3f929ae-f25f-4fea-a633-aaf1b0470cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873003201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.873003201
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1199812261
Short name T102
Test name
Test status
Simulation time 3506182060 ps
CPU time 16.54 seconds
Started Jun 30 05:27:55 PM PDT 24
Finished Jun 30 05:28:12 PM PDT 24
Peak memory 215532 kb
Host smart-dc354bae-b0d0-4a59-a159-e68bff1d2251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199812261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1199812261
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3354341485
Short name T43
Test name
Test status
Simulation time 363535482689 ps
CPU time 673.57 seconds
Started Jun 30 06:59:17 PM PDT 24
Finished Jun 30 07:10:33 PM PDT 24
Peak memory 267708 kb
Host smart-45832bcc-75dd-4d32-bf95-b6f718c6634a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354341485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3354341485
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1912514701
Short name T63
Test name
Test status
Simulation time 24551953 ps
CPU time 0.74 seconds
Started Jun 30 06:58:30 PM PDT 24
Finished Jun 30 06:58:32 PM PDT 24
Peak memory 216148 kb
Host smart-66338544-2635-408c-9f64-3a264764107c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912514701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1912514701
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3453019786
Short name T14
Test name
Test status
Simulation time 5721955149 ps
CPU time 78.72 seconds
Started Jun 30 06:59:46 PM PDT 24
Finished Jun 30 07:01:09 PM PDT 24
Peak memory 260612 kb
Host smart-8e1d3c92-e5f7-4163-a28e-2ffe03e54a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453019786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3453019786
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3007474569
Short name T21
Test name
Test status
Simulation time 96980265111 ps
CPU time 514.05 seconds
Started Jun 30 06:58:55 PM PDT 24
Finished Jun 30 07:07:30 PM PDT 24
Peak memory 273844 kb
Host smart-4e6d2127-b27b-4bea-9ac4-e66a8c7dd7ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007474569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3007474569
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3028880504
Short name T37
Test name
Test status
Simulation time 5813179911 ps
CPU time 104.45 seconds
Started Jun 30 06:58:54 PM PDT 24
Finished Jun 30 07:00:40 PM PDT 24
Peak memory 256740 kb
Host smart-da5ef22b-d2f9-4e0e-8645-fd1fba4f2d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028880504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3028880504
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2872291417
Short name T80
Test name
Test status
Simulation time 44205998773 ps
CPU time 304.67 seconds
Started Jun 30 07:01:30 PM PDT 24
Finished Jun 30 07:06:36 PM PDT 24
Peak memory 273856 kb
Host smart-4c0ef066-ee1c-430d-a24d-12685db7eba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872291417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2872291417
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.500262493
Short name T33
Test name
Test status
Simulation time 154270640947 ps
CPU time 450.23 seconds
Started Jun 30 07:00:10 PM PDT 24
Finished Jun 30 07:07:47 PM PDT 24
Peak memory 257428 kb
Host smart-0313c228-0bbc-4d93-b34b-6c194a226f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500262493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.500262493
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1424357582
Short name T25
Test name
Test status
Simulation time 16219860751 ps
CPU time 36.15 seconds
Started Jun 30 07:00:04 PM PDT 24
Finished Jun 30 07:00:47 PM PDT 24
Peak memory 232776 kb
Host smart-a87dec81-0965-4cf0-adff-11395062320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424357582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1424357582
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.545392610
Short name T98
Test name
Test status
Simulation time 65613556 ps
CPU time 3.97 seconds
Started Jun 30 05:27:55 PM PDT 24
Finished Jun 30 05:27:59 PM PDT 24
Peak memory 215596 kb
Host smart-16445c93-c5f9-46ff-adcb-81ec9b0b09b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545392610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.545392610
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2175435151
Short name T60
Test name
Test status
Simulation time 19333366 ps
CPU time 0.74 seconds
Started Jun 30 06:59:06 PM PDT 24
Finished Jun 30 06:59:08 PM PDT 24
Peak memory 204840 kb
Host smart-ea788c85-19cd-4710-92e5-7eb475bf753c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175435151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2175435151
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.343693158
Short name T79
Test name
Test status
Simulation time 27466231290 ps
CPU time 212.94 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 07:02:10 PM PDT 24
Peak memory 271188 kb
Host smart-b62686e0-8902-4527-b4ba-c7c5751875b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343693158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.343693158
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.358962947
Short name T28
Test name
Test status
Simulation time 31759031938 ps
CPU time 309.25 seconds
Started Jun 30 06:59:04 PM PDT 24
Finished Jun 30 07:04:14 PM PDT 24
Peak memory 255792 kb
Host smart-1ab68f16-8f4f-4b2f-80bb-46da7d319f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358962947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.358962947
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.673486189
Short name T125
Test name
Test status
Simulation time 4296863859 ps
CPU time 25.68 seconds
Started Jun 30 05:27:11 PM PDT 24
Finished Jun 30 05:27:37 PM PDT 24
Peak memory 215416 kb
Host smart-8c2e3e33-dfc2-49f8-8bee-36d5c8ae8238
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673486189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.673486189
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.642099043
Short name T47
Test name
Test status
Simulation time 202625425958 ps
CPU time 954.01 seconds
Started Jun 30 07:01:08 PM PDT 24
Finished Jun 30 07:17:03 PM PDT 24
Peak memory 300408 kb
Host smart-e2c8d164-18d5-4005-9236-3aaedec7fff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642099043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.642099043
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2696643258
Short name T201
Test name
Test status
Simulation time 21669241779 ps
CPU time 123.73 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 07:00:52 PM PDT 24
Peak memory 273840 kb
Host smart-9fd515f8-bb4c-4ada-9d99-17502a8d8406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696643258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2696643258
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3283182326
Short name T35
Test name
Test status
Simulation time 54498312 ps
CPU time 1.03 seconds
Started Jun 30 06:58:30 PM PDT 24
Finished Jun 30 06:58:32 PM PDT 24
Peak memory 218016 kb
Host smart-995c0b23-d424-4fc7-97ff-8ec7e40c6fac
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283182326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3283182326
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.39926750
Short name T261
Test name
Test status
Simulation time 26880816056 ps
CPU time 303.7 seconds
Started Jun 30 06:59:18 PM PDT 24
Finished Jun 30 07:04:23 PM PDT 24
Peak memory 280644 kb
Host smart-f925d6e3-c3be-49ab-903b-a95e69a29223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39926750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.39926750
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.85942283
Short name T67
Test name
Test status
Simulation time 87731140 ps
CPU time 1.13 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 06:58:40 PM PDT 24
Peak memory 235912 kb
Host smart-194f363c-3986-4040-9b81-7a6aaf192cf6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85942283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.85942283
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3035984637
Short name T192
Test name
Test status
Simulation time 152681109139 ps
CPU time 371.14 seconds
Started Jun 30 07:00:22 PM PDT 24
Finished Jun 30 07:06:34 PM PDT 24
Peak memory 249240 kb
Host smart-941abf37-06c1-481d-85b0-6c3837e34668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035984637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3035984637
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.4205286648
Short name T260
Test name
Test status
Simulation time 41433352688 ps
CPU time 135.45 seconds
Started Jun 30 06:59:45 PM PDT 24
Finished Jun 30 07:02:05 PM PDT 24
Peak memory 262364 kb
Host smart-8a6bb6e1-8f80-47aa-bc5d-2283cbed675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205286648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4205286648
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1017506889
Short name T258
Test name
Test status
Simulation time 23075124738 ps
CPU time 188.64 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:03:08 PM PDT 24
Peak memory 266004 kb
Host smart-302120e6-5d02-493c-aca1-bdd4b0caf1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017506889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1017506889
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1722051864
Short name T31
Test name
Test status
Simulation time 24350639873 ps
CPU time 64.66 seconds
Started Jun 30 07:01:35 PM PDT 24
Finished Jun 30 07:02:41 PM PDT 24
Peak memory 256160 kb
Host smart-0bbaabde-3232-448e-906c-4fe20a78a84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722051864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1722051864
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3851250949
Short name T13
Test name
Test status
Simulation time 4677113407 ps
CPU time 62.73 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 07:00:01 PM PDT 24
Peak memory 249280 kb
Host smart-642e5b6d-6dbf-443c-9841-78838bae890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851250949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3851250949
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.499359
Short name T40
Test name
Test status
Simulation time 85153379913 ps
CPU time 365.12 seconds
Started Jun 30 07:00:00 PM PDT 24
Finished Jun 30 07:06:13 PM PDT 24
Peak memory 252088 kb
Host smart-a57a260b-72f6-4057-9181-f83856344939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.499359
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2309802521
Short name T189
Test name
Test status
Simulation time 7064125669 ps
CPU time 157.41 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 07:01:36 PM PDT 24
Peak memory 273768 kb
Host smart-04284dcd-2227-48bf-80bb-d3dd041ce708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309802521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2309802521
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1181767680
Short name T1143
Test name
Test status
Simulation time 1683397218 ps
CPU time 22.33 seconds
Started Jun 30 05:27:11 PM PDT 24
Finished Jun 30 05:27:34 PM PDT 24
Peak memory 215444 kb
Host smart-5e422e1d-3434-4593-abd1-ac82ad4408bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181767680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1181767680
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.410521885
Short name T219
Test name
Test status
Simulation time 6214936868 ps
CPU time 67.72 seconds
Started Jun 30 06:59:45 PM PDT 24
Finished Jun 30 07:00:57 PM PDT 24
Peak memory 256232 kb
Host smart-4335a57f-cb85-4f9c-bc50-752d9ea2789c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410521885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.410521885
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2622110293
Short name T820
Test name
Test status
Simulation time 22734907978 ps
CPU time 148.13 seconds
Started Jun 30 07:00:40 PM PDT 24
Finished Jun 30 07:03:10 PM PDT 24
Peak memory 267660 kb
Host smart-f3d26478-4ee4-4597-8faa-69ffe35a5fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622110293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2622110293
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1240473873
Short name T107
Test name
Test status
Simulation time 279993651 ps
CPU time 4.09 seconds
Started Jun 30 05:27:35 PM PDT 24
Finished Jun 30 05:27:39 PM PDT 24
Peak memory 215532 kb
Host smart-7fee47e6-d986-436a-a5b2-e68fedf02a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240473873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
240473873
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1899039843
Short name T281
Test name
Test status
Simulation time 65372969188 ps
CPU time 45.96 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:59:29 PM PDT 24
Peak memory 249180 kb
Host smart-1972bbc7-92da-41cc-8a06-89f6700885ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899039843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1899039843
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3117928535
Short name T229
Test name
Test status
Simulation time 218521055075 ps
CPU time 197.65 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 07:02:03 PM PDT 24
Peak memory 272900 kb
Host smart-e919d138-8b6e-4210-8012-322a9baa01f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117928535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3117928535
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1214868553
Short name T207
Test name
Test status
Simulation time 85990978668 ps
CPU time 169.29 seconds
Started Jun 30 06:59:44 PM PDT 24
Finished Jun 30 07:02:39 PM PDT 24
Peak memory 249148 kb
Host smart-d85fc100-a3ba-491a-be04-2a4200403800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214868553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1214868553
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.903479573
Short name T220
Test name
Test status
Simulation time 20507550952 ps
CPU time 133.09 seconds
Started Jun 30 07:01:35 PM PDT 24
Finished Jun 30 07:03:49 PM PDT 24
Peak memory 249552 kb
Host smart-25459ddb-4658-43c0-84f2-69e33b3acd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903479573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.903479573
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3073733397
Short name T41
Test name
Test status
Simulation time 10180121243 ps
CPU time 13.82 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 06:59:01 PM PDT 24
Peak memory 224616 kb
Host smart-8e081c48-5eba-4729-affe-6eb0e9ba21b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073733397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3073733397
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.942992246
Short name T1146
Test name
Test status
Simulation time 3408240659 ps
CPU time 22.4 seconds
Started Jun 30 05:27:54 PM PDT 24
Finished Jun 30 05:28:17 PM PDT 24
Peak memory 215504 kb
Host smart-9c59ab32-7651-43cc-93a8-d4232eb05c79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942992246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.942992246
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.634516713
Short name T89
Test name
Test status
Simulation time 4397527971 ps
CPU time 15.43 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:21 PM PDT 24
Peak memory 216252 kb
Host smart-13f68e85-500d-46a0-8783-f7b74f09c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634516713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.634516713
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2004713821
Short name T257
Test name
Test status
Simulation time 6215526907 ps
CPU time 45.25 seconds
Started Jun 30 06:59:18 PM PDT 24
Finished Jun 30 07:00:05 PM PDT 24
Peak memory 224520 kb
Host smart-0b826bfc-d227-49d8-9705-17fcf132c827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004713821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2004713821
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1724360957
Short name T807
Test name
Test status
Simulation time 23663921853 ps
CPU time 315.51 seconds
Started Jun 30 06:59:16 PM PDT 24
Finished Jun 30 07:04:34 PM PDT 24
Peak memory 271276 kb
Host smart-3db45cfc-dc1b-4a76-8204-c2f91b327a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724360957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1724360957
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2229334732
Short name T183
Test name
Test status
Simulation time 266339060 ps
CPU time 3.7 seconds
Started Jun 30 06:59:16 PM PDT 24
Finished Jun 30 06:59:22 PM PDT 24
Peak memory 232656 kb
Host smart-decd680a-47ac-4c12-adc9-bbfb3a8b1b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229334732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2229334732
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2754434730
Short name T278
Test name
Test status
Simulation time 200741420 ps
CPU time 6.56 seconds
Started Jun 30 06:59:21 PM PDT 24
Finished Jun 30 06:59:30 PM PDT 24
Peak memory 240828 kb
Host smart-75c10239-a765-4ca8-b75a-d9d943956a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754434730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2754434730
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3393243200
Short name T287
Test name
Test status
Simulation time 406913395 ps
CPU time 9.35 seconds
Started Jun 30 06:59:31 PM PDT 24
Finished Jun 30 06:59:41 PM PDT 24
Peak memory 240936 kb
Host smart-ff5c838f-86ca-44af-b495-c8f5a16db362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393243200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3393243200
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2942256415
Short name T273
Test name
Test status
Simulation time 59562797635 ps
CPU time 150.55 seconds
Started Jun 30 07:01:35 PM PDT 24
Finished Jun 30 07:04:07 PM PDT 24
Peak memory 249196 kb
Host smart-5ab55a7e-30a1-4430-a9a5-10f466acacc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942256415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2942256415
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2868555642
Short name T1003
Test name
Test status
Simulation time 818963310 ps
CPU time 2.93 seconds
Started Jun 30 06:59:13 PM PDT 24
Finished Jun 30 06:59:16 PM PDT 24
Peak memory 224412 kb
Host smart-534c3e73-bcea-4bab-9ef8-72791042e9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868555642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2868555642
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1589796351
Short name T1075
Test name
Test status
Simulation time 175813259 ps
CPU time 5.31 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:44 PM PDT 24
Peak memory 216528 kb
Host smart-e7e7ebaf-0a2b-4e6b-96f7-4b8bf50fe2d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589796351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1589796351
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1412099585
Short name T87
Test name
Test status
Simulation time 21594456 ps
CPU time 1.11 seconds
Started Jun 30 05:27:20 PM PDT 24
Finished Jun 30 05:27:21 PM PDT 24
Peak memory 207152 kb
Host smart-b3c2ce3f-150f-4ff4-b02d-2b695b7d4963
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412099585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1412099585
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.354027533
Short name T159
Test name
Test status
Simulation time 3251684684 ps
CPU time 14.33 seconds
Started Jun 30 05:27:12 PM PDT 24
Finished Jun 30 05:27:27 PM PDT 24
Peak memory 215388 kb
Host smart-365c3884-c6ac-42ea-8e73-d71ffc2d9d78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354027533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.354027533
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1751774026
Short name T85
Test name
Test status
Simulation time 35963521 ps
CPU time 0.94 seconds
Started Jun 30 05:27:18 PM PDT 24
Finished Jun 30 05:27:20 PM PDT 24
Peak memory 206916 kb
Host smart-9776e62c-d1cc-451d-8d64-33f43ccd7dbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751774026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1751774026
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2361419499
Short name T1145
Test name
Test status
Simulation time 464818719 ps
CPU time 3.7 seconds
Started Jun 30 05:27:12 PM PDT 24
Finished Jun 30 05:27:16 PM PDT 24
Peak memory 216748 kb
Host smart-5635ee03-7100-4cc9-951e-7bd925bb487c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361419499 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2361419499
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4052141116
Short name T124
Test name
Test status
Simulation time 239082688 ps
CPU time 1.37 seconds
Started Jun 30 05:27:18 PM PDT 24
Finished Jun 30 05:27:20 PM PDT 24
Peak memory 215400 kb
Host smart-93a75199-2770-472a-9474-8f7e82964de0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052141116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
052141116
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.834555600
Short name T1034
Test name
Test status
Simulation time 56825094 ps
CPU time 0.72 seconds
Started Jun 30 05:27:11 PM PDT 24
Finished Jun 30 05:27:12 PM PDT 24
Peak memory 204144 kb
Host smart-f04d85a5-17fd-4688-a6fd-9c88623ad75b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834555600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.834555600
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2788152752
Short name T130
Test name
Test status
Simulation time 72492533 ps
CPU time 1.36 seconds
Started Jun 30 05:27:11 PM PDT 24
Finished Jun 30 05:27:12 PM PDT 24
Peak memory 215388 kb
Host smart-4cbb1c7b-98e8-482a-8db3-8c6947c8a829
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788152752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2788152752
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.653194461
Short name T1088
Test name
Test status
Simulation time 13553198 ps
CPU time 0.64 seconds
Started Jun 30 05:27:10 PM PDT 24
Finished Jun 30 05:27:11 PM PDT 24
Peak memory 204044 kb
Host smart-dbf17584-ad44-42d9-9b15-c9319242f6af
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653194461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.653194461
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.55066806
Short name T1036
Test name
Test status
Simulation time 62265000 ps
CPU time 4.05 seconds
Started Jun 30 05:27:19 PM PDT 24
Finished Jun 30 05:27:23 PM PDT 24
Peak memory 215468 kb
Host smart-6ea914de-90f4-4382-9b0d-d0cf9f7d4845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55066806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_same_csr_outstanding.55066806
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.166623120
Short name T103
Test name
Test status
Simulation time 385005126 ps
CPU time 3.95 seconds
Started Jun 30 05:27:13 PM PDT 24
Finished Jun 30 05:27:17 PM PDT 24
Peak memory 215544 kb
Host smart-d8ec9fd3-eef2-4217-847c-ccac9c913554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166623120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.166623120
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1611622993
Short name T101
Test name
Test status
Simulation time 308492832 ps
CPU time 18.44 seconds
Started Jun 30 05:27:12 PM PDT 24
Finished Jun 30 05:27:31 PM PDT 24
Peak memory 215480 kb
Host smart-5052a7b7-9807-4ef4-bb03-3427bf21aacc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611622993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1611622993
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1488696143
Short name T1098
Test name
Test status
Simulation time 386947628 ps
CPU time 8.58 seconds
Started Jun 30 05:27:12 PM PDT 24
Finished Jun 30 05:27:21 PM PDT 24
Peak memory 215384 kb
Host smart-08c0098d-dbff-488a-8ae1-c18cbe8216fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488696143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1488696143
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2029408515
Short name T1130
Test name
Test status
Simulation time 3069697500 ps
CPU time 36.41 seconds
Started Jun 30 05:27:13 PM PDT 24
Finished Jun 30 05:27:51 PM PDT 24
Peak memory 207096 kb
Host smart-1f9135b2-e43a-4686-8cb5-669de1891f73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029408515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2029408515
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.316247286
Short name T1142
Test name
Test status
Simulation time 17265193 ps
CPU time 0.97 seconds
Started Jun 30 05:27:12 PM PDT 24
Finished Jun 30 05:27:13 PM PDT 24
Peak memory 206856 kb
Host smart-0e55db27-be83-4de4-a6ae-f086ccc92b0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316247286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.316247286
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2823620533
Short name T1045
Test name
Test status
Simulation time 69933459 ps
CPU time 2.18 seconds
Started Jun 30 05:27:13 PM PDT 24
Finished Jun 30 05:27:16 PM PDT 24
Peak memory 216484 kb
Host smart-bbf72a24-57e0-45dc-89e9-97af7e648b3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823620533 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2823620533
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1041593557
Short name T132
Test name
Test status
Simulation time 28154155 ps
CPU time 1.94 seconds
Started Jun 30 05:27:13 PM PDT 24
Finished Jun 30 05:27:16 PM PDT 24
Peak memory 207312 kb
Host smart-fa87c04d-0c77-476b-91b4-247458f60800
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041593557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
041593557
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2368897175
Short name T1086
Test name
Test status
Simulation time 22136182 ps
CPU time 0.75 seconds
Started Jun 30 05:27:11 PM PDT 24
Finished Jun 30 05:27:13 PM PDT 24
Peak memory 203788 kb
Host smart-c93bf63a-6b7e-4d40-9417-1479b3f19b30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368897175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
368897175
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.670435359
Short name T121
Test name
Test status
Simulation time 58050763 ps
CPU time 1.34 seconds
Started Jun 30 05:27:12 PM PDT 24
Finished Jun 30 05:27:14 PM PDT 24
Peak memory 215396 kb
Host smart-fc2711ad-5b28-4821-aa45-f9478adfb0e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670435359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.670435359
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3205162914
Short name T1120
Test name
Test status
Simulation time 23344990 ps
CPU time 0.69 seconds
Started Jun 30 05:27:11 PM PDT 24
Finished Jun 30 05:27:12 PM PDT 24
Peak memory 204056 kb
Host smart-c2c7a60b-9cab-48bf-81f1-91ccb1a35f2d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205162914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3205162914
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.551718254
Short name T1032
Test name
Test status
Simulation time 43217891 ps
CPU time 3.07 seconds
Started Jun 30 05:27:12 PM PDT 24
Finished Jun 30 05:27:16 PM PDT 24
Peak memory 215368 kb
Host smart-8b20d317-51cd-46ac-8d16-b6e2ce2e4570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551718254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.551718254
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1867756358
Short name T1128
Test name
Test status
Simulation time 385801771 ps
CPU time 5.63 seconds
Started Jun 30 05:27:11 PM PDT 24
Finished Jun 30 05:27:17 PM PDT 24
Peak memory 215620 kb
Host smart-07a97e38-2f36-4852-b18d-5b5689d06286
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867756358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
867756358
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2005945704
Short name T1121
Test name
Test status
Simulation time 56038067 ps
CPU time 1.76 seconds
Started Jun 30 05:27:35 PM PDT 24
Finished Jun 30 05:27:38 PM PDT 24
Peak memory 215536 kb
Host smart-7da43a16-16f4-483c-9873-4abbc7638764
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005945704 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2005945704
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.720999259
Short name T1062
Test name
Test status
Simulation time 19797918 ps
CPU time 1.3 seconds
Started Jun 30 05:27:36 PM PDT 24
Finished Jun 30 05:27:38 PM PDT 24
Peak memory 215388 kb
Host smart-62d54e39-b1a8-4d25-946b-264dda1f9dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720999259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.720999259
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2493194206
Short name T1043
Test name
Test status
Simulation time 32600094 ps
CPU time 0.71 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:38 PM PDT 24
Peak memory 203820 kb
Host smart-f994d1db-dc94-4fcc-a733-e35663c45dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493194206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2493194206
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.342465110
Short name T148
Test name
Test status
Simulation time 128824414 ps
CPU time 1.96 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:40 PM PDT 24
Peak memory 207196 kb
Host smart-d6fed2ac-f722-4527-a186-41769e12e369
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342465110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.342465110
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2191202693
Short name T1071
Test name
Test status
Simulation time 178920838 ps
CPU time 4.31 seconds
Started Jun 30 05:27:35 PM PDT 24
Finished Jun 30 05:27:40 PM PDT 24
Peak memory 215616 kb
Host smart-49565d6b-affb-4aa1-8cfa-77e5a7e6c4cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191202693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2191202693
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1456606511
Short name T175
Test name
Test status
Simulation time 210606965 ps
CPU time 13.19 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:51 PM PDT 24
Peak memory 215520 kb
Host smart-0556f396-6b77-498a-a129-998b6099dad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456606511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1456606511
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3816033178
Short name T1125
Test name
Test status
Simulation time 592250970 ps
CPU time 3.94 seconds
Started Jun 30 05:27:35 PM PDT 24
Finished Jun 30 05:27:40 PM PDT 24
Peak memory 217168 kb
Host smart-365259f2-04b0-4ab7-99f3-ae32aa629ccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816033178 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3816033178
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.632448426
Short name T1117
Test name
Test status
Simulation time 115306335 ps
CPU time 1.84 seconds
Started Jun 30 05:27:34 PM PDT 24
Finished Jun 30 05:27:37 PM PDT 24
Peak memory 215404 kb
Host smart-d1a698ff-49d9-4454-888f-e2053d429cf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632448426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.632448426
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3525785613
Short name T1030
Test name
Test status
Simulation time 12537979 ps
CPU time 0.72 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:39 PM PDT 24
Peak memory 203772 kb
Host smart-c4f55b68-ee0a-4aca-acda-06490144991c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525785613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3525785613
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4098410072
Short name T158
Test name
Test status
Simulation time 143145109 ps
CPU time 2.97 seconds
Started Jun 30 05:27:34 PM PDT 24
Finished Jun 30 05:27:38 PM PDT 24
Peak memory 215444 kb
Host smart-ea83d00c-e910-4945-9bd6-37e8bb78d80e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098410072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4098410072
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3770704151
Short name T1111
Test name
Test status
Simulation time 118371300 ps
CPU time 4.06 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:43 PM PDT 24
Peak memory 215540 kb
Host smart-f9717ac6-e3bf-4ea3-baaf-2f1ad27493f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770704151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3770704151
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4094138263
Short name T1112
Test name
Test status
Simulation time 1109832674 ps
CPU time 25.12 seconds
Started Jun 30 05:27:35 PM PDT 24
Finished Jun 30 05:28:01 PM PDT 24
Peak memory 222232 kb
Host smart-4f8dd22c-8a9d-47bc-958e-057ed8cbb042
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094138263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4094138263
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1077772825
Short name T1095
Test name
Test status
Simulation time 95780396 ps
CPU time 2.73 seconds
Started Jun 30 05:27:43 PM PDT 24
Finished Jun 30 05:27:46 PM PDT 24
Peak memory 216688 kb
Host smart-a59ace49-c3f3-400e-8ebc-806364cf204c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077772825 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1077772825
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4210085097
Short name T1131
Test name
Test status
Simulation time 265454464 ps
CPU time 1.46 seconds
Started Jun 30 05:27:40 PM PDT 24
Finished Jun 30 05:27:42 PM PDT 24
Peak memory 207208 kb
Host smart-75423ae2-d8f3-4e7c-8e74-a87e02880958
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210085097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4210085097
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.158692437
Short name T1052
Test name
Test status
Simulation time 13498545 ps
CPU time 0.71 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:39 PM PDT 24
Peak memory 203792 kb
Host smart-7905e6f1-21b8-4bb0-bc79-a8716d24ce43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158692437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.158692437
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2791499529
Short name T1110
Test name
Test status
Simulation time 55267338 ps
CPU time 1.77 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:40 PM PDT 24
Peak memory 215472 kb
Host smart-b246c525-93af-4baa-9abe-07697915b0eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791499529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2791499529
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3987328039
Short name T115
Test name
Test status
Simulation time 301163533 ps
CPU time 19.35 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:57 PM PDT 24
Peak memory 215396 kb
Host smart-bc87d8ae-096f-479e-b53b-8e3cc0de95d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987328039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3987328039
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.624415897
Short name T1091
Test name
Test status
Simulation time 41159790 ps
CPU time 2.83 seconds
Started Jun 30 05:28:08 PM PDT 24
Finished Jun 30 05:28:12 PM PDT 24
Peak memory 217148 kb
Host smart-c4fe2b29-b03a-4e7f-8752-2964b4f30a84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624415897 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.624415897
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.852995968
Short name T127
Test name
Test status
Simulation time 36556267 ps
CPU time 2.57 seconds
Started Jun 30 05:27:41 PM PDT 24
Finished Jun 30 05:27:44 PM PDT 24
Peak memory 215400 kb
Host smart-6322bd31-c85b-4b06-9b88-c8f9928c8452
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852995968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.852995968
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3907888258
Short name T1048
Test name
Test status
Simulation time 18038000 ps
CPU time 0.71 seconds
Started Jun 30 05:28:02 PM PDT 24
Finished Jun 30 05:28:03 PM PDT 24
Peak memory 204140 kb
Host smart-b3a04c41-9bb6-46f1-bf01-fe1c3b7fbcbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907888258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3907888258
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3234285747
Short name T1135
Test name
Test status
Simulation time 201632983 ps
CPU time 4.14 seconds
Started Jun 30 05:27:44 PM PDT 24
Finished Jun 30 05:27:49 PM PDT 24
Peak memory 215432 kb
Host smart-e4f01215-323c-4938-a713-78f1128e8031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234285747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3234285747
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2374540419
Short name T1101
Test name
Test status
Simulation time 128288999 ps
CPU time 3.33 seconds
Started Jun 30 05:27:44 PM PDT 24
Finished Jun 30 05:27:48 PM PDT 24
Peak memory 215636 kb
Host smart-19779d6d-8187-45fa-bff9-be0095c2ea5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374540419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2374540419
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1025611859
Short name T1133
Test name
Test status
Simulation time 110798573 ps
CPU time 2.82 seconds
Started Jun 30 05:27:43 PM PDT 24
Finished Jun 30 05:27:47 PM PDT 24
Peak memory 217056 kb
Host smart-6c6c7e39-3b30-48a2-b2d9-cae980194ccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025611859 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1025611859
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1605107818
Short name T1137
Test name
Test status
Simulation time 42512750 ps
CPU time 1.38 seconds
Started Jun 30 05:27:56 PM PDT 24
Finished Jun 30 05:27:59 PM PDT 24
Peak memory 215388 kb
Host smart-cc21342f-f895-4ec2-9517-9e972b89ea42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605107818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1605107818
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1070407137
Short name T1044
Test name
Test status
Simulation time 45569500 ps
CPU time 0.75 seconds
Started Jun 30 05:27:57 PM PDT 24
Finished Jun 30 05:27:59 PM PDT 24
Peak memory 203844 kb
Host smart-b181dd62-3c19-497c-8541-27fe4afdc501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070407137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1070407137
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3031991800
Short name T1100
Test name
Test status
Simulation time 136597788 ps
CPU time 1.78 seconds
Started Jun 30 05:27:45 PM PDT 24
Finished Jun 30 05:27:47 PM PDT 24
Peak memory 215408 kb
Host smart-db6db6b7-2f84-41ab-ab94-2e057853986e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031991800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3031991800
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1689110120
Short name T174
Test name
Test status
Simulation time 5348409274 ps
CPU time 7.69 seconds
Started Jun 30 05:28:08 PM PDT 24
Finished Jun 30 05:28:17 PM PDT 24
Peak memory 215732 kb
Host smart-1b0f0fa0-6f04-486c-82ba-22e256874de2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689110120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1689110120
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.239562714
Short name T113
Test name
Test status
Simulation time 146839373 ps
CPU time 1.8 seconds
Started Jun 30 05:27:43 PM PDT 24
Finished Jun 30 05:27:46 PM PDT 24
Peak memory 215432 kb
Host smart-af4d59a8-530f-4b2e-8dc1-7e96c87c85ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239562714 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.239562714
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4225338250
Short name T126
Test name
Test status
Simulation time 72257246 ps
CPU time 1.5 seconds
Started Jun 30 05:28:00 PM PDT 24
Finished Jun 30 05:28:02 PM PDT 24
Peak memory 207144 kb
Host smart-b348e579-c130-4e40-8280-45bd93cc1ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225338250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4225338250
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.159943636
Short name T1092
Test name
Test status
Simulation time 35352171 ps
CPU time 0.76 seconds
Started Jun 30 05:27:43 PM PDT 24
Finished Jun 30 05:27:45 PM PDT 24
Peak memory 204136 kb
Host smart-4f6227f9-6a16-44fe-93d3-a36287164013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159943636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.159943636
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2763164818
Short name T156
Test name
Test status
Simulation time 139422483 ps
CPU time 1.78 seconds
Started Jun 30 05:27:54 PM PDT 24
Finished Jun 30 05:27:57 PM PDT 24
Peak memory 215420 kb
Host smart-14912571-e7c1-4849-bc72-31a30e4da7bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763164818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2763164818
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1466488819
Short name T173
Test name
Test status
Simulation time 223641097 ps
CPU time 3.46 seconds
Started Jun 30 05:27:45 PM PDT 24
Finished Jun 30 05:27:49 PM PDT 24
Peak memory 215556 kb
Host smart-99ef0746-6674-4fe2-a065-b32b3bf86eec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466488819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1466488819
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1489226698
Short name T1107
Test name
Test status
Simulation time 1349895277 ps
CPU time 16.06 seconds
Started Jun 30 05:27:56 PM PDT 24
Finished Jun 30 05:28:13 PM PDT 24
Peak memory 215432 kb
Host smart-582bd600-718c-40e9-8fd8-aeda7465462e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489226698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1489226698
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.224464127
Short name T1115
Test name
Test status
Simulation time 131006156 ps
CPU time 3.91 seconds
Started Jun 30 05:28:05 PM PDT 24
Finished Jun 30 05:28:09 PM PDT 24
Peak memory 218052 kb
Host smart-1a275d4b-2074-4df9-94fe-3e7060e5adbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224464127 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.224464127
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4036803909
Short name T128
Test name
Test status
Simulation time 226543781 ps
CPU time 1.5 seconds
Started Jun 30 05:27:54 PM PDT 24
Finished Jun 30 05:27:56 PM PDT 24
Peak memory 207168 kb
Host smart-5ffd1f62-01d9-4e50-a39d-308511ba1c97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036803909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4036803909
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.534955816
Short name T1042
Test name
Test status
Simulation time 20990786 ps
CPU time 0.69 seconds
Started Jun 30 05:27:56 PM PDT 24
Finished Jun 30 05:27:57 PM PDT 24
Peak memory 203768 kb
Host smart-b3969a15-0eba-420b-b56c-ff149002b9cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534955816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.534955816
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4008768980
Short name T1126
Test name
Test status
Simulation time 1167816453 ps
CPU time 4.18 seconds
Started Jun 30 05:28:00 PM PDT 24
Finished Jun 30 05:28:05 PM PDT 24
Peak memory 215848 kb
Host smart-45aff5cb-9e2d-4ed1-b83f-9cd524221396
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008768980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4008768980
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3272589783
Short name T97
Test name
Test status
Simulation time 479244590 ps
CPU time 3.42 seconds
Started Jun 30 05:27:58 PM PDT 24
Finished Jun 30 05:28:03 PM PDT 24
Peak memory 215584 kb
Host smart-a1dd9a50-07dc-4884-82e7-70f5b0866a44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272589783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3272589783
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1176836410
Short name T114
Test name
Test status
Simulation time 1236001011 ps
CPU time 19.14 seconds
Started Jun 30 05:27:46 PM PDT 24
Finished Jun 30 05:28:05 PM PDT 24
Peak memory 215460 kb
Host smart-455afaa0-c8c4-4ba9-8685-b5f910a924c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176836410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1176836410
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4207542211
Short name T1066
Test name
Test status
Simulation time 207230458 ps
CPU time 3.65 seconds
Started Jun 30 05:27:55 PM PDT 24
Finished Jun 30 05:27:59 PM PDT 24
Peak memory 218536 kb
Host smart-200b10dc-c552-408a-920d-53fd242844af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207542211 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4207542211
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.486979761
Short name T1129
Test name
Test status
Simulation time 165484528 ps
CPU time 2.5 seconds
Started Jun 30 05:27:43 PM PDT 24
Finished Jun 30 05:27:46 PM PDT 24
Peak memory 215340 kb
Host smart-98573319-e5d7-425c-8d11-b52668d47a39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486979761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.486979761
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2872302976
Short name T1103
Test name
Test status
Simulation time 38647134 ps
CPU time 0.74 seconds
Started Jun 30 05:27:42 PM PDT 24
Finished Jun 30 05:27:43 PM PDT 24
Peak memory 204128 kb
Host smart-82c02a45-e62f-4361-96b8-60196b46a3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872302976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2872302976
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1919992783
Short name T1136
Test name
Test status
Simulation time 54386210 ps
CPU time 1.83 seconds
Started Jun 30 05:28:07 PM PDT 24
Finished Jun 30 05:28:09 PM PDT 24
Peak memory 215652 kb
Host smart-a3ff1c7b-97bf-4f43-95a3-016b565fc2af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919992783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1919992783
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3765794490
Short name T110
Test name
Test status
Simulation time 232972542 ps
CPU time 4.05 seconds
Started Jun 30 05:28:05 PM PDT 24
Finished Jun 30 05:28:10 PM PDT 24
Peak memory 215644 kb
Host smart-50d37049-d70b-46e5-94a0-521d01057a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765794490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3765794490
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2791511342
Short name T1106
Test name
Test status
Simulation time 124609933 ps
CPU time 3.69 seconds
Started Jun 30 05:28:08 PM PDT 24
Finished Jun 30 05:28:13 PM PDT 24
Peak memory 216760 kb
Host smart-2359b46c-f669-4283-88c8-8022752deef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791511342 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2791511342
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3936253359
Short name T1141
Test name
Test status
Simulation time 1405797942 ps
CPU time 2.81 seconds
Started Jun 30 05:27:44 PM PDT 24
Finished Jun 30 05:27:47 PM PDT 24
Peak memory 215348 kb
Host smart-45a0b637-cbd8-4403-94aa-ba17797087e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936253359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3936253359
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3911657984
Short name T1082
Test name
Test status
Simulation time 33265799 ps
CPU time 0.7 seconds
Started Jun 30 05:27:54 PM PDT 24
Finished Jun 30 05:27:55 PM PDT 24
Peak memory 204104 kb
Host smart-ca64d712-9c60-4149-b528-ac65784797e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911657984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3911657984
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.437388590
Short name T1114
Test name
Test status
Simulation time 47760634 ps
CPU time 1.92 seconds
Started Jun 30 05:28:00 PM PDT 24
Finished Jun 30 05:28:03 PM PDT 24
Peak memory 207232 kb
Host smart-fa8c8ed6-79e5-4584-b610-194d1cee09bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437388590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.437388590
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2622447595
Short name T105
Test name
Test status
Simulation time 112198921 ps
CPU time 2.81 seconds
Started Jun 30 05:27:45 PM PDT 24
Finished Jun 30 05:27:49 PM PDT 24
Peak memory 215616 kb
Host smart-4948b419-198b-4cb7-b4fe-778ade3f0958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622447595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2622447595
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.518390385
Short name T100
Test name
Test status
Simulation time 517361318 ps
CPU time 7.23 seconds
Started Jun 30 05:28:00 PM PDT 24
Finished Jun 30 05:28:08 PM PDT 24
Peak memory 221516 kb
Host smart-77620502-a5f4-4f43-9b36-296237d63058
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518390385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.518390385
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1267874163
Short name T1104
Test name
Test status
Simulation time 203559752 ps
CPU time 3.42 seconds
Started Jun 30 05:27:57 PM PDT 24
Finished Jun 30 05:28:01 PM PDT 24
Peak memory 218164 kb
Host smart-64bd7e4f-0c4c-45dc-ab6c-17e0921b48b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267874163 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1267874163
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1880262226
Short name T155
Test name
Test status
Simulation time 50108214 ps
CPU time 1.42 seconds
Started Jun 30 05:27:58 PM PDT 24
Finished Jun 30 05:28:00 PM PDT 24
Peak memory 207084 kb
Host smart-33a3e92e-5365-416b-a124-0a48c015b9b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880262226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1880262226
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3516126924
Short name T1122
Test name
Test status
Simulation time 18326514 ps
CPU time 0.77 seconds
Started Jun 30 05:28:02 PM PDT 24
Finished Jun 30 05:28:03 PM PDT 24
Peak memory 204352 kb
Host smart-0a5581de-3e27-4565-8d74-933377c9deb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516126924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3516126924
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3680521742
Short name T1039
Test name
Test status
Simulation time 153520264 ps
CPU time 1.9 seconds
Started Jun 30 05:27:54 PM PDT 24
Finished Jun 30 05:27:56 PM PDT 24
Peak memory 207204 kb
Host smart-bed08060-96fc-4708-9a1d-e7bbcbe7b68b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680521742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3680521742
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3279322432
Short name T1105
Test name
Test status
Simulation time 448273134 ps
CPU time 3.06 seconds
Started Jun 30 05:27:43 PM PDT 24
Finished Jun 30 05:27:47 PM PDT 24
Peak memory 215576 kb
Host smart-39bc7c17-6e74-48a2-9c3f-db9815105c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279322432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3279322432
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.338850982
Short name T162
Test name
Test status
Simulation time 8584165670 ps
CPU time 25.71 seconds
Started Jun 30 05:27:44 PM PDT 24
Finished Jun 30 05:28:10 PM PDT 24
Peak memory 215652 kb
Host smart-e1a97faa-b6f9-48ab-bd42-89133988ae57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338850982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.338850982
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4162537953
Short name T1138
Test name
Test status
Simulation time 311772803 ps
CPU time 22.14 seconds
Started Jun 30 05:27:21 PM PDT 24
Finished Jun 30 05:27:43 PM PDT 24
Peak memory 215396 kb
Host smart-20650c45-c36e-47c8-a49a-ce68e57ebb7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162537953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4162537953
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3022152832
Short name T119
Test name
Test status
Simulation time 1754218672 ps
CPU time 22.81 seconds
Started Jun 30 05:27:20 PM PDT 24
Finished Jun 30 05:27:43 PM PDT 24
Peak memory 207084 kb
Host smart-4f701df5-d955-4f95-bf53-a05dbad7550d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022152832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3022152832
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1456412309
Short name T1113
Test name
Test status
Simulation time 91165962 ps
CPU time 2.86 seconds
Started Jun 30 05:27:20 PM PDT 24
Finished Jun 30 05:27:23 PM PDT 24
Peak memory 216736 kb
Host smart-48a53856-766b-4a33-9ede-51ff85c6b944
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456412309 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1456412309
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.493772135
Short name T1058
Test name
Test status
Simulation time 35056450 ps
CPU time 1.26 seconds
Started Jun 30 05:27:21 PM PDT 24
Finished Jun 30 05:27:23 PM PDT 24
Peak memory 215316 kb
Host smart-4922da46-e516-4617-8275-710d30290138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493772135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.493772135
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1111884962
Short name T1046
Test name
Test status
Simulation time 23539468 ps
CPU time 0.77 seconds
Started Jun 30 05:27:21 PM PDT 24
Finished Jun 30 05:27:22 PM PDT 24
Peak memory 203884 kb
Host smart-6f9ef6a1-a0a1-4fbc-a9e9-1ee6e1f78dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111884962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
111884962
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2503168888
Short name T122
Test name
Test status
Simulation time 132809158 ps
CPU time 1.38 seconds
Started Jun 30 05:27:18 PM PDT 24
Finished Jun 30 05:27:20 PM PDT 24
Peak memory 215472 kb
Host smart-e0a14f5e-cc70-4950-bc7c-6850866a8e8c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503168888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2503168888
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1771769763
Short name T1050
Test name
Test status
Simulation time 13025023 ps
CPU time 0.66 seconds
Started Jun 30 05:27:20 PM PDT 24
Finished Jun 30 05:27:21 PM PDT 24
Peak memory 203708 kb
Host smart-af768654-e2d8-413a-a11f-97f9d98e04c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771769763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1771769763
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.407884880
Short name T1116
Test name
Test status
Simulation time 584738272 ps
CPU time 3.31 seconds
Started Jun 30 05:27:19 PM PDT 24
Finished Jun 30 05:27:23 PM PDT 24
Peak memory 215448 kb
Host smart-275c4862-b7d4-4611-966e-7dbcea5bcddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407884880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.407884880
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2230123007
Short name T108
Test name
Test status
Simulation time 34221086 ps
CPU time 1.78 seconds
Started Jun 30 05:27:22 PM PDT 24
Finished Jun 30 05:27:24 PM PDT 24
Peak memory 217312 kb
Host smart-9d7e85ee-8295-44be-bff8-c8c282bae242
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230123007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
230123007
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3562549610
Short name T1144
Test name
Test status
Simulation time 2083718715 ps
CPU time 16.02 seconds
Started Jun 30 05:27:21 PM PDT 24
Finished Jun 30 05:27:37 PM PDT 24
Peak memory 215332 kb
Host smart-05ff56c3-e4dd-482f-9354-67785286d697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562549610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3562549610
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2069403643
Short name T1040
Test name
Test status
Simulation time 42258330 ps
CPU time 0.73 seconds
Started Jun 30 05:28:00 PM PDT 24
Finished Jun 30 05:28:01 PM PDT 24
Peak memory 204132 kb
Host smart-b6cfc908-2e17-4955-889b-8cd2204d3961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069403643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2069403643
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4081758953
Short name T1148
Test name
Test status
Simulation time 20384991 ps
CPU time 0.75 seconds
Started Jun 30 05:27:56 PM PDT 24
Finished Jun 30 05:27:57 PM PDT 24
Peak memory 203820 kb
Host smart-6d3fa4c4-2690-4887-b549-78c8fb375748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081758953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4081758953
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3180316854
Short name T1067
Test name
Test status
Simulation time 13212726 ps
CPU time 0.74 seconds
Started Jun 30 05:28:00 PM PDT 24
Finished Jun 30 05:28:02 PM PDT 24
Peak memory 203780 kb
Host smart-f0e38f01-02ab-47e8-9cb8-7ca45990573d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180316854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3180316854
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2307278992
Short name T1149
Test name
Test status
Simulation time 19195791 ps
CPU time 0.71 seconds
Started Jun 30 05:27:58 PM PDT 24
Finished Jun 30 05:28:00 PM PDT 24
Peak memory 204084 kb
Host smart-0023f8ae-79f7-42a1-b6db-8bb487ce5420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307278992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2307278992
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1942832728
Short name T1134
Test name
Test status
Simulation time 33697112 ps
CPU time 0.73 seconds
Started Jun 30 05:27:44 PM PDT 24
Finished Jun 30 05:27:45 PM PDT 24
Peak memory 203860 kb
Host smart-8f0c4cfa-59f8-4720-961b-406a2aeb2c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942832728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1942832728
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.110466827
Short name T1083
Test name
Test status
Simulation time 20275925 ps
CPU time 0.71 seconds
Started Jun 30 05:27:42 PM PDT 24
Finished Jun 30 05:27:43 PM PDT 24
Peak memory 203788 kb
Host smart-fe151eb8-c7c7-4d34-9035-1fb46f16c558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110466827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.110466827
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2484077469
Short name T1124
Test name
Test status
Simulation time 13185902 ps
CPU time 0.74 seconds
Started Jun 30 05:27:59 PM PDT 24
Finished Jun 30 05:28:00 PM PDT 24
Peak memory 204132 kb
Host smart-cc5ded34-df0c-4972-b567-4a7d17ff3b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484077469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2484077469
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3281523712
Short name T1072
Test name
Test status
Simulation time 15957133 ps
CPU time 0.74 seconds
Started Jun 30 05:27:57 PM PDT 24
Finished Jun 30 05:27:59 PM PDT 24
Peak memory 203884 kb
Host smart-acad12f0-d656-47a2-a84e-63d06cfec452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281523712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3281523712
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.313112544
Short name T1087
Test name
Test status
Simulation time 35220580 ps
CPU time 0.81 seconds
Started Jun 30 05:28:00 PM PDT 24
Finished Jun 30 05:28:02 PM PDT 24
Peak memory 204128 kb
Host smart-4de2a0d4-9dc4-40ae-9cd6-0dcae4305df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313112544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.313112544
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2604209502
Short name T1041
Test name
Test status
Simulation time 15000918 ps
CPU time 0.72 seconds
Started Jun 30 05:28:08 PM PDT 24
Finished Jun 30 05:28:10 PM PDT 24
Peak memory 203816 kb
Host smart-dff9cf38-6787-47c3-8536-018f77d76971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604209502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2604209502
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2079340641
Short name T120
Test name
Test status
Simulation time 960254149 ps
CPU time 23.62 seconds
Started Jun 30 05:27:27 PM PDT 24
Finished Jun 30 05:27:52 PM PDT 24
Peak memory 215312 kb
Host smart-e366a319-0ee8-4663-97ea-b5c672ff4020
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079340641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2079340641
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1601788949
Short name T1069
Test name
Test status
Simulation time 359479489 ps
CPU time 12.41 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:38 PM PDT 24
Peak memory 207140 kb
Host smart-e0789187-45fc-45ac-87d4-4e13f1b25fb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601788949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1601788949
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1939943278
Short name T86
Test name
Test status
Simulation time 44186420 ps
CPU time 1.37 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:27 PM PDT 24
Peak memory 207092 kb
Host smart-6d252161-1035-439b-8d2a-cc9a04c46435
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939943278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1939943278
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1919552435
Short name T111
Test name
Test status
Simulation time 776745473 ps
CPU time 2.68 seconds
Started Jun 30 05:27:26 PM PDT 24
Finished Jun 30 05:27:29 PM PDT 24
Peak memory 216448 kb
Host smart-63d83702-bfcb-414d-ac57-8198e9bc1e9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919552435 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1919552435
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4271984932
Short name T131
Test name
Test status
Simulation time 79970014 ps
CPU time 2.13 seconds
Started Jun 30 05:27:26 PM PDT 24
Finished Jun 30 05:27:29 PM PDT 24
Peak memory 215392 kb
Host smart-45ca0805-f1ac-4e11-b2b8-2b47d1c8503f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271984932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
271984932
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3921105686
Short name T1037
Test name
Test status
Simulation time 140587811 ps
CPU time 0.76 seconds
Started Jun 30 05:27:27 PM PDT 24
Finished Jun 30 05:27:29 PM PDT 24
Peak memory 204136 kb
Host smart-33e0ca36-0d17-40b4-baa2-bd358cb39bcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921105686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
921105686
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2864730731
Short name T1123
Test name
Test status
Simulation time 82253081 ps
CPU time 1.51 seconds
Started Jun 30 05:27:27 PM PDT 24
Finished Jun 30 05:27:29 PM PDT 24
Peak memory 215432 kb
Host smart-aecda565-e6ca-445e-8d02-50c7a7308089
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864730731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2864730731
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3551790708
Short name T1029
Test name
Test status
Simulation time 25213470 ps
CPU time 0.65 seconds
Started Jun 30 05:27:27 PM PDT 24
Finished Jun 30 05:27:28 PM PDT 24
Peak memory 203700 kb
Host smart-6a7718ef-7202-4089-8e71-1652252b5574
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551790708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3551790708
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.380827948
Short name T1070
Test name
Test status
Simulation time 426385412 ps
CPU time 3.06 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:29 PM PDT 24
Peak memory 215464 kb
Host smart-2c7b8fe1-ad54-4512-b75e-ab01209a034e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380827948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.380827948
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2403666913
Short name T106
Test name
Test status
Simulation time 499639769 ps
CPU time 3.3 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:28 PM PDT 24
Peak memory 215708 kb
Host smart-cd4e6172-8d42-48f1-a654-d01ff0deffd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403666913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
403666913
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1889800917
Short name T1054
Test name
Test status
Simulation time 814229402 ps
CPU time 12.39 seconds
Started Jun 30 05:27:26 PM PDT 24
Finished Jun 30 05:27:39 PM PDT 24
Peak memory 215560 kb
Host smart-04e99a1f-ccaa-481f-93ab-041176d20e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889800917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1889800917
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.167768226
Short name T1068
Test name
Test status
Simulation time 43091446 ps
CPU time 0.79 seconds
Started Jun 30 05:27:59 PM PDT 24
Finished Jun 30 05:28:01 PM PDT 24
Peak memory 203880 kb
Host smart-e4fda811-3cf2-4788-82dd-3f32faf479c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167768226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.167768226
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2747994639
Short name T1097
Test name
Test status
Simulation time 141325728 ps
CPU time 0.7 seconds
Started Jun 30 05:27:56 PM PDT 24
Finished Jun 30 05:27:58 PM PDT 24
Peak memory 203796 kb
Host smart-3f3434d2-d0eb-48fe-b790-2867819aa861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747994639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2747994639
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1421160680
Short name T1031
Test name
Test status
Simulation time 30446013 ps
CPU time 0.75 seconds
Started Jun 30 05:27:54 PM PDT 24
Finished Jun 30 05:27:55 PM PDT 24
Peak memory 203872 kb
Host smart-b5ffc132-b3db-4384-9f45-d5ad56825229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421160680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1421160680
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.850990447
Short name T1049
Test name
Test status
Simulation time 36541074 ps
CPU time 0.7 seconds
Started Jun 30 05:27:58 PM PDT 24
Finished Jun 30 05:28:00 PM PDT 24
Peak memory 203784 kb
Host smart-c56dfce7-1c10-4c4d-8a8b-9b6bc2e59253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850990447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.850990447
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2102433683
Short name T1090
Test name
Test status
Simulation time 46734003 ps
CPU time 0.83 seconds
Started Jun 30 05:28:00 PM PDT 24
Finished Jun 30 05:28:01 PM PDT 24
Peak memory 203868 kb
Host smart-b31c9457-9586-42ae-86a4-f8fd4f2f10bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102433683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2102433683
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1715580352
Short name T1084
Test name
Test status
Simulation time 11507587 ps
CPU time 0.7 seconds
Started Jun 30 05:27:58 PM PDT 24
Finished Jun 30 05:28:00 PM PDT 24
Peak memory 204140 kb
Host smart-9542818e-e3af-4115-8606-b8b19ce6724c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715580352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1715580352
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1102070286
Short name T1053
Test name
Test status
Simulation time 11991528 ps
CPU time 0.7 seconds
Started Jun 30 05:27:55 PM PDT 24
Finished Jun 30 05:27:56 PM PDT 24
Peak memory 204108 kb
Host smart-69aa21cc-7efe-4ed6-85e4-d35ed7fad64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102070286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1102070286
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.294754200
Short name T1077
Test name
Test status
Simulation time 35012248 ps
CPU time 0.78 seconds
Started Jun 30 05:27:56 PM PDT 24
Finished Jun 30 05:27:58 PM PDT 24
Peak memory 204112 kb
Host smart-44d14237-887d-4921-87c1-84c14eee5b58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294754200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.294754200
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3104791253
Short name T1056
Test name
Test status
Simulation time 37328441 ps
CPU time 0.76 seconds
Started Jun 30 05:28:08 PM PDT 24
Finished Jun 30 05:28:10 PM PDT 24
Peak memory 203876 kb
Host smart-13392f98-e61f-47aa-ad38-9e99678c4ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104791253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3104791253
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3672392111
Short name T1118
Test name
Test status
Simulation time 14967100 ps
CPU time 0.76 seconds
Started Jun 30 05:27:55 PM PDT 24
Finished Jun 30 05:27:56 PM PDT 24
Peak memory 203864 kb
Host smart-a778d68d-78f0-4bee-bfa3-f35e89d1c3c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672392111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3672392111
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1388932697
Short name T1147
Test name
Test status
Simulation time 224775342 ps
CPU time 7.54 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:33 PM PDT 24
Peak memory 215404 kb
Host smart-ec4e3e3b-703d-4aea-adf3-5f90121118a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388932697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1388932697
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1870925295
Short name T1061
Test name
Test status
Simulation time 15125686098 ps
CPU time 35.58 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:28:01 PM PDT 24
Peak memory 207176 kb
Host smart-092d6a76-7179-41e8-b7d8-ff735e0ee0a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870925295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1870925295
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1001577844
Short name T84
Test name
Test status
Simulation time 32441538 ps
CPU time 1.2 seconds
Started Jun 30 05:27:27 PM PDT 24
Finished Jun 30 05:27:29 PM PDT 24
Peak memory 216404 kb
Host smart-12cc0127-90f6-46c2-bf08-1bd01b6be441
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001577844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1001577844
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1255312180
Short name T112
Test name
Test status
Simulation time 92702302 ps
CPU time 3.13 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:29 PM PDT 24
Peak memory 217976 kb
Host smart-583dec81-bc10-4a18-8c87-ad34a785fcfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255312180 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1255312180
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2156503019
Short name T1038
Test name
Test status
Simulation time 95902058 ps
CPU time 2.63 seconds
Started Jun 30 05:27:27 PM PDT 24
Finished Jun 30 05:27:30 PM PDT 24
Peak memory 207208 kb
Host smart-39b029d1-7e8c-4ac5-a03b-cf25407434c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156503019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
156503019
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.21665324
Short name T1081
Test name
Test status
Simulation time 11866973 ps
CPU time 0.75 seconds
Started Jun 30 05:27:28 PM PDT 24
Finished Jun 30 05:27:29 PM PDT 24
Peak memory 203872 kb
Host smart-1422ecf4-7cb7-417f-95d7-506f25cf1eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21665324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.21665324
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3594749269
Short name T1108
Test name
Test status
Simulation time 34797979 ps
CPU time 1.26 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:27 PM PDT 24
Peak memory 215476 kb
Host smart-6ba8b15f-ad9c-4eca-9d42-0743780e5c4c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594749269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3594749269
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2682871931
Short name T1099
Test name
Test status
Simulation time 14090691 ps
CPU time 0.64 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:27 PM PDT 24
Peak memory 203700 kb
Host smart-118e2a3c-9502-4800-a61a-990abd23c238
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682871931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2682871931
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.122821359
Short name T1085
Test name
Test status
Simulation time 160043656 ps
CPU time 4.56 seconds
Started Jun 30 05:27:27 PM PDT 24
Finished Jun 30 05:27:33 PM PDT 24
Peak memory 215368 kb
Host smart-e3c0cdd1-dfec-4b36-9558-90b9c8579264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122821359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.122821359
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2497360653
Short name T1060
Test name
Test status
Simulation time 818548222 ps
CPU time 4.73 seconds
Started Jun 30 05:27:26 PM PDT 24
Finished Jun 30 05:27:31 PM PDT 24
Peak memory 215756 kb
Host smart-a1861744-f2dc-402b-aa1d-b4a564f89cae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497360653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
497360653
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.752700262
Short name T1073
Test name
Test status
Simulation time 912759422 ps
CPU time 7.15 seconds
Started Jun 30 05:27:27 PM PDT 24
Finished Jun 30 05:27:35 PM PDT 24
Peak memory 215440 kb
Host smart-cd27a884-5555-4c1d-8088-0d07ac580f29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752700262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.752700262
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1722381502
Short name T1140
Test name
Test status
Simulation time 100933200 ps
CPU time 0.72 seconds
Started Jun 30 05:27:57 PM PDT 24
Finished Jun 30 05:27:58 PM PDT 24
Peak memory 204140 kb
Host smart-e098a0eb-09e3-4e08-969e-5cd47136a44f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722381502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1722381502
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1805265059
Short name T1064
Test name
Test status
Simulation time 52745226 ps
CPU time 0.78 seconds
Started Jun 30 05:27:57 PM PDT 24
Finished Jun 30 05:27:59 PM PDT 24
Peak memory 203824 kb
Host smart-0cb85a37-2527-4dea-88ad-09a7e44b2356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805265059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1805265059
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1730498954
Short name T1076
Test name
Test status
Simulation time 14025592 ps
CPU time 0.72 seconds
Started Jun 30 05:27:58 PM PDT 24
Finished Jun 30 05:28:00 PM PDT 24
Peak memory 203752 kb
Host smart-4392d5e7-41c5-4587-8824-dbb053393b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730498954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1730498954
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.457849414
Short name T1102
Test name
Test status
Simulation time 34029813 ps
CPU time 0.75 seconds
Started Jun 30 05:27:56 PM PDT 24
Finished Jun 30 05:27:57 PM PDT 24
Peak memory 203840 kb
Host smart-a1e733a9-7a0e-4f5f-aa04-f0cf477a6072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457849414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.457849414
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1265740746
Short name T1119
Test name
Test status
Simulation time 14337090 ps
CPU time 0.74 seconds
Started Jun 30 05:27:57 PM PDT 24
Finished Jun 30 05:27:59 PM PDT 24
Peak memory 203872 kb
Host smart-133b6789-ea70-4f20-af36-121955591c57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265740746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1265740746
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2414577473
Short name T1079
Test name
Test status
Simulation time 33685597 ps
CPU time 0.72 seconds
Started Jun 30 05:27:57 PM PDT 24
Finished Jun 30 05:27:59 PM PDT 24
Peak memory 203880 kb
Host smart-bcbe0ac4-37b5-4366-9437-318d70d95a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414577473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2414577473
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3764291415
Short name T1063
Test name
Test status
Simulation time 42493031 ps
CPU time 0.7 seconds
Started Jun 30 05:27:59 PM PDT 24
Finished Jun 30 05:28:01 PM PDT 24
Peak memory 203808 kb
Host smart-18ee56c1-f481-4cbb-97c1-5c9aff7f02d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764291415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3764291415
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2535952299
Short name T1094
Test name
Test status
Simulation time 28657441 ps
CPU time 0.72 seconds
Started Jun 30 05:27:59 PM PDT 24
Finished Jun 30 05:28:01 PM PDT 24
Peak memory 203812 kb
Host smart-26ebe952-4434-4645-b7e8-914118d6d354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535952299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2535952299
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2824339015
Short name T1065
Test name
Test status
Simulation time 16587625 ps
CPU time 0.77 seconds
Started Jun 30 05:28:07 PM PDT 24
Finished Jun 30 05:28:08 PM PDT 24
Peak memory 204032 kb
Host smart-02637a0f-a633-47cf-96f7-66f2f7b8453d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824339015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2824339015
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1270231320
Short name T1047
Test name
Test status
Simulation time 23535477 ps
CPU time 0.77 seconds
Started Jun 30 05:27:56 PM PDT 24
Finished Jun 30 05:27:58 PM PDT 24
Peak memory 204060 kb
Host smart-ee050b2c-d6cc-4d7f-8ae0-4df65461d963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270231320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1270231320
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1340475054
Short name T99
Test name
Test status
Simulation time 151579603 ps
CPU time 2.58 seconds
Started Jun 30 05:27:26 PM PDT 24
Finished Jun 30 05:27:29 PM PDT 24
Peak memory 217144 kb
Host smart-9cb0d8ee-a481-4ea0-9f28-3c432ba5e334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340475054 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1340475054
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4032768554
Short name T1059
Test name
Test status
Simulation time 71773193 ps
CPU time 1.29 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:28 PM PDT 24
Peak memory 215344 kb
Host smart-b27b82c4-00a9-4e84-8daf-2de45065ca2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032768554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
032768554
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1444773268
Short name T1028
Test name
Test status
Simulation time 14071118 ps
CPU time 0.76 seconds
Started Jun 30 05:27:26 PM PDT 24
Finished Jun 30 05:27:28 PM PDT 24
Peak memory 203728 kb
Host smart-6d7eb5e2-d910-4f4f-a8c3-3929190e3b1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444773268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
444773268
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2844751631
Short name T1096
Test name
Test status
Simulation time 738157055 ps
CPU time 4.4 seconds
Started Jun 30 05:27:26 PM PDT 24
Finished Jun 30 05:27:31 PM PDT 24
Peak memory 215352 kb
Host smart-10eb164f-5bb4-4e78-94ed-78aa2c6eca3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844751631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2844751631
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.567763401
Short name T1109
Test name
Test status
Simulation time 177521765 ps
CPU time 4.05 seconds
Started Jun 30 05:27:26 PM PDT 24
Finished Jun 30 05:27:31 PM PDT 24
Peak memory 215712 kb
Host smart-ac89009a-d00c-44f5-b1c9-339288334b75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567763401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.567763401
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2833732087
Short name T176
Test name
Test status
Simulation time 1172725581 ps
CPU time 19.93 seconds
Started Jun 30 05:27:26 PM PDT 24
Finished Jun 30 05:27:47 PM PDT 24
Peak memory 215964 kb
Host smart-76a34045-71fb-4a87-93fe-4059862bd6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833732087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2833732087
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.974037323
Short name T160
Test name
Test status
Simulation time 214633672 ps
CPU time 3.87 seconds
Started Jun 30 05:27:35 PM PDT 24
Finished Jun 30 05:27:39 PM PDT 24
Peak memory 216528 kb
Host smart-f9abdd05-e1fe-4fb2-883a-738bff89a2e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974037323 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.974037323
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3732188342
Short name T1055
Test name
Test status
Simulation time 227912695 ps
CPU time 2.01 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:40 PM PDT 24
Peak memory 215404 kb
Host smart-16acb9ee-2ff6-4dd2-975b-ca462b6f67fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732188342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
732188342
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1287677581
Short name T1132
Test name
Test status
Simulation time 14495637 ps
CPU time 0.75 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:27 PM PDT 24
Peak memory 204136 kb
Host smart-8e370f68-32bb-4f19-9f00-d5e7646da1e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287677581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
287677581
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.127807901
Short name T147
Test name
Test status
Simulation time 116898276 ps
CPU time 2.7 seconds
Started Jun 30 05:27:35 PM PDT 24
Finished Jun 30 05:27:39 PM PDT 24
Peak memory 215416 kb
Host smart-de5f5929-97b8-4a9b-a8f5-6092e0a8d6cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127807901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.127807901
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1280816571
Short name T161
Test name
Test status
Simulation time 329282887 ps
CPU time 4.2 seconds
Started Jun 30 05:27:27 PM PDT 24
Finished Jun 30 05:27:32 PM PDT 24
Peak memory 215748 kb
Host smart-8f65588d-c391-4bb8-b16b-2b7e43fc18ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280816571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
280816571
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1615909454
Short name T116
Test name
Test status
Simulation time 106675438 ps
CPU time 6.34 seconds
Started Jun 30 05:27:25 PM PDT 24
Finished Jun 30 05:27:32 PM PDT 24
Peak memory 215408 kb
Host smart-5c3056cc-30a9-443b-b541-8bfec551271f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615909454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1615909454
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1998515224
Short name T157
Test name
Test status
Simulation time 125433694 ps
CPU time 3 seconds
Started Jun 30 05:27:35 PM PDT 24
Finished Jun 30 05:27:39 PM PDT 24
Peak memory 218060 kb
Host smart-0660482d-7c3f-4b74-8f73-b35f2ce18040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998515224 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1998515224
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.473100826
Short name T123
Test name
Test status
Simulation time 123326887 ps
CPU time 2.28 seconds
Started Jun 30 05:27:36 PM PDT 24
Finished Jun 30 05:27:39 PM PDT 24
Peak memory 215296 kb
Host smart-de86d64d-5b8b-4f14-bc34-13265ace6312
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473100826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.473100826
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1587738785
Short name T1033
Test name
Test status
Simulation time 56632364 ps
CPU time 0.78 seconds
Started Jun 30 05:27:34 PM PDT 24
Finished Jun 30 05:27:36 PM PDT 24
Peak memory 203860 kb
Host smart-59735cf8-2b4c-4552-94a6-e41664de138b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587738785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
587738785
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1550395552
Short name T1139
Test name
Test status
Simulation time 103878116 ps
CPU time 1.86 seconds
Started Jun 30 05:27:36 PM PDT 24
Finished Jun 30 05:27:38 PM PDT 24
Peak memory 215372 kb
Host smart-3424ba16-855f-419f-bd8f-37e545ef32a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550395552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1550395552
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1802060633
Short name T1151
Test name
Test status
Simulation time 302019684 ps
CPU time 17.13 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:56 PM PDT 24
Peak memory 215592 kb
Host smart-31869583-c4db-4665-83cd-f90737165ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802060633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1802060633
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1034833830
Short name T1051
Test name
Test status
Simulation time 336540876 ps
CPU time 3.18 seconds
Started Jun 30 05:27:35 PM PDT 24
Finished Jun 30 05:27:38 PM PDT 24
Peak memory 218000 kb
Host smart-ac40ba2d-3562-496e-9ae6-16a0f7454676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034833830 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1034833830
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.94468501
Short name T1035
Test name
Test status
Simulation time 39461219 ps
CPU time 1.32 seconds
Started Jun 30 05:27:39 PM PDT 24
Finished Jun 30 05:27:41 PM PDT 24
Peak memory 215324 kb
Host smart-b0e98a22-33e4-47e3-b56c-c984f06ab482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94468501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.94468501
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1922340655
Short name T1150
Test name
Test status
Simulation time 11073549 ps
CPU time 0.69 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:39 PM PDT 24
Peak memory 203824 kb
Host smart-8581f7dc-25c0-460a-8193-51a8d49d0e3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922340655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
922340655
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2109398687
Short name T1074
Test name
Test status
Simulation time 44884251 ps
CPU time 2.92 seconds
Started Jun 30 05:27:40 PM PDT 24
Finished Jun 30 05:27:43 PM PDT 24
Peak memory 215464 kb
Host smart-efce59c2-7e5e-4d2f-8533-798718858d20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109398687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2109398687
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.648777125
Short name T1093
Test name
Test status
Simulation time 193530624 ps
CPU time 3.46 seconds
Started Jun 30 05:27:37 PM PDT 24
Finished Jun 30 05:27:42 PM PDT 24
Peak memory 215560 kb
Host smart-ec8f09de-f7b3-4761-8465-c4ad2cb5566b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648777125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.648777125
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1634528009
Short name T1089
Test name
Test status
Simulation time 110458186 ps
CPU time 7.06 seconds
Started Jun 30 05:27:36 PM PDT 24
Finished Jun 30 05:27:43 PM PDT 24
Peak memory 215376 kb
Host smart-bef04566-73a1-4c09-9b2f-ec1e1aea70ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634528009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1634528009
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3001207683
Short name T1057
Test name
Test status
Simulation time 224669712 ps
CPU time 3.54 seconds
Started Jun 30 05:27:38 PM PDT 24
Finished Jun 30 05:27:42 PM PDT 24
Peak memory 217392 kb
Host smart-a2a06150-3b96-49fb-b86b-d485d89eec4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001207683 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3001207683
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2045850145
Short name T129
Test name
Test status
Simulation time 85030143 ps
CPU time 1.42 seconds
Started Jun 30 05:27:36 PM PDT 24
Finished Jun 30 05:27:38 PM PDT 24
Peak memory 215316 kb
Host smart-7c9b2e9c-2774-4a2d-9f7c-beee2ce5f647
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045850145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
045850145
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4034208340
Short name T1078
Test name
Test status
Simulation time 30473654 ps
CPU time 0.77 seconds
Started Jun 30 05:27:36 PM PDT 24
Finished Jun 30 05:27:37 PM PDT 24
Peak memory 204032 kb
Host smart-dbba0b1c-e104-4755-8882-4f32d33e9007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034208340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
034208340
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3521190731
Short name T1080
Test name
Test status
Simulation time 161078382 ps
CPU time 3.1 seconds
Started Jun 30 05:27:32 PM PDT 24
Finished Jun 30 05:27:36 PM PDT 24
Peak memory 215444 kb
Host smart-971152b0-2869-4027-897a-e3f0b6ab2fa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521190731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3521190731
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1532482176
Short name T109
Test name
Test status
Simulation time 358088722 ps
CPU time 3.27 seconds
Started Jun 30 05:27:35 PM PDT 24
Finished Jun 30 05:27:39 PM PDT 24
Peak memory 215596 kb
Host smart-70ea0568-1ac2-4a79-9bc4-c67c329438de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532482176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
532482176
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3010151680
Short name T1127
Test name
Test status
Simulation time 1850462561 ps
CPU time 12.27 seconds
Started Jun 30 05:27:39 PM PDT 24
Finished Jun 30 05:27:52 PM PDT 24
Peak memory 215968 kb
Host smart-d4e8a325-e1f6-489c-a19e-8e81c462e8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010151680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3010151680
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.129510509
Short name T803
Test name
Test status
Simulation time 14327036 ps
CPU time 0.75 seconds
Started Jun 30 06:58:38 PM PDT 24
Finished Jun 30 06:58:40 PM PDT 24
Peak memory 205392 kb
Host smart-ee353e42-d1cb-40d9-b895-045bc997df26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129510509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.129510509
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2297062869
Short name T981
Test name
Test status
Simulation time 78411132 ps
CPU time 2.79 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 06:58:42 PM PDT 24
Peak memory 232640 kb
Host smart-3dc25d0e-402d-4ee6-8d4f-d0716a415269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297062869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2297062869
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2512236861
Short name T899
Test name
Test status
Simulation time 14366422 ps
CPU time 0.76 seconds
Started Jun 30 06:58:29 PM PDT 24
Finished Jun 30 06:58:31 PM PDT 24
Peak memory 205508 kb
Host smart-a8046154-834f-4101-b044-b69133659c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512236861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2512236861
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.661780387
Short name T943
Test name
Test status
Simulation time 44323003724 ps
CPU time 106.46 seconds
Started Jun 30 06:58:38 PM PDT 24
Finished Jun 30 07:00:26 PM PDT 24
Peak memory 249164 kb
Host smart-2709ad52-1554-496e-aede-cc4938ef596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661780387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.661780387
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2160556744
Short name T811
Test name
Test status
Simulation time 81112740137 ps
CPU time 731.19 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 07:10:48 PM PDT 24
Peak memory 263864 kb
Host smart-92c13676-bee1-46d7-99de-3538dcfb0433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160556744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2160556744
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3532727270
Short name T997
Test name
Test status
Simulation time 1150052740 ps
CPU time 6.87 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 06:58:45 PM PDT 24
Peak memory 217444 kb
Host smart-c242733a-42ed-4ccf-9347-3f7ee00b9e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532727270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3532727270
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.397097912
Short name T255
Test name
Test status
Simulation time 21866301352 ps
CPU time 147.39 seconds
Started Jun 30 06:58:38 PM PDT 24
Finished Jun 30 07:01:07 PM PDT 24
Peak memory 249136 kb
Host smart-1263a927-dfc0-4a10-8477-06a5d9d48445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397097912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
397097912
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2155846606
Short name T197
Test name
Test status
Simulation time 2457825140 ps
CPU time 9.34 seconds
Started Jun 30 06:58:33 PM PDT 24
Finished Jun 30 06:58:42 PM PDT 24
Peak memory 232744 kb
Host smart-1f970d22-9a0e-425d-ae00-5b3ebbf21cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155846606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2155846606
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1961893811
Short name T644
Test name
Test status
Simulation time 4970706932 ps
CPU time 15.43 seconds
Started Jun 30 06:58:27 PM PDT 24
Finished Jun 30 06:58:44 PM PDT 24
Peak memory 232700 kb
Host smart-fdb15037-02e3-4201-8138-912c38483b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961893811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1961893811
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2609393119
Short name T262
Test name
Test status
Simulation time 24466809497 ps
CPU time 12.53 seconds
Started Jun 30 06:58:34 PM PDT 24
Finished Jun 30 06:58:47 PM PDT 24
Peak memory 240440 kb
Host smart-ab215dd7-46b5-4843-91ac-a559922ab636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609393119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2609393119
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2613186098
Short name T749
Test name
Test status
Simulation time 3583557507 ps
CPU time 11.66 seconds
Started Jun 30 06:58:31 PM PDT 24
Finished Jun 30 06:58:43 PM PDT 24
Peak memory 232772 kb
Host smart-e6e01f80-6bde-4ed6-a0c7-97bc7c28c8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613186098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2613186098
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2368004561
Short name T823
Test name
Test status
Simulation time 1439849871 ps
CPU time 12.97 seconds
Started Jun 30 06:58:39 PM PDT 24
Finished Jun 30 06:58:53 PM PDT 24
Peak memory 223096 kb
Host smart-7fbc6633-fd0a-4199-895f-fb5538901afa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2368004561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2368004561
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3198461580
Short name T551
Test name
Test status
Simulation time 60892087064 ps
CPU time 574.21 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 07:08:13 PM PDT 24
Peak memory 265632 kb
Host smart-0dc953f7-6552-4b7e-98a6-eb994cd70412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198461580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3198461580
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.910922370
Short name T527
Test name
Test status
Simulation time 6818070523 ps
CPU time 39.72 seconds
Started Jun 30 06:58:35 PM PDT 24
Finished Jun 30 06:59:16 PM PDT 24
Peak memory 220092 kb
Host smart-070138b9-a0bc-4ee0-9263-cd097bb99a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910922370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.910922370
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3185364570
Short name T605
Test name
Test status
Simulation time 9865383043 ps
CPU time 15.46 seconds
Started Jun 30 06:58:29 PM PDT 24
Finished Jun 30 06:58:46 PM PDT 24
Peak memory 216276 kb
Host smart-5c6b4999-d409-4fef-a1b1-49b8badc33c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185364570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3185364570
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2683411839
Short name T581
Test name
Test status
Simulation time 42424149 ps
CPU time 1.62 seconds
Started Jun 30 06:58:30 PM PDT 24
Finished Jun 30 06:58:33 PM PDT 24
Peak memory 207972 kb
Host smart-dd4b5a1a-3a81-480e-aeee-d8f133c786a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683411839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2683411839
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3158903639
Short name T636
Test name
Test status
Simulation time 259710768 ps
CPU time 0.88 seconds
Started Jun 30 06:58:30 PM PDT 24
Finished Jun 30 06:58:32 PM PDT 24
Peak memory 205800 kb
Host smart-96b09ff6-dbb8-445e-9a82-95d61892942b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158903639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3158903639
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1452622600
Short name T307
Test name
Test status
Simulation time 3826700360 ps
CPU time 8.3 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:58:52 PM PDT 24
Peak memory 224600 kb
Host smart-5158bbf9-6cbe-4d0d-97b7-b17a8b849fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452622600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1452622600
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.171343829
Short name T839
Test name
Test status
Simulation time 72703070 ps
CPU time 0.77 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:58:37 PM PDT 24
Peak memory 205408 kb
Host smart-cde9b282-dbc4-4548-b7ed-556a2dbe0af7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171343829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.171343829
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3535307402
Short name T373
Test name
Test status
Simulation time 1562170346 ps
CPU time 8.91 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 06:58:47 PM PDT 24
Peak memory 232576 kb
Host smart-8b62d37c-69fe-440b-b6bc-eee83f65e9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535307402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3535307402
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3906517935
Short name T808
Test name
Test status
Simulation time 97863240 ps
CPU time 0.83 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:58:38 PM PDT 24
Peak memory 206572 kb
Host smart-785f6579-4b1f-4295-8fd3-469471a5ff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906517935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3906517935
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1479830133
Short name T685
Test name
Test status
Simulation time 9264500298 ps
CPU time 15.02 seconds
Started Jun 30 06:58:38 PM PDT 24
Finished Jun 30 06:58:54 PM PDT 24
Peak memory 224552 kb
Host smart-cc991ad7-1305-47bd-9d42-3ae91c1484b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479830133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1479830133
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3979430496
Short name T542
Test name
Test status
Simulation time 6224263188 ps
CPU time 26.27 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:59:04 PM PDT 24
Peak memory 224616 kb
Host smart-fe852380-f90c-42f1-8698-09f98c1053a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979430496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3979430496
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.275161127
Short name T279
Test name
Test status
Simulation time 1432564877 ps
CPU time 25.93 seconds
Started Jun 30 06:58:41 PM PDT 24
Finished Jun 30 06:59:07 PM PDT 24
Peak memory 240820 kb
Host smart-d73f300a-63e9-4cc0-9a97-c341f971a260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275161127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.275161127
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1249857159
Short name T178
Test name
Test status
Simulation time 54167119661 ps
CPU time 110.92 seconds
Started Jun 30 06:58:35 PM PDT 24
Finished Jun 30 07:00:27 PM PDT 24
Peak memory 249164 kb
Host smart-44db8d6c-c2bc-4de3-a230-8cf2066af5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249857159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1249857159
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4293707918
Short name T679
Test name
Test status
Simulation time 412097591 ps
CPU time 4.63 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 06:58:43 PM PDT 24
Peak memory 224504 kb
Host smart-98e8b75c-b26a-481d-8d39-431f8bcaee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293707918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4293707918
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.864334826
Short name T349
Test name
Test status
Simulation time 26408596411 ps
CPU time 37.9 seconds
Started Jun 30 06:58:34 PM PDT 24
Finished Jun 30 06:59:13 PM PDT 24
Peak memory 232788 kb
Host smart-9ccab0d5-f7a0-4c70-ad85-8f398083c302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864334826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.864334826
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1567702351
Short name T409
Test name
Test status
Simulation time 15480315 ps
CPU time 1.03 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:58:38 PM PDT 24
Peak memory 216772 kb
Host smart-638f7abe-af57-48cd-9315-d751af2ba673
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567702351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1567702351
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3553316856
Short name T931
Test name
Test status
Simulation time 50513050 ps
CPU time 2.35 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 06:58:40 PM PDT 24
Peak memory 224420 kb
Host smart-dcc46743-3325-430f-97cc-4ec83f93b178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553316856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3553316856
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1271421746
Short name T243
Test name
Test status
Simulation time 778935345 ps
CPU time 6.38 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:58:43 PM PDT 24
Peak memory 232668 kb
Host smart-196ae032-080b-442c-9846-9bb5c6d11126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271421746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1271421746
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3472703758
Short name T723
Test name
Test status
Simulation time 1016279473 ps
CPU time 5.33 seconds
Started Jun 30 06:58:34 PM PDT 24
Finished Jun 30 06:58:40 PM PDT 24
Peak memory 222448 kb
Host smart-dd8dae36-9235-41a8-a04f-b8a381afc6ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3472703758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3472703758
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1864393349
Short name T64
Test name
Test status
Simulation time 93393298 ps
CPU time 1.25 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:58:38 PM PDT 24
Peak memory 236576 kb
Host smart-0631fe21-98eb-456d-9420-84d8432dc777
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864393349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1864393349
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1931504281
Short name T164
Test name
Test status
Simulation time 11764091604 ps
CPU time 146.22 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 07:01:03 PM PDT 24
Peak memory 266804 kb
Host smart-ade72f6e-380c-4bff-9a4b-62bc528422e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931504281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1931504281
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.912281233
Short name T927
Test name
Test status
Simulation time 1900726533 ps
CPU time 18.21 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:58:55 PM PDT 24
Peak memory 216436 kb
Host smart-149955f0-ce87-4345-a19b-d7052acd0861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912281233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.912281233
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1337470723
Short name T500
Test name
Test status
Simulation time 3568231298 ps
CPU time 10.48 seconds
Started Jun 30 06:58:38 PM PDT 24
Finished Jun 30 06:58:50 PM PDT 24
Peak memory 216308 kb
Host smart-75e29b81-3194-4895-98f4-074d853bcd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337470723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1337470723
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2668810200
Short name T314
Test name
Test status
Simulation time 40064377 ps
CPU time 0.89 seconds
Started Jun 30 06:58:35 PM PDT 24
Finished Jun 30 06:58:36 PM PDT 24
Peak memory 207880 kb
Host smart-1f698d53-9f5a-4cdf-9bec-8b7e496360d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668810200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2668810200
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2450591068
Short name T810
Test name
Test status
Simulation time 16984306 ps
CPU time 0.73 seconds
Started Jun 30 06:58:35 PM PDT 24
Finished Jun 30 06:58:36 PM PDT 24
Peak memory 205892 kb
Host smart-d5d9d5d1-a531-45e2-95af-0d20945b563c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450591068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2450591068
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1508067132
Short name T562
Test name
Test status
Simulation time 91293710 ps
CPU time 2.39 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:58:40 PM PDT 24
Peak memory 224488 kb
Host smart-fc709ebb-c289-4fdd-b9ca-f85e1e9cff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508067132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1508067132
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1288782514
Short name T391
Test name
Test status
Simulation time 51155978 ps
CPU time 2.49 seconds
Started Jun 30 06:59:07 PM PDT 24
Finished Jun 30 06:59:10 PM PDT 24
Peak memory 232648 kb
Host smart-7731b876-aae5-4be0-9379-4aaecc76f17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288782514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1288782514
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3201405971
Short name T170
Test name
Test status
Simulation time 19913842 ps
CPU time 0.78 seconds
Started Jun 30 06:59:04 PM PDT 24
Finished Jun 30 06:59:06 PM PDT 24
Peak memory 205520 kb
Host smart-e80b36f1-ae55-4ec8-8e65-733c849b3aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201405971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3201405971
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2613981259
Short name T244
Test name
Test status
Simulation time 15160996822 ps
CPU time 132.95 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 07:01:19 PM PDT 24
Peak memory 255572 kb
Host smart-baaf6148-79a3-45d6-9dfb-7436c0030717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613981259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2613981259
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.461185118
Short name T140
Test name
Test status
Simulation time 4820003579 ps
CPU time 14.55 seconds
Started Jun 30 06:59:04 PM PDT 24
Finished Jun 30 06:59:19 PM PDT 24
Peak memory 217632 kb
Host smart-a3a5b134-0a82-4766-9b27-ce97feb73072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461185118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.461185118
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2640286812
Short name T716
Test name
Test status
Simulation time 9013695609 ps
CPU time 57.7 seconds
Started Jun 30 06:59:03 PM PDT 24
Finished Jun 30 07:00:02 PM PDT 24
Peak memory 249264 kb
Host smart-de78a204-393d-4856-8603-b6e5ef929505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640286812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2640286812
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.41648234
Short name T154
Test name
Test status
Simulation time 5636388312 ps
CPU time 21.3 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:28 PM PDT 24
Peak memory 224596 kb
Host smart-40f10d52-a911-4bdc-80c6-50400ad96764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41648234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.41648234
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1528545828
Short name T233
Test name
Test status
Simulation time 47274044148 ps
CPU time 378.91 seconds
Started Jun 30 06:59:06 PM PDT 24
Finished Jun 30 07:05:26 PM PDT 24
Peak memory 266584 kb
Host smart-c2bc0fa7-d010-49a6-84cf-8bb3bd4a2815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528545828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1528545828
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1984365767
Short name T499
Test name
Test status
Simulation time 7335855608 ps
CPU time 18.29 seconds
Started Jun 30 06:59:07 PM PDT 24
Finished Jun 30 06:59:26 PM PDT 24
Peak memory 224552 kb
Host smart-cf486c21-4095-498a-8365-d36a32e03a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984365767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1984365767
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.14559702
Short name T955
Test name
Test status
Simulation time 345445236 ps
CPU time 2.52 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:09 PM PDT 24
Peak memory 224408 kb
Host smart-c68ca008-f017-4ba3-b173-15d8f38b4598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14559702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.14559702
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.4196511691
Short name T345
Test name
Test status
Simulation time 15619143 ps
CPU time 1.03 seconds
Started Jun 30 06:59:04 PM PDT 24
Finished Jun 30 06:59:06 PM PDT 24
Peak memory 216764 kb
Host smart-097a2858-d171-4c7d-a529-80ed302fa54b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196511691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.4196511691
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1549189399
Short name T639
Test name
Test status
Simulation time 2087071283 ps
CPU time 7.84 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:14 PM PDT 24
Peak memory 224424 kb
Host smart-c0c5192e-50b6-451d-be92-2dd5d09e9550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549189399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1549189399
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.589438800
Short name T198
Test name
Test status
Simulation time 29561381430 ps
CPU time 20.96 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:27 PM PDT 24
Peak memory 232756 kb
Host smart-bafb5b4a-a530-4e0f-94b6-cdc88b560f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589438800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.589438800
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1742018366
Short name T984
Test name
Test status
Simulation time 380684519 ps
CPU time 5.69 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:12 PM PDT 24
Peak memory 219244 kb
Host smart-fe584141-0d00-4fe8-b7e7-59922418be93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1742018366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1742018366
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2799926018
Short name T143
Test name
Test status
Simulation time 39688799764 ps
CPU time 259.01 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 07:03:26 PM PDT 24
Peak memory 265636 kb
Host smart-9b0610c2-90c5-4b61-9ca5-c5eec40cad53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799926018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2799926018
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3734118935
Short name T735
Test name
Test status
Simulation time 293342967 ps
CPU time 0.71 seconds
Started Jun 30 06:59:07 PM PDT 24
Finished Jun 30 06:59:08 PM PDT 24
Peak memory 205700 kb
Host smart-c365f868-6e94-4fcf-8b8c-85f0be568c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734118935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3734118935
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1440582456
Short name T962
Test name
Test status
Simulation time 11002305402 ps
CPU time 7.3 seconds
Started Jun 30 06:59:06 PM PDT 24
Finished Jun 30 06:59:14 PM PDT 24
Peak memory 216348 kb
Host smart-e837af63-76f7-4891-96eb-d09d7288fc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440582456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1440582456
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.646980918
Short name T987
Test name
Test status
Simulation time 35510332 ps
CPU time 2 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:09 PM PDT 24
Peak memory 216196 kb
Host smart-723262ac-2560-4950-b459-52ad54d62b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646980918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.646980918
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2152689294
Short name T733
Test name
Test status
Simulation time 45122388 ps
CPU time 0.75 seconds
Started Jun 30 06:59:04 PM PDT 24
Finished Jun 30 06:59:05 PM PDT 24
Peak memory 205892 kb
Host smart-2bd2e0e0-1811-412a-9a7c-506b08e0c9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152689294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2152689294
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1105096398
Short name T371
Test name
Test status
Simulation time 110678383 ps
CPU time 2.56 seconds
Started Jun 30 06:59:06 PM PDT 24
Finished Jun 30 06:59:10 PM PDT 24
Peak memory 224444 kb
Host smart-b97bf1b0-b043-47d8-9030-946208602ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105096398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1105096398
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4169588275
Short name T418
Test name
Test status
Simulation time 17514115 ps
CPU time 0.78 seconds
Started Jun 30 06:59:10 PM PDT 24
Finished Jun 30 06:59:12 PM PDT 24
Peak memory 204844 kb
Host smart-56d74c78-955b-44ab-b0ec-cc3fe87bad82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169588275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4169588275
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3132384759
Short name T367
Test name
Test status
Simulation time 17019290 ps
CPU time 0.76 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:07 PM PDT 24
Peak memory 205492 kb
Host smart-a5702ac0-03d4-4901-89e0-284021788b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132384759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3132384759
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.4285030391
Short name T82
Test name
Test status
Simulation time 24513006307 ps
CPU time 99.06 seconds
Started Jun 30 06:59:10 PM PDT 24
Finished Jun 30 07:00:50 PM PDT 24
Peak memory 267500 kb
Host smart-f0ce1b02-3f3a-4667-a7e3-1a528d132f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285030391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.4285030391
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1833885852
Short name T888
Test name
Test status
Simulation time 16854160687 ps
CPU time 130.06 seconds
Started Jun 30 06:59:11 PM PDT 24
Finished Jun 30 07:01:22 PM PDT 24
Peak memory 256436 kb
Host smart-ccdafdcd-4d5f-4bc8-81af-ce522b514adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833885852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1833885852
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1124305696
Short name T600
Test name
Test status
Simulation time 526910253 ps
CPU time 4.66 seconds
Started Jun 30 06:59:10 PM PDT 24
Finished Jun 30 06:59:16 PM PDT 24
Peak memory 217472 kb
Host smart-7c801f21-ce2b-4c1b-9a20-6fa748ef11b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124305696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1124305696
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2873271128
Short name T1018
Test name
Test status
Simulation time 443066007 ps
CPU time 5.62 seconds
Started Jun 30 06:59:08 PM PDT 24
Finished Jun 30 06:59:15 PM PDT 24
Peak memory 233664 kb
Host smart-9db9e478-9668-4367-a1ce-a34e505a1565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873271128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2873271128
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.4219458142
Short name T413
Test name
Test status
Simulation time 2100145224 ps
CPU time 15.12 seconds
Started Jun 30 06:59:10 PM PDT 24
Finished Jun 30 06:59:27 PM PDT 24
Peak memory 224472 kb
Host smart-d89e3f27-3083-47d7-b100-3390d10d0a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219458142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.4219458142
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2215527382
Short name T470
Test name
Test status
Simulation time 3680473780 ps
CPU time 13.63 seconds
Started Jun 30 06:59:08 PM PDT 24
Finished Jun 30 06:59:22 PM PDT 24
Peak memory 232692 kb
Host smart-e4c52c9d-5064-437e-84cf-1f87fffa1991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215527382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2215527382
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1597562822
Short name T32
Test name
Test status
Simulation time 6179055028 ps
CPU time 74.27 seconds
Started Jun 30 06:59:10 PM PDT 24
Finished Jun 30 07:00:26 PM PDT 24
Peak memory 224548 kb
Host smart-cae2b62c-1d1c-42b3-9d63-20c12ed17bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597562822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1597562822
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3601571649
Short name T646
Test name
Test status
Simulation time 46524816 ps
CPU time 1.04 seconds
Started Jun 30 06:59:03 PM PDT 24
Finished Jun 30 06:59:05 PM PDT 24
Peak memory 218156 kb
Host smart-1499bc99-dfc8-41cb-9d71-f42ba62385e6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601571649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3601571649
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2193863762
Short name T358
Test name
Test status
Simulation time 1722742701 ps
CPU time 4.84 seconds
Started Jun 30 06:59:12 PM PDT 24
Finished Jun 30 06:59:17 PM PDT 24
Peak memory 227800 kb
Host smart-a86427d6-53aa-4563-badc-ca51ee3cf5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193863762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2193863762
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.89131373
Short name T191
Test name
Test status
Simulation time 462102700 ps
CPU time 5.97 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:16 PM PDT 24
Peak memory 224448 kb
Host smart-4a7eabde-a131-4609-bc6e-c8c89bd1c466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89131373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.89131373
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2453185362
Short name T153
Test name
Test status
Simulation time 1494226637 ps
CPU time 14.79 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:25 PM PDT 24
Peak memory 219132 kb
Host smart-eac8e44e-e590-44bd-844a-cc9075b36157
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2453185362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2453185362
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2655963519
Short name T168
Test name
Test status
Simulation time 26448714368 ps
CPU time 242.24 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 07:03:13 PM PDT 24
Peak memory 250816 kb
Host smart-e4b60e4b-1ca6-48ca-b793-859f007a2c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655963519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2655963519
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.473085489
Short name T834
Test name
Test status
Simulation time 1028626813 ps
CPU time 11.61 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:18 PM PDT 24
Peak memory 216476 kb
Host smart-29402e53-a22d-4ace-85de-9fa185604f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473085489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.473085489
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2375142556
Short name T632
Test name
Test status
Simulation time 82869818 ps
CPU time 1.92 seconds
Started Jun 30 06:59:08 PM PDT 24
Finished Jun 30 06:59:10 PM PDT 24
Peak memory 216264 kb
Host smart-80db53d7-df56-4de0-b58c-88f10bc84301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375142556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2375142556
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.726119737
Short name T805
Test name
Test status
Simulation time 243285804 ps
CPU time 0.83 seconds
Started Jun 30 06:59:10 PM PDT 24
Finished Jun 30 06:59:12 PM PDT 24
Peak memory 205888 kb
Host smart-7249876d-48d9-4e50-8f69-0e56a8161fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726119737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.726119737
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2472335918
Short name T954
Test name
Test status
Simulation time 7796248499 ps
CPU time 7.48 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:17 PM PDT 24
Peak memory 224536 kb
Host smart-7061bd7d-cfe8-4fa7-97fc-c95635d74f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472335918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2472335918
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2687364904
Short name T667
Test name
Test status
Simulation time 38860715 ps
CPU time 0.67 seconds
Started Jun 30 06:59:15 PM PDT 24
Finished Jun 30 06:59:17 PM PDT 24
Peak memory 205756 kb
Host smart-3f6e0c20-7d51-45de-b05c-95d31f5b9cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687364904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2687364904
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2545660997
Short name T628
Test name
Test status
Simulation time 251895083 ps
CPU time 2.69 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:13 PM PDT 24
Peak memory 224504 kb
Host smart-032d51b6-5b2a-45e6-acb6-f8ea4442eb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545660997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2545660997
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.646215521
Short name T729
Test name
Test status
Simulation time 79029484 ps
CPU time 0.81 seconds
Started Jun 30 06:59:12 PM PDT 24
Finished Jun 30 06:59:14 PM PDT 24
Peak memory 206548 kb
Host smart-6787c912-8952-4ac2-8cdf-d0dc5b9eb4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646215521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.646215521
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2045713015
Short name T268
Test name
Test status
Simulation time 23705098110 ps
CPU time 218.59 seconds
Started Jun 30 06:59:17 PM PDT 24
Finished Jun 30 07:02:58 PM PDT 24
Peak memory 265544 kb
Host smart-188bcb59-d282-4a84-9b43-181c6eaf842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045713015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2045713015
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1401115600
Short name T668
Test name
Test status
Simulation time 5254913752 ps
CPU time 40.11 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:49 PM PDT 24
Peak memory 240992 kb
Host smart-8953951f-1cdd-43cb-80c2-9c5fb9b86566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401115600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1401115600
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1620347361
Short name T913
Test name
Test status
Simulation time 2175657194 ps
CPU time 44.34 seconds
Started Jun 30 06:59:11 PM PDT 24
Finished Jun 30 06:59:56 PM PDT 24
Peak memory 256504 kb
Host smart-b04b3208-2c33-4e7d-adef-f402848d948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620347361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1620347361
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2605306977
Short name T617
Test name
Test status
Simulation time 234277985 ps
CPU time 3.21 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:13 PM PDT 24
Peak memory 232660 kb
Host smart-ea08d061-2c0f-41fd-a60c-9891887e0671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605306977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2605306977
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3204546437
Short name T929
Test name
Test status
Simulation time 446882697 ps
CPU time 7.03 seconds
Started Jun 30 06:59:10 PM PDT 24
Finished Jun 30 06:59:19 PM PDT 24
Peak memory 232556 kb
Host smart-3ad8e29d-ea69-42dd-9d81-7d85cbc2b679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204546437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3204546437
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2670083800
Short name T725
Test name
Test status
Simulation time 97246196 ps
CPU time 1.09 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:12 PM PDT 24
Peak memory 216760 kb
Host smart-1aea8da3-f8ee-4f39-a7d8-b4dd41a23a70
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670083800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2670083800
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.934518056
Short name T638
Test name
Test status
Simulation time 775758244 ps
CPU time 4.07 seconds
Started Jun 30 06:59:11 PM PDT 24
Finished Jun 30 06:59:16 PM PDT 24
Peak memory 224456 kb
Host smart-e846194a-29a9-46c0-8aa2-cfb62386a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934518056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.934518056
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2153824363
Short name T236
Test name
Test status
Simulation time 9539562735 ps
CPU time 8.53 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:18 PM PDT 24
Peak memory 234548 kb
Host smart-24d639b0-f313-4ff4-b905-8c77fcfbdc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153824363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2153824363
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2005829926
Short name T747
Test name
Test status
Simulation time 1532908480 ps
CPU time 23.76 seconds
Started Jun 30 06:59:14 PM PDT 24
Finished Jun 30 06:59:39 PM PDT 24
Peak memory 219196 kb
Host smart-ff69456d-f333-4766-93f8-83411dd5cb06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2005829926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2005829926
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2008353296
Short name T794
Test name
Test status
Simulation time 18167407920 ps
CPU time 39.97 seconds
Started Jun 30 06:59:08 PM PDT 24
Finished Jun 30 06:59:49 PM PDT 24
Peak memory 216336 kb
Host smart-847e63cb-55d6-4e60-90e4-9f766dafc3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008353296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2008353296
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.842043298
Short name T7
Test name
Test status
Simulation time 344743526 ps
CPU time 2.6 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:13 PM PDT 24
Peak memory 216180 kb
Host smart-83fc16a7-5b19-4407-87de-6b92e7cbe6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842043298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.842043298
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3402574342
Short name T647
Test name
Test status
Simulation time 288114332 ps
CPU time 1.19 seconds
Started Jun 30 06:59:11 PM PDT 24
Finished Jun 30 06:59:13 PM PDT 24
Peak memory 207864 kb
Host smart-ef23820c-36ac-4ae4-891d-df2bb545dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402574342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3402574342
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2845681934
Short name T311
Test name
Test status
Simulation time 58822220 ps
CPU time 0.74 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:11 PM PDT 24
Peak memory 205896 kb
Host smart-101739d6-c5f7-4954-952e-2926e1a526b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845681934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2845681934
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.930761327
Short name T72
Test name
Test status
Simulation time 43949254546 ps
CPU time 20.9 seconds
Started Jun 30 06:59:09 PM PDT 24
Finished Jun 30 06:59:31 PM PDT 24
Peak memory 240824 kb
Host smart-555183f7-0fe3-490c-9195-d5cf968ec893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930761327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.930761327
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3144775704
Short name T59
Test name
Test status
Simulation time 63571760 ps
CPU time 0.72 seconds
Started Jun 30 06:59:15 PM PDT 24
Finished Jun 30 06:59:17 PM PDT 24
Peak memory 205416 kb
Host smart-69c22eb4-7558-49d7-bebb-64a2f1716449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144775704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3144775704
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1353791834
Short name T983
Test name
Test status
Simulation time 31355833 ps
CPU time 0.8 seconds
Started Jun 30 06:59:17 PM PDT 24
Finished Jun 30 06:59:20 PM PDT 24
Peak memory 206552 kb
Host smart-4a9b8120-ecdd-4732-ac0b-298477baf6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353791834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1353791834
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.324734819
Short name T222
Test name
Test status
Simulation time 12337420298 ps
CPU time 148.52 seconds
Started Jun 30 06:59:17 PM PDT 24
Finished Jun 30 07:01:48 PM PDT 24
Peak memory 273788 kb
Host smart-5df49cdb-004b-4229-aa88-f49ed7601784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324734819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.324734819
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2690153693
Short name T1017
Test name
Test status
Simulation time 2315661462 ps
CPU time 28.81 seconds
Started Jun 30 06:59:16 PM PDT 24
Finished Jun 30 06:59:46 PM PDT 24
Peak memory 222572 kb
Host smart-65ae16bb-22c0-42c1-9c67-395baceb5737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690153693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2690153693
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4009786301
Short name T591
Test name
Test status
Simulation time 1483996492 ps
CPU time 3.99 seconds
Started Jun 30 06:59:15 PM PDT 24
Finished Jun 30 06:59:21 PM PDT 24
Peak memory 233312 kb
Host smart-60d7fd62-cab0-4261-82ef-c876f2aafd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009786301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4009786301
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1516503408
Short name T908
Test name
Test status
Simulation time 90145612371 ps
CPU time 273.79 seconds
Started Jun 30 06:59:16 PM PDT 24
Finished Jun 30 07:03:52 PM PDT 24
Peak memory 273144 kb
Host smart-3833606a-ba71-43a8-9ce5-59a2bea62ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516503408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1516503408
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1842381746
Short name T683
Test name
Test status
Simulation time 193708170 ps
CPU time 2.69 seconds
Started Jun 30 06:59:15 PM PDT 24
Finished Jun 30 06:59:20 PM PDT 24
Peak memory 224500 kb
Host smart-2468a5d6-37c1-4bd2-99db-17c5aad61feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842381746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1842381746
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3317443430
Short name T879
Test name
Test status
Simulation time 12349532191 ps
CPU time 126.91 seconds
Started Jun 30 06:59:16 PM PDT 24
Finished Jun 30 07:01:25 PM PDT 24
Peak memory 232764 kb
Host smart-0c46e3f1-fbf5-4f8b-a115-cfaec9fbc765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317443430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3317443430
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.869033483
Short name T977
Test name
Test status
Simulation time 28203684 ps
CPU time 1.08 seconds
Started Jun 30 06:59:18 PM PDT 24
Finished Jun 30 06:59:21 PM PDT 24
Peak memory 218012 kb
Host smart-d69c2c87-60fd-4ae6-8210-8a080f9a46b0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869033483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.869033483
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2985420820
Short name T774
Test name
Test status
Simulation time 2111919978 ps
CPU time 5.44 seconds
Started Jun 30 06:59:14 PM PDT 24
Finished Jun 30 06:59:21 PM PDT 24
Peak memory 232608 kb
Host smart-b0aa7642-e411-435f-bdf3-366bbac61af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985420820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2985420820
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2705654295
Short name T250
Test name
Test status
Simulation time 1367245301 ps
CPU time 3.04 seconds
Started Jun 30 06:59:16 PM PDT 24
Finished Jun 30 06:59:20 PM PDT 24
Peak memory 224436 kb
Host smart-94624de1-ecd6-4291-a761-5b223d959794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705654295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2705654295
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1762893261
Short name T549
Test name
Test status
Simulation time 1065998312 ps
CPU time 11.99 seconds
Started Jun 30 06:59:18 PM PDT 24
Finished Jun 30 06:59:32 PM PDT 24
Peak memory 222380 kb
Host smart-0ba3a8fc-8955-4491-bacd-f7e936c2868f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1762893261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1762893261
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2948799100
Short name T616
Test name
Test status
Simulation time 9581145081 ps
CPU time 22.9 seconds
Started Jun 30 06:59:17 PM PDT 24
Finished Jun 30 06:59:43 PM PDT 24
Peak memory 216340 kb
Host smart-85bb2ed7-45d6-40f7-ad2b-a98331784821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948799100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2948799100
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1053236301
Short name T670
Test name
Test status
Simulation time 3369956581 ps
CPU time 10.76 seconds
Started Jun 30 06:59:16 PM PDT 24
Finished Jun 30 06:59:29 PM PDT 24
Peak memory 216332 kb
Host smart-361f206c-1b36-4c05-89c4-5cf6563d1a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053236301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1053236301
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1439587060
Short name T780
Test name
Test status
Simulation time 21000922 ps
CPU time 0.92 seconds
Started Jun 30 06:59:16 PM PDT 24
Finished Jun 30 06:59:19 PM PDT 24
Peak memory 206880 kb
Host smart-f0f6bdff-a3d1-46f6-92be-70c5f5e124e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439587060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1439587060
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3865067111
Short name T1
Test name
Test status
Simulation time 23902185 ps
CPU time 0.79 seconds
Started Jun 30 06:59:16 PM PDT 24
Finished Jun 30 06:59:19 PM PDT 24
Peak memory 205892 kb
Host smart-b4e02acf-168f-4adb-a6a7-d3311189fc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865067111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3865067111
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.77747515
Short name T959
Test name
Test status
Simulation time 1375905300 ps
CPU time 7.97 seconds
Started Jun 30 06:59:18 PM PDT 24
Finished Jun 30 06:59:28 PM PDT 24
Peak memory 240684 kb
Host smart-41b2ea1e-0c45-429d-9a5f-934f58ca11c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77747515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.77747515
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3205331730
Short name T711
Test name
Test status
Simulation time 69563628 ps
CPU time 0.72 seconds
Started Jun 30 06:59:19 PM PDT 24
Finished Jun 30 06:59:21 PM PDT 24
Peak memory 205432 kb
Host smart-05e385d8-dc53-4c49-a914-67e1f28ce0a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205331730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3205331730
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1932398515
Short name T234
Test name
Test status
Simulation time 147829805 ps
CPU time 4.27 seconds
Started Jun 30 06:59:21 PM PDT 24
Finished Jun 30 06:59:27 PM PDT 24
Peak memory 224432 kb
Host smart-c6eaad9b-e36a-410a-9b8a-927aad454291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932398515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1932398515
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1103502959
Short name T565
Test name
Test status
Simulation time 68697916 ps
CPU time 0.82 seconds
Started Jun 30 06:59:20 PM PDT 24
Finished Jun 30 06:59:23 PM PDT 24
Peak memory 206900 kb
Host smart-f5ad1172-c939-4aa2-9345-8f25f0c63d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103502959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1103502959
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3829029892
Short name T202
Test name
Test status
Simulation time 29790614353 ps
CPU time 85.22 seconds
Started Jun 30 06:59:22 PM PDT 24
Finished Jun 30 07:00:49 PM PDT 24
Peak memory 249436 kb
Host smart-61e49530-3956-49bf-a4f9-a5dbaf5ea81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829029892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3829029892
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1838075372
Short name T254
Test name
Test status
Simulation time 21646378689 ps
CPU time 126.06 seconds
Started Jun 30 06:59:23 PM PDT 24
Finished Jun 30 07:01:31 PM PDT 24
Peak memory 263780 kb
Host smart-3d4e317b-ba30-47ee-a3d9-42c0c31660ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838075372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1838075372
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.634326201
Short name T208
Test name
Test status
Simulation time 13178464028 ps
CPU time 216.45 seconds
Started Jun 30 06:59:25 PM PDT 24
Finished Jun 30 07:03:03 PM PDT 24
Peak memory 257392 kb
Host smart-8e2e9861-f4b6-4c88-b5aa-1feefca9f409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634326201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.634326201
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.207064940
Short name T462
Test name
Test status
Simulation time 961031874 ps
CPU time 8.32 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:36 PM PDT 24
Peak memory 224480 kb
Host smart-5e3a0120-5cf5-451f-9367-449aeaa7459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207064940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.207064940
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.624434899
Short name T712
Test name
Test status
Simulation time 22717631860 ps
CPU time 77.03 seconds
Started Jun 30 06:59:24 PM PDT 24
Finished Jun 30 07:00:42 PM PDT 24
Peak memory 236280 kb
Host smart-bac7c96b-894f-4146-8f00-4950e0b74a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624434899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.624434899
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2335462005
Short name T330
Test name
Test status
Simulation time 3665205917 ps
CPU time 11.24 seconds
Started Jun 30 06:59:23 PM PDT 24
Finished Jun 30 06:59:36 PM PDT 24
Peak memory 232704 kb
Host smart-f8bef7f2-1e28-46c8-894f-dc658bc9162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335462005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2335462005
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3347191206
Short name T200
Test name
Test status
Simulation time 1281949139 ps
CPU time 18.54 seconds
Started Jun 30 06:59:22 PM PDT 24
Finished Jun 30 06:59:42 PM PDT 24
Peak memory 236400 kb
Host smart-78e63230-617f-4c40-a62d-08223b066830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347191206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3347191206
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3017367043
Short name T370
Test name
Test status
Simulation time 59657422 ps
CPU time 1.12 seconds
Started Jun 30 06:59:21 PM PDT 24
Finished Jun 30 06:59:24 PM PDT 24
Peak memory 216768 kb
Host smart-ef0a33e2-a17e-481d-be4c-84f2ffaf61e9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017367043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3017367043
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.906188545
Short name T557
Test name
Test status
Simulation time 6042072650 ps
CPU time 16.12 seconds
Started Jun 30 06:59:24 PM PDT 24
Finished Jun 30 06:59:41 PM PDT 24
Peak memory 224520 kb
Host smart-f9530379-122a-4fa2-8460-62f3561c7e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906188545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.906188545
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1799502971
Short name T933
Test name
Test status
Simulation time 554242071 ps
CPU time 2.76 seconds
Started Jun 30 06:59:22 PM PDT 24
Finished Jun 30 06:59:26 PM PDT 24
Peak memory 224428 kb
Host smart-14079a7e-584b-4b43-b346-c0c188e64c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799502971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1799502971
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1877070524
Short name T765
Test name
Test status
Simulation time 2912973062 ps
CPU time 16.14 seconds
Started Jun 30 06:59:25 PM PDT 24
Finished Jun 30 06:59:42 PM PDT 24
Peak memory 221888 kb
Host smart-20c24387-6de2-4b36-8f12-ab95fda8c961
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1877070524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1877070524
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2798397435
Short name T882
Test name
Test status
Simulation time 73734579934 ps
CPU time 403.12 seconds
Started Jun 30 06:59:23 PM PDT 24
Finished Jun 30 07:06:08 PM PDT 24
Peak memory 269292 kb
Host smart-97d611ad-d70f-4863-8803-a97183a68d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798397435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2798397435
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3154785273
Short name T973
Test name
Test status
Simulation time 1910978334 ps
CPU time 19.94 seconds
Started Jun 30 06:59:24 PM PDT 24
Finished Jun 30 06:59:45 PM PDT 24
Peak memory 216264 kb
Host smart-b1ff2dc8-0f77-409d-9f82-99f7f243ecd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154785273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3154785273
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3987342863
Short name T919
Test name
Test status
Simulation time 704142772 ps
CPU time 2.1 seconds
Started Jun 30 06:59:25 PM PDT 24
Finished Jun 30 06:59:28 PM PDT 24
Peak memory 216020 kb
Host smart-12b68951-d2d9-4109-a6c4-d587a3244715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987342863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3987342863
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2359469097
Short name T300
Test name
Test status
Simulation time 392566841 ps
CPU time 1.54 seconds
Started Jun 30 06:59:20 PM PDT 24
Finished Jun 30 06:59:23 PM PDT 24
Peak memory 216256 kb
Host smart-55073f3d-5b8a-4a53-ae2e-0b5e4af56d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359469097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2359469097
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1651026341
Short name T952
Test name
Test status
Simulation time 62615006 ps
CPU time 0.77 seconds
Started Jun 30 06:59:19 PM PDT 24
Finished Jun 30 06:59:21 PM PDT 24
Peak memory 205932 kb
Host smart-47712ada-531b-45f5-8724-2ac62e873913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651026341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1651026341
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.146291402
Short name T504
Test name
Test status
Simulation time 4709655663 ps
CPU time 23.8 seconds
Started Jun 30 06:59:19 PM PDT 24
Finished Jun 30 06:59:45 PM PDT 24
Peak memory 232756 kb
Host smart-6d0fc9a2-6640-4eec-a499-43431dd88ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146291402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.146291402
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.66760327
Short name T865
Test name
Test status
Simulation time 13168104 ps
CPU time 0.73 seconds
Started Jun 30 06:59:30 PM PDT 24
Finished Jun 30 06:59:31 PM PDT 24
Peak memory 204844 kb
Host smart-c66f6604-eeb4-4134-b25e-327286a0f808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66760327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.66760327
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3954083601
Short name T1015
Test name
Test status
Simulation time 65307212 ps
CPU time 2.14 seconds
Started Jun 30 06:59:20 PM PDT 24
Finished Jun 30 06:59:24 PM PDT 24
Peak memory 232372 kb
Host smart-058d49a8-db21-49c8-ad72-78d716a8968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954083601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3954083601
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3119180095
Short name T390
Test name
Test status
Simulation time 19534523 ps
CPU time 0.76 seconds
Started Jun 30 06:59:25 PM PDT 24
Finished Jun 30 06:59:27 PM PDT 24
Peak memory 206488 kb
Host smart-0d7188c4-dbda-4e59-92aa-3b43a82a114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119180095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3119180095
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1518793882
Short name T312
Test name
Test status
Simulation time 1284478926 ps
CPU time 31.35 seconds
Started Jun 30 06:59:20 PM PDT 24
Finished Jun 30 06:59:53 PM PDT 24
Peak memory 256948 kb
Host smart-4efd8959-63d9-4dd8-8e6a-d348f71f8c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518793882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1518793882
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2828108757
Short name T914
Test name
Test status
Simulation time 11627450533 ps
CPU time 90.6 seconds
Started Jun 30 06:59:22 PM PDT 24
Finished Jun 30 07:00:55 PM PDT 24
Peak memory 234180 kb
Host smart-219d1c38-07d1-4692-b546-ee052665be91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828108757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2828108757
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1526220026
Short name T585
Test name
Test status
Simulation time 17518848732 ps
CPU time 114.07 seconds
Started Jun 30 06:59:26 PM PDT 24
Finished Jun 30 07:01:21 PM PDT 24
Peak memory 256612 kb
Host smart-32841c6b-dccd-4c71-82cc-6e452c255f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526220026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1526220026
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2479648497
Short name T269
Test name
Test status
Simulation time 4465531430 ps
CPU time 97.25 seconds
Started Jun 30 06:59:22 PM PDT 24
Finished Jun 30 07:01:01 PM PDT 24
Peak memory 265624 kb
Host smart-a0a27ce7-6c7b-4745-95d1-bc9f193181f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479648497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2479648497
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3865813663
Short name T755
Test name
Test status
Simulation time 39453566 ps
CPU time 2.39 seconds
Started Jun 30 06:59:24 PM PDT 24
Finished Jun 30 06:59:27 PM PDT 24
Peak memory 224436 kb
Host smart-a6bb3bd1-7c49-471d-a50c-2ea672bc1db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865813663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3865813663
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1398623198
Short name T104
Test name
Test status
Simulation time 3823159602 ps
CPU time 40.65 seconds
Started Jun 30 06:59:21 PM PDT 24
Finished Jun 30 07:00:03 PM PDT 24
Peak memory 224464 kb
Host smart-f16b2cdf-990d-4180-a718-d465e63957e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398623198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1398623198
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3116529439
Short name T738
Test name
Test status
Simulation time 44773319 ps
CPU time 1.06 seconds
Started Jun 30 06:59:19 PM PDT 24
Finished Jun 30 06:59:21 PM PDT 24
Peak memory 216772 kb
Host smart-e24818c9-7f30-438f-aec3-ed737fc8dc06
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116529439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3116529439
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2721276182
Short name T249
Test name
Test status
Simulation time 75709330 ps
CPU time 2.57 seconds
Started Jun 30 06:59:25 PM PDT 24
Finished Jun 30 06:59:28 PM PDT 24
Peak memory 232564 kb
Host smart-64d319f8-5b5a-4408-9f4e-da9130a8b5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721276182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2721276182
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.237424101
Short name T472
Test name
Test status
Simulation time 3461118859 ps
CPU time 4.27 seconds
Started Jun 30 06:59:25 PM PDT 24
Finished Jun 30 06:59:30 PM PDT 24
Peak memory 232740 kb
Host smart-ae558918-d87b-40c7-8f2d-9fb4237e7a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237424101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.237424101
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2994937293
Short name T903
Test name
Test status
Simulation time 1046104289 ps
CPU time 4.26 seconds
Started Jun 30 06:59:24 PM PDT 24
Finished Jun 30 06:59:29 PM PDT 24
Peak memory 221764 kb
Host smart-195a307f-d236-4bcc-a133-3463d524ed1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2994937293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2994937293
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1820808370
Short name T15
Test name
Test status
Simulation time 108335980167 ps
CPU time 262.87 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 07:03:52 PM PDT 24
Peak memory 249268 kb
Host smart-0d83db68-617f-4ee2-93b4-659fb8086f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820808370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1820808370
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3529246678
Short name T684
Test name
Test status
Simulation time 15500079794 ps
CPU time 18.76 seconds
Started Jun 30 06:59:26 PM PDT 24
Finished Jun 30 06:59:45 PM PDT 24
Peak memory 216288 kb
Host smart-5dda8d8e-e864-4e66-9452-09ec01883b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529246678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3529246678
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1010882837
Short name T52
Test name
Test status
Simulation time 740197113 ps
CPU time 2.86 seconds
Started Jun 30 06:59:21 PM PDT 24
Finished Jun 30 06:59:26 PM PDT 24
Peak memory 207836 kb
Host smart-c4eb281d-c84a-4e75-be24-80bfcb8e95da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010882837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1010882837
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4003497734
Short name T996
Test name
Test status
Simulation time 53510727 ps
CPU time 2.32 seconds
Started Jun 30 06:59:20 PM PDT 24
Finished Jun 30 06:59:24 PM PDT 24
Peak memory 216168 kb
Host smart-e00f1f51-5294-4f7a-bb00-04e4a8a52827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003497734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4003497734
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3905232813
Short name T923
Test name
Test status
Simulation time 201462333 ps
CPU time 0.92 seconds
Started Jun 30 06:59:19 PM PDT 24
Finished Jun 30 06:59:22 PM PDT 24
Peak memory 206856 kb
Host smart-a3ba7b8c-90b3-4f35-b1bc-14f7021b83c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905232813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3905232813
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3566931479
Short name T835
Test name
Test status
Simulation time 19252387204 ps
CPU time 17.47 seconds
Started Jun 30 06:59:21 PM PDT 24
Finished Jun 30 06:59:41 PM PDT 24
Peak memory 237872 kb
Host smart-f1839d71-e374-42fc-aef0-e3ec5474105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566931479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3566931479
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2707117892
Short name T826
Test name
Test status
Simulation time 24639989 ps
CPU time 0.77 seconds
Started Jun 30 06:59:29 PM PDT 24
Finished Jun 30 06:59:31 PM PDT 24
Peak memory 204828 kb
Host smart-2c69c010-027b-48ee-b285-fc801c38a379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707117892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2707117892
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2164104183
Short name T545
Test name
Test status
Simulation time 343413738 ps
CPU time 2.09 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:30 PM PDT 24
Peak memory 224384 kb
Host smart-20d60b99-033c-4e6b-94c1-6bfba2990021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164104183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2164104183
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1674191079
Short name T58
Test name
Test status
Simulation time 15553716 ps
CPU time 0.74 seconds
Started Jun 30 06:59:28 PM PDT 24
Finished Jun 30 06:59:30 PM PDT 24
Peak memory 205520 kb
Host smart-e737fe92-3dab-4a75-bcb5-32e9b2aaa6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674191079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1674191079
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3543305635
Short name T538
Test name
Test status
Simulation time 3367950148 ps
CPU time 45.61 seconds
Started Jun 30 06:59:28 PM PDT 24
Finished Jun 30 07:00:15 PM PDT 24
Peak memory 253780 kb
Host smart-c2f0c7e8-aa63-4f83-9d04-53a8b1c6c195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543305635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3543305635
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.767405806
Short name T945
Test name
Test status
Simulation time 52441884919 ps
CPU time 439.66 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 07:06:47 PM PDT 24
Peak memory 255772 kb
Host smart-efcfa70d-d545-4d2e-bb59-6b5c54f43343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767405806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.767405806
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.69152292
Short name T871
Test name
Test status
Simulation time 21228863564 ps
CPU time 65.83 seconds
Started Jun 30 06:59:28 PM PDT 24
Finished Jun 30 07:00:35 PM PDT 24
Peak memory 224008 kb
Host smart-7ac81c92-d27b-41be-97f6-19cb2ae62eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69152292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.69152292
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4218394667
Short name T447
Test name
Test status
Simulation time 368611099 ps
CPU time 3.34 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:32 PM PDT 24
Peak memory 232708 kb
Host smart-5dae0c69-526f-4faa-a5c3-06d06a9b7a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218394667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4218394667
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.43149214
Short name T880
Test name
Test status
Simulation time 23083962908 ps
CPU time 61.62 seconds
Started Jun 30 06:59:28 PM PDT 24
Finished Jun 30 07:00:30 PM PDT 24
Peak memory 249212 kb
Host smart-4ce9b859-3776-401b-8ffb-4d994fde13de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43149214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.43149214
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1902790099
Short name T862
Test name
Test status
Simulation time 831662343 ps
CPU time 10.04 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:38 PM PDT 24
Peak memory 232672 kb
Host smart-7d1af8bc-e187-47e6-9917-3501f63185e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902790099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1902790099
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2561496039
Short name T211
Test name
Test status
Simulation time 13993614509 ps
CPU time 97.91 seconds
Started Jun 30 06:59:28 PM PDT 24
Finished Jun 30 07:01:07 PM PDT 24
Peak memory 240904 kb
Host smart-974f15cb-cf9d-498f-afff-44661e19b4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561496039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2561496039
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1334758358
Short name T26
Test name
Test status
Simulation time 26644127 ps
CPU time 1.08 seconds
Started Jun 30 06:59:28 PM PDT 24
Finished Jun 30 06:59:31 PM PDT 24
Peak memory 218080 kb
Host smart-87ca6941-9ae5-4882-a52b-5592388539fc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334758358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1334758358
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2035609503
Short name T892
Test name
Test status
Simulation time 31658979138 ps
CPU time 8.45 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:37 PM PDT 24
Peak memory 232724 kb
Host smart-4b6b5040-7ce1-4292-9beb-d5676efaef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035609503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2035609503
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2393513559
Short name T837
Test name
Test status
Simulation time 3025330124 ps
CPU time 4.47 seconds
Started Jun 30 06:59:26 PM PDT 24
Finished Jun 30 06:59:31 PM PDT 24
Peak memory 232788 kb
Host smart-75da1db8-a50b-49a6-b2d4-9f61a1813d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393513559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2393513559
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3050587054
Short name T333
Test name
Test status
Simulation time 343507365 ps
CPU time 3.9 seconds
Started Jun 30 06:59:28 PM PDT 24
Finished Jun 30 06:59:33 PM PDT 24
Peak memory 220388 kb
Host smart-43e58aa4-8c84-4c13-93c1-81a069a2fd2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3050587054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3050587054
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3131441499
Short name T902
Test name
Test status
Simulation time 563524251 ps
CPU time 1.23 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:29 PM PDT 24
Peak memory 206984 kb
Host smart-9a3482e9-c774-40e2-bcf5-cd853eaf686d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131441499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3131441499
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.893399391
Short name T44
Test name
Test status
Simulation time 11166608694 ps
CPU time 31.67 seconds
Started Jun 30 06:59:28 PM PDT 24
Finished Jun 30 07:00:01 PM PDT 24
Peak memory 216344 kb
Host smart-18bff01e-55a1-4353-a02b-76b9c60db957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893399391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.893399391
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1235670608
Short name T921
Test name
Test status
Simulation time 1848333529 ps
CPU time 5.89 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:35 PM PDT 24
Peak memory 216132 kb
Host smart-99021f3e-4a8b-407a-b887-22bdfcc430d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235670608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1235670608
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.566453216
Short name T298
Test name
Test status
Simulation time 113721998 ps
CPU time 1.7 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:30 PM PDT 24
Peak memory 216280 kb
Host smart-75cc2762-1959-487b-a913-1aae234de89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566453216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.566453216
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3926257420
Short name T843
Test name
Test status
Simulation time 320385484 ps
CPU time 0.99 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:29 PM PDT 24
Peak memory 205872 kb
Host smart-cabeee4e-ebc0-4968-8986-fa53e7a662de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926257420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3926257420
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.328955528
Short name T74
Test name
Test status
Simulation time 5223882789 ps
CPU time 18 seconds
Started Jun 30 06:59:28 PM PDT 24
Finished Jun 30 06:59:47 PM PDT 24
Peak memory 232796 kb
Host smart-364f2067-a4e2-4c88-a1db-eb732dd95519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328955528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.328955528
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3841468061
Short name T602
Test name
Test status
Simulation time 14105071 ps
CPU time 0.71 seconds
Started Jun 30 06:59:33 PM PDT 24
Finished Jun 30 06:59:35 PM PDT 24
Peak memory 205416 kb
Host smart-9bcaca09-dc25-44e4-b2e8-a34ddbd2b3e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841468061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3841468061
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4184778774
Short name T986
Test name
Test status
Simulation time 95423830 ps
CPU time 2.25 seconds
Started Jun 30 06:59:32 PM PDT 24
Finished Jun 30 06:59:35 PM PDT 24
Peak memory 224468 kb
Host smart-4edbb843-eb55-42a9-83e9-92ea799fe69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184778774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4184778774
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.305669919
Short name T818
Test name
Test status
Simulation time 16289125 ps
CPU time 0.77 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:28 PM PDT 24
Peak memory 205536 kb
Host smart-8b61796c-597a-410a-b88a-d8bd14691283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305669919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.305669919
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2359906729
Short name T171
Test name
Test status
Simulation time 31529960122 ps
CPU time 217.66 seconds
Started Jun 30 06:59:33 PM PDT 24
Finished Jun 30 07:03:12 PM PDT 24
Peak memory 252668 kb
Host smart-d1434f60-64a4-4733-8766-752da3e5ba8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359906729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2359906729
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.4037404642
Short name T353
Test name
Test status
Simulation time 37362736741 ps
CPU time 82.73 seconds
Started Jun 30 06:59:34 PM PDT 24
Finished Jun 30 07:00:58 PM PDT 24
Peak memory 255544 kb
Host smart-08758220-ef52-42cd-9b46-32d1713b7112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037404642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4037404642
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1957972695
Short name T144
Test name
Test status
Simulation time 6549660072 ps
CPU time 51.71 seconds
Started Jun 30 06:59:33 PM PDT 24
Finished Jun 30 07:00:26 PM PDT 24
Peak memory 249256 kb
Host smart-3d27fe14-516a-4fdc-b662-17f739d509d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957972695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1957972695
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2079748368
Short name T703
Test name
Test status
Simulation time 40162620 ps
CPU time 2.48 seconds
Started Jun 30 06:59:38 PM PDT 24
Finished Jun 30 06:59:42 PM PDT 24
Peak memory 224472 kb
Host smart-6d7f23ce-a17b-437b-9f52-6a11f3656326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079748368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2079748368
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3714312412
Short name T1000
Test name
Test status
Simulation time 4690840755 ps
CPU time 33.53 seconds
Started Jun 30 06:59:38 PM PDT 24
Finished Jun 30 07:00:13 PM PDT 24
Peak memory 237260 kb
Host smart-c1912f88-f4b1-496a-884b-196066211c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714312412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3714312412
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1154803275
Short name T577
Test name
Test status
Simulation time 84820172 ps
CPU time 3.2 seconds
Started Jun 30 06:59:47 PM PDT 24
Finished Jun 30 06:59:56 PM PDT 24
Peak memory 232660 kb
Host smart-01092f35-622f-4797-b305-d5d9fc20d4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154803275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1154803275
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2744708058
Short name T213
Test name
Test status
Simulation time 22830274645 ps
CPU time 38.14 seconds
Started Jun 30 06:59:39 PM PDT 24
Finished Jun 30 07:00:20 PM PDT 24
Peak memory 232772 kb
Host smart-d897b3ec-96d4-444e-998e-3051b0557ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744708058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2744708058
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2790009200
Short name T316
Test name
Test status
Simulation time 51122701 ps
CPU time 1.04 seconds
Started Jun 30 06:59:27 PM PDT 24
Finished Jun 30 06:59:29 PM PDT 24
Peak memory 217992 kb
Host smart-2ba74df6-e405-4810-bad5-7ac1795a6387
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790009200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2790009200
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.408031435
Short name T653
Test name
Test status
Simulation time 4286884799 ps
CPU time 12.66 seconds
Started Jun 30 06:59:33 PM PDT 24
Finished Jun 30 06:59:47 PM PDT 24
Peak memory 250200 kb
Host smart-a1bfaa99-9973-4870-b3d4-0dcc48979e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408031435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.408031435
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2332808156
Short name T240
Test name
Test status
Simulation time 7105243669 ps
CPU time 18.98 seconds
Started Jun 30 06:59:33 PM PDT 24
Finished Jun 30 06:59:53 PM PDT 24
Peak memory 239392 kb
Host smart-ad4829db-4c48-439e-a4cf-e950b5270e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332808156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2332808156
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2852818424
Short name T726
Test name
Test status
Simulation time 176161579 ps
CPU time 4.92 seconds
Started Jun 30 06:59:38 PM PDT 24
Finished Jun 30 06:59:44 PM PDT 24
Peak memory 222472 kb
Host smart-9a2b244e-08b0-4a4e-bbdb-db57097ae1cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2852818424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2852818424
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3205954881
Short name T217
Test name
Test status
Simulation time 18330605552 ps
CPU time 93.41 seconds
Started Jun 30 06:59:32 PM PDT 24
Finished Jun 30 07:01:06 PM PDT 24
Peak memory 256816 kb
Host smart-6a2b7a07-ffd2-4c7a-a841-1d829a5f2b0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205954881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3205954881
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3663569999
Short name T56
Test name
Test status
Simulation time 3509107548 ps
CPU time 9.24 seconds
Started Jun 30 06:59:33 PM PDT 24
Finished Jun 30 06:59:43 PM PDT 24
Peak memory 218944 kb
Host smart-42101172-5292-4206-8dd3-c9faf1795cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663569999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3663569999
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.940076753
Short name T976
Test name
Test status
Simulation time 889851170 ps
CPU time 2.71 seconds
Started Jun 30 06:59:34 PM PDT 24
Finished Jun 30 06:59:38 PM PDT 24
Peak memory 216204 kb
Host smart-5228231d-bdb2-4c48-8924-57648290fbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940076753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.940076753
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2485311193
Short name T737
Test name
Test status
Simulation time 41590927 ps
CPU time 1.19 seconds
Started Jun 30 06:59:32 PM PDT 24
Finished Jun 30 06:59:34 PM PDT 24
Peak memory 207980 kb
Host smart-499f480a-15ae-450b-b3ab-3f83b97b51ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485311193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2485311193
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1390891672
Short name T578
Test name
Test status
Simulation time 85058213 ps
CPU time 0.83 seconds
Started Jun 30 06:59:34 PM PDT 24
Finished Jun 30 06:59:36 PM PDT 24
Peak memory 205888 kb
Host smart-1fa63bda-1f53-4347-a537-22be1d9b8db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390891672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1390891672
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4250768540
Short name T917
Test name
Test status
Simulation time 5251642066 ps
CPU time 16.59 seconds
Started Jun 30 06:59:37 PM PDT 24
Finished Jun 30 06:59:54 PM PDT 24
Peak memory 240060 kb
Host smart-988e793b-d2c6-4848-8c8b-963a3c30df41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250768540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4250768540
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3830108476
Short name T758
Test name
Test status
Simulation time 11368160 ps
CPU time 0.75 seconds
Started Jun 30 06:59:41 PM PDT 24
Finished Jun 30 06:59:45 PM PDT 24
Peak memory 204840 kb
Host smart-d9979797-57df-4085-8104-16d99992d5ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830108476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3830108476
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2591711235
Short name T322
Test name
Test status
Simulation time 210265933 ps
CPU time 2.57 seconds
Started Jun 30 06:59:34 PM PDT 24
Finished Jun 30 06:59:37 PM PDT 24
Peak memory 224424 kb
Host smart-e545bdb8-b56b-4a56-a952-9f5f6aed6983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591711235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2591711235
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2491729982
Short name T1025
Test name
Test status
Simulation time 18613056 ps
CPU time 0.78 seconds
Started Jun 30 06:59:35 PM PDT 24
Finished Jun 30 06:59:36 PM PDT 24
Peak memory 206872 kb
Host smart-b10e6972-a61e-4c75-ba8d-6182dcc6eb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491729982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2491729982
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2077132640
Short name T502
Test name
Test status
Simulation time 45706134718 ps
CPU time 79.54 seconds
Started Jun 30 06:59:40 PM PDT 24
Finished Jun 30 07:01:03 PM PDT 24
Peak memory 239412 kb
Host smart-3330cc77-0480-4d65-ba6a-403caf9a5ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077132640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2077132640
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1092626779
Short name T383
Test name
Test status
Simulation time 2757373194 ps
CPU time 67.89 seconds
Started Jun 30 06:59:56 PM PDT 24
Finished Jun 30 07:01:11 PM PDT 24
Peak memory 252368 kb
Host smart-f744b22f-ecc1-483a-92f2-18300359edfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092626779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1092626779
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.4121949490
Short name T714
Test name
Test status
Simulation time 7381827900 ps
CPU time 73.07 seconds
Started Jun 30 06:59:38 PM PDT 24
Finished Jun 30 07:00:53 PM PDT 24
Peak memory 249824 kb
Host smart-d0e84fde-eaa5-4090-a866-b5968d5b28a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121949490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.4121949490
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2891885634
Short name T940
Test name
Test status
Simulation time 11976730461 ps
CPU time 48.02 seconds
Started Jun 30 06:59:40 PM PDT 24
Finished Jun 30 07:00:32 PM PDT 24
Peak memory 249180 kb
Host smart-407b41ef-6a89-4796-afee-991c033131d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891885634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2891885634
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.114783580
Short name T429
Test name
Test status
Simulation time 3169219245 ps
CPU time 9.62 seconds
Started Jun 30 06:59:38 PM PDT 24
Finished Jun 30 06:59:49 PM PDT 24
Peak memory 224388 kb
Host smart-f12d7ff4-c755-42d3-bc70-871991f53716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114783580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.114783580
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.940311268
Short name T739
Test name
Test status
Simulation time 553340908 ps
CPU time 5.67 seconds
Started Jun 30 06:59:38 PM PDT 24
Finished Jun 30 06:59:45 PM PDT 24
Peak memory 232612 kb
Host smart-80318a8f-89e3-483b-8337-513b7c50d10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940311268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.940311268
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1491210761
Short name T969
Test name
Test status
Simulation time 28586720 ps
CPU time 1.1 seconds
Started Jun 30 06:59:33 PM PDT 24
Finished Jun 30 06:59:35 PM PDT 24
Peak memory 216760 kb
Host smart-4e69d431-ed5d-4319-a7e1-42db55edea2c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491210761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1491210761
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.375514096
Short name T204
Test name
Test status
Simulation time 2981580246 ps
CPU time 11.45 seconds
Started Jun 30 06:59:34 PM PDT 24
Finished Jun 30 06:59:46 PM PDT 24
Peak memory 224552 kb
Host smart-53735c03-d782-49bd-8676-07559fda79b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375514096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.375514096
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1311262559
Short name T972
Test name
Test status
Simulation time 1756631923 ps
CPU time 4.55 seconds
Started Jun 30 06:59:33 PM PDT 24
Finished Jun 30 06:59:39 PM PDT 24
Peak memory 233660 kb
Host smart-e798e45e-5dc3-4274-92f9-2c3e84a4c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311262559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1311262559
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3122095028
Short name T790
Test name
Test status
Simulation time 369585408 ps
CPU time 4.72 seconds
Started Jun 30 06:59:41 PM PDT 24
Finished Jun 30 06:59:50 PM PDT 24
Peak memory 222340 kb
Host smart-3491a243-646b-43d7-8a96-f88178192d20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3122095028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3122095028
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2595886401
Short name T885
Test name
Test status
Simulation time 21319385260 ps
CPU time 175.11 seconds
Started Jun 30 06:59:41 PM PDT 24
Finished Jun 30 07:02:40 PM PDT 24
Peak memory 252064 kb
Host smart-6972ef2c-b509-4d69-aa49-bdc50b767bad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595886401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2595886401
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3243053119
Short name T575
Test name
Test status
Simulation time 1640107357 ps
CPU time 3.51 seconds
Started Jun 30 06:59:34 PM PDT 24
Finished Jun 30 06:59:38 PM PDT 24
Peak memory 216152 kb
Host smart-170379ce-9511-4fb9-a663-e39ad82b2607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243053119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3243053119
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.222230079
Short name T303
Test name
Test status
Simulation time 1139469344 ps
CPU time 2.92 seconds
Started Jun 30 06:59:33 PM PDT 24
Finished Jun 30 06:59:37 PM PDT 24
Peak memory 216104 kb
Host smart-21118772-c166-4b99-ac2a-2dddb3aeb976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222230079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.222230079
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2536765549
Short name T334
Test name
Test status
Simulation time 215394905 ps
CPU time 5.42 seconds
Started Jun 30 06:59:31 PM PDT 24
Finished Jun 30 06:59:37 PM PDT 24
Peak memory 216188 kb
Host smart-be55fa69-bdcc-40dd-b8b2-0ceb19cfdf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536765549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2536765549
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4116438947
Short name T90
Test name
Test status
Simulation time 27123870 ps
CPU time 0.73 seconds
Started Jun 30 06:59:33 PM PDT 24
Finished Jun 30 06:59:35 PM PDT 24
Peak memory 205888 kb
Host smart-b49d8c81-0794-4aa3-8085-0b81197701a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116438947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4116438947
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.630715444
Short name T239
Test name
Test status
Simulation time 584367242 ps
CPU time 8.36 seconds
Started Jun 30 06:59:32 PM PDT 24
Finished Jun 30 06:59:41 PM PDT 24
Peak memory 238516 kb
Host smart-45341997-2372-4d44-ad02-80285f6820b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630715444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.630715444
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3792404522
Short name T674
Test name
Test status
Simulation time 13304793 ps
CPU time 0.73 seconds
Started Jun 30 06:59:39 PM PDT 24
Finished Jun 30 06:59:42 PM PDT 24
Peak memory 204852 kb
Host smart-d8866230-3544-4293-a23f-d84a2d56f962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792404522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3792404522
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2338552322
Short name T868
Test name
Test status
Simulation time 113601468 ps
CPU time 2.52 seconds
Started Jun 30 06:59:42 PM PDT 24
Finished Jun 30 06:59:48 PM PDT 24
Peak memory 232656 kb
Host smart-9a8b1037-65b2-4dc5-be5b-19f9c05d3982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338552322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2338552322
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1682199063
Short name T971
Test name
Test status
Simulation time 28964186 ps
CPU time 0.75 seconds
Started Jun 30 06:59:41 PM PDT 24
Finished Jun 30 06:59:46 PM PDT 24
Peak memory 205532 kb
Host smart-a675135f-288f-41de-b291-95e9a3fc872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682199063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1682199063
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.752575212
Short name T272
Test name
Test status
Simulation time 6092022995 ps
CPU time 7.71 seconds
Started Jun 30 06:59:39 PM PDT 24
Finished Jun 30 06:59:48 PM PDT 24
Peak memory 232832 kb
Host smart-ad0d96a7-0256-498c-95f8-17f9d82de66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752575212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.752575212
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3571577248
Short name T875
Test name
Test status
Simulation time 22496240200 ps
CPU time 257.62 seconds
Started Jun 30 06:59:40 PM PDT 24
Finished Jun 30 07:04:01 PM PDT 24
Peak memory 253124 kb
Host smart-97b90ce5-93aa-4b94-9dc0-34f76a559347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571577248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3571577248
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2136787956
Short name T172
Test name
Test status
Simulation time 7088444797 ps
CPU time 96.28 seconds
Started Jun 30 06:59:42 PM PDT 24
Finished Jun 30 07:01:22 PM PDT 24
Peak memory 250284 kb
Host smart-95216518-a0a9-445e-84f8-971c2937bc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136787956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2136787956
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.253711910
Short name T571
Test name
Test status
Simulation time 2224184474 ps
CPU time 9.93 seconds
Started Jun 30 06:59:42 PM PDT 24
Finished Jun 30 06:59:56 PM PDT 24
Peak memory 233708 kb
Host smart-dc7eb225-d1e1-46a2-aea3-e661363920cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253711910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.253711910
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.308290087
Short name T428
Test name
Test status
Simulation time 22995484794 ps
CPU time 74.13 seconds
Started Jun 30 06:59:39 PM PDT 24
Finished Jun 30 07:00:57 PM PDT 24
Peak memory 256568 kb
Host smart-1149258c-aea7-4b5e-9e9e-18f17291cb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308290087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.308290087
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.443495695
Short name T637
Test name
Test status
Simulation time 1783872136 ps
CPU time 16.09 seconds
Started Jun 30 06:59:49 PM PDT 24
Finished Jun 30 07:00:13 PM PDT 24
Peak memory 232648 kb
Host smart-c97c4451-6917-4b59-84b1-37d0f2f3fee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443495695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.443495695
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1854369112
Short name T235
Test name
Test status
Simulation time 8377300903 ps
CPU time 76.33 seconds
Started Jun 30 06:59:49 PM PDT 24
Finished Jun 30 07:01:13 PM PDT 24
Peak memory 234476 kb
Host smart-54fc7db4-73b3-43dd-878d-e6d4a24db075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854369112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1854369112
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2456462789
Short name T327
Test name
Test status
Simulation time 46205913 ps
CPU time 1.05 seconds
Started Jun 30 06:59:38 PM PDT 24
Finished Jun 30 06:59:41 PM PDT 24
Peak memory 216752 kb
Host smart-a5cd3b72-a897-4a99-a7e4-4b1b321fb0e8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456462789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2456462789
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.645076189
Short name T516
Test name
Test status
Simulation time 4550742178 ps
CPU time 5.75 seconds
Started Jun 30 06:59:49 PM PDT 24
Finished Jun 30 07:00:03 PM PDT 24
Peak memory 224560 kb
Host smart-dbacc6a9-6540-40b0-8750-9df7033eb39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645076189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.645076189
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1467237055
Short name T368
Test name
Test status
Simulation time 4684290425 ps
CPU time 17.29 seconds
Started Jun 30 06:59:38 PM PDT 24
Finished Jun 30 06:59:56 PM PDT 24
Peak memory 240640 kb
Host smart-7184f01e-8f28-4536-b8f8-3b96ff9b209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467237055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1467237055
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.950460257
Short name T149
Test name
Test status
Simulation time 518276961 ps
CPU time 3.87 seconds
Started Jun 30 06:59:41 PM PDT 24
Finished Jun 30 06:59:49 PM PDT 24
Peak memory 220368 kb
Host smart-26a48e79-0f06-44ff-b3dd-ab4662276ae3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=950460257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.950460257
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1734506372
Short name T19
Test name
Test status
Simulation time 42524613291 ps
CPU time 68.47 seconds
Started Jun 30 06:59:40 PM PDT 24
Finished Jun 30 07:00:52 PM PDT 24
Peak memory 248384 kb
Host smart-b025650c-e11c-4318-a4cf-f415c1b78beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734506372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1734506372
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.506546733
Short name T509
Test name
Test status
Simulation time 8680072896 ps
CPU time 18.46 seconds
Started Jun 30 06:59:41 PM PDT 24
Finished Jun 30 07:00:04 PM PDT 24
Peak memory 216424 kb
Host smart-b7b7c916-a1af-4d36-9245-fdaa323d2772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506546733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.506546733
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2028901447
Short name T304
Test name
Test status
Simulation time 1715133324 ps
CPU time 4.19 seconds
Started Jun 30 06:59:48 PM PDT 24
Finished Jun 30 06:59:59 PM PDT 24
Peak memory 216112 kb
Host smart-f8e37dad-dc4d-44a8-91fa-900e7f673254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028901447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2028901447
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2576522615
Short name T753
Test name
Test status
Simulation time 221909425 ps
CPU time 2.92 seconds
Started Jun 30 06:59:48 PM PDT 24
Finished Jun 30 06:59:58 PM PDT 24
Peak memory 216144 kb
Host smart-40120f68-a56d-4b08-84bc-eba1df4f3d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576522615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2576522615
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3334227059
Short name T561
Test name
Test status
Simulation time 60164505 ps
CPU time 0.9 seconds
Started Jun 30 06:59:40 PM PDT 24
Finished Jun 30 06:59:44 PM PDT 24
Peak memory 205872 kb
Host smart-9036ff47-c680-4a69-bc39-2e6981f1e5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334227059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3334227059
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3125708356
Short name T876
Test name
Test status
Simulation time 349634454 ps
CPU time 2.61 seconds
Started Jun 30 06:59:39 PM PDT 24
Finished Jun 30 06:59:45 PM PDT 24
Peak memory 224416 kb
Host smart-a82b341f-6caa-4c8d-9622-64668830e38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125708356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3125708356
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2517295206
Short name T305
Test name
Test status
Simulation time 53473356 ps
CPU time 0.73 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:58:43 PM PDT 24
Peak memory 205392 kb
Host smart-d9a7507d-df02-4c0a-b81b-2d9caf50d0d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517295206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
517295206
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4219292601
Short name T776
Test name
Test status
Simulation time 638306464 ps
CPU time 2.49 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:58:40 PM PDT 24
Peak memory 224460 kb
Host smart-753802ab-76c0-47a8-99d1-ee09351b48ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219292601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4219292601
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1992199859
Short name T635
Test name
Test status
Simulation time 16442788 ps
CPU time 0.76 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:58:38 PM PDT 24
Peak memory 205848 kb
Host smart-fb1ff6d2-99f4-46f9-a286-85d458887db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992199859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1992199859
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2225970701
Short name T263
Test name
Test status
Simulation time 5179145645 ps
CPU time 91.18 seconds
Started Jun 30 06:58:44 PM PDT 24
Finished Jun 30 07:00:17 PM PDT 24
Peak memory 256920 kb
Host smart-659b374f-88d5-49eb-a29a-8c792c15291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225970701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2225970701
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1807812439
Short name T980
Test name
Test status
Simulation time 30127372247 ps
CPU time 155.13 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 07:01:19 PM PDT 24
Peak memory 267776 kb
Host smart-3e431d0f-5c81-419c-a66f-fd97ef54a9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807812439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1807812439
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3708139142
Short name T73
Test name
Test status
Simulation time 254178654 ps
CPU time 5.55 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 06:58:49 PM PDT 24
Peak memory 224472 kb
Host smart-7c7874ce-1f73-40b8-b94f-1c5f5ef26063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708139142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3708139142
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.426574260
Short name T381
Test name
Test status
Simulation time 3661765743 ps
CPU time 25.58 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 06:59:03 PM PDT 24
Peak memory 237656 kb
Host smart-a736c365-644a-49f5-b1af-c74bca7e3b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426574260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
426574260
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3299419473
Short name T498
Test name
Test status
Simulation time 111496302 ps
CPU time 3.82 seconds
Started Jun 30 06:58:41 PM PDT 24
Finished Jun 30 06:58:45 PM PDT 24
Peak memory 232596 kb
Host smart-4d2de8db-9f9a-40d1-bf10-5a8263913ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299419473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3299419473
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3810435036
Short name T503
Test name
Test status
Simulation time 2205154908 ps
CPU time 6.27 seconds
Started Jun 30 06:58:41 PM PDT 24
Finished Jun 30 06:58:48 PM PDT 24
Peak memory 232660 kb
Host smart-0bb29686-8bb9-48cb-b670-f6e68d7241d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810435036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3810435036
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.353994641
Short name T988
Test name
Test status
Simulation time 35314099 ps
CPU time 1.1 seconds
Started Jun 30 06:58:38 PM PDT 24
Finished Jun 30 06:58:41 PM PDT 24
Peak memory 216716 kb
Host smart-a7df897d-cce8-4990-98ac-a63591344eed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353994641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.353994641
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.822764872
Short name T966
Test name
Test status
Simulation time 1608531425 ps
CPU time 6.57 seconds
Started Jun 30 06:58:35 PM PDT 24
Finished Jun 30 06:58:42 PM PDT 24
Peak memory 224496 kb
Host smart-aa48bbe6-1713-49fb-ae7e-1cc87fda0e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822764872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
822764872
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2593918437
Short name T302
Test name
Test status
Simulation time 32048097 ps
CPU time 2.52 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 06:58:41 PM PDT 24
Peak memory 232344 kb
Host smart-45d621f7-2eca-4103-83d4-61449b194993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593918437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2593918437
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4065896359
Short name T459
Test name
Test status
Simulation time 797518108 ps
CPU time 7.3 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 06:58:46 PM PDT 24
Peak memory 222376 kb
Host smart-8e698a85-8f5b-4528-9141-32fd4905c36e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4065896359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4065896359
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2929587384
Short name T68
Test name
Test status
Simulation time 146126768 ps
CPU time 0.98 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:58:44 PM PDT 24
Peak memory 235488 kb
Host smart-0ecfe0a3-e824-4e66-8c0a-54a5e012a558
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929587384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2929587384
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.242290410
Short name T81
Test name
Test status
Simulation time 32590024741 ps
CPU time 133.39 seconds
Started Jun 30 06:58:44 PM PDT 24
Finished Jun 30 07:00:58 PM PDT 24
Peak memory 256028 kb
Host smart-6b8e8b83-a7f4-45e5-a590-c5d0f3d5a4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242290410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.242290410
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.329594899
Short name T137
Test name
Test status
Simulation time 1258444175 ps
CPU time 5.73 seconds
Started Jun 30 06:58:38 PM PDT 24
Finished Jun 30 06:58:45 PM PDT 24
Peak memory 219272 kb
Host smart-3ef718db-f8f1-4647-b5d9-e80d47a5b351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329594899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.329594899
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.186105519
Short name T896
Test name
Test status
Simulation time 29059837339 ps
CPU time 15.04 seconds
Started Jun 30 06:58:37 PM PDT 24
Finished Jun 30 06:58:54 PM PDT 24
Peak memory 216380 kb
Host smart-efef7e71-0fef-439f-a2a6-b066194eba24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186105519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.186105519
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.897724966
Short name T8
Test name
Test status
Simulation time 114761929 ps
CPU time 1.21 seconds
Started Jun 30 06:58:36 PM PDT 24
Finished Jun 30 06:58:38 PM PDT 24
Peak memory 207132 kb
Host smart-749395ec-dc8b-4067-864b-eda1fcdcf17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897724966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.897724966
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2467565155
Short name T301
Test name
Test status
Simulation time 32074204 ps
CPU time 0.88 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 06:58:45 PM PDT 24
Peak memory 206908 kb
Host smart-49f28fb2-df6d-4bb3-8fe3-0be70b62bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467565155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2467565155
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.4172072235
Short name T477
Test name
Test status
Simulation time 3820305190 ps
CPU time 13.88 seconds
Started Jun 30 06:58:38 PM PDT 24
Finished Jun 30 06:58:53 PM PDT 24
Peak memory 239352 kb
Host smart-cb63fa97-fb6b-4475-b7b4-73c523beb4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172072235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4172072235
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3546311729
Short name T802
Test name
Test status
Simulation time 13936608 ps
CPU time 0.77 seconds
Started Jun 30 06:59:46 PM PDT 24
Finished Jun 30 06:59:52 PM PDT 24
Peak memory 204840 kb
Host smart-74e27b52-ca94-4af2-a258-98927541ea95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546311729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3546311729
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.889703379
Short name T425
Test name
Test status
Simulation time 43544917 ps
CPU time 2.58 seconds
Started Jun 30 06:59:46 PM PDT 24
Finished Jun 30 06:59:54 PM PDT 24
Peak memory 232344 kb
Host smart-9f286d3a-c3a4-4a6d-9a2e-a5f308220db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889703379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.889703379
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3957846640
Short name T722
Test name
Test status
Simulation time 19053817 ps
CPU time 0.77 seconds
Started Jun 30 06:59:38 PM PDT 24
Finished Jun 30 06:59:41 PM PDT 24
Peak memory 205528 kb
Host smart-fa835841-35a5-419b-b2cb-1aca5f499c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957846640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3957846640
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3461004725
Short name T956
Test name
Test status
Simulation time 302507720708 ps
CPU time 447.31 seconds
Started Jun 30 06:59:46 PM PDT 24
Finished Jun 30 07:07:18 PM PDT 24
Peak memory 252092 kb
Host smart-135cd751-9cd2-47ed-9da3-9db4cd0dc8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461004725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3461004725
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1542108792
Short name T993
Test name
Test status
Simulation time 210302828 ps
CPU time 3.61 seconds
Started Jun 30 06:59:45 PM PDT 24
Finished Jun 30 06:59:53 PM PDT 24
Peak memory 224484 kb
Host smart-b6ff16fc-52b3-4ac4-a7e4-12e4bac45b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542108792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1542108792
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4289164742
Short name T968
Test name
Test status
Simulation time 1812990603 ps
CPU time 4.72 seconds
Started Jun 30 06:59:42 PM PDT 24
Finished Jun 30 06:59:50 PM PDT 24
Peak memory 232652 kb
Host smart-8785bc4a-0f92-442d-aeef-68f1fcc0fe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289164742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4289164742
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2405623984
Short name T827
Test name
Test status
Simulation time 906666091 ps
CPU time 16.17 seconds
Started Jun 30 06:59:40 PM PDT 24
Finished Jun 30 07:00:00 PM PDT 24
Peak memory 232668 kb
Host smart-43c4338f-088d-4715-9822-ed4eec9fb40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405623984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2405623984
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.826844506
Short name T767
Test name
Test status
Simulation time 1285959367 ps
CPU time 3.25 seconds
Started Jun 30 06:59:42 PM PDT 24
Finished Jun 30 06:59:49 PM PDT 24
Peak memory 232580 kb
Host smart-296a097c-9715-44f3-9589-9d9ec79fb2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826844506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.826844506
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3416724225
Short name T1007
Test name
Test status
Simulation time 606119200 ps
CPU time 4.05 seconds
Started Jun 30 06:59:39 PM PDT 24
Finished Jun 30 06:59:46 PM PDT 24
Peak memory 232652 kb
Host smart-5cbad2b1-db72-4230-bec3-4c58467a8b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416724225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3416724225
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3482688326
Short name T849
Test name
Test status
Simulation time 1320779549 ps
CPU time 6.33 seconds
Started Jun 30 06:59:45 PM PDT 24
Finished Jun 30 06:59:56 PM PDT 24
Peak memory 222824 kb
Host smart-1496de4d-1a22-42c0-84b4-813da0123a60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482688326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3482688326
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3941461005
Short name T62
Test name
Test status
Simulation time 9542442990 ps
CPU time 59.23 seconds
Started Jun 30 06:59:47 PM PDT 24
Finished Jun 30 07:00:53 PM PDT 24
Peak memory 249256 kb
Host smart-e1c8379e-d65b-4b87-b44c-6c5cb4f4e9cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941461005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3941461005
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1696687254
Short name T770
Test name
Test status
Simulation time 2605915582 ps
CPU time 6.42 seconds
Started Jun 30 06:59:39 PM PDT 24
Finished Jun 30 06:59:49 PM PDT 24
Peak memory 216476 kb
Host smart-3247ad48-f286-4e64-b355-01f3028f728b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696687254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1696687254
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.205957435
Short name T422
Test name
Test status
Simulation time 875374344 ps
CPU time 6.93 seconds
Started Jun 30 06:59:39 PM PDT 24
Finished Jun 30 06:59:48 PM PDT 24
Peak memory 216140 kb
Host smart-c7333987-57cb-4e37-a09e-8acee531e8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205957435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.205957435
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.906915701
Short name T819
Test name
Test status
Simulation time 89176025 ps
CPU time 1.1 seconds
Started Jun 30 06:59:42 PM PDT 24
Finished Jun 30 06:59:47 PM PDT 24
Peak memory 207196 kb
Host smart-e2cc75e1-38c0-4d5e-ab11-fa2866106d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906915701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.906915701
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.710583330
Short name T501
Test name
Test status
Simulation time 83314791 ps
CPU time 0.95 seconds
Started Jun 30 06:59:42 PM PDT 24
Finished Jun 30 06:59:47 PM PDT 24
Peak memory 205868 kb
Host smart-ba1fc57b-025b-41fc-88e2-cd2234f3dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710583330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.710583330
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2344494459
Short name T665
Test name
Test status
Simulation time 1425532168 ps
CPU time 7.73 seconds
Started Jun 30 06:59:45 PM PDT 24
Finished Jun 30 06:59:58 PM PDT 24
Peak memory 240804 kb
Host smart-33230fd8-cfc3-42e5-a36a-76b1c4ca4668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344494459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2344494459
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1545298116
Short name T555
Test name
Test status
Simulation time 11863134 ps
CPU time 0.75 seconds
Started Jun 30 06:59:46 PM PDT 24
Finished Jun 30 06:59:53 PM PDT 24
Peak memory 205728 kb
Host smart-0c63f006-4b8a-4c42-9185-a876cf77223c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545298116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1545298116
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2438743468
Short name T938
Test name
Test status
Simulation time 4098488852 ps
CPU time 7.13 seconds
Started Jun 30 06:59:47 PM PDT 24
Finished Jun 30 07:00:00 PM PDT 24
Peak memory 232832 kb
Host smart-b4f18f33-2a2f-4a5f-959c-c1f33bbd19e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438743468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2438743468
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1703288593
Short name T859
Test name
Test status
Simulation time 47927392 ps
CPU time 0.77 seconds
Started Jun 30 06:59:47 PM PDT 24
Finished Jun 30 06:59:53 PM PDT 24
Peak memory 205896 kb
Host smart-dbd3be36-470e-4a6c-9fc3-e025b6f2b978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703288593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1703288593
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1331130552
Short name T38
Test name
Test status
Simulation time 2354131079 ps
CPU time 24.15 seconds
Started Jun 30 06:59:43 PM PDT 24
Finished Jun 30 07:00:12 PM PDT 24
Peak memory 248820 kb
Host smart-99f7222e-e486-4824-ba61-30db50203de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331130552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1331130552
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1373068309
Short name T138
Test name
Test status
Simulation time 19465015455 ps
CPU time 86.6 seconds
Started Jun 30 06:59:48 PM PDT 24
Finished Jun 30 07:01:22 PM PDT 24
Peak memory 253616 kb
Host smart-10131eca-7439-4c15-a8de-f50b9a0afbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373068309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1373068309
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.986316034
Short name T567
Test name
Test status
Simulation time 4730964936 ps
CPU time 111.21 seconds
Started Jun 30 06:59:47 PM PDT 24
Finished Jun 30 07:01:45 PM PDT 24
Peak memory 268148 kb
Host smart-a211a30a-5568-4dad-9557-1f8740719b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986316034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.986316034
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3585101924
Short name T285
Test name
Test status
Simulation time 575647491 ps
CPU time 14.7 seconds
Started Jun 30 06:59:47 PM PDT 24
Finished Jun 30 07:00:07 PM PDT 24
Peak memory 232672 kb
Host smart-169a869b-0858-4168-81ac-d04c11414451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585101924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3585101924
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2607803989
Short name T768
Test name
Test status
Simulation time 24737429193 ps
CPU time 41.91 seconds
Started Jun 30 06:59:48 PM PDT 24
Finished Jun 30 07:00:37 PM PDT 24
Peak memory 248536 kb
Host smart-a3a74aa6-c290-4589-b892-b862a0ab9047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607803989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2607803989
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1679580654
Short name T193
Test name
Test status
Simulation time 233461845 ps
CPU time 3.16 seconds
Started Jun 30 06:59:45 PM PDT 24
Finished Jun 30 06:59:53 PM PDT 24
Peak memory 224656 kb
Host smart-c6ae7e2b-e378-43a3-80e5-fea55a54774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679580654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1679580654
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3616108156
Short name T705
Test name
Test status
Simulation time 40362084548 ps
CPU time 70.42 seconds
Started Jun 30 06:59:49 PM PDT 24
Finished Jun 30 07:01:06 PM PDT 24
Peak memory 234116 kb
Host smart-0fe18367-dc50-4c02-9998-f65e7b153d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616108156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3616108156
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.24563565
Short name T690
Test name
Test status
Simulation time 882744767 ps
CPU time 4.36 seconds
Started Jun 30 06:59:46 PM PDT 24
Finished Jun 30 06:59:56 PM PDT 24
Peak memory 224428 kb
Host smart-a6508f74-556b-47bf-8524-e6a20baaf924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24563565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.24563565
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.227319482
Short name T23
Test name
Test status
Simulation time 95202061 ps
CPU time 2.89 seconds
Started Jun 30 06:59:43 PM PDT 24
Finished Jun 30 06:59:50 PM PDT 24
Peak memory 232596 kb
Host smart-504bdb68-ae3a-40da-8bff-b8225da896d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227319482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.227319482
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3250371671
Short name T356
Test name
Test status
Simulation time 5254025260 ps
CPU time 6.89 seconds
Started Jun 30 06:59:47 PM PDT 24
Finished Jun 30 07:00:01 PM PDT 24
Peak memory 220512 kb
Host smart-dc38115b-1e89-46f8-b328-29bd35c179af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3250371671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3250371671
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3035280074
Short name T1009
Test name
Test status
Simulation time 5174494642 ps
CPU time 31.56 seconds
Started Jun 30 06:59:47 PM PDT 24
Finished Jun 30 07:00:25 PM PDT 24
Peak memory 216308 kb
Host smart-1d93cb72-8c82-4392-a46e-bdead40a9f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035280074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3035280074
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2233787953
Short name T360
Test name
Test status
Simulation time 1934839289 ps
CPU time 6.79 seconds
Started Jun 30 06:59:46 PM PDT 24
Finished Jun 30 06:59:59 PM PDT 24
Peak memory 216228 kb
Host smart-0f3f0fb1-713e-46e7-aaa4-9a22aa19dd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233787953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2233787953
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2018710342
Short name T341
Test name
Test status
Simulation time 56219297 ps
CPU time 0.91 seconds
Started Jun 30 06:59:45 PM PDT 24
Finished Jun 30 06:59:51 PM PDT 24
Peak memory 206412 kb
Host smart-b44309a9-ccc2-4619-864f-02a2460b8f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018710342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2018710342
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4077740488
Short name T566
Test name
Test status
Simulation time 108371337 ps
CPU time 1.06 seconds
Started Jun 30 06:59:46 PM PDT 24
Finished Jun 30 06:59:51 PM PDT 24
Peak memory 206108 kb
Host smart-05822205-f6fe-4741-97d6-7484d306f570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077740488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4077740488
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1691384670
Short name T473
Test name
Test status
Simulation time 65243971992 ps
CPU time 45.92 seconds
Started Jun 30 06:59:44 PM PDT 24
Finished Jun 30 07:00:35 PM PDT 24
Peak memory 232720 kb
Host smart-b8e49060-5a2d-4f74-b1e5-84b566dd8e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691384670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1691384670
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2912612755
Short name T1005
Test name
Test status
Simulation time 22643904 ps
CPU time 0.8 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:00:02 PM PDT 24
Peak memory 205752 kb
Host smart-4f82ac9a-ab76-489c-99dc-c860304cc2a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912612755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2912612755
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3976414786
Short name T181
Test name
Test status
Simulation time 122954623 ps
CPU time 2.17 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:00:03 PM PDT 24
Peak memory 224440 kb
Host smart-e4dc7587-7a8c-455e-9bd5-f004b477012b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976414786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3976414786
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3436279417
Short name T405
Test name
Test status
Simulation time 17673602 ps
CPU time 0.84 seconds
Started Jun 30 06:59:46 PM PDT 24
Finished Jun 30 06:59:52 PM PDT 24
Peak memory 206576 kb
Host smart-ad8253c2-c3ec-4c47-aa81-3eb7954056d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436279417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3436279417
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3230596632
Short name T761
Test name
Test status
Simulation time 64464960285 ps
CPU time 137.44 seconds
Started Jun 30 06:59:56 PM PDT 24
Finished Jun 30 07:02:21 PM PDT 24
Peak memory 254900 kb
Host smart-b52c174a-fa5a-4d03-8279-cffa030cc781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230596632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3230596632
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3085659119
Short name T230
Test name
Test status
Simulation time 10527429372 ps
CPU time 128.71 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:02:09 PM PDT 24
Peak memory 252944 kb
Host smart-111ec0e2-9da4-4203-b1eb-53d8fb0dd0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085659119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3085659119
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.105018755
Short name T410
Test name
Test status
Simulation time 739024926 ps
CPU time 10.28 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:00:11 PM PDT 24
Peak memory 224468 kb
Host smart-22b78f75-af9c-45dc-a705-831d86f1d7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105018755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.105018755
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2212260446
Short name T675
Test name
Test status
Simulation time 59320722646 ps
CPU time 257.19 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:04:18 PM PDT 24
Peak memory 256648 kb
Host smart-6146ce7f-2c13-4628-a346-5d7600a1cbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212260446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2212260446
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2286384829
Short name T184
Test name
Test status
Simulation time 91574606 ps
CPU time 2.46 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:00:02 PM PDT 24
Peak memory 232652 kb
Host smart-6175a48d-71b5-4e6c-995f-63888c184cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286384829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2286384829
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1469797014
Short name T247
Test name
Test status
Simulation time 39560744457 ps
CPU time 102.66 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 232816 kb
Host smart-bdd5b1f6-fcc3-46b5-b4a3-3aa82182d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469797014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1469797014
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2546652850
Short name T212
Test name
Test status
Simulation time 16674896917 ps
CPU time 13.43 seconds
Started Jun 30 06:59:54 PM PDT 24
Finished Jun 30 07:00:15 PM PDT 24
Peak memory 224584 kb
Host smart-1be0bcb0-4c4a-404e-a916-66d4d941104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546652850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2546652850
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3605052228
Short name T363
Test name
Test status
Simulation time 1620479276 ps
CPU time 8.05 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:00:08 PM PDT 24
Peak memory 232668 kb
Host smart-1fd18a0f-d685-4fa2-9561-087916cbe8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605052228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3605052228
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3076694136
Short name T999
Test name
Test status
Simulation time 679268978 ps
CPU time 8.47 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:00:10 PM PDT 24
Peak memory 220144 kb
Host smart-5fc44a05-4544-40f1-ae90-03204e418fee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3076694136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3076694136
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2987792625
Short name T906
Test name
Test status
Simulation time 262470068 ps
CPU time 1 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:00:01 PM PDT 24
Peak memory 206940 kb
Host smart-8ba5e89a-01ef-413a-9c36-83b681b66be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987792625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2987792625
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1569671530
Short name T3
Test name
Test status
Simulation time 987344092 ps
CPU time 3.71 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:00:04 PM PDT 24
Peak memory 216216 kb
Host smart-c06a4561-64c1-4cc7-9d74-d89c88d070dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569671530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1569671530
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1959905022
Short name T335
Test name
Test status
Simulation time 10783479137 ps
CPU time 17.29 seconds
Started Jun 30 06:59:47 PM PDT 24
Finished Jun 30 07:00:10 PM PDT 24
Peak memory 216340 kb
Host smart-b5c6f3a3-d74f-4441-b9ca-2ed28809768f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959905022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1959905022
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3722541455
Short name T970
Test name
Test status
Simulation time 44304171 ps
CPU time 0.99 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:00:01 PM PDT 24
Peak memory 207864 kb
Host smart-8f5966d8-ba40-4163-a704-ce1fdce6f0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722541455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3722541455
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4141579859
Short name T924
Test name
Test status
Simulation time 44423778 ps
CPU time 0.65 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:00:00 PM PDT 24
Peak memory 205568 kb
Host smart-525e813f-7fd8-4684-ba61-6811de325055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141579859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4141579859
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1801190023
Short name T629
Test name
Test status
Simulation time 9812917940 ps
CPU time 21.03 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:00:22 PM PDT 24
Peak memory 240028 kb
Host smart-4a1874aa-d209-47ab-bab8-4208f7de8d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801190023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1801190023
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2780059861
Short name T751
Test name
Test status
Simulation time 14222123 ps
CPU time 0.71 seconds
Started Jun 30 07:00:01 PM PDT 24
Finished Jun 30 07:00:09 PM PDT 24
Peak memory 205744 kb
Host smart-e79ad9f0-a22b-40c2-bd32-1bd9c1641402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780059861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2780059861
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2792483775
Short name T601
Test name
Test status
Simulation time 4999493514 ps
CPU time 6.68 seconds
Started Jun 30 06:59:54 PM PDT 24
Finished Jun 30 07:00:08 PM PDT 24
Peak memory 224560 kb
Host smart-f6480f0f-9059-43d6-97ef-3d1d9360ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792483775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2792483775
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.854516990
Short name T417
Test name
Test status
Simulation time 17262671 ps
CPU time 0.82 seconds
Started Jun 30 06:59:54 PM PDT 24
Finished Jun 30 07:00:03 PM PDT 24
Peak memory 206548 kb
Host smart-d99a6449-0e5d-468c-84b1-d42d0cd0231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854516990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.854516990
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.4063383477
Short name T78
Test name
Test status
Simulation time 7096085568 ps
CPU time 49.28 seconds
Started Jun 30 07:00:01 PM PDT 24
Finished Jun 30 07:00:57 PM PDT 24
Peak memory 240648 kb
Host smart-0e70fb2e-cfed-4027-a324-aa76621160f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063383477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.4063383477
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.387660823
Short name T34
Test name
Test status
Simulation time 59474391351 ps
CPU time 235.93 seconds
Started Jun 30 06:59:58 PM PDT 24
Finished Jun 30 07:04:01 PM PDT 24
Peak memory 266364 kb
Host smart-a6aa52dc-0fbc-4656-8eb3-178aee9cee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387660823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.387660823
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1860415188
Short name T1001
Test name
Test status
Simulation time 2544691842 ps
CPU time 20.6 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:00:22 PM PDT 24
Peak memory 240520 kb
Host smart-297a918c-8f02-4bc6-afbf-d2c3010f972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860415188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1860415188
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1393340521
Short name T742
Test name
Test status
Simulation time 49136788777 ps
CPU time 56.22 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:00:57 PM PDT 24
Peak memory 249172 kb
Host smart-ad2ae4f8-6314-4bc9-acaf-6e0bfeeb5c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393340521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1393340521
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1610996382
Short name T324
Test name
Test status
Simulation time 177082755 ps
CPU time 2.58 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:00:04 PM PDT 24
Peak memory 232664 kb
Host smart-a44f13c7-acaf-4f15-be1c-cbf14bf5f72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610996382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1610996382
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1734301110
Short name T563
Test name
Test status
Simulation time 1858728739 ps
CPU time 21.34 seconds
Started Jun 30 06:59:51 PM PDT 24
Finished Jun 30 07:00:21 PM PDT 24
Peak memory 252480 kb
Host smart-a37a7b8b-03f5-40cf-a60a-e84450aff430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734301110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1734301110
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3287864187
Short name T474
Test name
Test status
Simulation time 665798848 ps
CPU time 2.82 seconds
Started Jun 30 06:59:56 PM PDT 24
Finished Jun 30 07:00:06 PM PDT 24
Peak memory 224508 kb
Host smart-4f5c9721-fc78-43e3-8886-755717c68af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287864187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3287864187
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3088399644
Short name T186
Test name
Test status
Simulation time 13706386820 ps
CPU time 17 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:00:16 PM PDT 24
Peak memory 240592 kb
Host smart-0326d82b-9073-4a4f-93a2-b08e446f678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088399644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3088399644
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.961820974
Short name T385
Test name
Test status
Simulation time 1030635673 ps
CPU time 7.79 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:00:07 PM PDT 24
Peak memory 222372 kb
Host smart-d4a19ffe-fe0c-4b4d-9e56-793ba68be06a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=961820974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.961820974
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.83409306
Short name T838
Test name
Test status
Simulation time 54256944 ps
CPU time 1.09 seconds
Started Jun 30 06:59:58 PM PDT 24
Finished Jun 30 07:00:06 PM PDT 24
Peak memory 207048 kb
Host smart-2c331dd7-d57a-45c0-8359-0c32ae847cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83409306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress
_all.83409306
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2746155138
Short name T292
Test name
Test status
Simulation time 27915616488 ps
CPU time 66.38 seconds
Started Jun 30 06:59:52 PM PDT 24
Finished Jun 30 07:01:07 PM PDT 24
Peak memory 216340 kb
Host smart-9ba93122-d62a-4979-8b11-9e9e66c8af6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746155138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2746155138
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2703748269
Short name T909
Test name
Test status
Simulation time 330154748 ps
CPU time 2.98 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:00:04 PM PDT 24
Peak memory 216092 kb
Host smart-b4891ae0-b2f5-4770-98b9-b3b7faa369a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703748269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2703748269
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3323072707
Short name T689
Test name
Test status
Simulation time 84178028 ps
CPU time 1.47 seconds
Started Jun 30 06:59:55 PM PDT 24
Finished Jun 30 07:00:04 PM PDT 24
Peak memory 216196 kb
Host smart-d49229e6-32dd-409e-99b2-85219d2bf901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323072707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3323072707
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2013796668
Short name T317
Test name
Test status
Simulation time 39868921 ps
CPU time 0.81 seconds
Started Jun 30 06:59:53 PM PDT 24
Finished Jun 30 07:00:02 PM PDT 24
Peak memory 205888 kb
Host smart-a6685d62-1dff-404c-b70b-6b88e3feee4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013796668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2013796668
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3282831609
Short name T615
Test name
Test status
Simulation time 678863407 ps
CPU time 9.13 seconds
Started Jun 30 06:59:51 PM PDT 24
Finished Jun 30 07:00:08 PM PDT 24
Peak memory 232592 kb
Host smart-66a6e4e3-c924-4b52-993f-c25c80fc7fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282831609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3282831609
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3922200842
Short name T309
Test name
Test status
Simulation time 41122366 ps
CPU time 0.73 seconds
Started Jun 30 06:59:57 PM PDT 24
Finished Jun 30 07:00:05 PM PDT 24
Peak memory 204800 kb
Host smart-a072acba-b6bd-4d47-ba25-abb3ce91bcac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922200842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3922200842
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1662827868
Short name T759
Test name
Test status
Simulation time 78553463 ps
CPU time 2.26 seconds
Started Jun 30 07:00:00 PM PDT 24
Finished Jun 30 07:00:09 PM PDT 24
Peak memory 224424 kb
Host smart-3c3a9484-a32e-4137-b40d-4bcc07229aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662827868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1662827868
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3024197567
Short name T695
Test name
Test status
Simulation time 26210286 ps
CPU time 0.79 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:07 PM PDT 24
Peak memory 205532 kb
Host smart-1ee214d3-cbdc-4316-93e8-530d2250470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024197567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3024197567
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1280735655
Short name T1002
Test name
Test status
Simulation time 918772127 ps
CPU time 18.4 seconds
Started Jun 30 06:59:57 PM PDT 24
Finished Jun 30 07:00:23 PM PDT 24
Peak memory 239580 kb
Host smart-d53af9a7-57ca-48e5-a981-56631806bd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280735655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1280735655
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1123387825
Short name T604
Test name
Test status
Simulation time 758803869 ps
CPU time 13.39 seconds
Started Jun 30 07:00:00 PM PDT 24
Finished Jun 30 07:00:20 PM PDT 24
Peak memory 232660 kb
Host smart-dac467d7-f12c-4444-9b76-c69a6b61e3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123387825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1123387825
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1581777018
Short name T842
Test name
Test status
Simulation time 9597194401 ps
CPU time 66.37 seconds
Started Jun 30 06:59:58 PM PDT 24
Finished Jun 30 07:01:12 PM PDT 24
Peak memory 249256 kb
Host smart-fc979283-7075-4456-ac09-2d65af81bf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581777018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1581777018
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.424462191
Short name T536
Test name
Test status
Simulation time 13184586714 ps
CPU time 24.28 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:30 PM PDT 24
Peak memory 234444 kb
Host smart-8188f577-ce73-49f6-a545-8333deefb002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424462191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.424462191
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3810088779
Short name T866
Test name
Test status
Simulation time 6061081527 ps
CPU time 85.45 seconds
Started Jun 30 06:59:57 PM PDT 24
Finished Jun 30 07:01:30 PM PDT 24
Peak memory 263892 kb
Host smart-23787edd-c2b9-45fb-b1ef-34e45f08b119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810088779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3810088779
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1969561030
Short name T623
Test name
Test status
Simulation time 19048603180 ps
CPU time 14.51 seconds
Started Jun 30 07:00:00 PM PDT 24
Finished Jun 30 07:00:21 PM PDT 24
Peak memory 232792 kb
Host smart-4f4ce549-86e6-4982-9560-aa4676233f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969561030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1969561030
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3334012826
Short name T210
Test name
Test status
Simulation time 38596477040 ps
CPU time 38.28 seconds
Started Jun 30 06:59:58 PM PDT 24
Finished Jun 30 07:00:43 PM PDT 24
Peak memory 232760 kb
Host smart-6680d852-7ad6-4302-8530-e28a94313718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334012826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3334012826
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4131563139
Short name T785
Test name
Test status
Simulation time 13269329571 ps
CPU time 12.53 seconds
Started Jun 30 07:00:00 PM PDT 24
Finished Jun 30 07:00:19 PM PDT 24
Peak memory 232796 kb
Host smart-029f63d9-4c0f-4491-9362-4422e807778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131563139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4131563139
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1922947326
Short name T540
Test name
Test status
Simulation time 370274163 ps
CPU time 3.53 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:09 PM PDT 24
Peak memory 232652 kb
Host smart-0333c0c6-f8c5-4097-a600-3be48e8d172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922947326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1922947326
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.984467778
Short name T400
Test name
Test status
Simulation time 200601784 ps
CPU time 4.6 seconds
Started Jun 30 07:00:01 PM PDT 24
Finished Jun 30 07:00:12 PM PDT 24
Peak memory 222536 kb
Host smart-c829d853-13d0-44d8-864d-fb7d1d795b70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=984467778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.984467778
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2586312879
Short name T961
Test name
Test status
Simulation time 89155034198 ps
CPU time 324.26 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:05:30 PM PDT 24
Peak memory 249220 kb
Host smart-4c3ba4b2-2102-4a89-aab4-b0f916537986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586312879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2586312879
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.62984597
Short name T854
Test name
Test status
Simulation time 3971928143 ps
CPU time 31.73 seconds
Started Jun 30 06:59:57 PM PDT 24
Finished Jun 30 07:00:36 PM PDT 24
Peak memory 216332 kb
Host smart-58082ef8-ea4c-4193-9d6a-de258f06f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62984597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.62984597
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3703696515
Short name T606
Test name
Test status
Simulation time 2377087728 ps
CPU time 7.2 seconds
Started Jun 30 07:00:02 PM PDT 24
Finished Jun 30 07:00:16 PM PDT 24
Peak memory 216312 kb
Host smart-efee9c29-e21d-407b-b134-9f6279adae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703696515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3703696515
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3271837506
Short name T299
Test name
Test status
Simulation time 84048006 ps
CPU time 0.83 seconds
Started Jun 30 06:59:57 PM PDT 24
Finished Jun 30 07:00:05 PM PDT 24
Peak memory 206152 kb
Host smart-ac8d08b5-8e81-40ed-87c1-92341e9cc3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271837506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3271837506
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4269204080
Short name T556
Test name
Test status
Simulation time 42368265 ps
CPU time 0.7 seconds
Started Jun 30 06:59:58 PM PDT 24
Finished Jun 30 07:00:06 PM PDT 24
Peak memory 205868 kb
Host smart-df55248f-ee58-421f-8f3b-57f578bddff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269204080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4269204080
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1698020753
Short name T434
Test name
Test status
Simulation time 1161168208 ps
CPU time 5.58 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:11 PM PDT 24
Peak memory 240852 kb
Host smart-90a11601-ae57-4002-b265-d1b5a673a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698020753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1698020753
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4117548307
Short name T482
Test name
Test status
Simulation time 48743301 ps
CPU time 0.73 seconds
Started Jun 30 07:00:02 PM PDT 24
Finished Jun 30 07:00:10 PM PDT 24
Peak memory 205736 kb
Host smart-648a01ff-058d-4bab-a7d7-94e7089e64ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117548307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4117548307
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1056197613
Short name T937
Test name
Test status
Simulation time 741520149 ps
CPU time 7.9 seconds
Started Jun 30 06:59:58 PM PDT 24
Finished Jun 30 07:00:13 PM PDT 24
Peak memory 224476 kb
Host smart-5e68b90d-e753-459e-a210-1158cc1264c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056197613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1056197613
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2405708704
Short name T377
Test name
Test status
Simulation time 18449684 ps
CPU time 0.79 seconds
Started Jun 30 06:59:57 PM PDT 24
Finished Jun 30 07:00:05 PM PDT 24
Peak memory 206520 kb
Host smart-d2e886d3-ce99-417a-8b6d-3fdc5b0097be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405708704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2405708704
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3099593984
Short name T624
Test name
Test status
Simulation time 65463355187 ps
CPU time 357.82 seconds
Started Jun 30 07:00:05 PM PDT 24
Finished Jun 30 07:06:10 PM PDT 24
Peak memory 256308 kb
Host smart-ee41ca2e-76c3-4239-a190-15ec21cd4612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099593984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3099593984
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3458508738
Short name T256
Test name
Test status
Simulation time 35814388083 ps
CPU time 348.2 seconds
Started Jun 30 07:00:02 PM PDT 24
Finished Jun 30 07:05:57 PM PDT 24
Peak memory 273464 kb
Host smart-632f5a1b-e140-4ee4-9f57-10d622565676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458508738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3458508738
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2769699293
Short name T912
Test name
Test status
Simulation time 456494342984 ps
CPU time 380.85 seconds
Started Jun 30 07:00:05 PM PDT 24
Finished Jun 30 07:06:33 PM PDT 24
Peak memory 273836 kb
Host smart-254dc248-e7f2-4f4f-b570-c7a69795a02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769699293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2769699293
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1648721529
Short name T656
Test name
Test status
Simulation time 455462945 ps
CPU time 4.14 seconds
Started Jun 30 07:00:01 PM PDT 24
Finished Jun 30 07:00:12 PM PDT 24
Peak memory 224416 kb
Host smart-a2f346d8-89a7-4341-8b39-304cb88b317d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648721529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1648721529
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3127098823
Short name T900
Test name
Test status
Simulation time 3489376784 ps
CPU time 36.69 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:42 PM PDT 24
Peak memory 249208 kb
Host smart-57f41bfd-a26c-4e00-b6a0-67878f0a04fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127098823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3127098823
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.575902049
Short name T911
Test name
Test status
Simulation time 542069081 ps
CPU time 4.33 seconds
Started Jun 30 07:00:01 PM PDT 24
Finished Jun 30 07:00:12 PM PDT 24
Peak memory 232676 kb
Host smart-e4baef4b-c5d7-41e6-89a0-95222214e197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575902049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.575902049
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2765269344
Short name T778
Test name
Test status
Simulation time 481636680 ps
CPU time 12.03 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:18 PM PDT 24
Peak memory 232668 kb
Host smart-81440cc8-e8de-4c57-844a-dd48bacc4225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765269344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2765269344
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2409821757
Short name T775
Test name
Test status
Simulation time 11739519330 ps
CPU time 11.59 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:17 PM PDT 24
Peak memory 232804 kb
Host smart-28461a80-bc2f-4a95-a59e-709ad4995253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409821757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2409821757
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1150919270
Short name T133
Test name
Test status
Simulation time 7360146499 ps
CPU time 23.36 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:29 PM PDT 24
Peak memory 240384 kb
Host smart-97d54923-e92d-4d1e-b1d2-13fcf2de999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150919270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1150919270
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2248224600
Short name T357
Test name
Test status
Simulation time 1368464052 ps
CPU time 4.3 seconds
Started Jun 30 07:00:02 PM PDT 24
Finished Jun 30 07:00:13 PM PDT 24
Peak memory 218704 kb
Host smart-b2ce5b02-a8ea-4649-b058-9cf607476003
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2248224600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2248224600
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.700454081
Short name T793
Test name
Test status
Simulation time 81334659 ps
CPU time 0.93 seconds
Started Jun 30 07:00:02 PM PDT 24
Finished Jun 30 07:00:10 PM PDT 24
Peak memory 206544 kb
Host smart-f6d7637a-df7b-4fd5-bda0-750269e671b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700454081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.700454081
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2557658506
Short name T840
Test name
Test status
Simulation time 2062963368 ps
CPU time 14.68 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:21 PM PDT 24
Peak memory 216320 kb
Host smart-14307894-67ca-4946-9b51-5a0e18a08876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557658506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2557658506
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2788707465
Short name T797
Test name
Test status
Simulation time 34693588 ps
CPU time 0.72 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:06 PM PDT 24
Peak memory 205660 kb
Host smart-2a1de914-3372-485f-8f11-d7a610c61638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788707465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2788707465
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2904309118
Short name T336
Test name
Test status
Simulation time 466628669 ps
CPU time 1.36 seconds
Started Jun 30 06:59:58 PM PDT 24
Finished Jun 30 07:00:06 PM PDT 24
Peak memory 215988 kb
Host smart-357bc7c2-c4d3-41b9-97c2-166d32959132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904309118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2904309118
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2570987730
Short name T864
Test name
Test status
Simulation time 17008997 ps
CPU time 0.72 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:07 PM PDT 24
Peak memory 205576 kb
Host smart-280008f3-ee6a-4ea5-a073-e9c813ea2856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570987730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2570987730
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2931499728
Short name T850
Test name
Test status
Simulation time 2319224562 ps
CPU time 4.79 seconds
Started Jun 30 06:59:59 PM PDT 24
Finished Jun 30 07:00:11 PM PDT 24
Peak memory 224600 kb
Host smart-f78d2ae5-9349-4da3-9309-85a6f57a9dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931499728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2931499728
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1182065592
Short name T598
Test name
Test status
Simulation time 13101981 ps
CPU time 0.74 seconds
Started Jun 30 07:00:05 PM PDT 24
Finished Jun 30 07:00:13 PM PDT 24
Peak memory 205436 kb
Host smart-96d7fede-e6a7-48c4-9bcb-1435c4f8423e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182065592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1182065592
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3646103044
Short name T957
Test name
Test status
Simulation time 122797436 ps
CPU time 2.81 seconds
Started Jun 30 07:00:06 PM PDT 24
Finished Jun 30 07:00:15 PM PDT 24
Peak memory 224452 kb
Host smart-0d35e393-a2ff-4aa8-97e2-fcbd13b8522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646103044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3646103044
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.826227934
Short name T829
Test name
Test status
Simulation time 44127400 ps
CPU time 0.77 seconds
Started Jun 30 07:00:05 PM PDT 24
Finished Jun 30 07:00:13 PM PDT 24
Peak memory 205536 kb
Host smart-cf25bf70-97f9-450f-a015-e2a4f33ce6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826227934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.826227934
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1516371969
Short name T713
Test name
Test status
Simulation time 4440615162 ps
CPU time 60.64 seconds
Started Jun 30 07:00:04 PM PDT 24
Finished Jun 30 07:01:12 PM PDT 24
Peak memory 249212 kb
Host smart-dad2d719-6e3e-469f-b353-f276a040c6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516371969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1516371969
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1765319772
Short name T798
Test name
Test status
Simulation time 3865152587 ps
CPU time 52.49 seconds
Started Jun 30 07:00:04 PM PDT 24
Finished Jun 30 07:01:03 PM PDT 24
Peak memory 249844 kb
Host smart-281a945d-307c-430c-b7e2-e839adb3a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765319772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1765319772
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.639703445
Short name T71
Test name
Test status
Simulation time 1253296433 ps
CPU time 6.62 seconds
Started Jun 30 07:00:06 PM PDT 24
Finished Jun 30 07:00:19 PM PDT 24
Peak memory 224328 kb
Host smart-32b6d1c6-17d0-485f-96a1-17e42bf734af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639703445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.639703445
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3572605811
Short name T94
Test name
Test status
Simulation time 20811624886 ps
CPU time 130.85 seconds
Started Jun 30 07:00:04 PM PDT 24
Finished Jun 30 07:02:22 PM PDT 24
Peak memory 268996 kb
Host smart-f8d9a1aa-01b5-4fdd-92e7-475e48abe95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572605811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3572605811
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2741095662
Short name T633
Test name
Test status
Simulation time 822120484 ps
CPU time 4.94 seconds
Started Jun 30 07:00:06 PM PDT 24
Finished Jun 30 07:00:18 PM PDT 24
Peak memory 232596 kb
Host smart-e3f67b68-a70d-4289-b015-88dceb3516c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741095662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2741095662
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.235222248
Short name T1021
Test name
Test status
Simulation time 5889154573 ps
CPU time 48.24 seconds
Started Jun 30 07:00:05 PM PDT 24
Finished Jun 30 07:00:59 PM PDT 24
Peak memory 232780 kb
Host smart-ae60b859-501a-4065-9dae-c2ef699f7193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235222248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.235222248
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2748666904
Short name T27
Test name
Test status
Simulation time 20028273273 ps
CPU time 17.16 seconds
Started Jun 30 07:00:04 PM PDT 24
Finished Jun 30 07:00:27 PM PDT 24
Peak memory 224588 kb
Host smart-a8788c3b-19fd-4999-9e5a-c349224bdd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748666904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2748666904
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3037550729
Short name T446
Test name
Test status
Simulation time 5822366567 ps
CPU time 16.21 seconds
Started Jun 30 07:00:05 PM PDT 24
Finished Jun 30 07:00:27 PM PDT 24
Peak memory 224580 kb
Host smart-ae38449d-f5ec-4557-802a-a943ad62d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037550729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3037550729
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3333957350
Short name T920
Test name
Test status
Simulation time 218316651 ps
CPU time 4.02 seconds
Started Jun 30 07:00:04 PM PDT 24
Finished Jun 30 07:00:15 PM PDT 24
Peak memory 219236 kb
Host smart-0b5a8a2b-9853-4634-a225-7b50b804ca70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3333957350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3333957350
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.996450821
Short name T51
Test name
Test status
Simulation time 2392824510 ps
CPU time 20.75 seconds
Started Jun 30 07:00:03 PM PDT 24
Finished Jun 30 07:00:30 PM PDT 24
Peak memory 216692 kb
Host smart-b02719d5-c9d7-46be-833c-f836d923e8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996450821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.996450821
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2401132727
Short name T596
Test name
Test status
Simulation time 1112597988 ps
CPU time 5.88 seconds
Started Jun 30 07:00:06 PM PDT 24
Finished Jun 30 07:00:18 PM PDT 24
Peak memory 216164 kb
Host smart-b0b32700-5102-46a2-8e5a-17d6c93deb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401132727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2401132727
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3750710373
Short name T666
Test name
Test status
Simulation time 499517272 ps
CPU time 4.26 seconds
Started Jun 30 07:00:06 PM PDT 24
Finished Jun 30 07:00:17 PM PDT 24
Peak memory 216228 kb
Host smart-cc136421-af6f-48e9-a966-a16b4aa084ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750710373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3750710373
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2197618783
Short name T442
Test name
Test status
Simulation time 73590514 ps
CPU time 0.8 seconds
Started Jun 30 07:00:05 PM PDT 24
Finished Jun 30 07:00:13 PM PDT 24
Peak memory 205896 kb
Host smart-7917bfc2-ae8f-49de-a41a-a23aea5e77df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197618783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2197618783
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1025600256
Short name T814
Test name
Test status
Simulation time 524326566 ps
CPU time 6.54 seconds
Started Jun 30 07:00:02 PM PDT 24
Finished Jun 30 07:00:15 PM PDT 24
Peak memory 224388 kb
Host smart-1117f562-a432-4cd5-ba47-f491222b411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025600256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1025600256
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1489810953
Short name T346
Test name
Test status
Simulation time 22457281 ps
CPU time 0.7 seconds
Started Jun 30 07:00:08 PM PDT 24
Finished Jun 30 07:00:15 PM PDT 24
Peak memory 205396 kb
Host smart-18e53e49-4cfb-47ef-947a-bcf205a0362a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489810953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1489810953
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1520979980
Short name T620
Test name
Test status
Simulation time 1155517111 ps
CPU time 2.65 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:18 PM PDT 24
Peak memory 224392 kb
Host smart-a342c2be-3595-4d4a-97ce-88356a656213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520979980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1520979980
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3457233196
Short name T686
Test name
Test status
Simulation time 28437751 ps
CPU time 0.78 seconds
Started Jun 30 07:00:04 PM PDT 24
Finished Jun 30 07:00:11 PM PDT 24
Peak memory 206892 kb
Host smart-7db7f5d7-4da9-4bc9-b67b-cfa1420712e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457233196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3457233196
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.937001188
Short name T347
Test name
Test status
Simulation time 199536344 ps
CPU time 5.12 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:21 PM PDT 24
Peak memory 236292 kb
Host smart-213d8a73-b4f4-4083-945c-32b671e76df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937001188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.937001188
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2861495624
Short name T232
Test name
Test status
Simulation time 143607990695 ps
CPU time 227.56 seconds
Started Jun 30 07:00:10 PM PDT 24
Finished Jun 30 07:04:04 PM PDT 24
Peak memory 264536 kb
Host smart-5bc5bf8a-aaa8-4924-ae13-e24916206a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861495624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2861495624
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3561117968
Short name T378
Test name
Test status
Simulation time 2357967712 ps
CPU time 13.8 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:29 PM PDT 24
Peak memory 232804 kb
Host smart-76072636-b9ff-4ef3-83c7-bba1272278bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561117968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3561117968
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.701821691
Short name T727
Test name
Test status
Simulation time 11055089308 ps
CPU time 140.7 seconds
Started Jun 30 07:00:08 PM PDT 24
Finished Jun 30 07:02:35 PM PDT 24
Peak memory 265504 kb
Host smart-2f7ce737-2b14-4354-9ba0-08ac9e14891d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701821691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.701821691
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2399874946
Short name T241
Test name
Test status
Simulation time 135406700 ps
CPU time 2.76 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:18 PM PDT 24
Peak memory 224408 kb
Host smart-1c09457c-e626-4060-92df-d1d43247b443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399874946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2399874946
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4258989614
Short name T169
Test name
Test status
Simulation time 1432296823 ps
CPU time 14.59 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:30 PM PDT 24
Peak memory 233140 kb
Host smart-67c48135-941b-4ce2-8e3e-bc9575e3cff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258989614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4258989614
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2548421606
Short name T372
Test name
Test status
Simulation time 4963226069 ps
CPU time 5.17 seconds
Started Jun 30 07:00:11 PM PDT 24
Finished Jun 30 07:00:22 PM PDT 24
Peak memory 224556 kb
Host smart-7fec0d02-011b-43c8-889a-14622b56685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548421606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2548421606
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2880777411
Short name T548
Test name
Test status
Simulation time 19096945657 ps
CPU time 13.86 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:29 PM PDT 24
Peak memory 224628 kb
Host smart-d93c5030-fcf0-4c36-aaf3-3b245883f8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880777411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2880777411
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2625439168
Short name T800
Test name
Test status
Simulation time 5764585200 ps
CPU time 16 seconds
Started Jun 30 07:00:10 PM PDT 24
Finished Jun 30 07:00:32 PM PDT 24
Peak memory 223028 kb
Host smart-4655a154-f3c0-4c0c-b7f1-892821e46d6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2625439168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2625439168
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3622220500
Short name T146
Test name
Test status
Simulation time 8482602194 ps
CPU time 143.33 seconds
Started Jun 30 07:00:08 PM PDT 24
Finished Jun 30 07:02:38 PM PDT 24
Peak memory 257420 kb
Host smart-82f5cfb6-81a4-496c-ab2f-bd82cfc8ec4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622220500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3622220500
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1415374602
Short name T1027
Test name
Test status
Simulation time 3142425230 ps
CPU time 27.69 seconds
Started Jun 30 07:00:05 PM PDT 24
Finished Jun 30 07:00:39 PM PDT 24
Peak memory 220188 kb
Host smart-75c255da-cd0e-4bd4-a864-41eba1a55c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415374602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1415374602
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2622480691
Short name T926
Test name
Test status
Simulation time 1989920040 ps
CPU time 2.58 seconds
Started Jun 30 07:00:04 PM PDT 24
Finished Jun 30 07:00:14 PM PDT 24
Peak memory 216184 kb
Host smart-34ba1fdb-8e93-4e48-b175-7bda31a528bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622480691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2622480691
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.882335811
Short name T907
Test name
Test status
Simulation time 146569881 ps
CPU time 4.59 seconds
Started Jun 30 07:00:10 PM PDT 24
Finished Jun 30 07:00:21 PM PDT 24
Peak memory 216232 kb
Host smart-4eda256c-b75e-43c6-843d-c43ac80408d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882335811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.882335811
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.418819918
Short name T611
Test name
Test status
Simulation time 50671589 ps
CPU time 0.85 seconds
Started Jun 30 07:00:12 PM PDT 24
Finished Jun 30 07:00:18 PM PDT 24
Peak memory 205880 kb
Host smart-7ff36ee2-4fa5-458d-abd9-25b4d6497dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418819918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.418819918
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3213363558
Short name T496
Test name
Test status
Simulation time 10930500719 ps
CPU time 30 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:45 PM PDT 24
Peak memory 232792 kb
Host smart-677d2a5f-63c9-412d-8924-55355222a699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213363558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3213363558
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3437248082
Short name T1016
Test name
Test status
Simulation time 24283862 ps
CPU time 0.7 seconds
Started Jun 30 07:00:14 PM PDT 24
Finished Jun 30 07:00:20 PM PDT 24
Peak memory 205392 kb
Host smart-1d27cc0f-b3f6-4fe7-b75a-733becdbf5e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437248082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3437248082
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3122243828
Short name T580
Test name
Test status
Simulation time 564927108 ps
CPU time 2.26 seconds
Started Jun 30 07:00:15 PM PDT 24
Finished Jun 30 07:00:22 PM PDT 24
Peak memory 232660 kb
Host smart-cd710d8d-e0ed-4619-8aec-48640e5a7dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122243828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3122243828
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2659572261
Short name T463
Test name
Test status
Simulation time 19928903 ps
CPU time 0.8 seconds
Started Jun 30 07:00:11 PM PDT 24
Finished Jun 30 07:00:18 PM PDT 24
Peak memory 206556 kb
Host smart-fbb706a1-1c8b-41c2-9bcd-d9f40f482caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659572261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2659572261
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3345425662
Short name T264
Test name
Test status
Simulation time 63313523043 ps
CPU time 216.19 seconds
Started Jun 30 07:00:13 PM PDT 24
Finished Jun 30 07:03:55 PM PDT 24
Peak memory 257040 kb
Host smart-656a4d33-9715-4d4a-a1e1-902d01164b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345425662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3345425662
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2385573395
Short name T537
Test name
Test status
Simulation time 6326212515 ps
CPU time 24.98 seconds
Started Jun 30 07:00:17 PM PDT 24
Finished Jun 30 07:00:46 PM PDT 24
Peak memory 254460 kb
Host smart-b5fb11d5-490f-4445-b601-3722f25a64d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385573395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2385573395
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.99291167
Short name T267
Test name
Test status
Simulation time 86882510226 ps
CPU time 373.47 seconds
Started Jun 30 07:00:17 PM PDT 24
Finished Jun 30 07:06:34 PM PDT 24
Peak memory 250036 kb
Host smart-8187210a-86ec-494f-8897-948e6dcf56ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99291167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.99291167
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1539003242
Short name T286
Test name
Test status
Simulation time 178142801 ps
CPU time 7.25 seconds
Started Jun 30 07:00:14 PM PDT 24
Finished Jun 30 07:00:26 PM PDT 24
Peak memory 232680 kb
Host smart-1250c7d0-78a1-409f-b196-352f1812ca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539003242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1539003242
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1137827245
Short name T640
Test name
Test status
Simulation time 294584801317 ps
CPU time 199.77 seconds
Started Jun 30 07:00:15 PM PDT 24
Finished Jun 30 07:03:40 PM PDT 24
Peak memory 251304 kb
Host smart-03a06ab7-f665-43b3-b5a2-5aae2af27cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137827245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1137827245
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.839233718
Short name T226
Test name
Test status
Simulation time 1354157832 ps
CPU time 14.13 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:30 PM PDT 24
Peak memory 232644 kb
Host smart-a51f923e-9ebf-4799-a36c-65c6fc5a261e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839233718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.839233718
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1502555164
Short name T939
Test name
Test status
Simulation time 17021349399 ps
CPU time 46.33 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:01:02 PM PDT 24
Peak memory 232756 kb
Host smart-a3779a33-cfc5-440f-b8b6-9a336ca142ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502555164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1502555164
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.499920127
Short name T55
Test name
Test status
Simulation time 5118782436 ps
CPU time 8.92 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:24 PM PDT 24
Peak memory 240636 kb
Host smart-519d08fd-bfe9-4264-9dfb-47e64b9328a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499920127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.499920127
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2845573806
Short name T592
Test name
Test status
Simulation time 293693593 ps
CPU time 3.16 seconds
Started Jun 30 07:00:10 PM PDT 24
Finished Jun 30 07:00:19 PM PDT 24
Peak memory 232864 kb
Host smart-6643d48f-7c16-49aa-a1d9-5e2ffffbf1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845573806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2845573806
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1653582680
Short name T395
Test name
Test status
Simulation time 1555870421 ps
CPU time 9.45 seconds
Started Jun 30 07:00:15 PM PDT 24
Finished Jun 30 07:00:29 PM PDT 24
Peak memory 218688 kb
Host smart-3b9c98b3-4c2b-4ec0-bedf-a479a01bf376
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1653582680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1653582680
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3628080598
Short name T142
Test name
Test status
Simulation time 29138638910 ps
CPU time 198.25 seconds
Started Jun 30 07:00:16 PM PDT 24
Finished Jun 30 07:03:39 PM PDT 24
Peak memory 254456 kb
Host smart-37147d23-590e-4b43-b5b9-c01fd03f43c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628080598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3628080598
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2670817034
Short name T515
Test name
Test status
Simulation time 21698891008 ps
CPU time 8.89 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:24 PM PDT 24
Peak memory 216752 kb
Host smart-27f61f78-999c-4e78-960f-1d074793df85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670817034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2670817034
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1612750074
Short name T321
Test name
Test status
Simulation time 38476266 ps
CPU time 0.74 seconds
Started Jun 30 07:00:10 PM PDT 24
Finished Jun 30 07:00:17 PM PDT 24
Peak memory 205696 kb
Host smart-29ba416a-18b6-4562-9193-d6ff28dfe5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612750074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1612750074
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2549738765
Short name T403
Test name
Test status
Simulation time 370333830 ps
CPU time 1.56 seconds
Started Jun 30 07:00:09 PM PDT 24
Finished Jun 30 07:00:17 PM PDT 24
Peak memory 216244 kb
Host smart-14886965-99ca-4a37-9e2f-3a0e8530fc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549738765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2549738765
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1891633883
Short name T466
Test name
Test status
Simulation time 171080571 ps
CPU time 0.91 seconds
Started Jun 30 07:00:11 PM PDT 24
Finished Jun 30 07:00:18 PM PDT 24
Peak memory 205888 kb
Host smart-5fb51d62-2c3a-4824-a12f-356c4e0c747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891633883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1891633883
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1145305899
Short name T550
Test name
Test status
Simulation time 8043696532 ps
CPU time 7.64 seconds
Started Jun 30 07:00:14 PM PDT 24
Finished Jun 30 07:00:27 PM PDT 24
Peak memory 232756 kb
Host smart-2301c4c9-493c-4bb4-8dfa-211c259282c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145305899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1145305899
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1755373324
Short name T420
Test name
Test status
Simulation time 36078113 ps
CPU time 0.74 seconds
Started Jun 30 07:00:22 PM PDT 24
Finished Jun 30 07:00:23 PM PDT 24
Peak memory 205460 kb
Host smart-4133240a-52f7-4cab-b5b6-56a6c85c90a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755373324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1755373324
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.79634131
Short name T92
Test name
Test status
Simulation time 303484600 ps
CPU time 4.27 seconds
Started Jun 30 07:00:21 PM PDT 24
Finished Jun 30 07:00:27 PM PDT 24
Peak memory 224484 kb
Host smart-75c0cb2c-979a-4523-9aa9-4d57d4e9707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79634131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.79634131
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3478513239
Short name T1022
Test name
Test status
Simulation time 73163633 ps
CPU time 0.8 seconds
Started Jun 30 07:00:16 PM PDT 24
Finished Jun 30 07:00:22 PM PDT 24
Peak memory 206516 kb
Host smart-b910542b-f9bd-469a-b34a-349fafbfe42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478513239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3478513239
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.338673509
Short name T846
Test name
Test status
Simulation time 87573538 ps
CPU time 0.81 seconds
Started Jun 30 07:00:21 PM PDT 24
Finished Jun 30 07:00:23 PM PDT 24
Peak memory 215972 kb
Host smart-38ce7078-3f89-45cf-96d3-98753d684191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338673509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.338673509
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2224535279
Short name T660
Test name
Test status
Simulation time 11358242506 ps
CPU time 34.07 seconds
Started Jun 30 07:00:20 PM PDT 24
Finished Jun 30 07:00:56 PM PDT 24
Peak memory 217664 kb
Host smart-74fb074c-c92b-4001-8124-24099ba4fdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224535279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2224535279
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.636637176
Short name T783
Test name
Test status
Simulation time 386045263 ps
CPU time 5.48 seconds
Started Jun 30 07:00:20 PM PDT 24
Finished Jun 30 07:00:27 PM PDT 24
Peak memory 232680 kb
Host smart-cad0c8a7-b41b-4dfe-892a-4ac1980585af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636637176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.636637176
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1314495169
Short name T568
Test name
Test status
Simulation time 78474847823 ps
CPU time 139.64 seconds
Started Jun 30 07:00:28 PM PDT 24
Finished Jun 30 07:02:50 PM PDT 24
Peak memory 249148 kb
Host smart-3a198b28-410c-4e12-94b2-2bc0242dd78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314495169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1314495169
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3451482091
Short name T708
Test name
Test status
Simulation time 202034416 ps
CPU time 4.33 seconds
Started Jun 30 07:00:17 PM PDT 24
Finished Jun 30 07:00:25 PM PDT 24
Peak memory 224684 kb
Host smart-40ac22d1-45fd-4c33-8c86-d511bd0856d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451482091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3451482091
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.545234989
Short name T376
Test name
Test status
Simulation time 18439810148 ps
CPU time 34.26 seconds
Started Jun 30 07:00:14 PM PDT 24
Finished Jun 30 07:00:53 PM PDT 24
Peak memory 232728 kb
Host smart-2179edfd-4618-4bf0-8fa2-04523cb1eaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545234989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.545234989
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.813324837
Short name T779
Test name
Test status
Simulation time 32746721 ps
CPU time 2.43 seconds
Started Jun 30 07:00:14 PM PDT 24
Finished Jun 30 07:00:22 PM PDT 24
Peak memory 232380 kb
Host smart-d69931c0-eed7-4405-b3b3-38195f802df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813324837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.813324837
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.290577987
Short name T1004
Test name
Test status
Simulation time 183904183 ps
CPU time 2.64 seconds
Started Jun 30 07:00:14 PM PDT 24
Finished Jun 30 07:00:22 PM PDT 24
Peak memory 224496 kb
Host smart-66dac1bf-a8ff-4b38-88bd-faa015355416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290577987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.290577987
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2168899916
Short name T520
Test name
Test status
Simulation time 173681494 ps
CPU time 3.83 seconds
Started Jun 30 07:00:20 PM PDT 24
Finished Jun 30 07:00:26 PM PDT 24
Peak memory 219220 kb
Host smart-36907652-a019-457a-b6d0-2485714f2019
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2168899916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2168899916
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3613740943
Short name T490
Test name
Test status
Simulation time 3420590678 ps
CPU time 25.41 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:55 PM PDT 24
Peak memory 232800 kb
Host smart-9b8de57a-3fd4-41da-8d4f-8cad19da7ea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613740943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3613740943
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2178189345
Short name T740
Test name
Test status
Simulation time 33188115437 ps
CPU time 48.96 seconds
Started Jun 30 07:00:14 PM PDT 24
Finished Jun 30 07:01:08 PM PDT 24
Peak memory 216360 kb
Host smart-84f5893d-827f-4620-b570-8469b9245d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178189345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2178189345
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3222269927
Short name T621
Test name
Test status
Simulation time 8685254813 ps
CPU time 6.03 seconds
Started Jun 30 07:00:17 PM PDT 24
Finished Jun 30 07:00:27 PM PDT 24
Peak memory 216272 kb
Host smart-29d4c8f4-941b-441b-b301-81f1b7b2e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222269927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3222269927
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2495694333
Short name T313
Test name
Test status
Simulation time 150235624 ps
CPU time 1.05 seconds
Started Jun 30 07:00:14 PM PDT 24
Finished Jun 30 07:00:20 PM PDT 24
Peak memory 207888 kb
Host smart-04962a12-a5a1-4647-acc4-d7d5a935d9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495694333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2495694333
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.98766776
Short name T513
Test name
Test status
Simulation time 143792087 ps
CPU time 0.86 seconds
Started Jun 30 07:00:15 PM PDT 24
Finished Jun 30 07:00:21 PM PDT 24
Peak memory 205892 kb
Host smart-5b8bf3fc-32fc-48bd-9ea6-7eb9c6609ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98766776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.98766776
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2425080419
Short name T781
Test name
Test status
Simulation time 108673192 ps
CPU time 2.47 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:33 PM PDT 24
Peak memory 224096 kb
Host smart-d5ea9730-8aa7-4d95-ade3-86f2b0de9de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425080419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2425080419
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3130680732
Short name T707
Test name
Test status
Simulation time 35131584 ps
CPU time 0.69 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:58:44 PM PDT 24
Peak memory 205412 kb
Host smart-ef4285d9-5453-404a-b286-5b13aed3659f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130680732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
130680732
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2162994935
Short name T238
Test name
Test status
Simulation time 230118183 ps
CPU time 2.41 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:58:45 PM PDT 24
Peak memory 224440 kb
Host smart-a838645e-d1f0-4979-bc90-5f0dd7950e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162994935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2162994935
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3453213427
Short name T75
Test name
Test status
Simulation time 20638515 ps
CPU time 0.85 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 06:58:46 PM PDT 24
Peak memory 206560 kb
Host smart-3f321b71-55d8-44aa-90fb-94b4ee11233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453213427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3453213427
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.508237447
Short name T412
Test name
Test status
Simulation time 35262942512 ps
CPU time 50.61 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 06:59:35 PM PDT 24
Peak memory 249164 kb
Host smart-aeb6e3f9-cf70-4473-9c43-daf56fc17c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508237447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.508237447
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.260297611
Short name T49
Test name
Test status
Simulation time 49348553411 ps
CPU time 86.61 seconds
Started Jun 30 06:58:44 PM PDT 24
Finished Jun 30 07:00:12 PM PDT 24
Peak memory 241036 kb
Host smart-e0c76f86-7636-4fe0-aafe-b363547617f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260297611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.260297611
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3453175215
Short name T48
Test name
Test status
Simulation time 47844553350 ps
CPU time 423.19 seconds
Started Jun 30 06:58:44 PM PDT 24
Finished Jun 30 07:05:48 PM PDT 24
Peak memory 251768 kb
Host smart-fdfe29ad-35f2-4018-8d91-6070e654ea50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453175215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3453175215
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2006597664
Short name T319
Test name
Test status
Simulation time 606035566 ps
CPU time 4.84 seconds
Started Jun 30 06:58:40 PM PDT 24
Finished Jun 30 06:58:45 PM PDT 24
Peak memory 232676 kb
Host smart-56ccdbe8-1b2a-4a8f-b4dc-ef89b275f2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006597664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2006597664
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.923303199
Short name T397
Test name
Test status
Simulation time 4815465874 ps
CPU time 26.66 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:59:10 PM PDT 24
Peak memory 235664 kb
Host smart-39936041-9a88-4434-856f-606dd0738a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923303199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
923303199
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2866704709
Short name T228
Test name
Test status
Simulation time 2120098942 ps
CPU time 15.71 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 06:59:00 PM PDT 24
Peak memory 224472 kb
Host smart-936d90c1-44f8-4530-9122-85ce8bb9b55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866704709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2866704709
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.817146782
Short name T936
Test name
Test status
Simulation time 262476825 ps
CPU time 3.04 seconds
Started Jun 30 06:58:45 PM PDT 24
Finished Jun 30 06:58:50 PM PDT 24
Peak memory 232636 kb
Host smart-997c9024-2847-4bcf-9bc7-f448bf105742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817146782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.817146782
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2842236688
Short name T36
Test name
Test status
Simulation time 187336651 ps
CPU time 1.04 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:58:44 PM PDT 24
Peak memory 218104 kb
Host smart-fbd41079-aefb-4904-9ce6-37a90d429fe9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842236688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2842236688
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3045872451
Short name T817
Test name
Test status
Simulation time 12952866740 ps
CPU time 4.74 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 06:58:49 PM PDT 24
Peak memory 224568 kb
Host smart-0aea9acd-b53b-4144-b2c2-062df4b05ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045872451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3045872451
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3806683405
Short name T456
Test name
Test status
Simulation time 2525092223 ps
CPU time 9.7 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 06:58:54 PM PDT 24
Peak memory 232800 kb
Host smart-3e3e43d7-9681-4481-8dd0-a5cbb1133b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806683405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3806683405
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2319583700
Short name T543
Test name
Test status
Simulation time 1457321870 ps
CPU time 4.99 seconds
Started Jun 30 06:58:41 PM PDT 24
Finished Jun 30 06:58:46 PM PDT 24
Peak memory 222532 kb
Host smart-009bc00d-0102-40dd-b11d-c0732881600d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2319583700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2319583700
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.368915959
Short name T66
Test name
Test status
Simulation time 94127460 ps
CPU time 1.21 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:58:45 PM PDT 24
Peak memory 235568 kb
Host smart-d9d56a1a-0da8-4412-8ee4-08c878a824dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368915959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.368915959
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2871525681
Short name T29
Test name
Test status
Simulation time 26248873445 ps
CPU time 50.66 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 06:59:35 PM PDT 24
Peak memory 249220 kb
Host smart-706225b6-f0ff-4d5f-98bb-77b7e5390cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871525681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2871525681
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3214932496
Short name T387
Test name
Test status
Simulation time 3773882648 ps
CPU time 21.94 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 06:59:06 PM PDT 24
Peak memory 216296 kb
Host smart-61e51c66-2ee5-4f5d-9de6-eb335c35ca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214932496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3214932496
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.118685371
Short name T415
Test name
Test status
Simulation time 1892382213 ps
CPU time 2.15 seconds
Started Jun 30 06:58:44 PM PDT 24
Finished Jun 30 06:58:47 PM PDT 24
Peak memory 206960 kb
Host smart-296116ad-d579-4a14-835b-efca5124a365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118685371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.118685371
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2207190491
Short name T857
Test name
Test status
Simulation time 60611314 ps
CPU time 1.07 seconds
Started Jun 30 06:58:45 PM PDT 24
Finished Jun 30 06:58:47 PM PDT 24
Peak memory 207676 kb
Host smart-a4ce2020-65ef-4c1e-818f-4c0ae1b9d774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207190491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2207190491
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1872979884
Short name T379
Test name
Test status
Simulation time 59708862 ps
CPU time 0.74 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 06:58:48 PM PDT 24
Peak memory 205920 kb
Host smart-1b1f5ecf-1ab3-48c2-bf42-d91ed8766b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872979884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1872979884
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1537744956
Short name T203
Test name
Test status
Simulation time 4547708226 ps
CPU time 4.37 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:58:47 PM PDT 24
Peak memory 224428 kb
Host smart-24fbcd51-2cc0-4055-b29e-902d5e6fea55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537744956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1537744956
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1798185957
Short name T815
Test name
Test status
Simulation time 14287334 ps
CPU time 0.71 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:30 PM PDT 24
Peak memory 204828 kb
Host smart-f907cc00-b842-4822-a366-21ad1b309a69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798185957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1798185957
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2080077310
Short name T530
Test name
Test status
Simulation time 157273566 ps
CPU time 2.97 seconds
Started Jun 30 07:00:19 PM PDT 24
Finished Jun 30 07:00:24 PM PDT 24
Peak memory 232640 kb
Host smart-21f4fef9-314d-4473-84be-45beafec1dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080077310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2080077310
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3577966682
Short name T337
Test name
Test status
Simulation time 18298562 ps
CPU time 0.76 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:31 PM PDT 24
Peak memory 205512 kb
Host smart-798a31ae-f0c3-42aa-86a1-b8126989f6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577966682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3577966682
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3314377478
Short name T199
Test name
Test status
Simulation time 1221159544 ps
CPU time 23.41 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:52 PM PDT 24
Peak memory 235188 kb
Host smart-338c2876-77f3-47e1-8ff7-562abffda90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314377478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3314377478
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.937919068
Short name T465
Test name
Test status
Simulation time 2089045247 ps
CPU time 37.23 seconds
Started Jun 30 07:00:26 PM PDT 24
Finished Jun 30 07:01:05 PM PDT 24
Peak memory 254720 kb
Host smart-bbfa05a5-f513-483f-ae02-0595dafd1d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937919068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.937919068
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1564290494
Short name T589
Test name
Test status
Simulation time 12969151908 ps
CPU time 169.14 seconds
Started Jun 30 07:00:25 PM PDT 24
Finished Jun 30 07:03:15 PM PDT 24
Peak memory 267408 kb
Host smart-f42ba258-30f1-45be-ae9f-8467d7a9201d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564290494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1564290494
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3245823542
Short name T795
Test name
Test status
Simulation time 339903573 ps
CPU time 6.03 seconds
Started Jun 30 07:00:21 PM PDT 24
Finished Jun 30 07:00:28 PM PDT 24
Peak memory 232708 kb
Host smart-8355e2b7-a690-4f5b-a401-ee099d662ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245823542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3245823542
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3905202361
Short name T526
Test name
Test status
Simulation time 6119299005 ps
CPU time 17.84 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:47 PM PDT 24
Peak memory 218772 kb
Host smart-e5c5edd5-18ac-40a4-a270-f225e3c0e699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905202361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3905202361
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3318591229
Short name T564
Test name
Test status
Simulation time 137920464 ps
CPU time 2.54 seconds
Started Jun 30 07:00:24 PM PDT 24
Finished Jun 30 07:00:26 PM PDT 24
Peak memory 224436 kb
Host smart-e7811e0b-e9f0-4e42-ab08-014f5d133efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318591229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3318591229
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.85865737
Short name T296
Test name
Test status
Simulation time 31971541 ps
CPU time 2.18 seconds
Started Jun 30 07:00:20 PM PDT 24
Finished Jun 30 07:00:24 PM PDT 24
Peak memory 224232 kb
Host smart-e9f01a18-0593-47d2-8cf2-3316b1fcf568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85865737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.85865737
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.19093811
Short name T483
Test name
Test status
Simulation time 68954656848 ps
CPU time 41.07 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:01:11 PM PDT 24
Peak memory 232736 kb
Host smart-bce0504b-f30f-4ad3-b062-c3dcdfff1d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19093811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.19093811
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2466791557
Short name T904
Test name
Test status
Simulation time 267787979 ps
CPU time 5.46 seconds
Started Jun 30 07:00:24 PM PDT 24
Finished Jun 30 07:00:29 PM PDT 24
Peak memory 237248 kb
Host smart-425fce50-d21e-4c67-9cf2-d7dc3bdfd748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466791557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2466791557
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2230060978
Short name T445
Test name
Test status
Simulation time 174062259 ps
CPU time 3.87 seconds
Started Jun 30 07:00:26 PM PDT 24
Finished Jun 30 07:00:32 PM PDT 24
Peak memory 222908 kb
Host smart-dd50af3b-4683-412b-bc6e-85f31f377613
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2230060978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2230060978
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2864173314
Short name T167
Test name
Test status
Simulation time 11454035865 ps
CPU time 104.21 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:02:14 PM PDT 24
Peak memory 250648 kb
Host smart-f002259f-3fbc-41f0-860a-1b691978a19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864173314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2864173314
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2525279121
Short name T710
Test name
Test status
Simulation time 24438680871 ps
CPU time 34.01 seconds
Started Jun 30 07:00:20 PM PDT 24
Finished Jun 30 07:00:56 PM PDT 24
Peak memory 216368 kb
Host smart-2ee62247-7865-4ff2-983b-d50f82a1ae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525279121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2525279121
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.256939749
Short name T619
Test name
Test status
Simulation time 5302900664 ps
CPU time 13.93 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:43 PM PDT 24
Peak memory 216296 kb
Host smart-1b718f0c-1b79-432a-aa30-b7f8ca608753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256939749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.256939749
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1742216842
Short name T343
Test name
Test status
Simulation time 148263052 ps
CPU time 2.89 seconds
Started Jun 30 07:00:21 PM PDT 24
Finished Jun 30 07:00:25 PM PDT 24
Peak memory 216176 kb
Host smart-02563aec-d63a-433c-8100-96cb391e6d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742216842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1742216842
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4001621450
Short name T54
Test name
Test status
Simulation time 91007486 ps
CPU time 0.86 seconds
Started Jun 30 07:00:21 PM PDT 24
Finished Jun 30 07:00:23 PM PDT 24
Peak memory 205848 kb
Host smart-168eedc4-e383-4a4a-b5b4-ab490e152375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001621450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4001621450
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3086416613
Short name T754
Test name
Test status
Simulation time 1253998044 ps
CPU time 6.09 seconds
Started Jun 30 07:00:21 PM PDT 24
Finished Jun 30 07:00:29 PM PDT 24
Peak memory 232692 kb
Host smart-c7453878-e2b5-4f35-8938-4850da02a2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086416613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3086416613
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1394492500
Short name T61
Test name
Test status
Simulation time 81595269 ps
CPU time 0.77 seconds
Started Jun 30 07:00:33 PM PDT 24
Finished Jun 30 07:00:37 PM PDT 24
Peak memory 205784 kb
Host smart-50b46e26-8ec9-4f2d-a447-c644d17ec9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394492500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1394492500
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3216853853
Short name T510
Test name
Test status
Simulation time 553622637 ps
CPU time 5.02 seconds
Started Jun 30 07:00:25 PM PDT 24
Finished Jun 30 07:00:31 PM PDT 24
Peak memory 224436 kb
Host smart-de0ac7b7-52f4-411e-acdf-c29ed703c997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216853853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3216853853
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2510629057
Short name T436
Test name
Test status
Simulation time 62492794 ps
CPU time 0.76 seconds
Started Jun 30 07:00:25 PM PDT 24
Finished Jun 30 07:00:26 PM PDT 24
Peak memory 205528 kb
Host smart-ab85b041-c4d2-414f-8c67-b96bbce22617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510629057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2510629057
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2633757182
Short name T916
Test name
Test status
Simulation time 3036221097 ps
CPU time 41.26 seconds
Started Jun 30 07:00:26 PM PDT 24
Finished Jun 30 07:01:09 PM PDT 24
Peak memory 237664 kb
Host smart-faa0dd66-2240-4a0e-8268-f74e83893adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633757182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2633757182
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2510016414
Short name T730
Test name
Test status
Simulation time 37760555370 ps
CPU time 172.73 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:03:22 PM PDT 24
Peak memory 249188 kb
Host smart-6091c90b-ce72-4f21-adc2-4e7c1d973c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510016414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2510016414
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3610126237
Short name T505
Test name
Test status
Simulation time 6209078009 ps
CPU time 90.28 seconds
Started Jun 30 07:00:25 PM PDT 24
Finished Jun 30 07:01:56 PM PDT 24
Peak memory 249524 kb
Host smart-b1a180ea-c145-484a-8057-7225bf79c11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610126237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3610126237
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.934113542
Short name T650
Test name
Test status
Simulation time 460706303 ps
CPU time 9.88 seconds
Started Jun 30 07:00:26 PM PDT 24
Finished Jun 30 07:00:38 PM PDT 24
Peak memory 232680 kb
Host smart-61a203fe-4f0b-4f91-9dce-b8c9c5e4ff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934113542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.934113542
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3164888835
Short name T799
Test name
Test status
Simulation time 23336557130 ps
CPU time 163.14 seconds
Started Jun 30 07:00:25 PM PDT 24
Finished Jun 30 07:03:09 PM PDT 24
Peak memory 252860 kb
Host smart-d8da14d6-edf6-427b-9600-3ef53c031d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164888835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3164888835
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.23261312
Short name T481
Test name
Test status
Simulation time 328726334 ps
CPU time 5.45 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:35 PM PDT 24
Peak memory 232656 kb
Host smart-65545566-8a2d-4e42-9be9-4a41bf94b45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23261312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.23261312
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1773179142
Short name T677
Test name
Test status
Simulation time 370165716 ps
CPU time 5.82 seconds
Started Jun 30 07:00:25 PM PDT 24
Finished Jun 30 07:00:32 PM PDT 24
Peak memory 233692 kb
Host smart-ea790b8a-7a01-48e8-9ef1-be4a3546a768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773179142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1773179142
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.4159586634
Short name T895
Test name
Test status
Simulation time 1119766002 ps
CPU time 5.23 seconds
Started Jun 30 07:00:26 PM PDT 24
Finished Jun 30 07:00:33 PM PDT 24
Peak memory 232604 kb
Host smart-0257689c-ae7c-443d-ad0a-bc7b48fc45c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159586634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.4159586634
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4085478454
Short name T641
Test name
Test status
Simulation time 349548659 ps
CPU time 5.5 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:34 PM PDT 24
Peak memory 232640 kb
Host smart-2ded330e-b4e1-4bbf-ba19-34ef1bbc7a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085478454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4085478454
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.881683327
Short name T401
Test name
Test status
Simulation time 1824309632 ps
CPU time 7.09 seconds
Started Jun 30 07:00:25 PM PDT 24
Finished Jun 30 07:00:34 PM PDT 24
Peak memory 222276 kb
Host smart-30c8f8d6-b54b-4a6b-afd1-399176742749
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=881683327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.881683327
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.649011866
Short name T270
Test name
Test status
Simulation time 495620665881 ps
CPU time 615.48 seconds
Started Jun 30 07:00:25 PM PDT 24
Finished Jun 30 07:10:42 PM PDT 24
Peak memory 286048 kb
Host smart-a1fb811a-7967-419e-805f-ef93aa3163da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649011866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.649011866
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3960927156
Short name T535
Test name
Test status
Simulation time 19184541441 ps
CPU time 50.07 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:01:19 PM PDT 24
Peak memory 216252 kb
Host smart-75ef7f3c-6ef0-4410-af53-31b6bf7ac74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960927156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3960927156
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2211234888
Short name T433
Test name
Test status
Simulation time 36066928225 ps
CPU time 18.28 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:48 PM PDT 24
Peak memory 216292 kb
Host smart-3573f4f4-9b2c-42f2-ba0c-c9b4bae32d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211234888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2211234888
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.4012355368
Short name T468
Test name
Test status
Simulation time 64931426 ps
CPU time 0.97 seconds
Started Jun 30 07:00:26 PM PDT 24
Finished Jun 30 07:00:29 PM PDT 24
Peak memory 207072 kb
Host smart-f3cf8d70-6e9d-4b23-a57d-eb4c2658e22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012355368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4012355368
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2899966560
Short name T320
Test name
Test status
Simulation time 40967017 ps
CPU time 0.82 seconds
Started Jun 30 07:00:24 PM PDT 24
Finished Jun 30 07:00:26 PM PDT 24
Peak memory 205868 kb
Host smart-5bb19c8b-fde4-44eb-88a3-67620f583050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899966560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2899966560
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1601231372
Short name T825
Test name
Test status
Simulation time 59656328 ps
CPU time 2.3 seconds
Started Jun 30 07:00:27 PM PDT 24
Finished Jun 30 07:00:32 PM PDT 24
Peak memory 224492 kb
Host smart-e4c8e64d-4654-463e-b92f-15458ecaae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601231372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1601231372
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.416804194
Short name T453
Test name
Test status
Simulation time 16226278 ps
CPU time 0.7 seconds
Started Jun 30 07:00:37 PM PDT 24
Finished Jun 30 07:00:40 PM PDT 24
Peak memory 204836 kb
Host smart-c8214e7e-d047-452e-b7dc-e96e3288b65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416804194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.416804194
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3806021406
Short name T806
Test name
Test status
Simulation time 109298636 ps
CPU time 2.66 seconds
Started Jun 30 07:00:31 PM PDT 24
Finished Jun 30 07:00:37 PM PDT 24
Peak memory 232672 kb
Host smart-25788ac9-6e96-4e4f-ab03-325849c2c2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806021406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3806021406
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1693510601
Short name T517
Test name
Test status
Simulation time 17500857 ps
CPU time 0.8 seconds
Started Jun 30 07:00:31 PM PDT 24
Finished Jun 30 07:00:35 PM PDT 24
Peak memory 206892 kb
Host smart-9336ddd0-121f-4c0a-964c-a555571e9a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693510601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1693510601
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3395767607
Short name T276
Test name
Test status
Simulation time 36894449117 ps
CPU time 235.66 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:04:36 PM PDT 24
Peak memory 249500 kb
Host smart-62c3e5ea-ac67-4644-81a4-7ff9979e13d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395767607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3395767607
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2057048161
Short name T720
Test name
Test status
Simulation time 16304782482 ps
CPU time 146.5 seconds
Started Jun 30 07:00:39 PM PDT 24
Finished Jun 30 07:03:07 PM PDT 24
Peak memory 237912 kb
Host smart-d54eea60-88eb-482b-8f9b-da57f60e62ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057048161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2057048161
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3548582288
Short name T46
Test name
Test status
Simulation time 52761094896 ps
CPU time 100.61 seconds
Started Jun 30 07:00:40 PM PDT 24
Finished Jun 30 07:02:22 PM PDT 24
Peak memory 249200 kb
Host smart-c8e3014e-72ea-4cd3-a9ef-11907fdf7a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548582288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3548582288
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3335217508
Short name T414
Test name
Test status
Simulation time 815349275 ps
CPU time 20.12 seconds
Started Jun 30 07:00:34 PM PDT 24
Finished Jun 30 07:00:57 PM PDT 24
Peak memory 257232 kb
Host smart-7ffe1758-1f6a-4000-a9ef-5dc8021b633e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335217508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3335217508
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2060337337
Short name T989
Test name
Test status
Simulation time 87557572169 ps
CPU time 201.57 seconds
Started Jun 30 07:00:33 PM PDT 24
Finished Jun 30 07:03:58 PM PDT 24
Peak memory 262848 kb
Host smart-9660bb56-e6d3-420e-8836-2201e7ca9b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060337337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2060337337
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.269477893
Short name T398
Test name
Test status
Simulation time 1276013260 ps
CPU time 4.63 seconds
Started Jun 30 07:00:33 PM PDT 24
Finished Jun 30 07:00:41 PM PDT 24
Peak memory 224440 kb
Host smart-5f40a342-6a0c-4133-8ad9-1a16a043a704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269477893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.269477893
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4265733541
Short name T392
Test name
Test status
Simulation time 231752766 ps
CPU time 4.59 seconds
Started Jun 30 07:00:31 PM PDT 24
Finished Jun 30 07:00:39 PM PDT 24
Peak memory 232648 kb
Host smart-19282c1c-ee74-40cf-b9fe-5d5f7825f65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265733541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4265733541
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3450958252
Short name T736
Test name
Test status
Simulation time 285065287 ps
CPU time 4.15 seconds
Started Jun 30 07:00:31 PM PDT 24
Finished Jun 30 07:00:39 PM PDT 24
Peak memory 240460 kb
Host smart-efeb7bd6-919d-4c4d-805b-a386d9189c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450958252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3450958252
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1858400414
Short name T985
Test name
Test status
Simulation time 387202655 ps
CPU time 4.2 seconds
Started Jun 30 07:00:32 PM PDT 24
Finished Jun 30 07:00:39 PM PDT 24
Peak memory 232652 kb
Host smart-300a51af-87d2-454a-b868-b43a8512ab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858400414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1858400414
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1141327942
Short name T704
Test name
Test status
Simulation time 7658825626 ps
CPU time 20.61 seconds
Started Jun 30 07:00:31 PM PDT 24
Finished Jun 30 07:00:56 PM PDT 24
Peak memory 220616 kb
Host smart-a808146d-ce85-4861-898a-716bb86cbe24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1141327942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1141327942
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2036581574
Short name T599
Test name
Test status
Simulation time 301212044 ps
CPU time 1.2 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:00:42 PM PDT 24
Peak memory 206984 kb
Host smart-1f58916e-45e1-46e0-98dd-81750d265f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036581574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2036581574
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2729450216
Short name T441
Test name
Test status
Simulation time 38846713 ps
CPU time 0.75 seconds
Started Jun 30 07:00:33 PM PDT 24
Finished Jun 30 07:00:37 PM PDT 24
Peak memory 205680 kb
Host smart-004f7d77-9a01-48e7-bf64-aa8cad5f63e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729450216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2729450216
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1409877410
Short name T750
Test name
Test status
Simulation time 12205901672 ps
CPU time 16.63 seconds
Started Jun 30 07:00:32 PM PDT 24
Finished Jun 30 07:00:53 PM PDT 24
Peak memory 216280 kb
Host smart-adfff622-f9ff-4e3c-9d77-d1d17c27bf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409877410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1409877410
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3675652756
Short name T851
Test name
Test status
Simulation time 145681375 ps
CPU time 1.31 seconds
Started Jun 30 07:00:35 PM PDT 24
Finished Jun 30 07:00:39 PM PDT 24
Peak memory 216088 kb
Host smart-147473b6-e15c-45bf-bb74-1f9c1d61f988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675652756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3675652756
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.746510981
Short name T998
Test name
Test status
Simulation time 60879515 ps
CPU time 0.84 seconds
Started Jun 30 07:00:32 PM PDT 24
Finished Jun 30 07:00:37 PM PDT 24
Peak memory 205844 kb
Host smart-00c4fd35-844f-4474-885e-10a4b9da305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746510981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.746510981
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1063361303
Short name T344
Test name
Test status
Simulation time 1220156721 ps
CPU time 10.86 seconds
Started Jun 30 07:00:32 PM PDT 24
Finished Jun 30 07:00:46 PM PDT 24
Peak memory 237580 kb
Host smart-0c216775-467c-4c43-8b51-50bc60a44b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063361303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1063361303
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4080763040
Short name T659
Test name
Test status
Simulation time 14260293 ps
CPU time 0.77 seconds
Started Jun 30 07:00:39 PM PDT 24
Finished Jun 30 07:00:42 PM PDT 24
Peak memory 205416 kb
Host smart-30d29bd8-5d57-47bb-8183-01d2aa5fc1c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080763040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4080763040
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2161699859
Short name T657
Test name
Test status
Simulation time 54778404 ps
CPU time 2.02 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:00:42 PM PDT 24
Peak memory 224396 kb
Host smart-8168d673-cc9c-434d-80c5-3426f41f0798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161699859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2161699859
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2617590440
Short name T570
Test name
Test status
Simulation time 17589831 ps
CPU time 0.91 seconds
Started Jun 30 07:00:39 PM PDT 24
Finished Jun 30 07:00:42 PM PDT 24
Peak memory 206544 kb
Host smart-89540e55-2966-481b-93d9-ae57615c74b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617590440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2617590440
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3699823773
Short name T631
Test name
Test status
Simulation time 213470169 ps
CPU time 4.85 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:00:45 PM PDT 24
Peak memory 224472 kb
Host smart-066b4380-120a-4849-a0e4-9ad480553b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699823773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3699823773
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2995694042
Short name T218
Test name
Test status
Simulation time 8470963299 ps
CPU time 86.14 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:02:07 PM PDT 24
Peak memory 259892 kb
Host smart-d2058edf-2566-499a-b80d-94315b6d89d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995694042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2995694042
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3030045008
Short name T760
Test name
Test status
Simulation time 243722392 ps
CPU time 7.72 seconds
Started Jun 30 07:00:37 PM PDT 24
Finished Jun 30 07:00:47 PM PDT 24
Peak memory 240900 kb
Host smart-74dc8b06-29d3-462c-8d64-6fa3cfa18399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030045008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3030045008
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1469918209
Short name T579
Test name
Test status
Simulation time 54486230112 ps
CPU time 39.86 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:01:20 PM PDT 24
Peak memory 224588 kb
Host smart-58709aa9-38b2-4f9b-b717-9bf8c8553dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469918209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1469918209
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1040762727
Short name T582
Test name
Test status
Simulation time 143491300 ps
CPU time 4.86 seconds
Started Jun 30 07:00:40 PM PDT 24
Finished Jun 30 07:00:46 PM PDT 24
Peak memory 232640 kb
Host smart-b94711d5-c676-4d94-9484-b83152d8993d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040762727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1040762727
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2730609960
Short name T672
Test name
Test status
Simulation time 28498344525 ps
CPU time 60.54 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:01:41 PM PDT 24
Peak memory 240796 kb
Host smart-ee2c339b-58fa-4632-990c-3e8c54c8e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730609960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2730609960
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.503314237
Short name T253
Test name
Test status
Simulation time 3864365327 ps
CPU time 14.79 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:00:56 PM PDT 24
Peak memory 240636 kb
Host smart-733b0c11-ae90-4110-8c4a-79375b1b8696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503314237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.503314237
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4248923243
Short name T941
Test name
Test status
Simulation time 18511463946 ps
CPU time 17.84 seconds
Started Jun 30 07:00:39 PM PDT 24
Finished Jun 30 07:00:59 PM PDT 24
Peak memory 232788 kb
Host smart-c89bc346-7a7b-49ba-8407-125f64ad0a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248923243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4248923243
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.858797795
Short name T772
Test name
Test status
Simulation time 2635467498 ps
CPU time 7.98 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:00:48 PM PDT 24
Peak memory 223028 kb
Host smart-8f376bca-63e6-4d5a-8608-957e9212efd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=858797795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.858797795
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3871739479
Short name T166
Test name
Test status
Simulation time 4174733258 ps
CPU time 85.95 seconds
Started Jun 30 07:00:39 PM PDT 24
Finished Jun 30 07:02:07 PM PDT 24
Peak memory 251888 kb
Host smart-bff19017-0dd4-4a73-babe-50ea8113d1f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871739479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3871739479
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1446095541
Short name T643
Test name
Test status
Simulation time 1224211266 ps
CPU time 18.16 seconds
Started Jun 30 07:00:39 PM PDT 24
Finished Jun 30 07:00:59 PM PDT 24
Peak memory 216224 kb
Host smart-378586a6-998f-4ee6-a7ec-12b411b7e667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446095541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1446095541
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1161380035
Short name T443
Test name
Test status
Simulation time 406124268 ps
CPU time 2.24 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:00:43 PM PDT 24
Peak memory 207728 kb
Host smart-98cb853d-bed6-435f-8af8-5c234e5b5dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161380035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1161380035
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3328259670
Short name T323
Test name
Test status
Simulation time 1931311121 ps
CPU time 1.47 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:00:42 PM PDT 24
Peak memory 216244 kb
Host smart-7db8e14d-1d55-4a8e-8d50-e9e64f5d7b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328259670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3328259670
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.167892269
Short name T883
Test name
Test status
Simulation time 93233421 ps
CPU time 0.76 seconds
Started Jun 30 07:00:37 PM PDT 24
Finished Jun 30 07:00:40 PM PDT 24
Peak memory 205884 kb
Host smart-8cf58832-dc79-4f72-baf0-f3ef1945b3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167892269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.167892269
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4118594601
Short name T867
Test name
Test status
Simulation time 2487059120 ps
CPU time 5.69 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:00:46 PM PDT 24
Peak memory 224548 kb
Host smart-02d7e122-b5d6-4475-896f-c5ff4ee0b0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118594601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4118594601
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2548931356
Short name T942
Test name
Test status
Simulation time 26530588 ps
CPU time 0.72 seconds
Started Jun 30 07:00:44 PM PDT 24
Finished Jun 30 07:00:45 PM PDT 24
Peak memory 205384 kb
Host smart-fb41b665-337e-4d65-a7a9-a16229fd258d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548931356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2548931356
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.775424805
Short name T93
Test name
Test status
Simulation time 281464223 ps
CPU time 3.64 seconds
Started Jun 30 07:00:52 PM PDT 24
Finished Jun 30 07:00:57 PM PDT 24
Peak memory 224416 kb
Host smart-c9a9cf21-702a-493e-b012-d7f5245ae751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775424805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.775424805
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4272005532
Short name T734
Test name
Test status
Simulation time 37380673 ps
CPU time 0.82 seconds
Started Jun 30 07:00:38 PM PDT 24
Finished Jun 30 07:00:41 PM PDT 24
Peak memory 206572 kb
Host smart-a12802e3-3876-4de5-b7b3-662a19d18835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272005532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4272005532
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.804805177
Short name T978
Test name
Test status
Simulation time 118237299985 ps
CPU time 112.09 seconds
Started Jun 30 07:00:52 PM PDT 24
Finished Jun 30 07:02:45 PM PDT 24
Peak memory 253424 kb
Host smart-16619f5f-4af2-4071-aea2-73ad344a16ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804805177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.804805177
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4229379824
Short name T393
Test name
Test status
Simulation time 20335116048 ps
CPU time 130.8 seconds
Started Jun 30 07:00:43 PM PDT 24
Finished Jun 30 07:02:55 PM PDT 24
Peak memory 253956 kb
Host smart-2f70c7e9-5cd7-477c-b436-ffb219af2437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229379824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4229379824
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3096795568
Short name T847
Test name
Test status
Simulation time 29642755360 ps
CPU time 35.12 seconds
Started Jun 30 07:00:43 PM PDT 24
Finished Jun 30 07:01:18 PM PDT 24
Peak memory 217600 kb
Host smart-0b3166e6-2b80-4931-867e-cc3c8c856696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096795568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3096795568
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3195812841
Short name T861
Test name
Test status
Simulation time 715231928 ps
CPU time 5.24 seconds
Started Jun 30 07:00:43 PM PDT 24
Finished Jun 30 07:00:49 PM PDT 24
Peak memory 224460 kb
Host smart-da146606-de5d-46f2-87c9-4770b2315845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195812841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3195812841
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.304332051
Short name T206
Test name
Test status
Simulation time 190747455554 ps
CPU time 322.74 seconds
Started Jun 30 07:00:43 PM PDT 24
Finished Jun 30 07:06:07 PM PDT 24
Peak memory 249644 kb
Host smart-193663cb-abdc-460f-92f9-c18a3daeb636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304332051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.304332051
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3950243021
Short name T464
Test name
Test status
Simulation time 3095171198 ps
CPU time 15.11 seconds
Started Jun 30 07:00:43 PM PDT 24
Finished Jun 30 07:00:59 PM PDT 24
Peak memory 232736 kb
Host smart-2258f3c3-2287-4f02-a5cb-573ef949d6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950243021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3950243021
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.777246898
Short name T524
Test name
Test status
Simulation time 34619447024 ps
CPU time 85.45 seconds
Started Jun 30 07:00:44 PM PDT 24
Finished Jun 30 07:02:10 PM PDT 24
Peak memory 240284 kb
Host smart-bc84f586-00a7-4a04-baf2-e1c27a3c3d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777246898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.777246898
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.918347953
Short name T586
Test name
Test status
Simulation time 1120679948 ps
CPU time 3.37 seconds
Started Jun 30 07:00:52 PM PDT 24
Finished Jun 30 07:00:56 PM PDT 24
Peak memory 224444 kb
Host smart-1dbb315c-48dd-4fcb-bd8e-185b4ed56f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918347953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.918347953
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.192488757
Short name T787
Test name
Test status
Simulation time 6065181105 ps
CPU time 13.58 seconds
Started Jun 30 07:00:52 PM PDT 24
Finished Jun 30 07:01:07 PM PDT 24
Peak memory 249156 kb
Host smart-f32fc960-bc28-45b1-851f-10fbd5930c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192488757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.192488757
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1862749599
Short name T1023
Test name
Test status
Simulation time 4818070501 ps
CPU time 5.18 seconds
Started Jun 30 07:00:44 PM PDT 24
Finished Jun 30 07:00:50 PM PDT 24
Peak memory 222224 kb
Host smart-ad2ba1b4-deca-46bf-b768-08662150345c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1862749599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1862749599
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1583722316
Short name T533
Test name
Test status
Simulation time 130568156664 ps
CPU time 137.02 seconds
Started Jun 30 07:00:51 PM PDT 24
Finished Jun 30 07:03:09 PM PDT 24
Peak memory 256316 kb
Host smart-e95d5909-277e-438a-b1ac-66dc72e805ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583722316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1583722316
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3734624937
Short name T424
Test name
Test status
Simulation time 11809439422 ps
CPU time 20.89 seconds
Started Jun 30 07:00:43 PM PDT 24
Finished Jun 30 07:01:04 PM PDT 24
Peak memory 218292 kb
Host smart-dcbc63ae-2219-4adc-8bfe-04eef90ae0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734624937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3734624937
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2809805657
Short name T809
Test name
Test status
Simulation time 1370020063 ps
CPU time 5.83 seconds
Started Jun 30 07:00:39 PM PDT 24
Finished Jun 30 07:00:47 PM PDT 24
Peak memory 216164 kb
Host smart-e8812ed8-13b9-4865-a0e4-50ccf75997e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809805657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2809805657
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4268486856
Short name T889
Test name
Test status
Simulation time 25462780 ps
CPU time 1.32 seconds
Started Jun 30 07:00:44 PM PDT 24
Finished Jun 30 07:00:46 PM PDT 24
Peak memory 216160 kb
Host smart-f133d3e1-d09e-4039-bde9-5ffd789693b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268486856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4268486856
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1605275709
Short name T830
Test name
Test status
Simulation time 75188470 ps
CPU time 0.75 seconds
Started Jun 30 07:00:46 PM PDT 24
Finished Jun 30 07:00:48 PM PDT 24
Peak memory 205892 kb
Host smart-ca0f62f1-1847-4321-871f-250da954da02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605275709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1605275709
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3060939718
Short name T553
Test name
Test status
Simulation time 5343732040 ps
CPU time 21.69 seconds
Started Jun 30 07:00:43 PM PDT 24
Finished Jun 30 07:01:06 PM PDT 24
Peak memory 241236 kb
Host smart-33781d33-c677-4131-87c4-efae311ef6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060939718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3060939718
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.522594076
Short name T610
Test name
Test status
Simulation time 11794490 ps
CPU time 0.73 seconds
Started Jun 30 07:00:49 PM PDT 24
Finished Jun 30 07:00:51 PM PDT 24
Peak memory 205396 kb
Host smart-84592d21-ce1d-46a1-8856-b83e55737bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522594076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.522594076
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3177342727
Short name T252
Test name
Test status
Simulation time 1155740117 ps
CPU time 5.72 seconds
Started Jun 30 07:00:51 PM PDT 24
Finished Jun 30 07:00:58 PM PDT 24
Peak memory 224172 kb
Host smart-1519c7a3-6f14-46a9-88a8-5d4340ccab8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177342727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3177342727
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.669594379
Short name T792
Test name
Test status
Simulation time 14451037 ps
CPU time 0.76 seconds
Started Jun 30 07:00:44 PM PDT 24
Finished Jun 30 07:00:45 PM PDT 24
Peak memory 205856 kb
Host smart-746f5a6e-3e4b-4a4a-8a75-4552aabaeb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669594379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.669594379
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3645453639
Short name T205
Test name
Test status
Simulation time 5546444201 ps
CPU time 76.66 seconds
Started Jun 30 07:00:49 PM PDT 24
Finished Jun 30 07:02:07 PM PDT 24
Peak memory 244320 kb
Host smart-ae9cc558-700b-4946-a44f-e557ce447086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645453639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3645453639
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3364550779
Short name T583
Test name
Test status
Simulation time 1383912798 ps
CPU time 13.36 seconds
Started Jun 30 07:00:50 PM PDT 24
Finished Jun 30 07:01:04 PM PDT 24
Peak memory 217436 kb
Host smart-71babd2f-44ff-4f50-b186-3cbd7edf7ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364550779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3364550779
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3683900008
Short name T179
Test name
Test status
Simulation time 3097544610 ps
CPU time 59.61 seconds
Started Jun 30 07:00:50 PM PDT 24
Finished Jun 30 07:01:50 PM PDT 24
Peak memory 249292 kb
Host smart-6698c74b-4938-45f4-ab37-b9c39ea1bc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683900008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3683900008
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1280296680
Short name T284
Test name
Test status
Simulation time 376379119 ps
CPU time 8.69 seconds
Started Jun 30 07:00:49 PM PDT 24
Finished Jun 30 07:00:58 PM PDT 24
Peak memory 232712 kb
Host smart-1df3e759-b31b-4392-b774-29ec95cea2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280296680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1280296680
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1594330746
Short name T539
Test name
Test status
Simulation time 9094722814 ps
CPU time 81.18 seconds
Started Jun 30 07:00:52 PM PDT 24
Finished Jun 30 07:02:14 PM PDT 24
Peak memory 256928 kb
Host smart-d2168c13-ee81-47b8-b9df-37e2f33651fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594330746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1594330746
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1571054460
Short name T728
Test name
Test status
Simulation time 762594738 ps
CPU time 5.29 seconds
Started Jun 30 07:00:46 PM PDT 24
Finished Jun 30 07:00:52 PM PDT 24
Peak memory 228896 kb
Host smart-cc3cc749-fea0-456b-a506-0c1c1992c6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571054460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1571054460
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2688096652
Short name T69
Test name
Test status
Simulation time 74399502 ps
CPU time 2.46 seconds
Started Jun 30 07:00:51 PM PDT 24
Finished Jun 30 07:00:55 PM PDT 24
Peak memory 232384 kb
Host smart-97f849ce-2b5f-4664-a31d-dcff4c395d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688096652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2688096652
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.465127899
Short name T886
Test name
Test status
Simulation time 87851292 ps
CPU time 2.2 seconds
Started Jun 30 07:00:44 PM PDT 24
Finished Jun 30 07:00:47 PM PDT 24
Peak memory 224416 kb
Host smart-3edaca11-7619-487f-b266-b035e6399200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465127899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.465127899
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.860721250
Short name T654
Test name
Test status
Simulation time 955763292 ps
CPU time 3.23 seconds
Started Jun 30 07:00:43 PM PDT 24
Finished Jun 30 07:00:47 PM PDT 24
Peak memory 232644 kb
Host smart-9beacbcb-c18c-4f04-bf24-ff86ea9f771a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860721250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.860721250
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.90539946
Short name T150
Test name
Test status
Simulation time 130024496 ps
CPU time 3.39 seconds
Started Jun 30 07:00:51 PM PDT 24
Finished Jun 30 07:00:55 PM PDT 24
Peak memory 218712 kb
Host smart-0ae43b09-8776-4c1d-ac57-1d62d16b6869
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=90539946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direc
t.90539946
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2964720501
Short name T884
Test name
Test status
Simulation time 7364305806 ps
CPU time 71.11 seconds
Started Jun 30 07:00:51 PM PDT 24
Finished Jun 30 07:02:03 PM PDT 24
Peak memory 252108 kb
Host smart-91ca4a58-df4e-45fb-bc7d-34f7b1f45d9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964720501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2964720501
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4207567154
Short name T958
Test name
Test status
Simulation time 1238107161 ps
CPU time 4.76 seconds
Started Jun 30 07:00:45 PM PDT 24
Finished Jun 30 07:00:51 PM PDT 24
Peak memory 216256 kb
Host smart-d396a872-4b5d-48b0-9aed-ade03fcaf541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207567154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4207567154
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2625511057
Short name T326
Test name
Test status
Simulation time 2318157766 ps
CPU time 8.8 seconds
Started Jun 30 07:00:52 PM PDT 24
Finished Jun 30 07:01:02 PM PDT 24
Peak memory 216280 kb
Host smart-12648e0a-74d0-4d1d-bfa8-f1bb8b3638a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625511057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2625511057
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2298430540
Short name T293
Test name
Test status
Simulation time 950067945 ps
CPU time 1.65 seconds
Started Jun 30 07:00:44 PM PDT 24
Finished Jun 30 07:00:47 PM PDT 24
Peak memory 216232 kb
Host smart-f66af59b-aa89-4660-a8ad-edc42507f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298430540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2298430540
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2782226809
Short name T584
Test name
Test status
Simulation time 39684497 ps
CPU time 0.83 seconds
Started Jun 30 07:00:43 PM PDT 24
Finished Jun 30 07:00:45 PM PDT 24
Peak memory 205892 kb
Host smart-dab60b2a-b170-4502-93b6-9a83bc553ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782226809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2782226809
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4196196754
Short name T688
Test name
Test status
Simulation time 5604828319 ps
CPU time 4.29 seconds
Started Jun 30 07:00:49 PM PDT 24
Finished Jun 30 07:00:54 PM PDT 24
Peak memory 232688 kb
Host smart-0b5615ff-251f-4607-acdf-d56d647f4492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196196754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4196196754
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1387053002
Short name T831
Test name
Test status
Simulation time 12107134 ps
CPU time 0.75 seconds
Started Jun 30 07:00:59 PM PDT 24
Finished Jun 30 07:01:00 PM PDT 24
Peak memory 204848 kb
Host smart-215f0052-7d59-4f41-bbb4-f207ff74bf14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387053002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1387053002
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2704176389
Short name T340
Test name
Test status
Simulation time 800131214 ps
CPU time 9.4 seconds
Started Jun 30 07:00:51 PM PDT 24
Finished Jun 30 07:01:01 PM PDT 24
Peak memory 224476 kb
Host smart-5ffefb9a-ae57-4d83-b4d9-ecf93b1933fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704176389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2704176389
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1816946202
Short name T572
Test name
Test status
Simulation time 66671011 ps
CPU time 0.75 seconds
Started Jun 30 07:00:51 PM PDT 24
Finished Jun 30 07:00:52 PM PDT 24
Peak memory 206536 kb
Host smart-811eb627-33c0-4753-90a1-e8f39d0f03bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816946202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1816946202
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2752389782
Short name T215
Test name
Test status
Simulation time 71926872818 ps
CPU time 184.43 seconds
Started Jun 30 07:00:50 PM PDT 24
Finished Jun 30 07:03:55 PM PDT 24
Peak memory 262864 kb
Host smart-a3bde83d-f304-4239-b8dd-da0a62b722c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752389782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2752389782
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.413132300
Short name T493
Test name
Test status
Simulation time 95771762612 ps
CPU time 198.89 seconds
Started Jun 30 07:00:49 PM PDT 24
Finished Jun 30 07:04:08 PM PDT 24
Peak memory 250504 kb
Host smart-2c1f5d49-4a73-4f6f-bd48-bce34f13adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413132300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.413132300
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1303213691
Short name T141
Test name
Test status
Simulation time 12335222973 ps
CPU time 71.69 seconds
Started Jun 30 07:00:57 PM PDT 24
Finished Jun 30 07:02:09 PM PDT 24
Peak memory 253800 kb
Host smart-bd47d38d-e413-49c3-a648-e174bf627f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303213691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1303213691
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2862707580
Short name T858
Test name
Test status
Simulation time 3206557323 ps
CPU time 7.91 seconds
Started Jun 30 07:00:49 PM PDT 24
Finished Jun 30 07:00:57 PM PDT 24
Peak memory 224556 kb
Host smart-ddb2b828-c992-42ec-9eda-d35a1947457d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862707580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2862707580
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3751081671
Short name T457
Test name
Test status
Simulation time 2645205036 ps
CPU time 23.01 seconds
Started Jun 30 07:00:50 PM PDT 24
Finished Jun 30 07:01:14 PM PDT 24
Peak memory 234892 kb
Host smart-031abe1b-b7ce-46bd-9922-03d94139fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751081671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3751081671
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2111926688
Short name T194
Test name
Test status
Simulation time 2106716818 ps
CPU time 21.88 seconds
Started Jun 30 07:00:53 PM PDT 24
Finished Jun 30 07:01:16 PM PDT 24
Peak memory 232648 kb
Host smart-70f62bbd-8044-4335-b399-a9573257cfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111926688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2111926688
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3194271863
Short name T382
Test name
Test status
Simulation time 4801183966 ps
CPU time 43.93 seconds
Started Jun 30 07:00:49 PM PDT 24
Finished Jun 30 07:01:34 PM PDT 24
Peak memory 239356 kb
Host smart-b39967ac-c783-4e85-ad02-16bfd1289336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194271863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3194271863
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3913695732
Short name T788
Test name
Test status
Simulation time 4785811478 ps
CPU time 7.49 seconds
Started Jun 30 07:00:51 PM PDT 24
Finished Jun 30 07:00:59 PM PDT 24
Peak memory 224584 kb
Host smart-063dc2f0-fede-4771-94af-ed2252e96bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913695732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3913695732
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2441418055
Short name T251
Test name
Test status
Simulation time 1507067625 ps
CPU time 5.01 seconds
Started Jun 30 07:00:50 PM PDT 24
Finished Jun 30 07:00:56 PM PDT 24
Peak memory 232608 kb
Host smart-8e9760c3-a398-42fb-8213-cc19493c4776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441418055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2441418055
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3984776745
Short name T484
Test name
Test status
Simulation time 3944300256 ps
CPU time 14.06 seconds
Started Jun 30 07:00:49 PM PDT 24
Finished Jun 30 07:01:03 PM PDT 24
Peak memory 220056 kb
Host smart-10219ec7-f95b-48c7-acfa-6f10083c5f73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3984776745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3984776745
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1807803701
Short name T951
Test name
Test status
Simulation time 17431575202 ps
CPU time 32.24 seconds
Started Jun 30 07:00:55 PM PDT 24
Finished Jun 30 07:01:28 PM PDT 24
Peak memory 224560 kb
Host smart-42d78e2a-00dd-4629-be7a-67d3a3654616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807803701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1807803701
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2545541024
Short name T508
Test name
Test status
Simulation time 6589007758 ps
CPU time 32.33 seconds
Started Jun 30 07:00:49 PM PDT 24
Finished Jun 30 07:01:21 PM PDT 24
Peak memory 216352 kb
Host smart-9dc33d51-7877-4e82-a13d-53281fd44db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545541024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2545541024
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2772008451
Short name T873
Test name
Test status
Simulation time 1198593158 ps
CPU time 6.39 seconds
Started Jun 30 07:00:49 PM PDT 24
Finished Jun 30 07:00:56 PM PDT 24
Peak memory 216152 kb
Host smart-916843eb-30d1-4cc9-8ef5-ac75b1413756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772008451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2772008451
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3749394035
Short name T706
Test name
Test status
Simulation time 228166271 ps
CPU time 4.21 seconds
Started Jun 30 07:00:51 PM PDT 24
Finished Jun 30 07:00:57 PM PDT 24
Peak memory 216216 kb
Host smart-49f2e8e4-dfdc-49cb-8b3e-3201d0d95986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749394035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3749394035
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2170722472
Short name T731
Test name
Test status
Simulation time 16138575 ps
CPU time 0.75 seconds
Started Jun 30 07:00:51 PM PDT 24
Finished Jun 30 07:00:53 PM PDT 24
Peak memory 205580 kb
Host smart-f29bf404-b996-47fb-a4f9-01c2fff9f71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170722472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2170722472
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3580527547
Short name T701
Test name
Test status
Simulation time 2423056974 ps
CPU time 13.63 seconds
Started Jun 30 07:00:50 PM PDT 24
Finished Jun 30 07:01:04 PM PDT 24
Peak memory 232792 kb
Host smart-f2413ad1-5555-4e41-8619-0dc9830bad1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580527547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3580527547
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3115718147
Short name T519
Test name
Test status
Simulation time 11891769 ps
CPU time 0.7 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:00:58 PM PDT 24
Peak memory 205640 kb
Host smart-a4cf8e68-a486-4a36-8cdd-d91af777bb03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115718147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3115718147
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2178635141
Short name T328
Test name
Test status
Simulation time 1012303497 ps
CPU time 4.15 seconds
Started Jun 30 07:00:59 PM PDT 24
Finished Jun 30 07:01:04 PM PDT 24
Peak memory 232672 kb
Host smart-d5d9c5f8-c580-4620-a845-acfca7630235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178635141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2178635141
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3582293670
Short name T652
Test name
Test status
Simulation time 53700837 ps
CPU time 0.75 seconds
Started Jun 30 07:00:59 PM PDT 24
Finished Jun 30 07:01:00 PM PDT 24
Peak memory 205524 kb
Host smart-855b2ed8-3931-473e-8b5d-02e4439a7979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582293670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3582293670
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1145023969
Short name T42
Test name
Test status
Simulation time 14310705221 ps
CPU time 156.12 seconds
Started Jun 30 07:00:58 PM PDT 24
Finished Jun 30 07:03:35 PM PDT 24
Peak memory 262996 kb
Host smart-07c25d89-af7a-4e41-b732-9bf4c777da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145023969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1145023969
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3732410133
Short name T766
Test name
Test status
Simulation time 33038230510 ps
CPU time 382.01 seconds
Started Jun 30 07:00:59 PM PDT 24
Finished Jun 30 07:07:22 PM PDT 24
Peak memory 265620 kb
Host smart-dc971705-d5c0-4af2-ba6b-55b5af660ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732410133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3732410133
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3298885759
Short name T57
Test name
Test status
Simulation time 2562416895 ps
CPU time 42.55 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:01:40 PM PDT 24
Peak memory 251816 kb
Host smart-330198e3-c2a7-4a58-ade3-15902f0eb50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298885759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3298885759
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2732582736
Short name T786
Test name
Test status
Simulation time 170214728 ps
CPU time 4.03 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:01:00 PM PDT 24
Peak memory 224444 kb
Host smart-55b8d958-66f8-409c-984b-fee23c240a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732582736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2732582736
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2014572398
Short name T177
Test name
Test status
Simulation time 15713404585 ps
CPU time 128.73 seconds
Started Jun 30 07:01:00 PM PDT 24
Finished Jun 30 07:03:10 PM PDT 24
Peak memory 249176 kb
Host smart-69c76184-8a3d-4112-b419-4d409c2e5531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014572398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2014572398
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2480876525
Short name T763
Test name
Test status
Simulation time 4062759574 ps
CPU time 9.61 seconds
Started Jun 30 07:00:59 PM PDT 24
Finished Jun 30 07:01:09 PM PDT 24
Peak memory 224596 kb
Host smart-374868b1-3001-41ad-9213-46ca39110958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480876525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2480876525
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4146347805
Short name T187
Test name
Test status
Simulation time 18118755552 ps
CPU time 68.42 seconds
Started Jun 30 07:01:00 PM PDT 24
Finished Jun 30 07:02:09 PM PDT 24
Peak memory 240912 kb
Host smart-ade10ed4-3015-41af-bd39-a4ff30957f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146347805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4146347805
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.831776571
Short name T874
Test name
Test status
Simulation time 11843246697 ps
CPU time 12.57 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:01:09 PM PDT 24
Peak memory 232808 kb
Host smart-c55d28e1-18fa-42c5-a6ce-66933a03ff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831776571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.831776571
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2400291818
Short name T782
Test name
Test status
Simulation time 239729790 ps
CPU time 3.29 seconds
Started Jun 30 07:00:58 PM PDT 24
Finished Jun 30 07:01:02 PM PDT 24
Peak memory 232608 kb
Host smart-fdf77ba3-8ac3-4ab9-888b-ae0cc6871a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400291818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2400291818
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1460155071
Short name T440
Test name
Test status
Simulation time 563627468 ps
CPU time 5.21 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:01:03 PM PDT 24
Peak memory 222160 kb
Host smart-a6f92ccc-5743-4eca-b173-2a1e4456b95a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1460155071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1460155071
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1635921370
Short name T693
Test name
Test status
Simulation time 50329147623 ps
CPU time 313.28 seconds
Started Jun 30 07:00:58 PM PDT 24
Finished Jun 30 07:06:12 PM PDT 24
Peak memory 252984 kb
Host smart-153d7e23-4527-4c52-9356-1992ab15295f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635921370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1635921370
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.367799671
Short name T590
Test name
Test status
Simulation time 3938861263 ps
CPU time 25.5 seconds
Started Jun 30 07:01:00 PM PDT 24
Finished Jun 30 07:01:26 PM PDT 24
Peak memory 216268 kb
Host smart-1c8a6ea3-c4ff-4829-a193-eac301a25695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367799671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.367799671
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3760839822
Short name T661
Test name
Test status
Simulation time 1086796187 ps
CPU time 8.27 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:01:06 PM PDT 24
Peak memory 216124 kb
Host smart-cec31798-591c-4b6c-a711-7014becb682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760839822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3760839822
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.827937252
Short name T756
Test name
Test status
Simulation time 162497624 ps
CPU time 2.05 seconds
Started Jun 30 07:00:58 PM PDT 24
Finished Jun 30 07:01:01 PM PDT 24
Peak memory 216144 kb
Host smart-fb223e81-d7d5-4952-829d-2d0021777897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827937252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.827937252
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1962395706
Short name T365
Test name
Test status
Simulation time 21825474 ps
CPU time 0.78 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:00:57 PM PDT 24
Peak memory 205900 kb
Host smart-b817824e-90d3-499d-8486-7631b94cc4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962395706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1962395706
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.994215778
Short name T318
Test name
Test status
Simulation time 2058994427 ps
CPU time 10.06 seconds
Started Jun 30 07:01:00 PM PDT 24
Finished Jun 30 07:01:10 PM PDT 24
Peak memory 244076 kb
Host smart-3aa0272d-8ae4-4a8e-97dd-c205810b586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994215778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.994215778
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.668060442
Short name T894
Test name
Test status
Simulation time 32039763 ps
CPU time 0.7 seconds
Started Jun 30 07:01:00 PM PDT 24
Finished Jun 30 07:01:02 PM PDT 24
Peak memory 204876 kb
Host smart-e8381427-3ef7-464f-9094-f9c30319ef47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668060442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.668060442
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2149557896
Short name T719
Test name
Test status
Simulation time 107605201 ps
CPU time 2.23 seconds
Started Jun 30 07:00:55 PM PDT 24
Finished Jun 30 07:00:58 PM PDT 24
Peak memory 223576 kb
Host smart-e39633ea-a574-4edc-b0e5-bdf77c1ec2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149557896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2149557896
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1654740607
Short name T891
Test name
Test status
Simulation time 54064177 ps
CPU time 0.79 seconds
Started Jun 30 07:00:59 PM PDT 24
Finished Jun 30 07:01:01 PM PDT 24
Peak memory 206560 kb
Host smart-b1309e32-7ca1-4838-95a1-46036a1efde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654740607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1654740607
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.143543481
Short name T910
Test name
Test status
Simulation time 2512869702 ps
CPU time 20.92 seconds
Started Jun 30 07:01:03 PM PDT 24
Finished Jun 30 07:01:26 PM PDT 24
Peak memory 251624 kb
Host smart-bdfe9266-f790-42d2-824f-4da402c98c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143543481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.143543481
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1611865235
Short name T479
Test name
Test status
Simulation time 26033667430 ps
CPU time 89.96 seconds
Started Jun 30 07:01:01 PM PDT 24
Finished Jun 30 07:02:31 PM PDT 24
Peak memory 264996 kb
Host smart-3df7bbb4-9e01-4bce-b088-329b992498e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611865235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1611865235
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3866375572
Short name T139
Test name
Test status
Simulation time 14652707128 ps
CPU time 39.01 seconds
Started Jun 30 07:01:01 PM PDT 24
Finished Jun 30 07:01:41 PM PDT 24
Peak memory 249448 kb
Host smart-c67a6166-4a24-4cb3-9702-eee8356cb6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866375572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3866375572
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.81667233
Short name T282
Test name
Test status
Simulation time 3721381929 ps
CPU time 54.93 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:59 PM PDT 24
Peak memory 239808 kb
Host smart-411cc511-5507-4f77-9642-434e93323210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81667233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.81667233
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2233122277
Short name T214
Test name
Test status
Simulation time 72454294194 ps
CPU time 263.44 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:05:27 PM PDT 24
Peak memory 255120 kb
Host smart-071cb7ad-bbcd-4004-94ec-130d6d5160fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233122277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2233122277
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2919619743
Short name T905
Test name
Test status
Simulation time 2763957794 ps
CPU time 8.74 seconds
Started Jun 30 07:00:58 PM PDT 24
Finished Jun 30 07:01:07 PM PDT 24
Peak memory 232764 kb
Host smart-6a58cfe0-4802-4c0e-b2b7-bd624fde45f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919619743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2919619743
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.456437530
Short name T852
Test name
Test status
Simulation time 2501773142 ps
CPU time 7.56 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:01:05 PM PDT 24
Peak memory 224548 kb
Host smart-fbad3696-5ffe-40e4-9967-9a5b99441aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456437530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.456437530
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3724896460
Short name T188
Test name
Test status
Simulation time 14466243400 ps
CPU time 21.07 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:01:18 PM PDT 24
Peak memory 240884 kb
Host smart-ca0f4cde-ed38-4d47-b8da-baeb062e2459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724896460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3724896460
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.711204575
Short name T494
Test name
Test status
Simulation time 733017865 ps
CPU time 2.52 seconds
Started Jun 30 07:01:00 PM PDT 24
Finished Jun 30 07:01:03 PM PDT 24
Peak memory 224380 kb
Host smart-cf62a9db-26c3-427e-bc11-63ca7dd33b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711204575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.711204575
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4152845113
Short name T438
Test name
Test status
Simulation time 974492893 ps
CPU time 10.3 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:15 PM PDT 24
Peak memory 221580 kb
Host smart-72f4e8e4-c9bd-41fe-ae1c-72f3cb3b017f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4152845113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4152845113
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3126955185
Short name T266
Test name
Test status
Simulation time 10973342571 ps
CPU time 220.28 seconds
Started Jun 30 07:01:01 PM PDT 24
Finished Jun 30 07:04:42 PM PDT 24
Peak memory 273300 kb
Host smart-0943e91c-950d-4735-8602-8de05de5ca6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126955185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3126955185
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4137334902
Short name T991
Test name
Test status
Simulation time 682523549 ps
CPU time 2.24 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:01:00 PM PDT 24
Peak memory 216640 kb
Host smart-a015e55c-8d5a-4d81-804e-08e99d26046b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137334902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4137334902
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.450262117
Short name T1008
Test name
Test status
Simulation time 1347938703 ps
CPU time 5.69 seconds
Started Jun 30 07:01:00 PM PDT 24
Finished Jun 30 07:01:06 PM PDT 24
Peak memory 216116 kb
Host smart-aa34cbb9-7fe1-4726-be3c-12c6c3281e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450262117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.450262117
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3597242324
Short name T495
Test name
Test status
Simulation time 665677300 ps
CPU time 2.31 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:01:00 PM PDT 24
Peak memory 216084 kb
Host smart-df386697-ed3e-458d-a5c4-b0516e2c6bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597242324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3597242324
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4258624846
Short name T375
Test name
Test status
Simulation time 29351115 ps
CPU time 0.83 seconds
Started Jun 30 07:00:56 PM PDT 24
Finished Jun 30 07:00:58 PM PDT 24
Peak memory 204900 kb
Host smart-88b1acac-2177-43e8-95e0-e2d8822c00cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258624846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4258624846
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3715548884
Short name T757
Test name
Test status
Simulation time 1537517132 ps
CPU time 7.21 seconds
Started Jun 30 07:01:00 PM PDT 24
Finished Jun 30 07:01:08 PM PDT 24
Peak memory 232680 kb
Host smart-e16c8519-074e-45f7-a7e2-f0b7ee78d886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715548884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3715548884
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4201467659
Short name T361
Test name
Test status
Simulation time 27738710 ps
CPU time 0.74 seconds
Started Jun 30 07:01:03 PM PDT 24
Finished Jun 30 07:01:06 PM PDT 24
Peak memory 205780 kb
Host smart-c5d709b6-bbb9-48dd-849b-739faf9b9e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201467659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4201467659
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4171192250
Short name T486
Test name
Test status
Simulation time 13173519368 ps
CPU time 26.55 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:30 PM PDT 24
Peak memory 224564 kb
Host smart-2783d6c5-8e07-4cc9-8afd-8db263b32dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171192250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4171192250
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1073911353
Short name T558
Test name
Test status
Simulation time 18440658 ps
CPU time 0.84 seconds
Started Jun 30 07:01:04 PM PDT 24
Finished Jun 30 07:01:06 PM PDT 24
Peak memory 205492 kb
Host smart-10424ae4-a7b1-417f-94f0-1f63ebcb30ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073911353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1073911353
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.67638534
Short name T935
Test name
Test status
Simulation time 475445663 ps
CPU time 6.98 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:11 PM PDT 24
Peak memory 224384 kb
Host smart-c2f448ff-5f32-4809-b2c3-a3810ec4bfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67638534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.67638534
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2686274290
Short name T426
Test name
Test status
Simulation time 3177269204 ps
CPU time 80.2 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:02:23 PM PDT 24
Peak memory 263740 kb
Host smart-2173e649-43d8-44cb-ad2c-fa689dfe9f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686274290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2686274290
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.530453811
Short name T423
Test name
Test status
Simulation time 5044313636 ps
CPU time 20.97 seconds
Started Jun 30 07:01:03 PM PDT 24
Finished Jun 30 07:01:26 PM PDT 24
Peak memory 222028 kb
Host smart-aac5c472-11f5-4221-91e2-de6ec8248144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530453811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.530453811
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1934502913
Short name T4
Test name
Test status
Simulation time 1322167582 ps
CPU time 7.79 seconds
Started Jun 30 07:01:04 PM PDT 24
Finished Jun 30 07:01:13 PM PDT 24
Peak memory 239412 kb
Host smart-64026214-8eb5-49ab-8c3c-fd2007e1b1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934502913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1934502913
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1094881580
Short name T744
Test name
Test status
Simulation time 49209183801 ps
CPU time 38.29 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 237400 kb
Host smart-5bfee4c1-9317-484a-a658-adb1e2ed2091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094881580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1094881580
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2893909238
Short name T185
Test name
Test status
Simulation time 2457343461 ps
CPU time 6.89 seconds
Started Jun 30 07:01:03 PM PDT 24
Finished Jun 30 07:01:12 PM PDT 24
Peak memory 224592 kb
Host smart-e778fba6-6c6b-4e62-a3e0-8bf576bbec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893909238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2893909238
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4022704472
Short name T514
Test name
Test status
Simulation time 10848631502 ps
CPU time 51.52 seconds
Started Jun 30 07:01:03 PM PDT 24
Finished Jun 30 07:01:56 PM PDT 24
Peak memory 232784 kb
Host smart-7736de73-6c35-43ea-8918-f54ef8d4524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022704472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4022704472
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3255958086
Short name T948
Test name
Test status
Simulation time 461616452 ps
CPU time 2.8 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:07 PM PDT 24
Peak memory 224388 kb
Host smart-9d72f522-aa1a-4481-a7a1-5598c3093c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255958086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3255958086
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.465814546
Short name T190
Test name
Test status
Simulation time 1384003364 ps
CPU time 7.82 seconds
Started Jun 30 07:01:03 PM PDT 24
Finished Jun 30 07:01:13 PM PDT 24
Peak memory 224460 kb
Host smart-9ba29581-36f5-46fc-bc6b-e37ce3077f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465814546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.465814546
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3592231917
Short name T718
Test name
Test status
Simulation time 3872586563 ps
CPU time 15.37 seconds
Started Jun 30 07:01:03 PM PDT 24
Finished Jun 30 07:01:21 PM PDT 24
Peak memory 218736 kb
Host smart-cae102f3-84ba-481c-8a9b-75c7150fba6c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3592231917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3592231917
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3710978449
Short name T265
Test name
Test status
Simulation time 17917171896 ps
CPU time 128.14 seconds
Started Jun 30 07:01:03 PM PDT 24
Finished Jun 30 07:03:13 PM PDT 24
Peak memory 265524 kb
Host smart-37e81ac7-0fa4-4db9-8a8e-0c6791a1d907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710978449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3710978449
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.96819480
Short name T804
Test name
Test status
Simulation time 5804376337 ps
CPU time 34.48 seconds
Started Jun 30 07:01:03 PM PDT 24
Finished Jun 30 07:01:40 PM PDT 24
Peak memory 216320 kb
Host smart-d221cba4-94a8-4c86-82f4-0576186b9536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96819480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.96819480
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4283096191
Short name T546
Test name
Test status
Simulation time 928385150 ps
CPU time 1.33 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:05 PM PDT 24
Peak memory 207592 kb
Host smart-5b86304e-fd35-4807-b9c3-6e2876a20391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283096191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4283096191
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1336085712
Short name T332
Test name
Test status
Simulation time 254858861 ps
CPU time 3.69 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:08 PM PDT 24
Peak memory 216240 kb
Host smart-2a334f0f-3c43-418e-894a-40072ea2ee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336085712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1336085712
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3624032100
Short name T450
Test name
Test status
Simulation time 142312019 ps
CPU time 0.87 seconds
Started Jun 30 07:01:01 PM PDT 24
Finished Jun 30 07:01:03 PM PDT 24
Peak memory 205888 kb
Host smart-1ab77b16-50b9-4a81-a03d-fb4d9c5d63a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624032100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3624032100
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.390894882
Short name T698
Test name
Test status
Simulation time 1576588404 ps
CPU time 7.57 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:11 PM PDT 24
Peak memory 238816 kb
Host smart-d9e34e58-dda8-4389-be60-4f810f7595a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390894882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.390894882
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2281438046
Short name T878
Test name
Test status
Simulation time 15670701 ps
CPU time 0.76 seconds
Started Jun 30 06:58:45 PM PDT 24
Finished Jun 30 06:58:47 PM PDT 24
Peak memory 204852 kb
Host smart-61cd8532-84d2-4c66-9feb-76108aec2118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281438046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
281438046
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2614803475
Short name T595
Test name
Test status
Simulation time 527986062 ps
CPU time 3.66 seconds
Started Jun 30 06:58:49 PM PDT 24
Finished Jun 30 06:58:53 PM PDT 24
Peak memory 224460 kb
Host smart-2a4b5e9e-afe1-4581-8a8d-c160f16e7760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614803475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2614803475
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3628830922
Short name T764
Test name
Test status
Simulation time 25798146 ps
CPU time 0.78 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:58:44 PM PDT 24
Peak memory 205516 kb
Host smart-6346d7c7-f4ac-4a07-82a0-403b848b487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628830922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3628830922
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3897957011
Short name T227
Test name
Test status
Simulation time 13860200156 ps
CPU time 56.12 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 06:59:43 PM PDT 24
Peak memory 256752 kb
Host smart-713bd338-ff80-49c1-9186-5011446e3229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897957011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3897957011
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3349949435
Short name T45
Test name
Test status
Simulation time 77178110198 ps
CPU time 110.41 seconds
Started Jun 30 06:58:47 PM PDT 24
Finished Jun 30 07:00:39 PM PDT 24
Peak memory 251516 kb
Host smart-61f140cf-6bfb-4018-b7a5-33c9f075e0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349949435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3349949435
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1910361115
Short name T856
Test name
Test status
Simulation time 493956306 ps
CPU time 3.99 seconds
Started Jun 30 06:58:50 PM PDT 24
Finished Jun 30 06:58:55 PM PDT 24
Peak memory 232668 kb
Host smart-64b515cd-71a9-4840-86cc-18cbe898544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910361115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1910361115
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3708054934
Short name T963
Test name
Test status
Simulation time 76441477835 ps
CPU time 150.65 seconds
Started Jun 30 06:58:50 PM PDT 24
Finished Jun 30 07:01:20 PM PDT 24
Peak memory 250156 kb
Host smart-fc83dcbf-abfe-46bf-8e88-eeb2d18d7aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708054934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3708054934
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2974584588
Short name T359
Test name
Test status
Simulation time 1469187839 ps
CPU time 13.41 seconds
Started Jun 30 06:58:44 PM PDT 24
Finished Jun 30 06:58:58 PM PDT 24
Peak memory 224420 kb
Host smart-97b76aa6-75be-4579-a199-9e655d4f2ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974584588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2974584588
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3407162602
Short name T634
Test name
Test status
Simulation time 1368706596 ps
CPU time 8.66 seconds
Started Jun 30 06:58:45 PM PDT 24
Finished Jun 30 06:58:55 PM PDT 24
Peak memory 240452 kb
Host smart-243af14c-c7c9-4deb-b4f3-4583806bc33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407162602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3407162602
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2893762939
Short name T492
Test name
Test status
Simulation time 52972467 ps
CPU time 1.14 seconds
Started Jun 30 06:58:44 PM PDT 24
Finished Jun 30 06:58:46 PM PDT 24
Peak memory 216764 kb
Host smart-b9c67eb9-bb23-4c55-9c2a-5b8875b944d2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893762939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2893762939
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.870826631
Short name T664
Test name
Test status
Simulation time 20596847691 ps
CPU time 18.4 seconds
Started Jun 30 06:58:40 PM PDT 24
Finished Jun 30 06:58:59 PM PDT 24
Peak memory 249432 kb
Host smart-548e74b4-5a30-402b-93d8-47511abca375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870826631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
870826631
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.773795446
Short name T209
Test name
Test status
Simulation time 50962396838 ps
CPU time 14.3 seconds
Started Jun 30 06:58:45 PM PDT 24
Finished Jun 30 06:59:01 PM PDT 24
Peak memory 232732 kb
Host smart-fe6da6d3-2cfd-457d-be8c-6f6d967d3456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773795446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.773795446
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.579606230
Short name T39
Test name
Test status
Simulation time 2092491512 ps
CPU time 15.71 seconds
Started Jun 30 06:58:47 PM PDT 24
Finished Jun 30 06:59:04 PM PDT 24
Peak memory 218664 kb
Host smart-9e5dc771-52ee-4595-8e64-75ed726c7305
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=579606230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.579606230
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1098388664
Short name T65
Test name
Test status
Simulation time 33024914 ps
CPU time 0.96 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 06:58:50 PM PDT 24
Peak memory 235448 kb
Host smart-915f02da-e44b-4272-b106-6b3ecf7ca118
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098388664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1098388664
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1752860857
Short name T609
Test name
Test status
Simulation time 47838814 ps
CPU time 0.94 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 06:58:49 PM PDT 24
Peak memory 205972 kb
Host smart-6ce13182-7ea7-4909-8fc7-60516447958d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752860857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1752860857
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2821355877
Short name T944
Test name
Test status
Simulation time 10441990103 ps
CPU time 25.8 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:59:08 PM PDT 24
Peak memory 216548 kb
Host smart-3997722b-8e06-446c-a86f-cbb6317e17e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821355877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2821355877
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2309841420
Short name T828
Test name
Test status
Simulation time 12595378 ps
CPU time 0.75 seconds
Started Jun 30 06:58:43 PM PDT 24
Finished Jun 30 06:58:46 PM PDT 24
Peak memory 205908 kb
Host smart-0d4f3369-b8c6-4191-86a2-316ca41d6727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309841420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2309841420
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1215719853
Short name T507
Test name
Test status
Simulation time 220932819 ps
CPU time 1.42 seconds
Started Jun 30 06:58:40 PM PDT 24
Finished Jun 30 06:58:42 PM PDT 24
Peak memory 216148 kb
Host smart-767c4b1a-d658-4737-ac12-097ba2d56b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215719853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1215719853
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2327526365
Short name T696
Test name
Test status
Simulation time 30903302 ps
CPU time 0.81 seconds
Started Jun 30 06:58:42 PM PDT 24
Finished Jun 30 06:58:44 PM PDT 24
Peak memory 205876 kb
Host smart-e9832aa5-09a9-422d-8864-cd135e4b8e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327526365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2327526365
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.808640861
Short name T53
Test name
Test status
Simulation time 1137107675 ps
CPU time 5.51 seconds
Started Jun 30 06:58:47 PM PDT 24
Finished Jun 30 06:58:53 PM PDT 24
Peak memory 232660 kb
Host smart-0033abbd-3628-42db-8988-2795f35bceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808640861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.808640861
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3325679659
Short name T671
Test name
Test status
Simulation time 45739755 ps
CPU time 0.72 seconds
Started Jun 30 07:01:09 PM PDT 24
Finished Jun 30 07:01:10 PM PDT 24
Peak memory 204828 kb
Host smart-f693e019-c049-485c-a108-c1b81c911dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325679659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3325679659
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1155901275
Short name T680
Test name
Test status
Simulation time 97809858 ps
CPU time 2.4 seconds
Started Jun 30 07:01:10 PM PDT 24
Finished Jun 30 07:01:13 PM PDT 24
Peak memory 224480 kb
Host smart-cad34c3a-c283-4e64-a4b7-ef51eced9797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155901275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1155901275
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3851754333
Short name T784
Test name
Test status
Simulation time 21768615 ps
CPU time 0.8 seconds
Started Jun 30 07:01:01 PM PDT 24
Finished Jun 30 07:01:03 PM PDT 24
Peak memory 206888 kb
Host smart-af5213a2-0265-4b22-a472-af90916667a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851754333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3851754333
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2838544317
Short name T196
Test name
Test status
Simulation time 99647071694 ps
CPU time 172.39 seconds
Started Jun 30 07:01:10 PM PDT 24
Finished Jun 30 07:04:04 PM PDT 24
Peak memory 255164 kb
Host smart-3ad3ec1b-9799-4ab9-a538-0594c6d87f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838544317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2838544317
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2231866373
Short name T83
Test name
Test status
Simulation time 291257993152 ps
CPU time 335.39 seconds
Started Jun 30 07:01:09 PM PDT 24
Finished Jun 30 07:06:46 PM PDT 24
Peak memory 252732 kb
Host smart-61318c19-8d8d-4af6-99b3-3573bb21a9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231866373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2231866373
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.197048112
Short name T613
Test name
Test status
Simulation time 6726800411 ps
CPU time 20.7 seconds
Started Jun 30 07:01:14 PM PDT 24
Finished Jun 30 07:01:36 PM PDT 24
Peak memory 217464 kb
Host smart-51b16e89-b8c3-4887-a340-898d7371372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197048112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.197048112
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2277830466
Short name T965
Test name
Test status
Simulation time 1139555910 ps
CPU time 20.24 seconds
Started Jun 30 07:01:10 PM PDT 24
Finished Jun 30 07:01:31 PM PDT 24
Peak memory 232664 kb
Host smart-91accd12-4610-4e51-805d-9fb53232be58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277830466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2277830466
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2427705601
Short name T475
Test name
Test status
Simulation time 85472563 ps
CPU time 0.73 seconds
Started Jun 30 07:01:09 PM PDT 24
Finished Jun 30 07:01:10 PM PDT 24
Peak memory 215840 kb
Host smart-5dd7d2f0-1b75-47de-b050-44c6933fb494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427705601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2427705601
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2684581316
Short name T762
Test name
Test status
Simulation time 2916010582 ps
CPU time 12.24 seconds
Started Jun 30 07:01:04 PM PDT 24
Finished Jun 30 07:01:18 PM PDT 24
Peak memory 218860 kb
Host smart-5d5c6318-8f5f-4aba-a528-8882ee54717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684581316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2684581316
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2696698859
Short name T5
Test name
Test status
Simulation time 4047664734 ps
CPU time 23.86 seconds
Started Jun 30 07:01:03 PM PDT 24
Finished Jun 30 07:01:29 PM PDT 24
Peak memory 232764 kb
Host smart-a0cc01f7-7bc9-450e-b2ee-9c8fc52e014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696698859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2696698859
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3696526149
Short name T216
Test name
Test status
Simulation time 92478597 ps
CPU time 2.58 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:06 PM PDT 24
Peak memory 224412 kb
Host smart-2044a2f3-ada1-4bb7-ad5c-d5a72c81e207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696526149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3696526149
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2780499569
Short name T224
Test name
Test status
Simulation time 434360368 ps
CPU time 5.08 seconds
Started Jun 30 07:01:01 PM PDT 24
Finished Jun 30 07:01:06 PM PDT 24
Peak memory 224424 kb
Host smart-c31055e6-349e-4147-8ea3-1bfaaf1ec2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780499569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2780499569
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4247379253
Short name T449
Test name
Test status
Simulation time 343802364 ps
CPU time 6.22 seconds
Started Jun 30 07:01:09 PM PDT 24
Finished Jun 30 07:01:17 PM PDT 24
Peak memory 218832 kb
Host smart-f45b16dc-b504-46af-bdaf-9521efa908a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4247379253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4247379253
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1228005818
Short name T491
Test name
Test status
Simulation time 788300006 ps
CPU time 5.45 seconds
Started Jun 30 07:01:04 PM PDT 24
Finished Jun 30 07:01:11 PM PDT 24
Peak memory 216224 kb
Host smart-b3607262-24e2-4e6a-931f-ceb3b659092f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228005818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1228005818
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1993827272
Short name T294
Test name
Test status
Simulation time 4216490111 ps
CPU time 9.35 seconds
Started Jun 30 07:01:04 PM PDT 24
Finished Jun 30 07:01:15 PM PDT 24
Peak memory 216264 kb
Host smart-8a04214a-3547-4de3-9d4b-98163ecd56a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993827272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1993827272
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1748306312
Short name T452
Test name
Test status
Simulation time 173006137 ps
CPU time 1.32 seconds
Started Jun 30 07:01:02 PM PDT 24
Finished Jun 30 07:01:06 PM PDT 24
Peak memory 216176 kb
Host smart-38a54e2c-fcc0-4db2-bf00-29b3486e20ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748306312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1748306312
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.767276425
Short name T342
Test name
Test status
Simulation time 13735489 ps
CPU time 0.71 seconds
Started Jun 30 07:01:01 PM PDT 24
Finished Jun 30 07:01:03 PM PDT 24
Peak memory 205888 kb
Host smart-e7291b04-7289-4d74-8fce-4d03f5762916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767276425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.767276425
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1572085055
Short name T663
Test name
Test status
Simulation time 316699620 ps
CPU time 6.75 seconds
Started Jun 30 07:01:07 PM PDT 24
Finished Jun 30 07:01:14 PM PDT 24
Peak memory 232672 kb
Host smart-226e0b62-e67c-4489-80fb-158b7924f032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572085055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1572085055
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.685192489
Short name T348
Test name
Test status
Simulation time 51327118 ps
CPU time 0.78 seconds
Started Jun 30 07:01:15 PM PDT 24
Finished Jun 30 07:01:17 PM PDT 24
Peak memory 205744 kb
Host smart-06b79d76-ef3f-426f-ab2d-c48312b2694b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685192489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.685192489
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2920854975
Short name T995
Test name
Test status
Simulation time 5197457517 ps
CPU time 10.39 seconds
Started Jun 30 07:01:10 PM PDT 24
Finished Jun 30 07:01:21 PM PDT 24
Peak memory 232716 kb
Host smart-4798ed62-aa59-43e1-9a26-0b4f37b9b00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920854975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2920854975
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.4146158346
Short name T832
Test name
Test status
Simulation time 58530355 ps
CPU time 0.8 seconds
Started Jun 30 07:01:10 PM PDT 24
Finished Jun 30 07:01:12 PM PDT 24
Peak memory 206560 kb
Host smart-0b3c4210-aa71-46f2-9a52-f82d90483be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146158346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.4146158346
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2467306927
Short name T242
Test name
Test status
Simulation time 19489567553 ps
CPU time 130.43 seconds
Started Jun 30 07:01:08 PM PDT 24
Finished Jun 30 07:03:19 PM PDT 24
Peak memory 273704 kb
Host smart-59e99617-854e-47dc-b8e2-d3bf3bef5eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467306927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2467306927
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2408654520
Short name T497
Test name
Test status
Simulation time 4829011316 ps
CPU time 36.53 seconds
Started Jun 30 07:01:08 PM PDT 24
Finished Jun 30 07:01:45 PM PDT 24
Peak memory 241012 kb
Host smart-73c51c8a-f674-43a8-89b1-281bf64f6ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408654520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2408654520
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3701342963
Short name T597
Test name
Test status
Simulation time 210265838 ps
CPU time 3.53 seconds
Started Jun 30 07:01:11 PM PDT 24
Finished Jun 30 07:01:16 PM PDT 24
Peak memory 232924 kb
Host smart-2e655986-4efc-42b5-88a7-2c1bb9157aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701342963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3701342963
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3406049069
Short name T22
Test name
Test status
Simulation time 18070754452 ps
CPU time 34.81 seconds
Started Jun 30 07:01:14 PM PDT 24
Finished Jun 30 07:01:50 PM PDT 24
Peak memory 224484 kb
Host smart-3c7a534c-33a3-4233-9bdd-013940bcd2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406049069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3406049069
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3286480823
Short name T626
Test name
Test status
Simulation time 422851975 ps
CPU time 4.25 seconds
Started Jun 30 07:01:14 PM PDT 24
Finished Jun 30 07:01:19 PM PDT 24
Peak memory 224440 kb
Host smart-f14d7adf-ea0d-4d72-beb5-8a2247c554bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286480823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3286480823
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3980049421
Short name T480
Test name
Test status
Simulation time 28215149967 ps
CPU time 43.36 seconds
Started Jun 30 07:01:13 PM PDT 24
Finished Jun 30 07:01:58 PM PDT 24
Peak memory 239544 kb
Host smart-6e0f2f6d-b57d-463c-8829-04e872b8729b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980049421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3980049421
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3768508123
Short name T898
Test name
Test status
Simulation time 27982522418 ps
CPU time 15.73 seconds
Started Jun 30 07:01:09 PM PDT 24
Finished Jun 30 07:01:25 PM PDT 24
Peak memory 232764 kb
Host smart-f16b7836-f288-4ece-a831-6982ca221f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768508123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3768508123
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1864113345
Short name T308
Test name
Test status
Simulation time 286767794 ps
CPU time 5.83 seconds
Started Jun 30 07:01:12 PM PDT 24
Finished Jun 30 07:01:19 PM PDT 24
Peak memory 239192 kb
Host smart-9c38bd50-30d1-479f-bbf6-1c0e5babfdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864113345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1864113345
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2113355118
Short name T151
Test name
Test status
Simulation time 740711935 ps
CPU time 7.94 seconds
Started Jun 30 07:01:07 PM PDT 24
Finished Jun 30 07:01:15 PM PDT 24
Peak memory 218952 kb
Host smart-4970f8d6-1f8d-4eee-a369-cae08b43d015
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2113355118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2113355118
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4057315979
Short name T18
Test name
Test status
Simulation time 9194723653 ps
CPU time 94.96 seconds
Started Jun 30 07:01:18 PM PDT 24
Finished Jun 30 07:02:54 PM PDT 24
Peak memory 249164 kb
Host smart-f9e44f3e-36d6-4e52-8eea-5f6ac2bc8a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057315979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4057315979
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1024575878
Short name T290
Test name
Test status
Simulation time 1566085174 ps
CPU time 19.18 seconds
Started Jun 30 07:01:08 PM PDT 24
Finished Jun 30 07:01:28 PM PDT 24
Peak memory 216148 kb
Host smart-02345043-3746-4b6b-a1d3-baff39568e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024575878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1024575878
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.896163858
Short name T350
Test name
Test status
Simulation time 25570940754 ps
CPU time 15.17 seconds
Started Jun 30 07:01:09 PM PDT 24
Finished Jun 30 07:01:25 PM PDT 24
Peak memory 216304 kb
Host smart-32259a60-6f4a-4bcd-bc3f-c79378416850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896163858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.896163858
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3826291986
Short name T469
Test name
Test status
Simulation time 168980026 ps
CPU time 2.83 seconds
Started Jun 30 07:01:13 PM PDT 24
Finished Jun 30 07:01:17 PM PDT 24
Peak memory 216072 kb
Host smart-1979f89d-8c30-47b3-a7c2-01d63eb8e8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826291986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3826291986
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1125598406
Short name T402
Test name
Test status
Simulation time 112592511 ps
CPU time 0.94 seconds
Started Jun 30 07:01:09 PM PDT 24
Finished Jun 30 07:01:11 PM PDT 24
Peak memory 205888 kb
Host smart-bff9ee3f-8352-4a10-b89a-af0c22295cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125598406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1125598406
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.450343739
Short name T180
Test name
Test status
Simulation time 29754746587 ps
CPU time 28.27 seconds
Started Jun 30 07:01:09 PM PDT 24
Finished Jun 30 07:01:38 PM PDT 24
Peak memory 249048 kb
Host smart-f8aca193-d60e-48c3-bb81-c03252500e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450343739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.450343739
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1098217860
Short name T1024
Test name
Test status
Simulation time 54697330 ps
CPU time 0.74 seconds
Started Jun 30 07:01:18 PM PDT 24
Finished Jun 30 07:01:20 PM PDT 24
Peak memory 205432 kb
Host smart-11525e64-94df-4bc5-b650-6bc06b169103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098217860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1098217860
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4175443600
Short name T587
Test name
Test status
Simulation time 4361837349 ps
CPU time 7.26 seconds
Started Jun 30 07:01:17 PM PDT 24
Finished Jun 30 07:01:26 PM PDT 24
Peak memory 224560 kb
Host smart-7c5b1630-51cd-499a-a0ca-e50e626bc138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175443600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4175443600
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2002177896
Short name T404
Test name
Test status
Simulation time 18319521 ps
CPU time 0.78 seconds
Started Jun 30 07:01:16 PM PDT 24
Finished Jun 30 07:01:18 PM PDT 24
Peak memory 206540 kb
Host smart-8cc4062e-7063-4ddd-8fe4-b66497cec3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002177896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2002177896
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1282125950
Short name T890
Test name
Test status
Simulation time 1763988950 ps
CPU time 24.44 seconds
Started Jun 30 07:01:16 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 238252 kb
Host smart-4ea8d303-9bda-4d13-abfe-a7fd4eb9d31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282125950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1282125950
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.797759467
Short name T949
Test name
Test status
Simulation time 42802632968 ps
CPU time 179.26 seconds
Started Jun 30 07:01:19 PM PDT 24
Finished Jun 30 07:04:19 PM PDT 24
Peak memory 254052 kb
Host smart-2e21a68f-5983-4b50-a4d9-79046d6c1b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797759467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.797759467
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4154651919
Short name T870
Test name
Test status
Simulation time 23145840350 ps
CPU time 47.11 seconds
Started Jun 30 07:01:15 PM PDT 24
Finished Jun 30 07:02:04 PM PDT 24
Peak memory 249256 kb
Host smart-790129dc-57d8-41aa-874a-c303945a2034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154651919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4154651919
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3229434939
Short name T283
Test name
Test status
Simulation time 145430742 ps
CPU time 5.65 seconds
Started Jun 30 07:01:19 PM PDT 24
Finished Jun 30 07:01:25 PM PDT 24
Peak memory 232668 kb
Host smart-e2db3094-7b82-49c7-9476-2296dc8242a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229434939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3229434939
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1240171366
Short name T271
Test name
Test status
Simulation time 44150882046 ps
CPU time 151.3 seconds
Started Jun 30 07:01:16 PM PDT 24
Finished Jun 30 07:03:49 PM PDT 24
Peak memory 255488 kb
Host smart-ef0ec581-6be5-40d6-bd52-43eff0a38303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240171366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1240171366
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.242145716
Short name T448
Test name
Test status
Simulation time 1155328969 ps
CPU time 6.44 seconds
Started Jun 30 07:01:16 PM PDT 24
Finished Jun 30 07:01:23 PM PDT 24
Peak memory 232616 kb
Host smart-81a372e1-ec42-4902-a5c9-1031a2cf6831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242145716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.242145716
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3558501259
Short name T223
Test name
Test status
Simulation time 6007374116 ps
CPU time 25.39 seconds
Started Jun 30 07:01:15 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 232760 kb
Host smart-d63a71dc-c626-4b4c-85bc-0350bf18a44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558501259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3558501259
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2631246752
Short name T374
Test name
Test status
Simulation time 51923620109 ps
CPU time 32.24 seconds
Started Jun 30 07:01:16 PM PDT 24
Finished Jun 30 07:01:50 PM PDT 24
Peak memory 248964 kb
Host smart-d5c15f99-a89e-40f8-b03d-274c234b582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631246752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2631246752
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3758081175
Short name T692
Test name
Test status
Simulation time 410964734 ps
CPU time 7.58 seconds
Started Jun 30 07:01:17 PM PDT 24
Finished Jun 30 07:01:26 PM PDT 24
Peak memory 232628 kb
Host smart-37f5e221-ac3f-4cc5-b7ed-372a8c2bcfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758081175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3758081175
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.913600755
Short name T560
Test name
Test status
Simulation time 1272909924 ps
CPU time 11.77 seconds
Started Jun 30 07:01:16 PM PDT 24
Finished Jun 30 07:01:30 PM PDT 24
Peak memory 222136 kb
Host smart-c205533b-0e5c-458f-9f95-95edbc0cadd0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=913600755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.913600755
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.601058086
Short name T1011
Test name
Test status
Simulation time 8947330625 ps
CPU time 111.39 seconds
Started Jun 30 07:01:18 PM PDT 24
Finished Jun 30 07:03:11 PM PDT 24
Peak memory 267276 kb
Host smart-6aee3995-c7fd-47da-b450-157ce64b7f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601058086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.601058086
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3595212492
Short name T541
Test name
Test status
Simulation time 299217159 ps
CPU time 3.26 seconds
Started Jun 30 07:01:15 PM PDT 24
Finished Jun 30 07:01:20 PM PDT 24
Peak memory 216372 kb
Host smart-71526d8b-bcd0-438b-bbc8-83ac73f6dc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595212492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3595212492
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3908138994
Short name T455
Test name
Test status
Simulation time 30742353 ps
CPU time 0.74 seconds
Started Jun 30 07:01:15 PM PDT 24
Finished Jun 30 07:01:17 PM PDT 24
Peak memory 205928 kb
Host smart-4ef99ffa-ba0f-425b-a6d8-d46c38be01ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908138994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3908138994
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3485536457
Short name T489
Test name
Test status
Simulation time 100770082 ps
CPU time 1.09 seconds
Started Jun 30 07:01:15 PM PDT 24
Finished Jun 30 07:01:17 PM PDT 24
Peak memory 207888 kb
Host smart-8d5d7e6f-5c9d-4e6b-a959-89c38d8c15dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485536457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3485536457
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3251449707
Short name T746
Test name
Test status
Simulation time 75436306 ps
CPU time 0.95 seconds
Started Jun 30 07:01:17 PM PDT 24
Finished Jun 30 07:01:19 PM PDT 24
Peak memory 205888 kb
Host smart-11bf0361-d4f6-4b1f-9014-895b93a95139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251449707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3251449707
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.524177460
Short name T70
Test name
Test status
Simulation time 12396636163 ps
CPU time 9.91 seconds
Started Jun 30 07:01:14 PM PDT 24
Finished Jun 30 07:01:26 PM PDT 24
Peak memory 232740 kb
Host smart-e256fd8b-1e82-4ad9-9136-c0f41d9fbe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524177460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.524177460
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1990068544
Short name T1013
Test name
Test status
Simulation time 13489192 ps
CPU time 0.74 seconds
Started Jun 30 07:01:21 PM PDT 24
Finished Jun 30 07:01:22 PM PDT 24
Peak memory 205308 kb
Host smart-2c9619a2-8d58-451d-a76e-c595e6080681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990068544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1990068544
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.274090718
Short name T872
Test name
Test status
Simulation time 1551187079 ps
CPU time 6.57 seconds
Started Jun 30 07:01:22 PM PDT 24
Finished Jun 30 07:01:30 PM PDT 24
Peak memory 224424 kb
Host smart-7ee15e9c-46a2-4db0-b832-e9054b3c2c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274090718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.274090718
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1878566302
Short name T860
Test name
Test status
Simulation time 82662358 ps
CPU time 0.79 seconds
Started Jun 30 07:01:13 PM PDT 24
Finished Jun 30 07:01:15 PM PDT 24
Peak memory 206564 kb
Host smart-b988914e-1208-4c42-9242-9bb7d60ac373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878566302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1878566302
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2931525177
Short name T195
Test name
Test status
Simulation time 81723763870 ps
CPU time 161.11 seconds
Started Jun 30 07:01:20 PM PDT 24
Finished Jun 30 07:04:01 PM PDT 24
Peak memory 249216 kb
Host smart-1b950ee3-1883-48cc-ab15-88aa990aea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931525177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2931525177
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4149219798
Short name T11
Test name
Test status
Simulation time 309935244975 ps
CPU time 413.54 seconds
Started Jun 30 07:01:23 PM PDT 24
Finished Jun 30 07:08:17 PM PDT 24
Peak memory 252316 kb
Host smart-1724078f-829d-4c11-9638-cc344b1999cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149219798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4149219798
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3805706398
Short name T932
Test name
Test status
Simulation time 7301592749 ps
CPU time 93.5 seconds
Started Jun 30 07:01:22 PM PDT 24
Finished Jun 30 07:02:56 PM PDT 24
Peak memory 264588 kb
Host smart-9278b6a4-0766-4b0a-b81f-fd66abd39d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805706398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3805706398
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2825918242
Short name T478
Test name
Test status
Simulation time 158250439 ps
CPU time 3.4 seconds
Started Jun 30 07:01:21 PM PDT 24
Finished Jun 30 07:01:25 PM PDT 24
Peak memory 224472 kb
Host smart-b6c42430-7471-408c-9a32-d0a109115a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825918242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2825918242
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.204653645
Short name T531
Test name
Test status
Simulation time 15291397421 ps
CPU time 20.77 seconds
Started Jun 30 07:01:21 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 238832 kb
Host smart-0b372cd2-841f-4334-8525-9144eb1107f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204653645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.204653645
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.982106369
Short name T848
Test name
Test status
Simulation time 650761539 ps
CPU time 7.72 seconds
Started Jun 30 07:01:21 PM PDT 24
Finished Jun 30 07:01:30 PM PDT 24
Peak memory 224408 kb
Host smart-0fd862b2-22ca-4b43-9483-179afb31548c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982106369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.982106369
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3177906038
Short name T950
Test name
Test status
Simulation time 5243921637 ps
CPU time 27.09 seconds
Started Jun 30 07:01:21 PM PDT 24
Finished Jun 30 07:01:49 PM PDT 24
Peak memory 232552 kb
Host smart-590c4f88-e4c9-4f6b-91b2-242c1f7a3442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177906038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3177906038
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1724363166
Short name T366
Test name
Test status
Simulation time 105746744 ps
CPU time 2.15 seconds
Started Jun 30 07:01:22 PM PDT 24
Finished Jun 30 07:01:25 PM PDT 24
Peak memory 224388 kb
Host smart-f105f6a4-0f16-414b-ae97-ef3684a25e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724363166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1724363166
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1821007679
Short name T990
Test name
Test status
Simulation time 1726197177 ps
CPU time 5.73 seconds
Started Jun 30 07:01:21 PM PDT 24
Finished Jun 30 07:01:28 PM PDT 24
Peak memory 232404 kb
Host smart-a7fa3f01-5a5b-4df1-939b-48c9fc6e2da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821007679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1821007679
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2680032236
Short name T471
Test name
Test status
Simulation time 4575524873 ps
CPU time 8.56 seconds
Started Jun 30 07:01:21 PM PDT 24
Finished Jun 30 07:01:30 PM PDT 24
Peak memory 222640 kb
Host smart-f2d4c61f-a847-429c-ba20-c440b34c71da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2680032236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2680032236
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4029545606
Short name T165
Test name
Test status
Simulation time 204840195 ps
CPU time 0.9 seconds
Started Jun 30 07:01:23 PM PDT 24
Finished Jun 30 07:01:24 PM PDT 24
Peak memory 206924 kb
Host smart-dd19ba5a-5739-4ba9-851f-dd5ef8b402b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029545606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4029545606
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1955241148
Short name T50
Test name
Test status
Simulation time 2685742781 ps
CPU time 7.4 seconds
Started Jun 30 07:01:21 PM PDT 24
Finished Jun 30 07:01:29 PM PDT 24
Peak memory 218560 kb
Host smart-1f491e9f-c596-4e0b-b6f9-8af84f5c3bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955241148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1955241148
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3836336735
Short name T821
Test name
Test status
Simulation time 344648978 ps
CPU time 1.7 seconds
Started Jun 30 07:01:17 PM PDT 24
Finished Jun 30 07:01:21 PM PDT 24
Peak memory 207704 kb
Host smart-8e1a1739-f6c5-429c-b223-adc7a08f8e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836336735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3836336735
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2078594752
Short name T315
Test name
Test status
Simulation time 16251256 ps
CPU time 0.83 seconds
Started Jun 30 07:01:24 PM PDT 24
Finished Jun 30 07:01:25 PM PDT 24
Peak memory 206708 kb
Host smart-4cc32fc4-30fa-4731-a40a-e835f0d5de69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078594752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2078594752
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3868513256
Short name T844
Test name
Test status
Simulation time 64150931 ps
CPU time 0.92 seconds
Started Jun 30 07:01:20 PM PDT 24
Finished Jun 30 07:01:22 PM PDT 24
Peak memory 205892 kb
Host smart-d285c48c-e106-418b-a082-dc3d8bc62084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868513256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3868513256
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1927965250
Short name T699
Test name
Test status
Simulation time 463909584 ps
CPU time 2.17 seconds
Started Jun 30 07:01:19 PM PDT 24
Finished Jun 30 07:01:22 PM PDT 24
Peak memory 224120 kb
Host smart-ca620d31-41fb-40c8-abab-79e24449b9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927965250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1927965250
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.162251999
Short name T700
Test name
Test status
Simulation time 10738383 ps
CPU time 0.69 seconds
Started Jun 30 07:01:28 PM PDT 24
Finished Jun 30 07:01:29 PM PDT 24
Peak memory 204844 kb
Host smart-a49b0fc0-f3cc-4bb0-88f4-3ea66673d327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162251999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.162251999
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2789712424
Short name T380
Test name
Test status
Simulation time 226636734 ps
CPU time 2.26 seconds
Started Jun 30 07:01:30 PM PDT 24
Finished Jun 30 07:01:34 PM PDT 24
Peak memory 224400 kb
Host smart-fefa91e7-a22d-4b5b-ab9c-25738c1f9466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789712424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2789712424
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3104611165
Short name T593
Test name
Test status
Simulation time 16227350 ps
CPU time 0.76 seconds
Started Jun 30 07:01:23 PM PDT 24
Finished Jun 30 07:01:24 PM PDT 24
Peak memory 206868 kb
Host smart-3d80f2f3-c0e4-45e0-b7cf-b9d64e3ef238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104611165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3104611165
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2328565023
Short name T225
Test name
Test status
Simulation time 9012513292 ps
CPU time 64.11 seconds
Started Jun 30 07:01:28 PM PDT 24
Finished Jun 30 07:02:34 PM PDT 24
Peak memory 253728 kb
Host smart-01b941a6-9f37-4c24-9837-e3da5d6ab14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328565023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2328565023
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.509766589
Short name T246
Test name
Test status
Simulation time 226696327497 ps
CPU time 333.85 seconds
Started Jun 30 07:01:27 PM PDT 24
Finished Jun 30 07:07:01 PM PDT 24
Peak memory 255180 kb
Host smart-450e8ac1-1ab0-4cac-8a73-fcd751bf4f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509766589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.509766589
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2951600382
Short name T979
Test name
Test status
Simulation time 3293718225 ps
CPU time 9.99 seconds
Started Jun 30 07:01:28 PM PDT 24
Finished Jun 30 07:01:39 PM PDT 24
Peak memory 224504 kb
Host smart-f8a4bbac-66e9-4997-a4d6-c4b6ebab385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951600382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2951600382
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4179031823
Short name T511
Test name
Test status
Simulation time 262498731 ps
CPU time 8.91 seconds
Started Jun 30 07:01:27 PM PDT 24
Finished Jun 30 07:01:37 PM PDT 24
Peak memory 224436 kb
Host smart-204f440a-8eb7-4686-bc0e-887998edd647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179031823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4179031823
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.4070677690
Short name T702
Test name
Test status
Simulation time 4195475587 ps
CPU time 32.66 seconds
Started Jun 30 07:01:29 PM PDT 24
Finished Jun 30 07:02:03 PM PDT 24
Peak memory 236728 kb
Host smart-f67f53bc-a688-4b2c-9ed9-015823c2bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070677690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.4070677690
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.607153020
Short name T362
Test name
Test status
Simulation time 183590596 ps
CPU time 2.24 seconds
Started Jun 30 07:01:29 PM PDT 24
Finished Jun 30 07:01:32 PM PDT 24
Peak memory 223440 kb
Host smart-a4234c96-e6b0-4c3f-9d35-b63319e87452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607153020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.607153020
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2887858059
Short name T461
Test name
Test status
Simulation time 16626578637 ps
CPU time 36.54 seconds
Started Jun 30 07:01:29 PM PDT 24
Finished Jun 30 07:02:07 PM PDT 24
Peak memory 218800 kb
Host smart-81347a87-1f61-4d0a-bc0f-ab915f812a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887858059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2887858059
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.647493098
Short name T248
Test name
Test status
Simulation time 400198694 ps
CPU time 3.74 seconds
Started Jun 30 07:01:22 PM PDT 24
Finished Jun 30 07:01:27 PM PDT 24
Peak memory 224420 kb
Host smart-d4130d83-efbd-4cb8-84f1-526b0519701b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647493098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.647493098
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1407054357
Short name T532
Test name
Test status
Simulation time 5380484041 ps
CPU time 11 seconds
Started Jun 30 07:01:22 PM PDT 24
Finished Jun 30 07:01:34 PM PDT 24
Peak memory 224572 kb
Host smart-bfb55111-e31b-4139-af1c-a2e207fb0e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407054357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1407054357
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2332318862
Short name T394
Test name
Test status
Simulation time 1304968815 ps
CPU time 10.58 seconds
Started Jun 30 07:01:28 PM PDT 24
Finished Jun 30 07:01:39 PM PDT 24
Peak memory 219348 kb
Host smart-8bcbaefc-80c4-4e44-a804-03804351f332
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2332318862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2332318862
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2269317272
Short name T432
Test name
Test status
Simulation time 827387842 ps
CPU time 12.71 seconds
Started Jun 30 07:01:23 PM PDT 24
Finished Jun 30 07:01:36 PM PDT 24
Peak memory 216240 kb
Host smart-ac936505-e320-4ba9-acd5-b7fb2f5a60ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269317272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2269317272
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2927974124
Short name T331
Test name
Test status
Simulation time 8437409595 ps
CPU time 2.5 seconds
Started Jun 30 07:01:19 PM PDT 24
Finished Jun 30 07:01:22 PM PDT 24
Peak memory 207996 kb
Host smart-18ded0bf-9afa-440a-8237-b1ba6bc331ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927974124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2927974124
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2604290149
Short name T76
Test name
Test status
Simulation time 98323140 ps
CPU time 0.94 seconds
Started Jun 30 07:01:23 PM PDT 24
Finished Jun 30 07:01:24 PM PDT 24
Peak memory 206960 kb
Host smart-3a3896fd-34ee-4a4a-b1cf-517029328007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604290149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2604290149
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3848350044
Short name T918
Test name
Test status
Simulation time 15031579 ps
CPU time 0.82 seconds
Started Jun 30 07:01:21 PM PDT 24
Finished Jun 30 07:01:23 PM PDT 24
Peak memory 205896 kb
Host smart-44261aa9-78cc-4f02-920d-96e611864f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848350044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3848350044
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3706817412
Short name T627
Test name
Test status
Simulation time 3577807534 ps
CPU time 15.25 seconds
Started Jun 30 07:01:30 PM PDT 24
Finished Jun 30 07:01:47 PM PDT 24
Peak memory 239216 kb
Host smart-4575fdc6-8fc2-4a90-b270-43db7695cc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706817412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3706817412
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3890206341
Short name T559
Test name
Test status
Simulation time 38074205 ps
CPU time 0.72 seconds
Started Jun 30 07:01:35 PM PDT 24
Finished Jun 30 07:01:36 PM PDT 24
Peak memory 205668 kb
Host smart-e596778b-2231-4ed8-85de-2943be99b726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890206341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3890206341
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3846595432
Short name T573
Test name
Test status
Simulation time 273100844 ps
CPU time 2.91 seconds
Started Jun 30 07:01:29 PM PDT 24
Finished Jun 30 07:01:33 PM PDT 24
Peak memory 232888 kb
Host smart-a331c0ca-b147-4215-8d58-89d03f950f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846595432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3846595432
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4251083068
Short name T743
Test name
Test status
Simulation time 38916853 ps
CPU time 0.74 seconds
Started Jun 30 07:01:28 PM PDT 24
Finished Jun 30 07:01:30 PM PDT 24
Peak memory 206888 kb
Host smart-eaa8c2a3-2189-44d7-9fef-9cef0e5d97f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251083068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4251083068
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2988857155
Short name T512
Test name
Test status
Simulation time 19071536765 ps
CPU time 149.3 seconds
Started Jun 30 07:01:35 PM PDT 24
Finished Jun 30 07:04:06 PM PDT 24
Peak memory 253576 kb
Host smart-606e48f6-8627-4b82-bf2e-f211bf9eaf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988857155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2988857155
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.521395637
Short name T588
Test name
Test status
Simulation time 28989988377 ps
CPU time 107.42 seconds
Started Jun 30 07:01:38 PM PDT 24
Finished Jun 30 07:03:26 PM PDT 24
Peak memory 266596 kb
Host smart-75a26d38-28b5-4828-8499-97663cac8ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521395637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.521395637
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2766734600
Short name T992
Test name
Test status
Simulation time 4078430874 ps
CPU time 41.53 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:02:16 PM PDT 24
Peak memory 238700 kb
Host smart-828a65f7-6f99-4ee2-b537-3c6cb9100450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766734600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2766734600
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2557086992
Short name T280
Test name
Test status
Simulation time 1605827600 ps
CPU time 12.23 seconds
Started Jun 30 07:01:27 PM PDT 24
Finished Jun 30 07:01:40 PM PDT 24
Peak memory 224476 kb
Host smart-c32c7c39-98ea-47da-b9eb-ed402b1aae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557086992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2557086992
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1199431940
Short name T796
Test name
Test status
Simulation time 21230951328 ps
CPU time 155.1 seconds
Started Jun 30 07:01:28 PM PDT 24
Finished Jun 30 07:04:04 PM PDT 24
Peak memory 251932 kb
Host smart-a1652ff0-e76c-44d6-a2ae-52254b808536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199431940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1199431940
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3560607274
Short name T789
Test name
Test status
Simulation time 12331875722 ps
CPU time 27.55 seconds
Started Jun 30 07:01:29 PM PDT 24
Finished Jun 30 07:01:58 PM PDT 24
Peak memory 232756 kb
Host smart-f3bacffa-cd79-496d-8c7b-faedc73b953c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560607274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3560607274
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1810151574
Short name T485
Test name
Test status
Simulation time 418766496 ps
CPU time 2.34 seconds
Started Jun 30 07:01:30 PM PDT 24
Finished Jun 30 07:01:34 PM PDT 24
Peak memory 223760 kb
Host smart-85e7a9ea-d363-449e-a07b-9bdb696eb1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810151574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1810151574
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1753323976
Short name T1006
Test name
Test status
Simulation time 146648914 ps
CPU time 3.95 seconds
Started Jun 30 07:01:28 PM PDT 24
Finished Jun 30 07:01:33 PM PDT 24
Peak memory 232648 kb
Host smart-eec730c7-f0e5-424b-98f0-4eb7347e9e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753323976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1753323976
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2316831660
Short name T645
Test name
Test status
Simulation time 732617956 ps
CPU time 9.05 seconds
Started Jun 30 07:01:31 PM PDT 24
Finished Jun 30 07:01:41 PM PDT 24
Peak memory 249064 kb
Host smart-2821e1ed-bd8e-4447-b18b-826020c1a895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316831660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2316831660
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1063554047
Short name T855
Test name
Test status
Simulation time 984409808 ps
CPU time 11.4 seconds
Started Jun 30 07:01:29 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 219968 kb
Host smart-f0917919-ecd5-4d1b-aeba-cfc77f7651a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1063554047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1063554047
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.722238337
Short name T259
Test name
Test status
Simulation time 126667621738 ps
CPU time 366.3 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:07:49 PM PDT 24
Peak memory 266372 kb
Host smart-20d82bd7-011f-49a3-9213-fd366897ec32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722238337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.722238337
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2074195847
Short name T289
Test name
Test status
Simulation time 5156418812 ps
CPU time 14.92 seconds
Started Jun 30 07:01:30 PM PDT 24
Finished Jun 30 07:01:47 PM PDT 24
Peak memory 219496 kb
Host smart-c7ba4ef8-a113-4832-9e8b-173a5214170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074195847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2074195847
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2017271931
Short name T681
Test name
Test status
Simulation time 22188896 ps
CPU time 0.7 seconds
Started Jun 30 07:01:30 PM PDT 24
Finished Jun 30 07:01:32 PM PDT 24
Peak memory 205624 kb
Host smart-3e6ca1fe-e528-417f-8605-004f95e47daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017271931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2017271931
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3659198832
Short name T697
Test name
Test status
Simulation time 109147959 ps
CPU time 1.09 seconds
Started Jun 30 07:01:29 PM PDT 24
Finished Jun 30 07:01:32 PM PDT 24
Peak memory 207864 kb
Host smart-143cc3c8-5ab4-4e1b-a4e3-3955bb0cae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659198832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3659198832
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.4055685696
Short name T732
Test name
Test status
Simulation time 73362600 ps
CPU time 0.8 seconds
Started Jun 30 07:01:30 PM PDT 24
Finished Jun 30 07:01:32 PM PDT 24
Peak memory 205892 kb
Host smart-4ba3b01f-cf18-40b3-8e5c-852bac38aef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055685696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4055685696
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1333837829
Short name T822
Test name
Test status
Simulation time 1959099842 ps
CPU time 7.86 seconds
Started Jun 30 07:01:30 PM PDT 24
Finished Jun 30 07:01:39 PM PDT 24
Peak memory 232596 kb
Host smart-fdd55625-f111-4bce-bd83-11be67da7408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333837829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1333837829
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.360330368
Short name T960
Test name
Test status
Simulation time 14898000 ps
CPU time 0.78 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:01:36 PM PDT 24
Peak memory 204828 kb
Host smart-304d9628-de29-4e6c-8358-7149b0657898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360330368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.360330368
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1384952198
Short name T460
Test name
Test status
Simulation time 166103280 ps
CPU time 3.43 seconds
Started Jun 30 07:01:38 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 232616 kb
Host smart-f4f377ca-09ee-4344-899b-97acfd0b69b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384952198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1384952198
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3741012281
Short name T877
Test name
Test status
Simulation time 52854031 ps
CPU time 0.84 seconds
Started Jun 30 07:01:36 PM PDT 24
Finished Jun 30 07:01:38 PM PDT 24
Peak memory 206568 kb
Host smart-075cd083-5f80-41f6-9847-29af8b3fe9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741012281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3741012281
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2050989212
Short name T351
Test name
Test status
Simulation time 7284912613 ps
CPU time 22.73 seconds
Started Jun 30 07:01:36 PM PDT 24
Finished Jun 30 07:02:00 PM PDT 24
Peak memory 236108 kb
Host smart-ddcb87be-34d9-4367-9c78-cc57a544b2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050989212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2050989212
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.195601859
Short name T975
Test name
Test status
Simulation time 99220675481 ps
CPU time 69.61 seconds
Started Jun 30 07:01:38 PM PDT 24
Finished Jun 30 07:02:48 PM PDT 24
Peak memory 224592 kb
Host smart-7d7cf327-5d15-4a56-a076-ee35266f1be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195601859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.195601859
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.443296705
Short name T277
Test name
Test status
Simulation time 1102842870 ps
CPU time 7.66 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 224424 kb
Host smart-91ef954d-983f-4cb5-b267-7b9d22f91697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443296705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.443296705
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2314514686
Short name T863
Test name
Test status
Simulation time 48150182409 ps
CPU time 316.71 seconds
Started Jun 30 07:01:37 PM PDT 24
Finished Jun 30 07:06:54 PM PDT 24
Peak memory 252784 kb
Host smart-683caf9f-e680-46ae-b907-ec93908eae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314514686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2314514686
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.184900119
Short name T237
Test name
Test status
Simulation time 1146472267 ps
CPU time 5.85 seconds
Started Jun 30 07:01:35 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 224452 kb
Host smart-764f7de3-107e-436b-9e2c-d816de4e0829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184900119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.184900119
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4244474121
Short name T136
Test name
Test status
Simulation time 1720696500 ps
CPU time 11.9 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:01:47 PM PDT 24
Peak memory 224448 kb
Host smart-0be16f2e-9c07-4936-ba53-899d932af6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244474121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4244474121
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1322694509
Short name T521
Test name
Test status
Simulation time 101047783 ps
CPU time 2.74 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:01:46 PM PDT 24
Peak memory 232352 kb
Host smart-98debdf0-6586-4ba2-81c4-c12931a6a09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322694509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1322694509
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3008730429
Short name T1010
Test name
Test status
Simulation time 37008145497 ps
CPU time 19.46 seconds
Started Jun 30 07:01:39 PM PDT 24
Finished Jun 30 07:01:59 PM PDT 24
Peak memory 240752 kb
Host smart-7746ca34-6771-4a6c-968b-0706d9e73788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008730429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3008730429
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2449705188
Short name T118
Test name
Test status
Simulation time 1596331459 ps
CPU time 13.53 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:01:48 PM PDT 24
Peak memory 221896 kb
Host smart-b68c6705-780f-4e53-9ba6-37ed2858f97e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2449705188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2449705188
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2514824180
Short name T16
Test name
Test status
Simulation time 13435750764 ps
CPU time 123.44 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:03:38 PM PDT 24
Peak memory 249260 kb
Host smart-1d750ee5-61b0-427a-ac2d-97fa4b9eba82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514824180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2514824180
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.588910857
Short name T1012
Test name
Test status
Simulation time 4295626169 ps
CPU time 21.55 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:01:57 PM PDT 24
Peak memory 216304 kb
Host smart-5b916cf3-8a65-4d9c-b561-8184c1a6ab65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588910857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.588910857
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1416578053
Short name T655
Test name
Test status
Simulation time 2326604094 ps
CPU time 6.79 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:01:41 PM PDT 24
Peak memory 216244 kb
Host smart-4125f05e-3a7b-441b-91a0-ae64f41148aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416578053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1416578053
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.395813600
Short name T354
Test name
Test status
Simulation time 19409518 ps
CPU time 0.71 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:01:36 PM PDT 24
Peak memory 205872 kb
Host smart-71e7b392-29c7-48a3-ab79-0eefe1928e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395813600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.395813600
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3053495713
Short name T745
Test name
Test status
Simulation time 109394569 ps
CPU time 0.79 seconds
Started Jun 30 07:01:36 PM PDT 24
Finished Jun 30 07:01:38 PM PDT 24
Peak memory 205892 kb
Host smart-8a7dfb17-e478-4711-8a39-53a779e40ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053495713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3053495713
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1391122076
Short name T444
Test name
Test status
Simulation time 2763724233 ps
CPU time 10.97 seconds
Started Jun 30 07:01:37 PM PDT 24
Finished Jun 30 07:01:49 PM PDT 24
Peak memory 232736 kb
Host smart-4c2567a0-6400-4f9f-adfd-4d5d790a4f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391122076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1391122076
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.592871628
Short name T487
Test name
Test status
Simulation time 36960260 ps
CPU time 0.72 seconds
Started Jun 30 07:01:38 PM PDT 24
Finished Jun 30 07:01:40 PM PDT 24
Peak memory 205768 kb
Host smart-c7b43768-594f-4e35-96b9-4e85a93d7006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592871628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.592871628
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3758441267
Short name T574
Test name
Test status
Simulation time 281313776 ps
CPU time 4.46 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:01:39 PM PDT 24
Peak memory 224436 kb
Host smart-d69c243e-788e-4a60-890c-c872cda4a496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758441267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3758441267
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2103399729
Short name T389
Test name
Test status
Simulation time 58189582 ps
CPU time 0.76 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:01:44 PM PDT 24
Peak memory 205508 kb
Host smart-8f15afb1-ed99-4a1c-ae9f-b7def597280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103399729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2103399729
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1170387113
Short name T612
Test name
Test status
Simulation time 3469813228 ps
CPU time 68.29 seconds
Started Jun 30 07:01:38 PM PDT 24
Finished Jun 30 07:02:47 PM PDT 24
Peak memory 255348 kb
Host smart-0bc414bb-b0a5-4a7e-b689-0d4ae48e2f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170387113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1170387113
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.841270641
Short name T339
Test name
Test status
Simulation time 606474313 ps
CPU time 6.41 seconds
Started Jun 30 07:01:37 PM PDT 24
Finished Jun 30 07:01:44 PM PDT 24
Peak memory 232604 kb
Host smart-80103a4c-6c02-443a-be2a-ebeb9daf29a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841270641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.841270641
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2595594692
Short name T274
Test name
Test status
Simulation time 4030039033 ps
CPU time 54.84 seconds
Started Jun 30 07:01:40 PM PDT 24
Finished Jun 30 07:02:35 PM PDT 24
Peak memory 249120 kb
Host smart-07eb09a8-267e-4613-b33a-bd98c7328436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595594692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2595594692
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2433471832
Short name T221
Test name
Test status
Simulation time 758554465 ps
CPU time 10.62 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:01:45 PM PDT 24
Peak memory 232852 kb
Host smart-025ed7fc-0c76-458b-86d6-dd91145b7373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433471832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2433471832
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3773884348
Short name T853
Test name
Test status
Simulation time 1360127423 ps
CPU time 19.49 seconds
Started Jun 30 07:01:35 PM PDT 24
Finished Jun 30 07:01:56 PM PDT 24
Peak memory 232620 kb
Host smart-4b0c08f2-c2ba-489c-bb48-159867fc2e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773884348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3773884348
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2061715195
Short name T576
Test name
Test status
Simulation time 152327300 ps
CPU time 2.23 seconds
Started Jun 30 07:01:36 PM PDT 24
Finished Jun 30 07:01:39 PM PDT 24
Peak memory 223608 kb
Host smart-f929a549-41b0-43f9-8a6f-cf403dcedb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061715195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2061715195
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3441025649
Short name T682
Test name
Test status
Simulation time 1982106830 ps
CPU time 6.72 seconds
Started Jun 30 07:01:36 PM PDT 24
Finished Jun 30 07:01:43 PM PDT 24
Peak memory 224452 kb
Host smart-28892c31-cb32-4c21-be9d-12c418c5bfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441025649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3441025649
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1256676177
Short name T836
Test name
Test status
Simulation time 348651462 ps
CPU time 3.4 seconds
Started Jun 30 07:01:38 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 219220 kb
Host smart-12ec1687-53aa-4e32-9c4d-0a61e6af670a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1256676177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1256676177
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2981061103
Short name T922
Test name
Test status
Simulation time 263538579404 ps
CPU time 275.48 seconds
Started Jun 30 07:01:39 PM PDT 24
Finished Jun 30 07:06:15 PM PDT 24
Peak memory 264424 kb
Host smart-f5b9e5ae-2769-47be-ac42-ed43e7530dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981061103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2981061103
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2802855165
Short name T687
Test name
Test status
Simulation time 23897996398 ps
CPU time 35.26 seconds
Started Jun 30 07:01:33 PM PDT 24
Finished Jun 30 07:02:09 PM PDT 24
Peak memory 216332 kb
Host smart-2c27fd37-693c-4fe3-9da7-051b74f529ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802855165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2802855165
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3878474100
Short name T547
Test name
Test status
Simulation time 2190070711 ps
CPU time 4.23 seconds
Started Jun 30 07:01:37 PM PDT 24
Finished Jun 30 07:01:42 PM PDT 24
Peak memory 216204 kb
Host smart-a7e6dcf5-3a54-43f7-bf95-9a734233a835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878474100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3878474100
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2114571485
Short name T915
Test name
Test status
Simulation time 23630419 ps
CPU time 1.33 seconds
Started Jun 30 07:01:37 PM PDT 24
Finished Jun 30 07:01:39 PM PDT 24
Peak memory 208016 kb
Host smart-d82c5bad-4714-4c55-a604-59e9a633daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114571485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2114571485
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2605332411
Short name T625
Test name
Test status
Simulation time 70985325 ps
CPU time 0.73 seconds
Started Jun 30 07:01:35 PM PDT 24
Finished Jun 30 07:01:37 PM PDT 24
Peak memory 205812 kb
Host smart-87746d8d-033d-4f77-85d2-da3816ca6050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605332411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2605332411
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.968246785
Short name T427
Test name
Test status
Simulation time 4548472627 ps
CPU time 14.55 seconds
Started Jun 30 07:01:33 PM PDT 24
Finished Jun 30 07:01:48 PM PDT 24
Peak memory 232776 kb
Host smart-bf6c6a88-1c59-42ea-a60d-38355c2d1bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968246785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.968246785
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2292750376
Short name T458
Test name
Test status
Simulation time 46416701 ps
CPU time 0.74 seconds
Started Jun 30 07:01:44 PM PDT 24
Finished Jun 30 07:01:45 PM PDT 24
Peak memory 205480 kb
Host smart-5cc85c27-7938-46b1-af80-e05b4c7bd8f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292750376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2292750376
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3813957008
Short name T1014
Test name
Test status
Simulation time 105773828 ps
CPU time 2.62 seconds
Started Jun 30 07:01:40 PM PDT 24
Finished Jun 30 07:01:43 PM PDT 24
Peak memory 232668 kb
Host smart-244acbd3-a0e4-45e0-96d6-b94d5e6c2734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813957008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3813957008
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2893806938
Short name T386
Test name
Test status
Simulation time 56744622 ps
CPU time 0.82 seconds
Started Jun 30 07:01:34 PM PDT 24
Finished Jun 30 07:01:36 PM PDT 24
Peak memory 206472 kb
Host smart-37044405-1570-44df-87e4-c4d8ab466873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893806938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2893806938
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3943444107
Short name T771
Test name
Test status
Simulation time 11316184346 ps
CPU time 119.73 seconds
Started Jun 30 07:01:43 PM PDT 24
Finished Jun 30 07:03:43 PM PDT 24
Peak memory 250480 kb
Host smart-86c92889-cb2d-4e27-89ed-c5ffe1939793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943444107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3943444107
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1125039699
Short name T145
Test name
Test status
Simulation time 59611061505 ps
CPU time 543.16 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:10:46 PM PDT 24
Peak memory 265772 kb
Host smart-249c4473-e13b-4ce4-86c0-1ab5de5487b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125039699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1125039699
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2950778487
Short name T408
Test name
Test status
Simulation time 32365640687 ps
CPU time 59.56 seconds
Started Jun 30 07:01:44 PM PDT 24
Finished Jun 30 07:02:44 PM PDT 24
Peak memory 241292 kb
Host smart-7a381ef7-f770-49b8-a422-42544a760db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950778487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2950778487
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.4271929845
Short name T994
Test name
Test status
Simulation time 1470843625 ps
CPU time 17.33 seconds
Started Jun 30 07:01:41 PM PDT 24
Finished Jun 30 07:01:59 PM PDT 24
Peak memory 240828 kb
Host smart-a3869fa3-019d-40ff-bb5f-ffb8e9b49184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271929845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4271929845
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1313602221
Short name T1020
Test name
Test status
Simulation time 28550385293 ps
CPU time 107.12 seconds
Started Jun 30 07:01:43 PM PDT 24
Finished Jun 30 07:03:31 PM PDT 24
Peak memory 240596 kb
Host smart-033bac62-5dd0-4438-84ad-4c70a579cb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313602221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1313602221
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.66096131
Short name T91
Test name
Test status
Simulation time 19729576444 ps
CPU time 39.96 seconds
Started Jun 30 07:01:40 PM PDT 24
Finished Jun 30 07:02:21 PM PDT 24
Peak memory 224484 kb
Host smart-87ceefc7-3aed-4ef0-8c08-ef357d3ae5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66096131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.66096131
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2169620556
Short name T928
Test name
Test status
Simulation time 1816958143 ps
CPU time 17.98 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:02:01 PM PDT 24
Peak memory 224444 kb
Host smart-7b4c79e9-2e48-4e5c-b70a-f49183ff36ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169620556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2169620556
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2238343087
Short name T554
Test name
Test status
Simulation time 8385514764 ps
CPU time 13.54 seconds
Started Jun 30 07:01:47 PM PDT 24
Finished Jun 30 07:02:01 PM PDT 24
Peak memory 232764 kb
Host smart-36aeca5c-fad4-492b-8ac5-03efa09e7b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238343087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2238343087
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.809923469
Short name T791
Test name
Test status
Simulation time 2313265367 ps
CPU time 7.06 seconds
Started Jun 30 07:01:45 PM PDT 24
Finished Jun 30 07:01:53 PM PDT 24
Peak memory 224524 kb
Host smart-80f4dabf-f465-4301-bf93-f399fb7e2e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809923469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.809923469
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2327426990
Short name T152
Test name
Test status
Simulation time 878926904 ps
CPU time 7.57 seconds
Started Jun 30 07:01:43 PM PDT 24
Finished Jun 30 07:01:52 PM PDT 24
Peak memory 219192 kb
Host smart-619686ab-7916-434a-af19-c82e0c19dda8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2327426990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2327426990
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.167013709
Short name T163
Test name
Test status
Simulation time 30802418214 ps
CPU time 336.32 seconds
Started Jun 30 07:01:44 PM PDT 24
Finished Jun 30 07:07:21 PM PDT 24
Peak memory 261356 kb
Host smart-762b18ff-2b9a-4c1c-b216-4656374316b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167013709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.167013709
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3154857182
Short name T925
Test name
Test status
Simulation time 1410091087 ps
CPU time 4.67 seconds
Started Jun 30 07:01:41 PM PDT 24
Finished Jun 30 07:01:46 PM PDT 24
Peak memory 216136 kb
Host smart-f11c10bb-a358-494e-a7ec-ef04ffe66d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154857182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3154857182
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1023821572
Short name T974
Test name
Test status
Simulation time 7520256414 ps
CPU time 19.18 seconds
Started Jun 30 07:01:35 PM PDT 24
Finished Jun 30 07:01:56 PM PDT 24
Peak memory 216380 kb
Host smart-1ad3e6f1-3f9c-41c1-8a8b-551aeeb85be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023821572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1023821572
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2357341014
Short name T437
Test name
Test status
Simulation time 50046320 ps
CPU time 0.97 seconds
Started Jun 30 07:01:45 PM PDT 24
Finished Jun 30 07:01:46 PM PDT 24
Peak memory 208136 kb
Host smart-8b466d73-4b8c-4466-8098-a895082fa5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357341014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2357341014
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3739936938
Short name T694
Test name
Test status
Simulation time 102590317 ps
CPU time 1.06 seconds
Started Jun 30 07:01:43 PM PDT 24
Finished Jun 30 07:01:45 PM PDT 24
Peak memory 206892 kb
Host smart-2eab31f2-6536-42ce-9c68-127d9eb4e705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739936938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3739936938
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1777534642
Short name T2
Test name
Test status
Simulation time 384957895 ps
CPU time 6.79 seconds
Started Jun 30 07:01:41 PM PDT 24
Finished Jun 30 07:01:48 PM PDT 24
Peak memory 224440 kb
Host smart-ca981193-ddcb-48c1-9d48-e3fd5eba44a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777534642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1777534642
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.614787461
Short name T421
Test name
Test status
Simulation time 31331697 ps
CPU time 0.75 seconds
Started Jun 30 07:01:49 PM PDT 24
Finished Jun 30 07:01:50 PM PDT 24
Peak memory 205412 kb
Host smart-86ce5d17-b63d-4d87-be13-4a45a64eaac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614787461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.614787461
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2640390458
Short name T824
Test name
Test status
Simulation time 147234132 ps
CPU time 2.73 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:01:46 PM PDT 24
Peak memory 224452 kb
Host smart-1485a984-220f-41b7-9ecd-2c70af10b653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640390458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2640390458
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2262456249
Short name T544
Test name
Test status
Simulation time 35166297 ps
CPU time 0.75 seconds
Started Jun 30 07:01:45 PM PDT 24
Finished Jun 30 07:01:46 PM PDT 24
Peak memory 206532 kb
Host smart-95d0ab40-6320-474d-b594-678fd95f6c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262456249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2262456249
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4191155874
Short name T662
Test name
Test status
Simulation time 6260137313 ps
CPU time 64.43 seconds
Started Jun 30 07:01:41 PM PDT 24
Finished Jun 30 07:02:47 PM PDT 24
Peak memory 265408 kb
Host smart-2506710d-5fca-4d97-b03a-c20e38e36c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191155874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4191155874
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1006652106
Short name T528
Test name
Test status
Simulation time 868335451624 ps
CPU time 420.96 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:08:44 PM PDT 24
Peak memory 265656 kb
Host smart-d61dcffd-6bfb-4bcd-bbd5-47498af325a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006652106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1006652106
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1179100703
Short name T411
Test name
Test status
Simulation time 25918673028 ps
CPU time 214.84 seconds
Started Jun 30 07:01:43 PM PDT 24
Finished Jun 30 07:05:19 PM PDT 24
Peak memory 252896 kb
Host smart-c682d53a-7352-4737-965d-f29cb09f1f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179100703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1179100703
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3217102855
Short name T982
Test name
Test status
Simulation time 393938961 ps
CPU time 5.57 seconds
Started Jun 30 07:01:47 PM PDT 24
Finished Jun 30 07:01:53 PM PDT 24
Peak memory 232712 kb
Host smart-42ff6c1b-fe4f-4d25-97c0-2d70c1378563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217102855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3217102855
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.4190203842
Short name T95
Test name
Test status
Simulation time 29618218505 ps
CPU time 65.06 seconds
Started Jun 30 07:01:40 PM PDT 24
Finished Jun 30 07:02:46 PM PDT 24
Peak memory 240960 kb
Host smart-390b233d-c6e1-46c5-9269-5e191bdc3c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190203842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.4190203842
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2394506236
Short name T488
Test name
Test status
Simulation time 710997380 ps
CPU time 4.82 seconds
Started Jun 30 07:01:47 PM PDT 24
Finished Jun 30 07:01:52 PM PDT 24
Peak memory 232640 kb
Host smart-74ee5912-d586-425a-b963-30837d3b4335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394506236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2394506236
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3403172169
Short name T881
Test name
Test status
Simulation time 604888641 ps
CPU time 6.91 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:01:50 PM PDT 24
Peak memory 224440 kb
Host smart-884d3a19-7b99-4b05-b74c-2c715840492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403172169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3403172169
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2140974627
Short name T676
Test name
Test status
Simulation time 296631699 ps
CPU time 2.56 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:01:46 PM PDT 24
Peak memory 223152 kb
Host smart-fb25caf5-4d1b-4b9e-9f04-543a3584e0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140974627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2140974627
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2849018721
Short name T552
Test name
Test status
Simulation time 89298265 ps
CPU time 2.12 seconds
Started Jun 30 07:01:48 PM PDT 24
Finished Jun 30 07:01:51 PM PDT 24
Peak memory 224280 kb
Host smart-6a63f2fe-4b69-44da-8757-2247254c16cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849018721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2849018721
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.829128305
Short name T364
Test name
Test status
Simulation time 760593313 ps
CPU time 4.57 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:01:48 PM PDT 24
Peak memory 218736 kb
Host smart-728e1e2f-1618-47b7-9802-e22405c1aee1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=829128305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.829128305
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2550193939
Short name T288
Test name
Test status
Simulation time 11881679594 ps
CPU time 76.75 seconds
Started Jun 30 07:01:44 PM PDT 24
Finished Jun 30 07:03:02 PM PDT 24
Peak memory 256468 kb
Host smart-eb4c36ec-5dcf-4f3a-804c-89cc137952b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550193939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2550193939
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3413909277
Short name T431
Test name
Test status
Simulation time 6073926307 ps
CPU time 24.74 seconds
Started Jun 30 07:01:42 PM PDT 24
Finished Jun 30 07:02:08 PM PDT 24
Peak memory 216368 kb
Host smart-dc4667b2-30b2-4971-a9f6-29d94f293901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413909277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3413909277
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2603097001
Short name T306
Test name
Test status
Simulation time 5783172438 ps
CPU time 16.09 seconds
Started Jun 30 07:01:41 PM PDT 24
Finished Jun 30 07:01:58 PM PDT 24
Peak memory 216348 kb
Host smart-df1088d9-dbcd-452d-8a82-598073ecfefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603097001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2603097001
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2585830534
Short name T407
Test name
Test status
Simulation time 40108628 ps
CPU time 0.72 seconds
Started Jun 30 07:01:43 PM PDT 24
Finished Jun 30 07:01:45 PM PDT 24
Peak memory 205600 kb
Host smart-50e3ff2f-7aa3-4108-93f2-47419f72746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585830534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2585830534
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.164535371
Short name T752
Test name
Test status
Simulation time 137125472 ps
CPU time 0.97 seconds
Started Jun 30 07:01:41 PM PDT 24
Finished Jun 30 07:01:44 PM PDT 24
Peak memory 206912 kb
Host smart-c26bcf6e-e5bf-4676-8e2e-35e16948a8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164535371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.164535371
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2709725033
Short name T642
Test name
Test status
Simulation time 1515031741 ps
CPU time 7.88 seconds
Started Jun 30 07:01:43 PM PDT 24
Finished Jun 30 07:01:51 PM PDT 24
Peak memory 232668 kb
Host smart-d5208970-0b87-416b-9bd5-516f66bfda54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709725033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2709725033
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2241353657
Short name T893
Test name
Test status
Simulation time 21539378 ps
CPU time 0.7 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 06:58:49 PM PDT 24
Peak memory 204780 kb
Host smart-8a6b3933-1e3b-4220-a1a4-2ed200963f52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241353657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
241353657
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4015371445
Short name T117
Test name
Test status
Simulation time 8810297446 ps
CPU time 16.01 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 06:59:05 PM PDT 24
Peak memory 232772 kb
Host smart-ab82a90f-15ef-4df2-ab17-ff28989f9a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015371445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4015371445
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1456116185
Short name T439
Test name
Test status
Simulation time 30184099 ps
CPU time 0.77 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 06:58:48 PM PDT 24
Peak memory 205540 kb
Host smart-704e9f1d-c784-40a1-9c87-cb28371317fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456116185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1456116185
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1114677277
Short name T608
Test name
Test status
Simulation time 46253493350 ps
CPU time 159.79 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 07:01:27 PM PDT 24
Peak memory 249316 kb
Host smart-c505c43d-0292-426a-9ff6-2afd473d14c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114677277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1114677277
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3952719662
Short name T649
Test name
Test status
Simulation time 4386122215 ps
CPU time 92.09 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 07:00:20 PM PDT 24
Peak memory 257432 kb
Host smart-67cd27af-f9f4-4d52-a72c-ea2226fadafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952719662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3952719662
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.346728088
Short name T777
Test name
Test status
Simulation time 4501912762 ps
CPU time 41.75 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 06:59:31 PM PDT 24
Peak memory 224504 kb
Host smart-42e860d2-e43f-4637-bdfe-543811553493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346728088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
346728088
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2522433843
Short name T897
Test name
Test status
Simulation time 3464983741 ps
CPU time 15.83 seconds
Started Jun 30 06:58:49 PM PDT 24
Finished Jun 30 06:59:05 PM PDT 24
Peak memory 234996 kb
Host smart-c6ba12fd-f358-4ee5-a67a-d215a31b1e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522433843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2522433843
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.649594933
Short name T967
Test name
Test status
Simulation time 12431557 ps
CPU time 0.76 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 06:58:48 PM PDT 24
Peak memory 215836 kb
Host smart-ba739861-a6c5-4091-8251-d87ff42ae422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649594933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
649594933
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1917905625
Short name T416
Test name
Test status
Simulation time 1092450440 ps
CPU time 4.89 seconds
Started Jun 30 06:58:47 PM PDT 24
Finished Jun 30 06:58:53 PM PDT 24
Peak memory 227820 kb
Host smart-6ae9c541-d1fd-402f-a21f-13f72d40e389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917905625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1917905625
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1188410283
Short name T816
Test name
Test status
Simulation time 428784108 ps
CPU time 4.19 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 06:58:52 PM PDT 24
Peak memory 224424 kb
Host smart-b1884eea-137a-4b91-9fa3-04ca7d4945a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188410283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1188410283
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3410007942
Short name T678
Test name
Test status
Simulation time 17663751 ps
CPU time 1.13 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 06:58:49 PM PDT 24
Peak memory 216768 kb
Host smart-ab6770a2-5edc-461a-a647-84db89a0fb1b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410007942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3410007942
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2309948007
Short name T369
Test name
Test status
Simulation time 561502546 ps
CPU time 4.87 seconds
Started Jun 30 06:58:49 PM PDT 24
Finished Jun 30 06:58:54 PM PDT 24
Peak memory 224428 kb
Host smart-14e2f832-6b27-45c0-a2df-3db032507a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309948007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2309948007
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.955624431
Short name T506
Test name
Test status
Simulation time 2060127955 ps
CPU time 18.36 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 06:59:07 PM PDT 24
Peak memory 219264 kb
Host smart-741a91d0-d584-4b57-ad4e-f87d4310b048
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=955624431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.955624431
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3262312848
Short name T630
Test name
Test status
Simulation time 48009463 ps
CPU time 0.92 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 06:58:48 PM PDT 24
Peak memory 206716 kb
Host smart-6ffd1d25-7938-4670-a7b2-359c374db279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262312848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3262312848
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1920159235
Short name T741
Test name
Test status
Simulation time 2243342487 ps
CPU time 14.12 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 06:59:03 PM PDT 24
Peak memory 216504 kb
Host smart-6219e366-b9ed-4c7d-87f3-370919336a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920159235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1920159235
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2336215486
Short name T717
Test name
Test status
Simulation time 16284143661 ps
CPU time 12.67 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 06:59:02 PM PDT 24
Peak memory 216280 kb
Host smart-f204ef82-c7c5-4a30-8513-ecde72cb81bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336215486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2336215486
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.782152179
Short name T419
Test name
Test status
Simulation time 82893835 ps
CPU time 2.08 seconds
Started Jun 30 06:58:45 PM PDT 24
Finished Jun 30 06:58:49 PM PDT 24
Peak memory 216216 kb
Host smart-0229b72b-83ae-4e78-8d5f-1eb887e5fe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782152179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.782152179
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.311424847
Short name T813
Test name
Test status
Simulation time 79100269 ps
CPU time 0.97 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 06:58:50 PM PDT 24
Peak memory 207164 kb
Host smart-fb6f7a02-99ea-4f87-9867-4d79bfd7ce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311424847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.311424847
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1480640391
Short name T669
Test name
Test status
Simulation time 7120898490 ps
CPU time 10.09 seconds
Started Jun 30 06:58:46 PM PDT 24
Finished Jun 30 06:58:58 PM PDT 24
Peak memory 240972 kb
Host smart-a9b2fa7c-0a2d-4723-913f-95b5c4d3df26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480640391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1480640391
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3555910873
Short name T618
Test name
Test status
Simulation time 25546073 ps
CPU time 0.73 seconds
Started Jun 30 06:58:53 PM PDT 24
Finished Jun 30 06:58:54 PM PDT 24
Peak memory 205424 kb
Host smart-d1c22456-c75c-42e5-95d7-436da9d1c844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555910873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
555910873
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.952019844
Short name T454
Test name
Test status
Simulation time 1253336702 ps
CPU time 5.75 seconds
Started Jun 30 06:58:53 PM PDT 24
Finished Jun 30 06:59:00 PM PDT 24
Peak memory 232684 kb
Host smart-5cbee069-ed71-4e2f-a6e4-11ddd7c0c153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952019844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.952019844
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.542334498
Short name T648
Test name
Test status
Simulation time 18034135 ps
CPU time 0.76 seconds
Started Jun 30 06:58:48 PM PDT 24
Finished Jun 30 06:58:50 PM PDT 24
Peak memory 205776 kb
Host smart-c485a3ec-0299-4b20-b506-d3d233747ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542334498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.542334498
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1114312046
Short name T715
Test name
Test status
Simulation time 63011814150 ps
CPU time 123.03 seconds
Started Jun 30 06:58:54 PM PDT 24
Finished Jun 30 07:00:58 PM PDT 24
Peak memory 250568 kb
Host smart-4e1325e1-b822-4ca5-a7b1-d204b359e6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114312046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1114312046
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.167428365
Short name T275
Test name
Test status
Simulation time 11467029431 ps
CPU time 187.94 seconds
Started Jun 30 06:58:57 PM PDT 24
Finished Jun 30 07:02:06 PM PDT 24
Peak memory 257452 kb
Host smart-71ede0df-4782-442b-ab93-7a570594a288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167428365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.167428365
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2225251508
Short name T476
Test name
Test status
Simulation time 20382384908 ps
CPU time 44.39 seconds
Started Jun 30 06:58:50 PM PDT 24
Finished Jun 30 06:59:35 PM PDT 24
Peak memory 232752 kb
Host smart-c3f9f624-98fe-4784-bd6e-f28f79292392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225251508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2225251508
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3344310159
Short name T887
Test name
Test status
Simulation time 1106270553 ps
CPU time 8.07 seconds
Started Jun 30 06:58:55 PM PDT 24
Finished Jun 30 06:59:04 PM PDT 24
Peak memory 240836 kb
Host smart-5ab6fab5-2dd2-45d4-b08a-dcea873e0b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344310159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3344310159
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.591320404
Short name T622
Test name
Test status
Simulation time 51411139403 ps
CPU time 90.58 seconds
Started Jun 30 06:58:52 PM PDT 24
Finished Jun 30 07:00:23 PM PDT 24
Peak memory 253360 kb
Host smart-bee5b747-2239-4055-8d8c-e7bb1b231c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591320404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
591320404
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2257407334
Short name T96
Test name
Test status
Simulation time 3339948384 ps
CPU time 5.44 seconds
Started Jun 30 06:58:52 PM PDT 24
Finished Jun 30 06:58:58 PM PDT 24
Peak memory 224504 kb
Host smart-8968fc41-4088-4edc-b3d1-9d2d2887042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257407334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2257407334
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3555645077
Short name T231
Test name
Test status
Simulation time 5618514977 ps
CPU time 13 seconds
Started Jun 30 06:58:53 PM PDT 24
Finished Jun 30 06:59:07 PM PDT 24
Peak memory 233764 kb
Host smart-7dff104f-7a2a-4d39-a9ce-6a06f0e0f325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555645077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3555645077
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2588058272
Short name T1019
Test name
Test status
Simulation time 32768870 ps
CPU time 1.11 seconds
Started Jun 30 06:58:52 PM PDT 24
Finished Jun 30 06:58:54 PM PDT 24
Peak memory 218016 kb
Host smart-98096d5c-7825-4984-bc39-4b72b0cfe902
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588058272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2588058272
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2274060615
Short name T406
Test name
Test status
Simulation time 1329237511 ps
CPU time 2.81 seconds
Started Jun 30 06:58:52 PM PDT 24
Finished Jun 30 06:58:55 PM PDT 24
Peak memory 224440 kb
Host smart-d55ae5b6-f736-4534-8c70-1005508e7c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274060615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2274060615
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2561984721
Short name T658
Test name
Test status
Simulation time 1303286255 ps
CPU time 11.33 seconds
Started Jun 30 06:58:55 PM PDT 24
Finished Jun 30 06:59:07 PM PDT 24
Peak memory 233696 kb
Host smart-cefe97ea-730f-4398-95fb-6c65bfdd76ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561984721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2561984721
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1273007021
Short name T10
Test name
Test status
Simulation time 491551663 ps
CPU time 4.37 seconds
Started Jun 30 06:58:55 PM PDT 24
Finished Jun 30 06:59:01 PM PDT 24
Peak memory 222440 kb
Host smart-8888ba97-3703-4a60-ad66-3a0c967558f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1273007021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1273007021
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3681977632
Short name T748
Test name
Test status
Simulation time 2036734961 ps
CPU time 9.31 seconds
Started Jun 30 06:58:54 PM PDT 24
Finished Jun 30 06:59:05 PM PDT 24
Peak memory 216212 kb
Host smart-d6a8e495-c3b9-484d-9553-62d5d3d10835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681977632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3681977632
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.730748902
Short name T594
Test name
Test status
Simulation time 7999426459 ps
CPU time 4.5 seconds
Started Jun 30 06:58:55 PM PDT 24
Finished Jun 30 06:59:01 PM PDT 24
Peak memory 216340 kb
Host smart-975e1d9c-1e6b-4778-a90b-2d5476e25295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730748902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.730748902
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.916157836
Short name T325
Test name
Test status
Simulation time 40778805 ps
CPU time 1.37 seconds
Started Jun 30 06:58:54 PM PDT 24
Finished Jun 30 06:58:56 PM PDT 24
Peak memory 216180 kb
Host smart-2aa472c1-1038-4f0b-a824-12cf72987d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916157836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.916157836
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.822857274
Short name T88
Test name
Test status
Simulation time 80579173 ps
CPU time 0.8 seconds
Started Jun 30 06:58:56 PM PDT 24
Finished Jun 30 06:58:57 PM PDT 24
Peak memory 205888 kb
Host smart-3ac0b663-63a1-4503-b550-5b4d30706f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822857274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.822857274
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3045549038
Short name T901
Test name
Test status
Simulation time 1379807463 ps
CPU time 5.62 seconds
Started Jun 30 06:58:52 PM PDT 24
Finished Jun 30 06:58:58 PM PDT 24
Peak memory 224476 kb
Host smart-94f74733-c08b-48d3-9a0e-68b72864b4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045549038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3045549038
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2266373999
Short name T841
Test name
Test status
Simulation time 110933878 ps
CPU time 0.76 seconds
Started Jun 30 06:58:56 PM PDT 24
Finished Jun 30 06:58:58 PM PDT 24
Peak memory 205412 kb
Host smart-7548c4bc-cad9-4fe9-98b6-9672add87923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266373999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
266373999
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2239613209
Short name T6
Test name
Test status
Simulation time 554814469 ps
CPU time 3.76 seconds
Started Jun 30 06:58:55 PM PDT 24
Finished Jun 30 06:59:00 PM PDT 24
Peak memory 224456 kb
Host smart-277d98aa-ff1b-484f-9c1f-5a4793df840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239613209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2239613209
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3642619703
Short name T947
Test name
Test status
Simulation time 15326820 ps
CPU time 0.76 seconds
Started Jun 30 06:58:53 PM PDT 24
Finished Jun 30 06:58:54 PM PDT 24
Peak memory 206860 kb
Host smart-f0612ce9-b731-4a4b-9878-730dce9807ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642619703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3642619703
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3841477550
Short name T1026
Test name
Test status
Simulation time 827141547 ps
CPU time 7.33 seconds
Started Jun 30 06:58:53 PM PDT 24
Finished Jun 30 06:59:00 PM PDT 24
Peak memory 224448 kb
Host smart-6fd27035-492d-4347-b47d-d9d495e81cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841477550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3841477550
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.960457669
Short name T291
Test name
Test status
Simulation time 14744318426 ps
CPU time 45.54 seconds
Started Jun 30 06:58:55 PM PDT 24
Finished Jun 30 06:59:42 PM PDT 24
Peak memory 218508 kb
Host smart-f972c1fa-1ef4-4e9f-8274-7c950b420a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960457669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.960457669
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1898935364
Short name T388
Test name
Test status
Simulation time 1171921685 ps
CPU time 16.34 seconds
Started Jun 30 06:58:54 PM PDT 24
Finished Jun 30 06:59:12 PM PDT 24
Peak memory 217380 kb
Host smart-7683994b-ad83-4c84-ba91-21d8515d17fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898935364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1898935364
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4077375035
Short name T773
Test name
Test status
Simulation time 252597396 ps
CPU time 8.2 seconds
Started Jun 30 06:58:53 PM PDT 24
Finished Jun 30 06:59:02 PM PDT 24
Peak memory 232648 kb
Host smart-93cb24b5-a800-4af5-a2ea-013301609410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077375035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4077375035
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2780841706
Short name T529
Test name
Test status
Simulation time 2196139737 ps
CPU time 6.82 seconds
Started Jun 30 06:58:55 PM PDT 24
Finished Jun 30 06:59:03 PM PDT 24
Peak memory 232724 kb
Host smart-d4222336-c57f-4127-9328-f2ce91fe48e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780841706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2780841706
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3944343237
Short name T24
Test name
Test status
Simulation time 438400796 ps
CPU time 11.23 seconds
Started Jun 30 06:58:57 PM PDT 24
Finished Jun 30 06:59:09 PM PDT 24
Peak memory 240712 kb
Host smart-0eb8beb3-1d8a-410c-b19f-29f9dd907fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944343237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3944343237
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.276671897
Short name T435
Test name
Test status
Simulation time 58042942 ps
CPU time 1.09 seconds
Started Jun 30 06:58:54 PM PDT 24
Finished Jun 30 06:58:56 PM PDT 24
Peak memory 216776 kb
Host smart-ce8e8fb2-f80c-4771-9cad-0d73786b83fc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276671897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.276671897
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3458349305
Short name T384
Test name
Test status
Simulation time 1051088336 ps
CPU time 8.37 seconds
Started Jun 30 06:58:54 PM PDT 24
Finished Jun 30 06:59:03 PM PDT 24
Peak memory 232596 kb
Host smart-721c516c-2806-44ab-b09b-3c0bf7f66d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458349305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3458349305
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.249952477
Short name T329
Test name
Test status
Simulation time 6973899940 ps
CPU time 18.57 seconds
Started Jun 30 06:58:54 PM PDT 24
Finished Jun 30 06:59:14 PM PDT 24
Peak memory 224636 kb
Host smart-6cca7ff6-3028-49c6-958f-9ece13dd8bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249952477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.249952477
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4102846044
Short name T569
Test name
Test status
Simulation time 409686733 ps
CPU time 4.13 seconds
Started Jun 30 06:58:54 PM PDT 24
Finished Jun 30 06:58:59 PM PDT 24
Peak memory 219616 kb
Host smart-3ef937ad-50b4-4494-80b3-7f5e178402f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4102846044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4102846044
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2370574622
Short name T20
Test name
Test status
Simulation time 936780493450 ps
CPU time 477.92 seconds
Started Jun 30 06:58:57 PM PDT 24
Finished Jun 30 07:06:56 PM PDT 24
Peak memory 252776 kb
Host smart-6897288b-05bf-4e00-bbf9-8e87c77c413d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370574622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2370574622
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.519709283
Short name T525
Test name
Test status
Simulation time 559261490 ps
CPU time 3.88 seconds
Started Jun 30 06:58:55 PM PDT 24
Finished Jun 30 06:59:00 PM PDT 24
Peak memory 216132 kb
Host smart-a05fa838-f251-4166-981c-92eeb77e1749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519709283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.519709283
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3626143711
Short name T338
Test name
Test status
Simulation time 680839057 ps
CPU time 4.21 seconds
Started Jun 30 06:58:54 PM PDT 24
Finished Jun 30 06:58:59 PM PDT 24
Peak memory 216172 kb
Host smart-f7fe33ef-ef28-4a4e-ade3-57603599c199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626143711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3626143711
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.145528113
Short name T518
Test name
Test status
Simulation time 95453028 ps
CPU time 1.34 seconds
Started Jun 30 06:58:56 PM PDT 24
Finished Jun 30 06:58:58 PM PDT 24
Peak memory 207884 kb
Host smart-f65c88c2-14eb-456a-ba47-97ad26d7c68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145528113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.145528113
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3314783000
Short name T467
Test name
Test status
Simulation time 69502088 ps
CPU time 0.78 seconds
Started Jun 30 06:58:51 PM PDT 24
Finished Jun 30 06:58:52 PM PDT 24
Peak memory 205856 kb
Host smart-f7c66aa6-2a6c-4984-988a-8af75aaf3d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314783000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3314783000
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2501126808
Short name T845
Test name
Test status
Simulation time 7440825938 ps
CPU time 22.86 seconds
Started Jun 30 06:58:52 PM PDT 24
Finished Jun 30 06:59:16 PM PDT 24
Peak memory 232764 kb
Host smart-b80661a3-80da-4982-a0a6-cb2673bd80e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501126808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2501126808
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.854539038
Short name T769
Test name
Test status
Simulation time 12301091 ps
CPU time 0.78 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 06:59:00 PM PDT 24
Peak memory 204820 kb
Host smart-40370864-4505-4559-bec9-4e814d81f6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854539038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.854539038
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2812290448
Short name T12
Test name
Test status
Simulation time 154694341 ps
CPU time 3.17 seconds
Started Jun 30 06:58:57 PM PDT 24
Finished Jun 30 06:59:01 PM PDT 24
Peak memory 232664 kb
Host smart-a2b3409f-103e-4e2f-9d51-6300628bac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812290448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2812290448
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.710196601
Short name T833
Test name
Test status
Simulation time 34241061 ps
CPU time 0.84 seconds
Started Jun 30 06:59:02 PM PDT 24
Finished Jun 30 06:59:03 PM PDT 24
Peak memory 206532 kb
Host smart-e7b04ee2-e7c3-44d4-aa7a-bc7e54c9c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710196601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.710196601
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1031607243
Short name T245
Test name
Test status
Simulation time 11266020397 ps
CPU time 37.87 seconds
Started Jun 30 06:58:57 PM PDT 24
Finished Jun 30 06:59:36 PM PDT 24
Peak memory 248932 kb
Host smart-8870a941-77f9-449b-8c9f-daf63ae526b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031607243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1031607243
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3746926224
Short name T135
Test name
Test status
Simulation time 682816620 ps
CPU time 3.37 seconds
Started Jun 30 06:59:00 PM PDT 24
Finished Jun 30 06:59:04 PM PDT 24
Peak memory 224412 kb
Host smart-9bc33919-2918-42ba-b5f2-4e8a0c4b08bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746926224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3746926224
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.850362577
Short name T812
Test name
Test status
Simulation time 2592793893 ps
CPU time 16.37 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 06:59:15 PM PDT 24
Peak memory 234476 kb
Host smart-8d625715-4d1a-4bf0-92b6-91953b088d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850362577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
850362577
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.83290489
Short name T607
Test name
Test status
Simulation time 9320103916 ps
CPU time 25.27 seconds
Started Jun 30 06:58:59 PM PDT 24
Finished Jun 30 06:59:25 PM PDT 24
Peak memory 224552 kb
Host smart-8fa222d7-7b01-43d7-aa01-29d6ebbe9fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83290489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.83290489
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3845496559
Short name T709
Test name
Test status
Simulation time 5534836365 ps
CPU time 38.25 seconds
Started Jun 30 06:58:56 PM PDT 24
Finished Jun 30 06:59:35 PM PDT 24
Peak memory 224480 kb
Host smart-c3c9063c-279c-4891-aa20-c06e83181e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845496559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3845496559
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3674770028
Short name T869
Test name
Test status
Simulation time 33285553 ps
CPU time 1.07 seconds
Started Jun 30 06:58:56 PM PDT 24
Finished Jun 30 06:58:58 PM PDT 24
Peak memory 216776 kb
Host smart-2741b47e-843b-4781-b09a-26af684da40c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674770028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3674770028
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2845804844
Short name T534
Test name
Test status
Simulation time 952617325 ps
CPU time 3.98 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 06:59:04 PM PDT 24
Peak memory 232572 kb
Host smart-4530c3fc-4ff4-4a86-a718-df4543efdc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845804844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2845804844
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.880696770
Short name T430
Test name
Test status
Simulation time 503251124 ps
CPU time 4.99 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 06:59:04 PM PDT 24
Peak memory 240392 kb
Host smart-ea72a61a-f82d-44d9-b109-6a715eaf9688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880696770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.880696770
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1874841032
Short name T691
Test name
Test status
Simulation time 3374011237 ps
CPU time 8.77 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 06:59:08 PM PDT 24
Peak memory 223076 kb
Host smart-2498f226-d5f5-448d-8b12-8c24fec373c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1874841032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1874841032
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.966949996
Short name T724
Test name
Test status
Simulation time 2136496233 ps
CPU time 30.82 seconds
Started Jun 30 06:58:57 PM PDT 24
Finished Jun 30 06:59:28 PM PDT 24
Peak memory 232868 kb
Host smart-d09e7608-d7cc-4845-888d-47583d6017dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966949996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.966949996
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3699897755
Short name T352
Test name
Test status
Simulation time 3176468570 ps
CPU time 11.68 seconds
Started Jun 30 06:59:00 PM PDT 24
Finished Jun 30 06:59:12 PM PDT 24
Peak memory 216592 kb
Host smart-51f77e18-ada4-4914-9f0a-201505321890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699897755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3699897755
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.347584683
Short name T934
Test name
Test status
Simulation time 9995405788 ps
CPU time 7.86 seconds
Started Jun 30 06:58:56 PM PDT 24
Finished Jun 30 06:59:05 PM PDT 24
Peak memory 217480 kb
Host smart-c94faec5-346f-4da6-b0c9-35359760a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347584683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.347584683
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2094368954
Short name T310
Test name
Test status
Simulation time 103630100 ps
CPU time 1.27 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 06:59:01 PM PDT 24
Peak memory 207880 kb
Host smart-5059f9d7-43ca-4035-8153-e444fcdb02d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094368954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2094368954
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1350220084
Short name T673
Test name
Test status
Simulation time 83992865 ps
CPU time 0.96 seconds
Started Jun 30 06:58:57 PM PDT 24
Finished Jun 30 06:58:59 PM PDT 24
Peak memory 206088 kb
Host smart-30ceff82-a70d-4497-8082-1f0d8bc8c3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350220084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1350220084
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2104564869
Short name T134
Test name
Test status
Simulation time 158303971 ps
CPU time 2.56 seconds
Started Jun 30 06:58:57 PM PDT 24
Finished Jun 30 06:59:01 PM PDT 24
Peak memory 224456 kb
Host smart-dea28c9e-30f6-40a3-ae30-fbc0c91e4251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104564869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2104564869
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.150640173
Short name T614
Test name
Test status
Simulation time 51448802 ps
CPU time 0.79 seconds
Started Jun 30 06:59:03 PM PDT 24
Finished Jun 30 06:59:04 PM PDT 24
Peak memory 204848 kb
Host smart-6bb11a58-5127-4931-bbb0-86644d5bcdc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150640173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.150640173
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3798783932
Short name T721
Test name
Test status
Simulation time 106043052 ps
CPU time 2.19 seconds
Started Jun 30 06:59:03 PM PDT 24
Finished Jun 30 06:59:06 PM PDT 24
Peak memory 223036 kb
Host smart-d5bafeeb-822a-4268-80ea-52d4d9604a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798783932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3798783932
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.845160846
Short name T297
Test name
Test status
Simulation time 23949273 ps
CPU time 0.77 seconds
Started Jun 30 06:59:02 PM PDT 24
Finished Jun 30 06:59:03 PM PDT 24
Peak memory 206544 kb
Host smart-05c66067-0a6f-4cb2-aeff-767682b45a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845160846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.845160846
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2858171321
Short name T77
Test name
Test status
Simulation time 12041525 ps
CPU time 0.76 seconds
Started Jun 30 06:59:06 PM PDT 24
Finished Jun 30 06:59:08 PM PDT 24
Peak memory 215852 kb
Host smart-4a37d5b6-fbd9-4d99-8651-773b6f02dee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858171321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2858171321
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3686493100
Short name T801
Test name
Test status
Simulation time 23613842649 ps
CPU time 103.76 seconds
Started Jun 30 06:59:03 PM PDT 24
Finished Jun 30 07:00:48 PM PDT 24
Peak memory 253976 kb
Host smart-94678990-49a7-4d6e-a263-04ad21c24310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686493100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3686493100
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.489878705
Short name T523
Test name
Test status
Simulation time 284920700 ps
CPU time 3.6 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:10 PM PDT 24
Peak memory 232676 kb
Host smart-56839060-e4f0-42c5-bd29-3ba9961eb882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489878705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.489878705
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1980974921
Short name T399
Test name
Test status
Simulation time 56759114085 ps
CPU time 209.79 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 07:02:36 PM PDT 24
Peak memory 257380 kb
Host smart-63e7f993-c54f-43a4-a398-c59ac881815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980974921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1980974921
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.39971406
Short name T603
Test name
Test status
Simulation time 100095365 ps
CPU time 3.19 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 06:59:03 PM PDT 24
Peak memory 232668 kb
Host smart-f31cb2c1-b947-4912-b4af-a4097378fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39971406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.39971406
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1236888191
Short name T953
Test name
Test status
Simulation time 29501717703 ps
CPU time 121.71 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 07:01:00 PM PDT 24
Peak memory 232756 kb
Host smart-8e624ff0-44f3-4284-80a2-78be075f7a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236888191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1236888191
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.4025802074
Short name T946
Test name
Test status
Simulation time 15372684 ps
CPU time 1.11 seconds
Started Jun 30 06:59:00 PM PDT 24
Finished Jun 30 06:59:01 PM PDT 24
Peak memory 217020 kb
Host smart-7699746a-0ea8-4161-abd7-af1176b31d46
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025802074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4025802074
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3151577475
Short name T651
Test name
Test status
Simulation time 4493490153 ps
CPU time 14.08 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 06:59:13 PM PDT 24
Peak memory 232736 kb
Host smart-4591ae20-9439-4e0d-8c45-81ba1873fb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151577475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3151577475
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1065935919
Short name T964
Test name
Test status
Simulation time 1409892873 ps
CPU time 3.14 seconds
Started Jun 30 06:58:57 PM PDT 24
Finished Jun 30 06:59:01 PM PDT 24
Peak memory 224420 kb
Host smart-1d067f7a-2279-428e-924a-fa56860f1ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065935919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1065935919
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.484143197
Short name T451
Test name
Test status
Simulation time 4157974652 ps
CPU time 11.91 seconds
Started Jun 30 06:59:05 PM PDT 24
Finished Jun 30 06:59:18 PM PDT 24
Peak memory 222128 kb
Host smart-5daec630-ac1b-4747-82c6-e30e1f8baf1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=484143197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.484143197
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4291137646
Short name T295
Test name
Test status
Simulation time 25859320976 ps
CPU time 175.82 seconds
Started Jun 30 06:59:04 PM PDT 24
Finished Jun 30 07:02:01 PM PDT 24
Peak memory 257160 kb
Host smart-daa526a2-d0c4-4f67-a5e4-c86e04943d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291137646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4291137646
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3773085965
Short name T930
Test name
Test status
Simulation time 5896484236 ps
CPU time 36 seconds
Started Jun 30 06:58:57 PM PDT 24
Finished Jun 30 06:59:34 PM PDT 24
Peak memory 216572 kb
Host smart-4bab00c9-5772-44fe-ac6f-4f4ada62554d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773085965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3773085965
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.678778753
Short name T522
Test name
Test status
Simulation time 38595547478 ps
CPU time 24.45 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 06:59:24 PM PDT 24
Peak memory 216272 kb
Host smart-e2fa9df8-e255-4c68-a8f4-3167606af28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678778753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.678778753
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2264567637
Short name T396
Test name
Test status
Simulation time 67987660 ps
CPU time 1.17 seconds
Started Jun 30 06:59:02 PM PDT 24
Finished Jun 30 06:59:03 PM PDT 24
Peak memory 207884 kb
Host smart-6d475ef9-ac6e-48da-b773-fec5530610b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264567637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2264567637
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1731455790
Short name T355
Test name
Test status
Simulation time 390753671 ps
CPU time 0.83 seconds
Started Jun 30 06:59:00 PM PDT 24
Finished Jun 30 06:59:02 PM PDT 24
Peak memory 205876 kb
Host smart-f67243a9-761d-43ea-a00e-87aeb07038f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731455790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1731455790
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1766804183
Short name T182
Test name
Test status
Simulation time 15585407362 ps
CPU time 14.5 seconds
Started Jun 30 06:58:58 PM PDT 24
Finished Jun 30 06:59:14 PM PDT 24
Peak memory 232824 kb
Host smart-7bab4934-ac00-4174-90a8-bf93ce2edc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766804183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1766804183
Directory /workspace/9.spi_device_upload/latest
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