Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2377630	1			T1	1		T3	1		T4	1
all_values[1]	2377630	1			T1	1		T3	1		T4	1
all_values[2]	2377630	1			T1	1		T3	1		T4	1
all_values[3]	2377630	1			T1	1		T3	1		T4	1
all_values[4]	2377630	1			T1	1		T3	1		T4	1
all_values[5]	2377630	1			T1	1		T3	1		T4	1
all_values[6]	2377630	1			T1	1		T3	1		T4	1
all_values[7]	2377630	1			T1	1		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17901101

1

T1

8

T3

8

T4

8

auto[1]

1119939

1

T8

129

T29

39

T16

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18992513

1

T1

8

T3

8

T4

8

auto[1]

28527

1

T8

224

T28

230

T29

257

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2227428	1			T1	1		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	13268	1			T8	48		T28	115		T29	131
all_values[0]	auto[1]	auto[0]	136370	1			T8	15		T29	4		T16	2
all_values[0]	auto[1]	auto[1]	564	1			T8	4		T29	2		T17	117
all_values[1]	auto[0]	auto[0]	2320634	1			T1	1		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	8764	1			T8	46		T28	58		T29	100
all_values[1]	auto[1]	auto[0]	47744	1			T8	10		T29	1		T16	5
all_values[1]	auto[1]	auto[1]	488	1			T8	7		T16	4		T17	1
all_values[2]	auto[0]	auto[0]	2224039	1			T1	1		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	3195	1			T8	53		T28	57		T29	14
all_values[2]	auto[1]	auto[0]	150061	1			T8	6		T29	6		T16	8
all_values[2]	auto[1]	auto[1]	335	1			T8	4		T17	3		T19	44
all_values[3]	auto[0]	auto[0]	2197324	1			T1	1		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	192	1			T8	9		T16	3		T17	2
all_values[3]	auto[1]	auto[0]	179951	1			T8	9		T29	6		T16	2
all_values[3]	auto[1]	auto[1]	163	1			T8	1		T16	2		T17	2
all_values[4]	auto[0]	auto[0]	2203868	1			T1	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	207	1			T8	8		T29	2		T16	4
all_values[4]	auto[1]	auto[0]	173366	1			T8	8		T16	2		T17	64899
all_values[4]	auto[1]	auto[1]	189	1			T8	6		T29	2		T16	2
all_values[5]	auto[0]	auto[0]	2253042	1			T1	1		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	197	1			T8	5		T29	1		T16	1
all_values[5]	auto[1]	auto[0]	124218	1			T8	10		T29	4		T16	3
all_values[5]	auto[1]	auto[1]	173	1			T8	8		T29	2		T16	2
all_values[6]	auto[0]	auto[0]	2274777	1			T1	1		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	188	1			T8	5		T29	1		T16	6
all_values[6]	auto[1]	auto[0]	102479	1			T8	14		T29	5		T16	2
all_values[6]	auto[1]	auto[1]	186	1			T8	7		T16	4		T17	3
all_values[7]	auto[0]	auto[0]	2173769	1			T1	1		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	209	1			T8	5		T16	5		T17	4
all_values[7]	auto[1]	auto[0]	203443	1			T8	12		T29	5		T16	1
all_values[7]	auto[1]	auto[1]	209	1			T8	8		T29	2		T16	3