Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35874	1			T1	4		T8	26		T10	9
auto[SpiFlashAddrCfg]	7436	1			T8	7		T10	4		T12	31
auto[SpiFlashAddr3b]	9307	1			T1	6		T8	6		T10	2
auto[SpiFlashAddr4b]	7592	1			T6	2		T8	4		T10	5

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32912

1

T1

10

T6

2

T8

37

auto[1]

27297

1

T8

6

T10

11

T12

56

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31680

1

T1

4

T6

2

T8

9

auto[1]

28529

1

T1

6

T8

34

T10

11

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40795	1			T1	4		T8	32		T10	15
values[1]	1116	1			T12	4		T14	5		T28	3
values[2]	1437	1			T10	1		T12	8		T13	1
values[3]	1376	1			T8	1		T10	1		T12	2
values[4]	1407	1			T8	1		T12	4		T14	6
values[5]	1352	1			T8	1		T12	11		T13	1
values[6]	1507	1			T8	1		T10	1		T12	5
values[7]	1458	1			T6	2		T8	4		T11	2
values[8]	9761	1			T1	6		T8	3		T10	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29354

1

T1

10

T8

43

T11

2

auto[1]

30855

1

T6

2

T10

20

T13

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56832

1

T1

10

T6

2

T8

41

write

3377

1

T8

2

T10

1

T12

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19113

1

T1

6

T6

2

T8

10

valids[0x1]

41096

1

T1

4

T8

33

T10

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1575	1			T10	2		T12	5		T14	8
internal_process_ops[0x5a]	1591	1			T8	1		T10	2		T12	4
internal_process_ops[0x05]	21980	1			T1	4		T8	25		T10	2
internal_process_ops[0x35]	1600	1			T10	1		T12	2		T14	9
internal_process_ops[0x15]	1575	1			T12	6		T14	5		T25	2
internal_process_ops[0x03]	1046	1			T8	1		T10	1		T12	3
internal_process_ops[0x0b]	1006	1			T8	1		T12	6		T13	1
internal_process_ops[0x3b]	967	1			T8	1		T12	3		T14	6
internal_process_ops[0x6b]	1047	1			T8	1		T12	2		T14	13
internal_process_ops[0xbb]	1009	1			T1	6		T6	2		T8	1
internal_process_ops[0xeb]	995	1			T12	2		T13	1		T14	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58531

1

T1

10

T6

2

T8

42

auto[1]

1678

1

T8

1

T12

4

T14

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57733

1

T1

10

T6

2

T8

42

auto[1]

2476

1

T8

1

T10

3

T12

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9160

1

T1

4

T8

26

T12

23

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7561

1

T12

6

T14

77

T29

37

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1774

1

T8

4

T12

13

T14

25

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1530

1

T8

3

T12

17

T14

18

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2315

1

T1

6

T8

5

T11

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1962

1

T8

1

T12

15

T14

18

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1899

1

T8

1

T12

9

T14

16

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1623

1

T8

1

T12

14

T14

20

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

88

1

T29

1

T42

4

T15

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

71

1

T44

4

T15

3

T165

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

130

1

T12

3

T29

3

T44

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

103

1

T14

1

T29

1

T44

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

94

1

T14

2

T29

1

T42

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T29

1

T44

2

T15

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

82

1

T12

1

T14

1

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

90

1

T44

2

T15

1

T46

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

129

1

T12

1

T15

5

T46

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

112

1

T12

3

T29

2

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

77

1

T29

1

T15

2

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T14

5

T44

1

T166

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

110

1

T8

1

T12

3

T14

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

97

1

T12

1

T29

2

T15

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

55

1

T44

2

T15

2

T167

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

102

1

T8

1

T45

2

T46

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10588

1

T10

5

T25

81

T28

77

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7731

1

T10

4

T25

26

T28

23

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1663

1

T10

1

T13

1

T25

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1642

1

T10

2

T25

16

T28

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2132

1

T13

1

T25

7

T28

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2009

1

T10

2

T25

17

T28

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1688

1

T6

2

T10

3

T13

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1555

1

T10

2

T25

13

T28

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

102

1

T40

1

T63

1

T168

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

110

1

T25

4

T40

2

T63

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

125

1

T63

1

T62

2

T169

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

105

1

T63

2

T48

3

T62

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

116

1

T28

2

T48

4

T169

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

114

1

T28

1

T63

1

T48

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

132

1

T10

1

T48

2

T55

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

119

1

T40

2

T169

1

T168

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

118

1

T28

1

T63

2

T48

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

120

1

T40

3

T63

2

T48

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

112

1

T28

3

T63

1

T62

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

111

1

T25

1

T63

3

T62

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

112

1

T25

1

T28

1

T63

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

120

1

T40

4

T62

2

T78

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

117

1

T40

3

T63

4

T48

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T63

1

T168

1

T170

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3366	1			T8	1		T12	14		T14	24
auto[0]	values[0]	valids[0x1]	16120	1			T1	4		T8	31		T12	39
auto[0]	values[1]	valids[0x1]	558	1			T12	4		T14	5		T29	5
auto[0]	values[2]	valids[0x0]	471	1			T12	3		T14	5		T29	2
auto[0]	values[2]	valids[0x1]	281	1			T12	5		T14	1		T29	2
auto[0]	values[3]	valids[0x0]	480	1			T8	1		T12	1		T14	1
auto[0]	values[3]	valids[0x1]	252	1			T12	1		T14	3		T44	3
auto[0]	values[4]	valids[0x0]	431	1			T8	1		T12	4		T14	1
auto[0]	values[4]	valids[0x1]	186	1			T14	5		T29	1		T44	2
auto[0]	values[5]	valids[0x0]	463	1			T8	1		T12	11		T14	19
auto[0]	values[5]	valids[0x1]	226	1			T14	6		T29	1		T89	6
auto[0]	values[6]	valids[0x0]	517	1			T8	1		T12	3		T14	9
auto[0]	values[6]	valids[0x1]	294	1			T12	2		T29	7		T44	6
auto[0]	values[7]	valids[0x0]	429	1			T8	2		T12	4		T14	8
auto[0]	values[7]	valids[0x1]	254	1			T8	2		T11	2		T14	6
auto[0]	values[8]	valids[0x0]	3192	1			T1	6		T8	3		T12	18
auto[0]	values[8]	valids[0x1]	1834	1			T12	11		T14	19		T29	9
auto[1]	values[0]	valids[0x0]	4422	1			T10	5		T25	26		T28	27
auto[1]	values[0]	valids[0x1]	16887	1			T10	10		T25	94		T28	82
auto[1]	values[1]	valids[0x1]	558	1			T28	3		T63	7		T48	2
auto[1]	values[2]	valids[0x0]	413	1			T10	1		T25	4		T40	2
auto[1]	values[2]	valids[0x1]	272	1			T13	1		T28	1		T40	3
auto[1]	values[3]	valids[0x0]	396	1			T10	1		T25	7		T28	1
auto[1]	values[3]	valids[0x1]	248	1			T28	3		T40	4		T63	1
auto[1]	values[4]	valids[0x0]	495	1			T25	3		T28	2		T40	4
auto[1]	values[4]	valids[0x1]	295	1			T28	1		T40	2		T63	1
auto[1]	values[5]	valids[0x0]	368	1			T25	3		T28	1		T40	2
auto[1]	values[5]	valids[0x1]	295	1			T13	1		T25	3		T28	2
auto[1]	values[6]	valids[0x0]	394	1			T25	2		T28	3		T63	2
auto[1]	values[6]	valids[0x1]	302	1			T10	1		T25	4		T28	3
auto[1]	values[7]	valids[0x0]	450	1			T6	2		T25	3		T28	1
auto[1]	values[7]	valids[0x1]	325	1			T25	6		T28	4		T40	3
auto[1]	values[8]	valids[0x0]	2826	1			T13	2		T25	17		T28	23
auto[1]	values[8]	valids[0x1]	1909	1			T10	2		T25	11		T28	11