Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3055361

1

T1

735

T3

869

T6

3282

auto[1]

29536

1

T8

23

T10

87

T12

6

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

752765

1

T1

735

T3

869

T6

3282

auto[1]

2332132

1

T8

1056

T10

977

T12

7102

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	610124	1			T1	52		T3	264		T6	998
auto[524288:1048575]	381984	1			T1	54		T10	6		T12	14
auto[1048576:1572863]	379688	1			T1	56		T3	603		T12	9
auto[1572864:2097151]	328971	1			T1	1		T12	2542		T13	2
auto[2097152:2621439]	311319	1			T1	320		T12	149		T13	2
auto[2621440:3145727]	376642	1			T6	92		T12	264		T14	64
auto[3145728:3670015]	326738	1			T6	2187		T8	1035		T12	695
auto[3670016:4194303]	369431	1			T1	252		T3	2		T6	5

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2365041

1

T1

63

T3

5

T6

13

auto[1]

719856

1

T1

672

T3

864

T6

3269

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2677280

1

T1

735

T3

869

T6

3282

auto[1]

407617

1

T12

22

T14

7178

T25

261

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	179707	1			T1	52		T3	264		T6	998
auto[0]	auto[0]	auto[0:524287]	auto[1]	380381	1			T8	1		T10	121		T12	3074
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	62586	1			T1	54		T10	6		T12	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	253198	1			T14	2731		T25	641		T28	1631
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	115960	1			T1	56		T3	603		T12	9
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	211154	1			T14	516		T28	1		T29	3882
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	55131	1			T1	1		T12	46		T13	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	229170	1			T12	2483		T14	8		T28	1655
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	59835	1			T1	320		T12	19		T13	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	190801	1			T12	128		T25	769		T40	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	111870	1			T6	92		T12	8		T14	18
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	220345	1			T12	256		T14	6		T25	660
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	60865	1			T6	2187		T8	2		T12	55
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	215410	1			T8	1033		T12	640		T14	2941
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	96547	1			T1	252		T3	2		T6	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	209713	1			T10	787		T12	521		T14	395
auto[0]	auto[1]	auto[0:524287]	auto[0]	851	1			T14	1		T25	2		T28	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	44412	1			T28	5		T63	2262		T46	394
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	583	1			T12	8		T25	2		T40	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	62042	1			T14	512		T40	256		T15	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	561	1			T14	6		T29	1		T62	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	49054	1			T14	2811		T28	256		T43	512
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	555	1			T12	10		T14	5		T28	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	41055	1			T14	190		T28	257		T29	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	937	1			T12	2		T25	1		T28	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	56558	1			T25	256		T29	129		T15	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	543	1			T14	1		T44	3		T63	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	41180	1			T63	1		T48	110		T62	257
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1603	1			T14	2		T29	1		T40	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	43579	1			T14	3650		T40	117		T48	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	608	1			T12	2		T29	1		T44	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	58567	1			T44	2759		T63	1964		T15	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	536	1			T8	1		T10	8		T14	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	3365	1			T8	22		T10	7		T14	19
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	402	1			T14	1		T25	1		T28	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2462	1			T14	3		T25	7		T28	14
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	400	1			T14	1		T29	3		T48	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2129	1			T14	3		T29	25		T48	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	382	1			T12	3		T28	1		T40	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2247	1			T40	32		T63	24		T46	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	416	1			T40	1		T63	2		T15	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2291	1			T63	16		T15	6		T48	8
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	296	1			T14	3		T44	1		T63	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1770	1			T14	36		T44	34		T63	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	363	1			T14	2		T25	1		T29	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	4165	1			T14	13		T25	13		T29	17
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	492	1			T10	10		T12	3		T14	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2891	1			T10	62		T14	7		T25	33
auto[1]	auto[1]	auto[0:524287]	auto[0]	107	1			T28	1		T63	2		T46	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	765	1			T28	4		T63	31		T46	19
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	86	1			T15	1		T48	1		T46	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	625	1			T48	3		T62	22		T207	8
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	80	1			T41	1		T208	1		T78	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	350	1			T41	3		T208	7		T78	9
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	111	1			T28	1		T29	1		T41	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	320	1			T28	16		T29	1		T41	41
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	95	1			T29	1		T15	1		T169	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	386	1			T29	3		T169	1		T78	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	69	1			T63	1		T48	1		T62	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	569	1			T63	2		T48	5		T62	12
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	89	1			T226	1		T43	4		T41	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	664	1			T226	7		T41	47		T88	77
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	99	1			T44	1		T63	4		T43	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	514	1			T44	6		T63	33		T169	11

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1935409	1			T1	63		T3	5		T6	13
auto[0]	auto[0]	auto[1]	717264	1			T1	672		T3	864		T6	3269
auto[0]	auto[1]	auto[0]	400802	1			T12	22		T14	7178		T25	261
auto[0]	auto[1]	auto[1]	1886	1			T44	1		T63	5		T15	1
auto[1]	auto[0]	auto[0]	24034	1			T8	23		T10	84		T12	4
auto[1]	auto[0]	auto[1]	573	1			T10	3		T12	2		T14	5
auto[1]	auto[1]	auto[0]	4796	1			T28	22		T29	6		T44	7
auto[1]	auto[1]	auto[1]	133	1			T63	6		T46	1		T43	1