Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2377630	1			T1	1		T3	1		T4	1
all_pins[1]	2377630	1			T1	1		T3	1		T4	1
all_pins[2]	2377630	1			T1	1		T3	1		T4	1
all_pins[3]	2377630	1			T1	1		T3	1		T4	1
all_pins[4]	2377630	1			T1	1		T3	1		T4	1
all_pins[5]	2377630	1			T1	1		T3	1		T4	1
all_pins[6]	2377630	1			T1	1		T3	1		T4	1
all_pins[7]	2377630	1			T1	1		T3	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18914076	1			T1	8		T3	8		T4	8
values[0x1]	106964	1			T8	45		T29	8		T16	17
transitions[0x0=>0x1]	105458	1			T8	34		T29	6		T16	14
transitions[0x1=>0x0]	105467	1			T8	34		T29	6		T16	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2377016	1			T1	1		T3	1		T4	1
all_pins[0]	values[0x1]	614	1			T8	4		T29	2		T17	127
all_pins[0]	transitions[0x0=>0x1]	375	1			T8	1		T29	2		T17	127
all_pins[0]	transitions[0x1=>0x0]	290	1			T8	4		T16	4		T17	1
all_pins[1]	values[0x0]	2377101	1			T1	1		T3	1		T4	1
all_pins[1]	values[0x1]	529	1			T8	7		T16	4		T17	1
all_pins[1]	transitions[0x0=>0x1]	379	1			T8	5		T16	4		T17	1
all_pins[1]	transitions[0x1=>0x0]	202	1			T8	2		T17	3		T19	4
all_pins[2]	values[0x0]	2377278	1			T1	1		T3	1		T4	1
all_pins[2]	values[0x1]	352	1			T8	4		T17	3		T19	48
all_pins[2]	transitions[0x0=>0x1]	322	1			T8	4		T17	3		T19	43
all_pins[2]	transitions[0x1=>0x0]	133	1			T8	1		T16	2		T17	2
all_pins[3]	values[0x0]	2377467	1			T1	1		T3	1		T4	1
all_pins[3]	values[0x1]	163	1			T8	1		T16	2		T17	2
all_pins[3]	transitions[0x0=>0x1]	124	1			T16	2		T17	2		T19	6
all_pins[3]	transitions[0x1=>0x0]	150	1			T8	5		T29	2		T16	2
all_pins[4]	values[0x0]	2377441	1			T1	1		T3	1		T4	1
all_pins[4]	values[0x1]	189	1			T8	6		T29	2		T16	2
all_pins[4]	transitions[0x0=>0x1]	146	1			T8	4		T29	1		T17	1
all_pins[4]	transitions[0x1=>0x0]	2578	1			T8	6		T29	1		T19	422
all_pins[5]	values[0x0]	2375009	1			T1	1		T3	1		T4	1
all_pins[5]	values[0x1]	2621	1			T8	8		T29	2		T16	2
all_pins[5]	transitions[0x0=>0x1]	1714	1			T8	7		T29	2		T16	1
all_pins[5]	transitions[0x1=>0x0]	101380	1			T8	6		T16	3		T17	64874
all_pins[6]	values[0x0]	2275343	1			T1	1		T3	1		T4	1
all_pins[6]	values[0x1]	102287	1			T8	7		T16	4		T17	64874
all_pins[6]	transitions[0x0=>0x1]	102243	1			T8	7		T16	4		T17	64873
all_pins[6]	transitions[0x1=>0x0]	165	1			T8	8		T29	2		T16	3
all_pins[7]	values[0x0]	2377421	1			T1	1		T3	1		T4	1
all_pins[7]	values[0x1]	209	1			T8	8		T29	2		T16	3
all_pins[7]	transitions[0x0=>0x1]	155	1			T8	6		T29	1		T16	3
all_pins[7]	transitions[0x1=>0x0]	569	1			T8	2		T29	1		T17	125