Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15929

1

T1

10

T8

37

T11

2

auto[1]

13425

1

T8

6

T12

56

T14

140

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4132	1			T12	20		T14	28		T29	66
values[1]	3517	1			T11	2		T12	20		T14	69
values[2]	3688	1			T14	68		T29	43		T45	8
values[3]	3458	1			T12	20		T14	67		T29	27
values[4]	3363	1			T8	43		T14	20		T29	45
values[5]	4347	1			T12	20		T14	20		T29	43
values[6]	3471	1			T1	10		T12	20		T15	20
values[7]	3378	1			T12	20		T14	20		T44	94

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3825	1			T12	40		T14	115		T44	86
values[1]	3218	1			T8	43		T12	40		T14	20
values[2]	3246	1			T12	20		T14	63		T29	20
values[3]	4490	1			T1	10		T89	22		T58	10
values[4]	3278	1			T14	28		T29	23		T44	20
values[5]	5012	1			T11	2		T29	43		T42	16
values[6]	3050	1			T12	20		T14	26		T29	65
values[7]	3235	1			T14	40		T29	27		T44	56

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	181	1			T17	12		T49	11		T195	11
auto[0]	values[0]	values[1]	351	1			T12	10		T29	36		T41	11
auto[0]	values[0]	values[2]	225	1			T43	12		T172	12		T204	12
auto[0]	values[0]	values[3]	268	1			T46	12		T41	42		T212	22
auto[0]	values[0]	values[4]	268	1			T14	19		T41	11		T227	2
auto[0]	values[0]	values[5]	359	1			T29	12		T44	68		T228	6
auto[0]	values[0]	values[6]	156	1			T172	13		T182	8		T229	12
auto[0]	values[0]	values[7]	365	1			T15	9		T49	15		T201	11
auto[0]	values[1]	values[0]	358	1			T44	10		T46	14		T182	9
auto[0]	values[1]	values[1]	173	1			T215	10		T182	13		T187	18
auto[0]	values[1]	values[2]	292	1			T12	8		T14	33		T15	17
auto[0]	values[1]	values[3]	238	1			T46	17		T41	15		T172	11
auto[0]	values[1]	values[4]	179	1			T44	15		T172	9		T167	14
auto[0]	values[1]	values[5]	480	1			T11	2		T41	6		T88	12
auto[0]	values[1]	values[6]	141	1			T14	10		T165	16		T178	16
auto[0]	values[1]	values[7]	143	1			T206	7		T230	6		T231	10
auto[0]	values[2]	values[0]	250	1			T14	31		T216	10		T17	9
auto[0]	values[2]	values[1]	188	1			T14	11		T44	30		T41	11
auto[0]	values[2]	values[2]	351	1			T29	11		T185	52		T200	13
auto[0]	values[2]	values[3]	316	1			T46	36		T182	10		T17	11
auto[0]	values[2]	values[4]	218	1			T172	9		T182	11		T232	8
auto[0]	values[2]	values[5]	399	1			T29	16		T185	10		T186	13
auto[0]	values[2]	values[6]	147	1			T23	10		T233	8		T234	6
auto[0]	values[2]	values[7]	169	1			T88	10		T203	2		T195	12
auto[0]	values[3]	values[0]	208	1			T12	14		T14	11		T88	9
auto[0]	values[3]	values[1]	137	1			T44	13		T41	7		T206	10
auto[0]	values[3]	values[2]	227	1			T44	9		T235	22		T176	11
auto[0]	values[3]	values[3]	299	1			T46	24		T49	29		T167	12
auto[0]	values[3]	values[4]	166	1			T176	22		T167	16		T23	13
auto[0]	values[3]	values[5]	517	1			T42	16		T43	13		T88	13
auto[0]	values[3]	values[6]	127	1			T41	8		T199	13		T167	14
auto[0]	values[3]	values[7]	244	1			T29	17		T43	8		T49	12
auto[0]	values[4]	values[0]	287	1			T15	14		T46	8		T41	3
auto[0]	values[4]	values[1]	159	1			T8	37		T225	12		T167	12
auto[0]	values[4]	values[2]	158	1			T59	14		T206	16		T223	4
auto[0]	values[4]	values[3]	285	1			T89	22		T88	12		T182	20
auto[0]	values[4]	values[4]	310	1			T29	15		T166	11		T165	9
auto[0]	values[4]	values[5]	107	1			T41	10		T176	11		T199	12
auto[0]	values[4]	values[6]	157	1			T29	13		T15	7		T166	9
auto[0]	values[4]	values[7]	283	1			T14	9		T44	19		T165	21
auto[0]	values[5]	values[0]	244	1			T12	13		T15	12		T41	12
auto[0]	values[5]	values[1]	279	1			T44	18		T15	9		T236	18
auto[0]	values[5]	values[2]	181	1			T46	14		T43	12		T199	33
auto[0]	values[5]	values[3]	379	1			T182	14		T237	4		T201	19
auto[0]	values[5]	values[4]	169	1			T17	13		T238	12		T239	6
auto[0]	values[5]	values[5]	313	1			T43	12		T224	12		T185	48
auto[0]	values[5]	values[6]	305	1			T29	9		T88	12		T185	10
auto[0]	values[5]	values[7]	335	1			T14	14		T88	9		T172	9
auto[0]	values[6]	values[0]	224	1			T197	24		T74	13		T23	15
auto[0]	values[6]	values[1]	135	1			T12	11		T90	14		T88	8
auto[0]	values[6]	values[2]	169	1			T176	13		T49	20		T19	10
auto[0]	values[6]	values[3]	218	1			T1	10		T19	19		T240	2
auto[0]	values[6]	values[4]	247	1			T167	35		T209	10		T22	9
auto[0]	values[6]	values[5]	369	1			T15	14		T43	15		T167	42
auto[0]	values[6]	values[6]	315	1			T43	23		T17	8		T167	13
auto[0]	values[6]	values[7]	147	1			T22	15		T130	11		T233	11
auto[0]	values[7]	values[0]	221	1			T44	56		T166	12		T241	4
auto[0]	values[7]	values[1]	146	1			T43	12		T172	10		T126	8
auto[0]	values[7]	values[2]	359	1			T14	14		T15	7		T43	5
auto[0]	values[7]	values[3]	264	1			T172	13		T182	11		T17	13
auto[0]	values[7]	values[4]	257	1			T88	17		T176	30		T185	34
auto[0]	values[7]	values[5]	346	1			T17	16		T167	11		T201	16
auto[0]	values[7]	values[6]	232	1			T12	8		T15	13		T41	8
auto[0]	values[7]	values[7]	189	1			T44	26		T220	22		T222	9
auto[1]	values[0]	values[0]	149	1			T17	10		T49	9		T184	12
auto[1]	values[0]	values[1]	453	1			T12	10		T29	10		T41	12
auto[1]	values[0]	values[2]	189	1			T43	8		T172	8		T20	9
auto[1]	values[0]	values[3]	224	1			T46	20		T41	17		T199	14
auto[1]	values[0]	values[4]	241	1			T14	9		T41	11		T17	17
auto[1]	values[0]	values[5]	407	1			T29	8		T44	5		T200	18
auto[1]	values[0]	values[6]	92	1			T172	7		T182	12		T200	9
auto[1]	values[0]	values[7]	204	1			T15	13		T49	5		T201	9
auto[1]	values[1]	values[0]	245	1			T44	10		T46	27		T182	11
auto[1]	values[1]	values[1]	241	1			T182	7		T188	20		T19	10
auto[1]	values[1]	values[2]	121	1			T12	12		T14	10		T15	12
auto[1]	values[1]	values[3]	322	1			T46	9		T41	5		T172	9
auto[1]	values[1]	values[4]	105	1			T44	5		T172	11		T167	6
auto[1]	values[1]	values[5]	202	1			T41	42		T88	8		T182	12
auto[1]	values[1]	values[6]	132	1			T14	16		T165	13		T178	24
auto[1]	values[1]	values[7]	145	1			T206	17		T231	10		T242	62
auto[1]	values[2]	values[0]	102	1			T14	17		T17	13		T178	10
auto[1]	values[2]	values[1]	168	1			T14	9		T44	10		T41	44
auto[1]	values[2]	values[2]	180	1			T29	9		T185	8		T200	7
auto[1]	values[2]	values[3]	432	1			T46	15		T182	10		T17	9
auto[1]	values[2]	values[4]	162	1			T172	11		T182	9		T185	9
auto[1]	values[2]	values[5]	204	1			T29	7		T185	10		T186	7
auto[1]	values[2]	values[6]	165	1			T45	8		T243	16		T23	72
auto[1]	values[2]	values[7]	237	1			T88	10		T70	6		T195	10
auto[1]	values[3]	values[0]	207	1			T12	6		T14	56		T88	11
auto[1]	values[3]	values[1]	159	1			T44	7		T41	95		T206	10
auto[1]	values[3]	values[2]	133	1			T44	11		T176	9		T201	23
auto[1]	values[3]	values[3]	235	1			T46	18		T49	8		T167	32
auto[1]	values[3]	values[4]	70	1			T176	4		T167	4		T23	7
auto[1]	values[3]	values[5]	407	1			T43	7		T88	7		T17	9
auto[1]	values[3]	values[6]	121	1			T41	12		T199	7		T167	31
auto[1]	values[3]	values[7]	201	1			T29	10		T43	12		T49	8
auto[1]	values[4]	values[0]	243	1			T15	8		T46	28		T41	34
auto[1]	values[4]	values[1]	175	1			T8	6		T167	8		T185	6
auto[1]	values[4]	values[2]	191	1			T206	4		T244	11		T245	72
auto[1]	values[4]	values[3]	139	1			T88	8		T182	20		T246	20
auto[1]	values[4]	values[4]	392	1			T29	8		T247	8		T166	9
auto[1]	values[4]	values[5]	206	1			T41	10		T176	48		T199	14
auto[1]	values[4]	values[6]	114	1			T29	9		T15	16		T166	11
auto[1]	values[4]	values[7]	157	1			T14	11		T44	9		T165	10
auto[1]	values[5]	values[0]	465	1			T12	7		T15	53		T41	122
auto[1]	values[5]	values[1]	200	1			T44	45		T15	13		T20	97
auto[1]	values[5]	values[2]	80	1			T46	6		T43	8		T199	12
auto[1]	values[5]	values[3]	442	1			T58	10		T182	6		T201	6
auto[1]	values[5]	values[4]	176	1			T17	7		T190	10		T200	15
auto[1]	values[5]	values[5]	325	1			T43	8		T185	8		T186	31
auto[1]	values[5]	values[6]	360	1			T29	34		T88	8		T185	10
auto[1]	values[5]	values[7]	94	1			T14	6		T88	11		T172	11
auto[1]	values[6]	values[0]	243	1			T74	8		T23	5		T126	2
auto[1]	values[6]	values[1]	116	1			T12	9		T88	12		T182	5
auto[1]	values[6]	values[2]	159	1			T176	11		T49	7		T19	22
auto[1]	values[6]	values[3]	266	1			T19	71		T23	23		T248	10
auto[1]	values[6]	values[4]	174	1			T167	8		T22	51		T249	7
auto[1]	values[6]	values[5]	159	1			T15	6		T43	5		T167	9
auto[1]	values[6]	values[6]	329	1			T43	17		T17	16		T167	7
auto[1]	values[6]	values[7]	201	1			T22	5		T130	9		T233	9
auto[1]	values[7]	values[0]	198	1			T44	10		T166	8		T165	10
auto[1]	values[7]	values[1]	138	1			T43	8		T172	10		T126	12
auto[1]	values[7]	values[2]	231	1			T14	6		T15	13		T43	15
auto[1]	values[7]	values[3]	163	1			T172	7		T182	9		T17	10
auto[1]	values[7]	values[4]	144	1			T88	3		T176	8		T185	11
auto[1]	values[7]	values[5]	212	1			T17	7		T167	77		T201	4
auto[1]	values[7]	values[6]	157	1			T12	12		T15	14		T41	12
auto[1]	values[7]	values[7]	121	1			T44	2		T222	11		T195	8