Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	346	1			T12	1		T14	4		T29	2
auto[ReadAddrCrossIntoMailbox]	276	1			T8	1		T12	1		T14	2
auto[ReadAddrCrossOutOfMailbox]	259	1			T12	1		T14	1		T29	1
auto[ReadAddrCrossAllMailbox]	191	1			T12	3		T14	5		T44	1
auto[ReadAddrOutsideMailbox]	3189	1			T1	6		T8	4		T12	16

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2064

1

T1

3

T8

2

T12

8

auto[1]

2197

1

T1

3

T8

3

T12

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	736	1			T8	1		T12	3		T14	6
read_ops[0x0b]	697	1			T8	1		T12	6		T14	11
read_ops[0x3b]	675	1			T8	1		T12	3		T14	6
read_ops[0x6b]	737	1			T8	1		T12	2		T14	13
read_ops[0xbb]	719	1			T1	6		T8	1		T12	6
read_ops[0xeb]	697	1			T12	2		T14	4		T29	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T185	1		T201	1		T250	3
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T15	1		T166	1		T17	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T44	1		T88	1		T17	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T29	1		T88	1		T166	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T46	1		T182	1		T190	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T166	1		T17	1		T167	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T43	1		T41	1		T172	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T15	2		T176	1		T204	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	292	1			T8	1		T14	4		T29	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	274	1			T12	3		T14	2		T29	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T14	3		T29	1		T44	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T88	1		T167	1		T251	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T44	1		T15	1		T176	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T43	1		T88	1		T201	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T29	1		T15	1		T46	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T195	1		T23	2		T244	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T41	1		T183	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T88	1		T190	1		T233	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T8	1		T14	8		T29	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T12	6		T44	5		T15	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T12	1		T43	1		T228	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T29	1		T228	1		T17	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T172	1		T167	1		T201	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T43	1		T88	1		T17	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T46	1		T88	1		T200	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T43	1		T88	2		T182	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T20	1		T126	1		T249	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T178	1		T186	1		T22	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	254	1			T12	1		T14	4		T29	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	258	1			T8	1		T12	1		T14	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T43	1		T41	1		T17	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T15	1		T88	1		T204	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T172	1		T204	1		T19	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T14	2		T44	1		T15	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T43	1		T176	1		T165	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T14	1		T44	1		T41	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T12	1		T17	1		T244	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T14	2		T88	1		T201	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	274	1			T12	1		T14	5		T29	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T8	1		T14	3		T29	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T41	1		T167	1		T218	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T14	1		T88	2		T185	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T43	1		T166	1		T204	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T8	1		T43	1		T88	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T46	1		T41	1		T204	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T12	1		T182	1		T17	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T14	1		T46	1		T176	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T12	2		T14	1		T88	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T1	3		T12	3		T14	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T1	3		T14	2		T29	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T88	1		T228	1		T17	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T43	1		T88	1		T228	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T12	1		T29	1		T41	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T17	1		T178	3		T201	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T41	2		T199	1		T167	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T15	1		T43	1		T172	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T46	1		T182	1		T185	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T14	1		T44	1		T182	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	239	1			T14	2		T29	2		T89	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T12	1		T14	1		T29	2