Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3838	1			T14	20		T45	8		T44	68
values[1]	3448	1			T12	40		T14	46		T29	43
values[2]	4072	1			T11	2		T14	28		T44	86
values[3]	3731	1			T8	43		T14	130		T29	46
values[4]	3702	1			T12	20		T29	50		T15	42
values[5]	3877	1			T12	20		T14	48		T29	23
values[6]	3199	1			T1	10		T12	20		T14	20
values[7]	3487	1			T12	20		T29	62		T44	73

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4014	1			T12	20		T29	47		T44	28
values[1]	3553	1			T14	20		T29	69		T44	40
values[2]	3813	1			T8	43		T12	20		T29	45
values[3]	3535	1			T12	20		T14	40		T29	20
values[4]	4065	1			T14	26		T44	43		T46	99
values[5]	3490	1			T11	2		T12	20		T14	67
values[6]	3640	1			T12	20		T14	68		T29	43
values[7]	3244	1			T1	10		T12	20		T14	71

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28589

1

T1

10

T8

42

T11

2

auto[1]

765

1

T8

1

T12

4

T14

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	482	1			T44	28		T201	20		T19	32
auto[0]	values[0]	values[1]	494	1			T15	29		T186	26		T252	6
auto[0]	values[0]	values[2]	203	1			T45	6		T44	20		T43	20
auto[0]	values[0]	values[3]	308	1			T44	19		T15	19		T216	10
auto[0]	values[0]	values[4]	333	1			T46	23		T166	20		T17	18
auto[0]	values[0]	values[5]	623	1			T220	22		T186	28		T20	20
auto[0]	values[0]	values[6]	734	1			T14	20		T41	19		T172	20
auto[0]	values[0]	values[7]	568	1			T46	20		T253	4		T167	60
auto[0]	values[1]	values[0]	451	1			T227	2		T247	8		T172	20
auto[0]	values[1]	values[1]	583	1			T44	18		T43	20		T88	19
auto[0]	values[1]	values[2]	365	1			T46	22		T88	20		T172	20
auto[0]	values[1]	values[3]	551	1			T14	20		T254	22		T200	20
auto[0]	values[1]	values[4]	324	1			T14	25		T235	22		T172	18
auto[0]	values[1]	values[5]	543	1			T12	20		T15	20		T182	20
auto[0]	values[1]	values[6]	309	1			T29	43		T182	20		T199	23
auto[0]	values[1]	values[7]	230	1			T12	18		T44	20		T187	18
auto[0]	values[2]	values[0]	542	1			T172	20		T176	19		T49	19
auto[0]	values[2]	values[1]	366	1			T44	20		T43	19		T172	20
auto[0]	values[2]	values[2]	472	1			T43	19		T41	23		T172	20
auto[0]	values[2]	values[3]	327	1			T182	20		T17	23		T190	19
auto[0]	values[2]	values[4]	560	1			T182	17		T255	2		T23	81
auto[0]	values[2]	values[5]	430	1			T11	2		T88	18		T197	24
auto[0]	values[2]	values[6]	591	1			T44	63		T59	14		T46	30
auto[0]	values[2]	values[7]	672	1			T14	28		T165	19		T178	20
auto[0]	values[3]	values[0]	625	1			T43	17		T167	19		T185	63
auto[0]	values[3]	values[1]	269	1			T29	44		T41	20		T166	20
auto[0]	values[3]	values[2]	400	1			T8	42		T172	20		T167	45
auto[0]	values[3]	values[3]	557	1			T89	22		T17	21		T167	103
auto[0]	values[3]	values[4]	773	1			T44	41		T90	14		T88	38
auto[0]	values[3]	values[5]	460	1			T14	63		T46	35		T172	18
auto[0]	values[3]	values[6]	391	1			T14	20		T44	27		T41	37
auto[0]	values[3]	values[7]	140	1			T14	42		T44	20		T182	20
auto[0]	values[4]	values[0]	462	1			T29	26		T15	21		T41	55
auto[0]	values[4]	values[1]	523	1			T17	16		T176	23		T256	4
auto[0]	values[4]	values[2]	500	1			T12	20		T29	22		T15	20
auto[0]	values[4]	values[3]	492	1			T172	20		T182	20		T17	20
auto[0]	values[4]	values[4]	430	1			T41	39		T19	46		T23	19
auto[0]	values[4]	values[5]	248	1			T215	10		T172	20		T186	40
auto[0]	values[4]	values[6]	368	1			T41	66		T185	56		T200	51
auto[0]	values[4]	values[7]	574	1			T41	133		T88	18		T182	18
auto[0]	values[5]	values[0]	618	1			T58	10		T43	19		T185	20
auto[0]	values[5]	values[1]	277	1			T14	20		T29	21		T41	20
auto[0]	values[5]	values[2]	516	1			T15	20		T17	24		T186	43
auto[0]	values[5]	values[3]	534	1			T12	19		T44	20		T49	35
auto[0]	values[5]	values[4]	607	1			T46	70		T41	102		T22	64
auto[0]	values[5]	values[5]	329	1			T15	27		T46	19		T41	21
auto[0]	values[5]	values[6]	416	1			T14	28		T15	22		T43	20
auto[0]	values[5]	values[7]	480	1			T182	19		T178	61		T190	56
auto[0]	values[6]	values[0]	412	1			T12	20		T165	20		T184	12
auto[0]	values[6]	values[1]	651	1			T182	19		T17	20		T19	22
auto[0]	values[6]	values[2]	514	1			T41	20		T257	82		T199	26
auto[0]	values[6]	values[3]	396	1			T14	20		T166	19		T237	4
auto[0]	values[6]	values[4]	397	1			T204	12		T19	89		T195	38
auto[0]	values[6]	values[5]	305	1			T42	16		T15	63		T46	20
auto[0]	values[6]	values[6]	238	1			T224	12		T167	43		T20	49
auto[0]	values[6]	values[7]	222	1			T1	10		T41	39		T250	12
auto[0]	values[7]	values[0]	317	1			T29	20		T166	20		T182	19
auto[0]	values[7]	values[1]	295	1			T172	20		T49	20		T165	20
auto[0]	values[7]	values[2]	767	1			T29	22		T43	17		T88	20
auto[0]	values[7]	values[3]	266	1			T29	20		T19	20		T196	20
auto[0]	values[7]	values[4]	525	1			T17	20		T49	44		T258	2
auto[0]	values[7]	values[5]	459	1			T88	19		T182	20		T199	20
auto[0]	values[7]	values[6]	494	1			T12	19		T44	71		T88	20
auto[0]	values[7]	values[7]	281	1			T43	20		T259	14		T178	61
auto[1]	values[0]	values[0]	7	1			T23	1		T130	1		T242	1
auto[1]	values[0]	values[1]	10	1			T186	3		T174	1		T175	1
auto[1]	values[0]	values[2]	3	1			T45	2		T260	1		-	-
auto[1]	values[0]	values[3]	11	1			T44	1		T15	1		T199	1
auto[1]	values[0]	values[4]	13	1			T46	3		T17	2		T245	2
auto[1]	values[0]	values[5]	19	1			T186	2		T22	2		T23	3
auto[1]	values[0]	values[6]	18	1			T41	1		T200	2		T211	1
auto[1]	values[0]	values[7]	12	1			T188	4		T233	3		T156	1
auto[1]	values[1]	values[0]	11	1			T165	3		T233	1		T134	2
auto[1]	values[1]	values[1]	19	1			T44	2		T88	1		T176	4
auto[1]	values[1]	values[2]	8	1			T20	1		T261	4		T181	3
auto[1]	values[1]	values[3]	15	1			T20	3		T211	1		T262	2
auto[1]	values[1]	values[4]	6	1			T14	1		T172	2		T182	1
auto[1]	values[1]	values[5]	12	1			T15	2		T23	1		T249	3
auto[1]	values[1]	values[6]	17	1			T199	2		T36	4		T263	4
auto[1]	values[1]	values[7]	4	1			T12	2		T264	2		-	-
auto[1]	values[2]	values[0]	18	1			T176	1		T49	1		T265	4
auto[1]	values[2]	values[1]	17	1			T43	1		T167	2		T200	1
auto[1]	values[2]	values[2]	16	1			T43	1		T185	5		T201	2
auto[1]	values[2]	values[3]	12	1			T190	1		T200	5		T211	1
auto[1]	values[2]	values[4]	12	1			T182	3		T23	1		T249	4
auto[1]	values[2]	values[5]	13	1			T88	2		T201	1		T126	1
auto[1]	values[2]	values[6]	13	1			T44	3		T46	1		T88	3
auto[1]	values[2]	values[7]	11	1			T165	1		T196	2		T126	2
auto[1]	values[3]	values[0]	21	1			T43	3		T167	1		T185	2
auto[1]	values[3]	values[1]	7	1			T29	2		T195	3		T249	1
auto[1]	values[3]	values[2]	6	1			T8	1		T185	1		T186	1
auto[1]	values[3]	values[3]	19	1			T17	1		T167	5		T22	1
auto[1]	values[3]	values[4]	24	1			T44	2		T88	2		T178	2
auto[1]	values[3]	values[5]	16	1			T14	4		T46	1		T172	2
auto[1]	values[3]	values[6]	15	1			T44	1		T195	3		T265	1
auto[1]	values[3]	values[7]	8	1			T14	1		T190	4		T130	3
auto[1]	values[4]	values[0]	7	1			T29	1		T15	1		T202	1
auto[1]	values[4]	values[1]	16	1			T17	7		T176	1		T22	2
auto[1]	values[4]	values[2]	10	1			T29	1		T43	2		T196	2
auto[1]	values[4]	values[3]	14	1			T185	3		T206	3		T244	1
auto[1]	values[4]	values[4]	15	1			T41	2		T19	2		T23	1
auto[1]	values[4]	values[5]	10	1			T206	2		T214	1		T174	1
auto[1]	values[4]	values[6]	12	1			T41	2		T200	5		T186	1
auto[1]	values[4]	values[7]	21	1			T41	1		T88	2		T182	2
auto[1]	values[5]	values[0]	23	1			T43	1		T243	6		T126	3
auto[1]	values[5]	values[1]	5	1			T29	2		T244	1		T266	2
auto[1]	values[5]	values[2]	16	1			T15	3		T74	2		T19	1
auto[1]	values[5]	values[3]	10	1			T12	1		T49	2		T158	1
auto[1]	values[5]	values[4]	19	1			T46	3		T22	2		T126	3
auto[1]	values[5]	values[5]	4	1			T46	1		T41	1		T20	1
auto[1]	values[5]	values[6]	7	1			T201	1		T260	3		T267	1
auto[1]	values[5]	values[7]	16	1			T182	1		T190	2		T214	4
auto[1]	values[6]	values[0]	7	1			T130	1		T192	2		T249	1
auto[1]	values[6]	values[1]	12	1			T182	1		T20	1		T193	2
auto[1]	values[6]	values[2]	4	1			T190	1		T195	2		T268	1
auto[1]	values[6]	values[3]	15	1			T166	1		T178	1		T175	5
auto[1]	values[6]	values[4]	13	1			T19	1		T195	2		T193	1
auto[1]	values[6]	values[5]	5	1			T15	2		T167	1		T269	2
auto[1]	values[6]	values[6]	5	1			T20	3		T270	2		-	-
auto[1]	values[6]	values[7]	3	1			T196	1		T271	2		-	-
auto[1]	values[7]	values[0]	11	1			T182	1		T196	3		T244	2
auto[1]	values[7]	values[1]	9	1			T201	2		T134	2		T221	4
auto[1]	values[7]	values[2]	13	1			T43	3		T165	3		T246	2
auto[1]	values[7]	values[3]	8	1			T272	4		T35	1		T181	1
auto[1]	values[7]	values[4]	14	1			T17	2		T49	4		T196	3
auto[1]	values[7]	values[5]	14	1			T88	1		T185	3		T22	3
auto[1]	values[7]	values[6]	12	1			T12	1		T44	2		T182	2
auto[1]	values[7]	values[7]	2	1			T178	1		T219	1		-	-