Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	827	1			T8	27		T29	4		T16	11
all_values[1]	827	1			T8	27		T29	4		T16	11
all_values[2]	827	1			T8	27		T29	4		T16	11
all_values[3]	827	1			T8	27		T29	4		T16	11
all_values[4]	827	1			T8	27		T29	4		T16	11
all_values[5]	827	1			T8	27		T29	4		T16	11
all_values[6]	827	1			T8	27		T29	4		T16	11
all_values[7]	827	1			T8	27		T29	4		T16	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3566

1

T8

119

T29

17

T16

54

auto[1]

3050

1

T8

97

T29

15

T16

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2704

1

T8

91

T29

13

T16

36

auto[1]

3912

1

T8

125

T29

19

T16

52

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3802

1

T8

126

T29

17

T16

50

auto[1]

2814

1

T8

90

T29

15

T16

38

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	170	1			T8	7		T29	1		T16	3
all_values[0]	auto[0]	auto[0]	auto[1]	89	1			T8	3		T16	1		T19	5
all_values[0]	auto[0]	auto[1]	auto[0]	139	1			T8	6		T16	3		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	86	1			T8	1		T29	1		T17	4
all_values[0]	auto[1]	auto[0]	auto[1]	177	1			T8	4		T29	1		T16	4
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T8	6		T29	1		T17	3
all_values[1]	auto[0]	auto[0]	auto[0]	185	1			T8	7		T29	2		T17	5
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T8	2		T16	1		T17	1
all_values[1]	auto[0]	auto[1]	auto[0]	139	1			T8	5		T16	2		T17	2
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T8	3		T16	2		T17	2
all_values[1]	auto[1]	auto[0]	auto[1]	171	1			T8	4		T29	2		T16	4
all_values[1]	auto[1]	auto[1]	auto[1]	181	1			T8	6		T16	2		T17	3
all_values[2]	auto[0]	auto[0]	auto[0]	197	1			T8	8		T29	1		T16	4
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T8	6		T17	3		T19	4
all_values[2]	auto[0]	auto[1]	auto[0]	137	1			T8	3		T29	1		T16	3
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T8	1		T19	3		T164	1
all_values[2]	auto[1]	auto[0]	auto[1]	178	1			T8	6		T29	1		T16	2
all_values[2]	auto[1]	auto[1]	auto[1]	159	1			T8	3		T29	1		T16	2
all_values[3]	auto[0]	auto[0]	auto[0]	202	1			T8	10		T29	2		T16	3
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T8	4		T17	1		T19	3
all_values[3]	auto[0]	auto[1]	auto[0]	147	1			T8	5		T29	1		T16	2
all_values[3]	auto[0]	auto[1]	auto[1]	63	1			T19	4		T164	2		T130	2
all_values[3]	auto[1]	auto[0]	auto[1]	176	1			T8	4		T16	4		T17	5
all_values[3]	auto[1]	auto[1]	auto[1]	154	1			T8	4		T29	1		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	160	1			T8	5		T16	4		T17	3
all_values[4]	auto[0]	auto[0]	auto[1]	89	1			T8	2		T29	2		T16	1
all_values[4]	auto[0]	auto[1]	auto[0]	154	1			T8	2		T16	1		T17	7
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T8	2		T17	1		T19	2
all_values[4]	auto[1]	auto[0]	auto[1]	185	1			T8	10		T29	1		T16	3
all_values[4]	auto[1]	auto[1]	auto[1]	161	1			T8	6		T29	1		T16	2
all_values[5]	auto[0]	auto[0]	auto[0]	252	1			T8	8		T16	6		T17	6
all_values[5]	auto[0]	auto[1]	auto[0]	205	1			T8	6		T29	1		T16	2
all_values[5]	auto[1]	auto[0]	auto[1]	213	1			T8	4		T29	1		T16	1
all_values[5]	auto[1]	auto[1]	auto[1]	157	1			T8	9		T29	2		T16	2
all_values[6]	auto[0]	auto[0]	auto[0]	177	1			T8	4		T29	1		T17	3
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T8	3		T16	4		T17	2
all_values[6]	auto[0]	auto[1]	auto[0]	158	1			T8	5		T29	1		T16	1
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T8	3		T16	2		T17	2
all_values[6]	auto[1]	auto[0]	auto[1]	190	1			T8	5		T29	1		T16	3
all_values[6]	auto[1]	auto[1]	auto[1]	155	1			T8	7		T29	1		T16	1
all_values[7]	auto[0]	auto[0]	auto[0]	165	1			T8	5		T29	1		T16	2
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T8	2		T16	2		T19	4
all_values[7]	auto[0]	auto[1]	auto[0]	117	1			T8	5		T29	1		T17	3
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T8	3		T29	1		T16	1
all_values[7]	auto[1]	auto[0]	auto[1]	201	1			T8	6		T16	2		T17	4
all_values[7]	auto[1]	auto[1]	auto[1]	190	1			T8	6		T29	1		T16	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal