Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1671

1

T5

9

T8

2

T9

9

auto[1]

1644

1

T5

6

T8

8

T9

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1888

1

T5

15

T8

7

T9

13

auto[1]

1427

1

T8

3

T9

4

T27

21

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2588

1

T5

9

T8

7

T9

14

auto[1]

727

1

T5

6

T8

3

T9

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	654	1			T5	5		T9	3		T27	4
valid[1]	684	1			T5	2		T8	3		T9	4
valid[2]	680	1			T5	4		T8	4		T9	1
valid[3]	662	1			T5	2		T8	1		T9	4
valid[4]	635	1			T5	2		T8	2		T9	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	121	1			T5	4		T9	3		T29	1
auto[0]	auto[0]	valid[0]	auto[1]	150	1			T27	4		T29	1		T32	2
auto[0]	auto[0]	valid[1]	auto[0]	128	1			T5	1		T8	1		T9	3
auto[0]	auto[0]	valid[1]	auto[1]	143	1			T27	3		T86	1		T57	1
auto[0]	auto[0]	valid[2]	auto[0]	94	1			T5	2		T28	2		T48	1
auto[0]	auto[0]	valid[2]	auto[1]	151	1			T27	4		T32	1		T298	1
auto[0]	auto[0]	valid[3]	auto[0]	119	1			T9	1		T28	3		T15	1
auto[0]	auto[0]	valid[3]	auto[1]	139	1			T27	2		T29	2		T86	4
auto[0]	auto[0]	valid[4]	auto[0]	119	1			T5	1		T9	1		T28	3
auto[0]	auto[0]	valid[4]	auto[1]	141	1			T9	1		T27	1		T31	1
auto[0]	auto[1]	valid[0]	auto[0]	110	1			T295	1		T292	1		T293	1
auto[0]	auto[1]	valid[0]	auto[1]	148	1			T31	2		T15	1		T86	2
auto[0]	auto[1]	valid[1]	auto[0]	123	1			T9	1		T28	1		T29	2
auto[0]	auto[1]	valid[1]	auto[1]	141	1			T8	2		T27	3		T57	1
auto[0]	auto[1]	valid[2]	auto[0]	118	1			T8	2		T28	2		T15	1
auto[0]	auto[1]	valid[2]	auto[1]	153	1			T8	1		T86	3		T48	1
auto[0]	auto[1]	valid[3]	auto[0]	112	1			T28	1		T29	3		T31	1
auto[0]	auto[1]	valid[3]	auto[1]	144	1			T9	2		T27	1		T57	2
auto[0]	auto[1]	valid[4]	auto[0]	117	1			T5	1		T8	1		T9	1
auto[0]	auto[1]	valid[4]	auto[1]	117	1			T9	1		T27	3		T33	1
auto[1]	auto[0]	valid[0]	auto[0]	59	1			T28	1		T29	1		T15	1
auto[1]	auto[0]	valid[1]	auto[0]	71	1			T29	1		T15	1		T292	1
auto[1]	auto[0]	valid[2]	auto[0]	87	1			T5	1		T29	1		T46	1
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T28	2		T46	1		T61	1
auto[1]	auto[0]	valid[4]	auto[0]	73	1			T8	1		T29	1		T295	2
auto[1]	auto[1]	valid[0]	auto[0]	66	1			T5	1		T48	1		T61	1
auto[1]	auto[1]	valid[1]	auto[0]	78	1			T5	1		T29	1		T15	1
auto[1]	auto[1]	valid[2]	auto[0]	77	1			T5	1		T8	1		T9	1
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T5	2		T8	1		T9	1
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T9	1		T15	1		T292	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal