Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48258

1

T5

357

T8

202

T9

408

auto[1]

14833

1

T8

59

T9

105

T27

312

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45787

1

T5

252

T8

181

T9

354

auto[1]

17304

1

T5

105

T8

80

T9

159

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32287	1			T5	179		T8	137		T9	268
others[1]	5331	1			T5	34		T8	23		T9	43
others[2]	5218	1			T5	29		T8	19		T9	46
others[3]	6098	1			T5	41		T8	31		T9	43
interest[1]	3515	1			T5	18		T8	16		T9	17
interest[4]	21145	1			T5	116		T8	89		T9	168
interest[64]	10642	1			T5	56		T8	35		T9	96

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15766	1			T5	128		T8	74		T9	130
auto[0]	auto[0]	others[1]	2652	1			T5	26		T8	8		T9	21
auto[0]	auto[0]	others[2]	2553	1			T5	17		T8	6		T9	20
auto[0]	auto[0]	others[3]	3029	1			T5	30		T8	15		T9	19
auto[0]	auto[0]	interest[1]	1715	1			T5	11		T8	6		T9	8
auto[0]	auto[0]	interest[4]	10207	1			T5	76		T8	47		T9	78
auto[0]	auto[0]	interest[64]	5239	1			T5	40		T8	13		T9	51
auto[0]	auto[1]	others[0]	7791	1			T8	27		T9	54		T27	165
auto[0]	auto[1]	others[1]	1201	1			T8	7		T9	7		T27	32
auto[0]	auto[1]	others[2]	1209	1			T8	3		T9	12		T27	24
auto[0]	auto[1]	others[3]	1367	1			T8	8		T9	12		T27	27
auto[0]	auto[1]	interest[1]	817	1			T8	4		T9	5		T27	27
auto[0]	auto[1]	interest[4]	5212	1			T8	17		T9	32		T27	105
auto[0]	auto[1]	interest[64]	2448	1			T8	10		T9	15		T27	37
auto[1]	auto[0]	others[0]	8730	1			T5	51		T8	36		T9	84
auto[1]	auto[0]	others[1]	1478	1			T5	8		T8	8		T9	15
auto[1]	auto[0]	others[2]	1456	1			T5	12		T8	10		T9	14
auto[1]	auto[0]	others[3]	1702	1			T5	11		T8	8		T9	12
auto[1]	auto[0]	interest[1]	983	1			T5	7		T8	6		T9	4
auto[1]	auto[0]	interest[4]	5726	1			T5	40		T8	25		T9	58
auto[1]	auto[0]	interest[64]	2955	1			T5	16		T8	12		T9	30

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal