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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.21


Total test records in report: 1151
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T1036 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3778293619 Jul 01 10:35:17 AM PDT 24 Jul 01 10:35:22 AM PDT 24 33559611 ps
T118 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2268665442 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:18 AM PDT 24 35153166 ps
T109 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3873495289 Jul 01 10:35:12 AM PDT 24 Jul 01 10:35:24 AM PDT 24 468352703 ps
T106 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1337737742 Jul 01 10:35:14 AM PDT 24 Jul 01 10:35:22 AM PDT 24 168709298 ps
T110 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3586304713 Jul 01 10:35:04 AM PDT 24 Jul 01 10:35:13 AM PDT 24 133930931 ps
T111 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.90000671 Jul 01 10:35:05 AM PDT 24 Jul 01 10:35:24 AM PDT 24 215381942 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3982747278 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:17 AM PDT 24 102576766 ps
T1037 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3571585621 Jul 01 10:35:06 AM PDT 24 Jul 01 10:35:15 AM PDT 24 102974972 ps
T162 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2248814136 Jul 01 10:35:21 AM PDT 24 Jul 01 10:35:31 AM PDT 24 2637984005 ps
T1038 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2721545084 Jul 01 10:35:12 AM PDT 24 Jul 01 10:35:18 AM PDT 24 28640068 ps
T1039 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2178121586 Jul 01 10:35:06 AM PDT 24 Jul 01 10:35:16 AM PDT 24 59630598 ps
T149 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3463053100 Jul 01 10:35:05 AM PDT 24 Jul 01 10:35:19 AM PDT 24 4324349509 ps
T160 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.936531861 Jul 01 10:35:08 AM PDT 24 Jul 01 10:35:34 AM PDT 24 314692926 ps
T1040 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1738204310 Jul 01 10:35:04 AM PDT 24 Jul 01 10:35:16 AM PDT 24 24041178 ps
T104 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1654947429 Jul 01 10:35:08 AM PDT 24 Jul 01 10:35:17 AM PDT 24 86002409 ps
T150 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2380237651 Jul 01 10:35:17 AM PDT 24 Jul 01 10:35:26 AM PDT 24 201414495 ps
T151 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2665868730 Jul 01 10:35:02 AM PDT 24 Jul 01 10:35:08 AM PDT 24 54478429 ps
T119 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.208904668 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:17 AM PDT 24 27851043 ps
T1041 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4176427103 Jul 01 10:35:00 AM PDT 24 Jul 01 10:35:04 AM PDT 24 16162524 ps
T1042 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.967987036 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:16 AM PDT 24 14023302 ps
T152 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.899364095 Jul 01 10:35:04 AM PDT 24 Jul 01 10:35:12 AM PDT 24 87328902 ps
T153 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1946163308 Jul 01 10:35:12 AM PDT 24 Jul 01 10:35:21 AM PDT 24 422190902 ps
T1043 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2610121406 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:18 AM PDT 24 420727891 ps
T1044 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3620477412 Jul 01 10:35:58 AM PDT 24 Jul 01 10:36:02 AM PDT 24 28027976 ps
T1045 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1160707867 Jul 01 10:35:30 AM PDT 24 Jul 01 10:35:32 AM PDT 24 16325655 ps
T1046 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1761520099 Jul 01 10:35:15 AM PDT 24 Jul 01 10:35:23 AM PDT 24 77899026 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3478298456 Jul 01 10:35:08 AM PDT 24 Jul 01 10:35:47 AM PDT 24 2444967934 ps
T1047 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1942072177 Jul 01 10:35:14 AM PDT 24 Jul 01 10:35:20 AM PDT 24 16969507 ps
T1048 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.563724142 Jul 01 10:35:13 AM PDT 24 Jul 01 10:35:19 AM PDT 24 20986668 ps
T98 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.183269184 Jul 01 10:35:00 AM PDT 24 Jul 01 10:35:08 AM PDT 24 1478937808 ps
T99 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3387743861 Jul 01 10:35:04 AM PDT 24 Jul 01 10:35:13 AM PDT 24 64525177 ps
T1049 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4179142455 Jul 01 10:35:23 AM PDT 24 Jul 01 10:35:25 AM PDT 24 15989321 ps
T1050 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2397344706 Jul 01 10:35:19 AM PDT 24 Jul 01 10:35:30 AM PDT 24 282848078 ps
T1051 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3261080647 Jul 01 10:35:04 AM PDT 24 Jul 01 10:35:21 AM PDT 24 617435639 ps
T1052 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.570937129 Jul 01 10:36:04 AM PDT 24 Jul 01 10:36:07 AM PDT 24 16875174 ps
T154 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1578964177 Jul 01 10:35:25 AM PDT 24 Jul 01 10:35:35 AM PDT 24 453362964 ps
T1053 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1624903387 Jul 01 10:35:03 AM PDT 24 Jul 01 10:35:21 AM PDT 24 212165458 ps
T121 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1658564214 Jul 01 10:35:04 AM PDT 24 Jul 01 10:35:12 AM PDT 24 132699766 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.990323865 Jul 01 10:35:34 AM PDT 24 Jul 01 10:35:40 AM PDT 24 768406218 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2572703683 Jul 01 10:35:03 AM PDT 24 Jul 01 10:35:20 AM PDT 24 637968764 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1620790372 Jul 01 10:35:30 AM PDT 24 Jul 01 10:35:33 AM PDT 24 46209086 ps
T100 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2121731006 Jul 01 10:35:13 AM PDT 24 Jul 01 10:35:24 AM PDT 24 258532235 ps
T1057 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3210646876 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:16 AM PDT 24 14894914 ps
T163 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2494137526 Jul 01 10:35:26 AM PDT 24 Jul 01 10:35:33 AM PDT 24 110982570 ps
T1058 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1246345890 Jul 01 10:35:14 AM PDT 24 Jul 01 10:35:20 AM PDT 24 22875582 ps
T101 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1339924374 Jul 01 10:35:39 AM PDT 24 Jul 01 10:35:43 AM PDT 24 84060786 ps
T1059 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1020212648 Jul 01 10:34:59 AM PDT 24 Jul 01 10:35:04 AM PDT 24 216740514 ps
T1060 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.767184323 Jul 01 10:35:05 AM PDT 24 Jul 01 10:35:17 AM PDT 24 37861151 ps
T155 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3119533013 Jul 01 10:35:34 AM PDT 24 Jul 01 10:35:55 AM PDT 24 987360468 ps
T1061 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.832248818 Jul 01 10:35:31 AM PDT 24 Jul 01 10:35:33 AM PDT 24 92070624 ps
T122 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2058452578 Jul 01 10:35:02 AM PDT 24 Jul 01 10:35:27 AM PDT 24 354229720 ps
T123 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4254890065 Jul 01 10:35:08 AM PDT 24 Jul 01 10:35:18 AM PDT 24 183593498 ps
T161 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2362002527 Jul 01 10:35:22 AM PDT 24 Jul 01 10:35:36 AM PDT 24 210493531 ps
T1062 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3054509084 Jul 01 10:35:05 AM PDT 24 Jul 01 10:35:14 AM PDT 24 173650780 ps
T1063 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.185032046 Jul 01 10:35:33 AM PDT 24 Jul 01 10:35:40 AM PDT 24 16845447 ps
T1064 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1880657895 Jul 01 10:35:38 AM PDT 24 Jul 01 10:35:40 AM PDT 24 14459388 ps
T1065 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1706173624 Jul 01 10:35:41 AM PDT 24 Jul 01 10:35:43 AM PDT 24 12152550 ps
T83 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2799771001 Jul 01 10:35:04 AM PDT 24 Jul 01 10:35:11 AM PDT 24 71558618 ps
T1066 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.637639863 Jul 01 10:35:18 AM PDT 24 Jul 01 10:35:23 AM PDT 24 14748037 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.624954936 Jul 01 10:35:06 AM PDT 24 Jul 01 10:35:15 AM PDT 24 87910674 ps
T1068 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.952921312 Jul 01 10:35:11 AM PDT 24 Jul 01 10:35:19 AM PDT 24 28202233 ps
T1069 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2877533904 Jul 01 10:35:55 AM PDT 24 Jul 01 10:36:00 AM PDT 24 205493362 ps
T102 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3557191005 Jul 01 10:35:16 AM PDT 24 Jul 01 10:35:25 AM PDT 24 374793354 ps
T1070 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1594877592 Jul 01 10:35:13 AM PDT 24 Jul 01 10:35:20 AM PDT 24 134068563 ps
T1071 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3133598328 Jul 01 10:35:16 AM PDT 24 Jul 01 10:35:22 AM PDT 24 18157657 ps
T1072 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4053377857 Jul 01 10:35:42 AM PDT 24 Jul 01 10:35:44 AM PDT 24 31208266 ps
T107 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3395712571 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:19 AM PDT 24 517833145 ps
T84 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2847424788 Jul 01 10:35:43 AM PDT 24 Jul 01 10:35:45 AM PDT 24 46006815 ps
T1073 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.546530909 Jul 01 10:35:10 AM PDT 24 Jul 01 10:35:17 AM PDT 24 13433371 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2152725305 Jul 01 10:34:59 AM PDT 24 Jul 01 10:35:03 AM PDT 24 11471122 ps
T1075 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1429294515 Jul 01 10:35:23 AM PDT 24 Jul 01 10:35:41 AM PDT 24 588253690 ps
T1076 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3188475029 Jul 01 10:35:02 AM PDT 24 Jul 01 10:35:14 AM PDT 24 108037384 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.537006157 Jul 01 10:35:25 AM PDT 24 Jul 01 10:35:27 AM PDT 24 941143476 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1967878269 Jul 01 10:35:02 AM PDT 24 Jul 01 10:35:23 AM PDT 24 3219618377 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1773338157 Jul 01 10:35:29 AM PDT 24 Jul 01 10:35:34 AM PDT 24 854047289 ps
T1080 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.944858161 Jul 01 10:35:33 AM PDT 24 Jul 01 10:35:40 AM PDT 24 48350886 ps
T1081 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3223865948 Jul 01 10:35:15 AM PDT 24 Jul 01 10:35:24 AM PDT 24 838879885 ps
T1082 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3114745277 Jul 01 10:35:12 AM PDT 24 Jul 01 10:35:20 AM PDT 24 37649530 ps
T1083 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4273930000 Jul 01 10:35:18 AM PDT 24 Jul 01 10:35:23 AM PDT 24 51618555 ps
T1084 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.128241487 Jul 01 10:35:01 AM PDT 24 Jul 01 10:35:18 AM PDT 24 413438509 ps
T1085 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2403679939 Jul 01 10:34:58 AM PDT 24 Jul 01 10:35:05 AM PDT 24 162672239 ps
T1086 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1254911747 Jul 01 10:35:19 AM PDT 24 Jul 01 10:35:23 AM PDT 24 76790177 ps
T1087 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1554291492 Jul 01 10:35:03 AM PDT 24 Jul 01 10:35:10 AM PDT 24 79696427 ps
T1088 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1969718612 Jul 01 10:35:44 AM PDT 24 Jul 01 10:35:47 AM PDT 24 30173008 ps
T1089 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3231245307 Jul 01 10:35:16 AM PDT 24 Jul 01 10:35:22 AM PDT 24 30940943 ps
T1090 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4038417843 Jul 01 10:35:08 AM PDT 24 Jul 01 10:35:21 AM PDT 24 1017054524 ps
T1091 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1028579756 Jul 01 10:35:25 AM PDT 24 Jul 01 10:35:27 AM PDT 24 21633057 ps
T1092 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4077889503 Jul 01 10:35:37 AM PDT 24 Jul 01 10:35:41 AM PDT 24 58471324 ps
T105 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2636112545 Jul 01 10:35:43 AM PDT 24 Jul 01 10:35:48 AM PDT 24 2005067913 ps
T1093 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2238680518 Jul 01 10:35:25 AM PDT 24 Jul 01 10:35:26 AM PDT 24 30143705 ps
T1094 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3327051290 Jul 01 10:35:10 AM PDT 24 Jul 01 10:35:17 AM PDT 24 15821784 ps
T1095 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.952028216 Jul 01 10:35:30 AM PDT 24 Jul 01 10:35:32 AM PDT 24 18223258 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.378665913 Jul 01 10:35:03 AM PDT 24 Jul 01 10:35:11 AM PDT 24 102731111 ps
T1097 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1017453194 Jul 01 10:35:21 AM PDT 24 Jul 01 10:35:37 AM PDT 24 1036949127 ps
T1098 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3581929353 Jul 01 10:35:17 AM PDT 24 Jul 01 10:35:34 AM PDT 24 1701088836 ps
T1099 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3068829390 Jul 01 10:35:20 AM PDT 24 Jul 01 10:35:27 AM PDT 24 115200624 ps
T85 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1646619287 Jul 01 10:35:05 AM PDT 24 Jul 01 10:35:14 AM PDT 24 15456538 ps
T1100 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2659937286 Jul 01 10:35:16 AM PDT 24 Jul 01 10:35:22 AM PDT 24 60681425 ps
T1101 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3576018229 Jul 01 10:35:11 AM PDT 24 Jul 01 10:35:17 AM PDT 24 25213117 ps
T1102 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3092498790 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:18 AM PDT 24 85359618 ps
T1103 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3630802347 Jul 01 10:35:16 AM PDT 24 Jul 01 10:35:22 AM PDT 24 16445713 ps
T103 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2858399510 Jul 01 10:35:17 AM PDT 24 Jul 01 10:35:25 AM PDT 24 53549443 ps
T1104 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1329590924 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:17 AM PDT 24 38332304 ps
T1105 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3939594934 Jul 01 10:35:24 AM PDT 24 Jul 01 10:35:26 AM PDT 24 15050601 ps
T1106 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3801273592 Jul 01 10:35:10 AM PDT 24 Jul 01 10:35:35 AM PDT 24 201965218 ps
T1107 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1811189176 Jul 01 10:35:35 AM PDT 24 Jul 01 10:35:39 AM PDT 24 29563352 ps
T1108 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.334148852 Jul 01 10:35:10 AM PDT 24 Jul 01 10:35:17 AM PDT 24 14797112 ps
T1109 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.628991614 Jul 01 10:35:36 AM PDT 24 Jul 01 10:35:41 AM PDT 24 141727946 ps
T1110 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3430526961 Jul 01 10:35:42 AM PDT 24 Jul 01 10:35:45 AM PDT 24 23197801 ps
T1111 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.516886398 Jul 01 10:35:18 AM PDT 24 Jul 01 10:35:23 AM PDT 24 17427454 ps
T1112 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3356832426 Jul 01 10:35:12 AM PDT 24 Jul 01 10:35:18 AM PDT 24 17316303 ps
T1113 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3434466537 Jul 01 10:35:46 AM PDT 24 Jul 01 10:35:50 AM PDT 24 45666625 ps
T1114 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1662357318 Jul 01 10:35:35 AM PDT 24 Jul 01 10:35:40 AM PDT 24 122557608 ps
T1115 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2384936975 Jul 01 10:35:59 AM PDT 24 Jul 01 10:36:03 AM PDT 24 14664455 ps
T1116 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3973285585 Jul 01 10:35:04 AM PDT 24 Jul 01 10:35:10 AM PDT 24 30893751 ps
T1117 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3710759522 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:18 AM PDT 24 721263387 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2068540194 Jul 01 10:35:24 AM PDT 24 Jul 01 10:35:27 AM PDT 24 214995896 ps
T1119 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.247217499 Jul 01 10:35:12 AM PDT 24 Jul 01 10:35:20 AM PDT 24 68807845 ps
T1120 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1068266660 Jul 01 10:35:16 AM PDT 24 Jul 01 10:35:22 AM PDT 24 12147283 ps
T1121 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.43091133 Jul 01 10:35:11 AM PDT 24 Jul 01 10:35:17 AM PDT 24 21914508 ps
T1122 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1147467603 Jul 01 10:35:19 AM PDT 24 Jul 01 10:35:23 AM PDT 24 31434596 ps
T1123 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2586335792 Jul 01 10:35:25 AM PDT 24 Jul 01 10:35:29 AM PDT 24 45928916 ps
T1124 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3544843316 Jul 01 10:35:13 AM PDT 24 Jul 01 10:35:19 AM PDT 24 17163605 ps
T1125 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.409051487 Jul 01 10:35:23 AM PDT 24 Jul 01 10:35:27 AM PDT 24 38104676 ps
T1126 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1378639206 Jul 01 10:35:00 AM PDT 24 Jul 01 10:35:17 AM PDT 24 207099866 ps
T1127 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4055254013 Jul 01 10:35:11 AM PDT 24 Jul 01 10:35:20 AM PDT 24 204853463 ps
T1128 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2898027682 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:18 AM PDT 24 118900006 ps
T1129 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4071339806 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:19 AM PDT 24 824784413 ps
T1130 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1662772072 Jul 01 10:35:40 AM PDT 24 Jul 01 10:35:42 AM PDT 24 13388900 ps
T1131 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.788258436 Jul 01 10:35:45 AM PDT 24 Jul 01 10:35:54 AM PDT 24 1009916761 ps
T171 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2381856036 Jul 01 10:35:14 AM PDT 24 Jul 01 10:35:21 AM PDT 24 248320188 ps
T1132 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3766778318 Jul 01 10:35:19 AM PDT 24 Jul 01 10:35:25 AM PDT 24 34921836 ps
T1133 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.928587350 Jul 01 10:35:37 AM PDT 24 Jul 01 10:35:39 AM PDT 24 39398956 ps
T1134 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1718774178 Jul 01 10:35:11 AM PDT 24 Jul 01 10:35:18 AM PDT 24 43970702 ps
T1135 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4171143977 Jul 01 10:37:12 AM PDT 24 Jul 01 10:37:16 AM PDT 24 341848053 ps
T1136 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1010621562 Jul 01 10:35:31 AM PDT 24 Jul 01 10:35:47 AM PDT 24 630710217 ps
T1137 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1776283227 Jul 01 10:35:08 AM PDT 24 Jul 01 10:35:17 AM PDT 24 50045537 ps
T1138 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2178869645 Jul 01 10:35:10 AM PDT 24 Jul 01 10:35:19 AM PDT 24 77457124 ps
T1139 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.18981567 Jul 01 10:35:25 AM PDT 24 Jul 01 10:35:27 AM PDT 24 12388083 ps
T1140 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4225260573 Jul 01 10:35:16 AM PDT 24 Jul 01 10:35:21 AM PDT 24 81059738 ps
T1141 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.156022653 Jul 01 10:35:15 AM PDT 24 Jul 01 10:35:23 AM PDT 24 400477707 ps
T1142 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.522334371 Jul 01 10:35:05 AM PDT 24 Jul 01 10:35:13 AM PDT 24 30527567 ps
T1143 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3066202504 Jul 01 10:37:20 AM PDT 24 Jul 01 10:37:23 AM PDT 24 249442374 ps
T1144 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2048900695 Jul 01 10:35:17 AM PDT 24 Jul 01 10:35:23 AM PDT 24 40810654 ps
T1145 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1401686978 Jul 01 10:35:06 AM PDT 24 Jul 01 10:35:15 AM PDT 24 71651457 ps
T1146 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.707109888 Jul 01 10:35:16 AM PDT 24 Jul 01 10:35:21 AM PDT 24 40876736 ps
T1147 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3406856220 Jul 01 10:35:08 AM PDT 24 Jul 01 10:35:18 AM PDT 24 233953523 ps
T1148 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4018538632 Jul 01 10:35:08 AM PDT 24 Jul 01 10:35:21 AM PDT 24 542675241 ps
T1149 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.161750206 Jul 01 10:35:11 AM PDT 24 Jul 01 10:35:18 AM PDT 24 213873246 ps
T1150 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.945736569 Jul 01 10:35:09 AM PDT 24 Jul 01 10:35:18 AM PDT 24 72626586 ps
T1151 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3046525207 Jul 01 10:35:07 AM PDT 24 Jul 01 10:35:16 AM PDT 24 88538561 ps

Test location /workspace/coverage/default/41.spi_device_stress_all.2797900594
Short name T8
Test name
Test status
Simulation time 4494420666 ps
CPU time 22.33 seconds
Started Jul 01 11:53:38 AM PDT 24
Finished Jul 01 11:54:05 AM PDT 24
Peak memory 250464 kb
Host smart-0bcc20aa-3542-49e1-a6c1-ac851025094f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797900594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2797900594
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1565045678
Short name T14
Test name
Test status
Simulation time 65476039924 ps
CPU time 416.31 seconds
Started Jul 01 11:53:08 AM PDT 24
Finished Jul 01 12:00:07 PM PDT 24
Peak memory 258512 kb
Host smart-a5b05315-251d-4f19-bf94-42bacddf5a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565045678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1565045678
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.59780075
Short name T46
Test name
Test status
Simulation time 8295109765 ps
CPU time 141.41 seconds
Started Jul 01 11:51:13 AM PDT 24
Finished Jul 01 11:53:36 AM PDT 24
Peak memory 255532 kb
Host smart-8e011d4a-7e12-4960-8e0f-63f0436c7f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59780075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.59780075
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1899836139
Short name T93
Test name
Test status
Simulation time 739725107 ps
CPU time 15.83 seconds
Started Jul 01 10:35:39 AM PDT 24
Finished Jul 01 10:35:56 AM PDT 24
Peak memory 215600 kb
Host smart-4e771b65-3406-44c8-b700-25e3d82f1501
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899836139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1899836139
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1685605288
Short name T29
Test name
Test status
Simulation time 5205873781 ps
CPU time 101.41 seconds
Started Jul 01 11:53:07 AM PDT 24
Finished Jul 01 11:54:51 AM PDT 24
Peak memory 257364 kb
Host smart-be0e0464-264a-4056-bb32-f01e45035f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685605288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1685605288
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2613385685
Short name T20
Test name
Test status
Simulation time 294438065453 ps
CPU time 651.55 seconds
Started Jul 01 11:49:01 AM PDT 24
Finished Jul 01 11:59:54 AM PDT 24
Peak memory 275024 kb
Host smart-c760913a-6a1c-4384-bcd7-278ea8844267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613385685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2613385685
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.484159928
Short name T65
Test name
Test status
Simulation time 39015310 ps
CPU time 0.81 seconds
Started Jul 01 11:48:01 AM PDT 24
Finished Jul 01 11:48:02 AM PDT 24
Peak memory 217052 kb
Host smart-d921c82f-459a-4141-b946-d64b618664a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484159928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.484159928
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3538458041
Short name T28
Test name
Test status
Simulation time 4136878889 ps
CPU time 53.31 seconds
Started Jul 01 11:53:51 AM PDT 24
Finished Jul 01 11:54:48 AM PDT 24
Peak memory 242084 kb
Host smart-16d0292a-5e07-4cb0-abf8-c56df9eeaa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538458041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3538458041
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3986854902
Short name T23
Test name
Test status
Simulation time 68820690286 ps
CPU time 242.01 seconds
Started Jul 01 11:52:57 AM PDT 24
Finished Jul 01 11:57:01 AM PDT 24
Peak memory 283844 kb
Host smart-aac596ee-0e41-4a40-b3cb-9e1237b43aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986854902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3986854902
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2370005552
Short name T182
Test name
Test status
Simulation time 69301295371 ps
CPU time 465.21 seconds
Started Jul 01 11:53:51 AM PDT 24
Finished Jul 01 12:01:39 PM PDT 24
Peak memory 262296 kb
Host smart-394c561f-5782-4613-ac49-d62875a4b820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370005552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2370005552
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1139967543
Short name T167
Test name
Test status
Simulation time 8791272752 ps
CPU time 117.03 seconds
Started Jul 01 11:51:57 AM PDT 24
Finished Jul 01 11:53:55 AM PDT 24
Peak memory 257676 kb
Host smart-50a8d865-73c4-4343-a915-6210c8628cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139967543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1139967543
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3943762058
Short name T22
Test name
Test status
Simulation time 98435968660 ps
CPU time 418.73 seconds
Started Jul 01 11:48:32 AM PDT 24
Finished Jul 01 11:55:31 AM PDT 24
Peak memory 268212 kb
Host smart-e3ddabb0-94e6-487a-86a4-880ff463a02a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943762058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3943762058
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.636544111
Short name T146
Test name
Test status
Simulation time 6496727064 ps
CPU time 30.73 seconds
Started Jul 01 11:49:38 AM PDT 24
Finished Jul 01 11:50:09 AM PDT 24
Peak memory 225708 kb
Host smart-0f32a63c-caff-472b-9956-417a49a6fd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636544111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.636544111
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3071551626
Short name T92
Test name
Test status
Simulation time 256880216 ps
CPU time 3.13 seconds
Started Jul 01 10:35:12 AM PDT 24
Finished Jul 01 10:35:20 AM PDT 24
Peak memory 215784 kb
Host smart-b38efe69-8353-439d-8b69-c6b526d7bf52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071551626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3071551626
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1016231342
Short name T2
Test name
Test status
Simulation time 17047401 ps
CPU time 0.75 seconds
Started Jul 01 11:54:15 AM PDT 24
Finished Jul 01 11:54:17 AM PDT 24
Peak memory 206388 kb
Host smart-3f080c76-2f0d-45e3-8e38-dfe6d8649006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016231342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1016231342
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1208676175
Short name T19
Test name
Test status
Simulation time 6040000022 ps
CPU time 133.65 seconds
Started Jul 01 11:54:16 AM PDT 24
Finished Jul 01 11:56:32 AM PDT 24
Peak memory 272288 kb
Host smart-b9f5f80e-16dc-453d-aa05-2ebbf6bdddaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208676175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1208676175
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1504291755
Short name T48
Test name
Test status
Simulation time 7127520133 ps
CPU time 53.88 seconds
Started Jul 01 11:49:44 AM PDT 24
Finished Jul 01 11:50:39 AM PDT 24
Peak memory 253036 kb
Host smart-e3c814c5-a5f7-49d6-b349-90c28cf886c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504291755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1504291755
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1018368600
Short name T199
Test name
Test status
Simulation time 50659984194 ps
CPU time 260.13 seconds
Started Jul 01 11:51:24 AM PDT 24
Finished Jul 01 11:55:45 AM PDT 24
Peak memory 254100 kb
Host smart-dfc06e49-dba2-4376-8f2f-5531776d8285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018368600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1018368600
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.393420316
Short name T81
Test name
Test status
Simulation time 118262018 ps
CPU time 0.94 seconds
Started Jul 01 10:35:04 AM PDT 24
Finished Jul 01 10:35:11 AM PDT 24
Peak memory 206960 kb
Host smart-9610e943-af2b-43be-9ce3-fac9ffa0c46a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393420316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.393420316
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2399729122
Short name T201
Test name
Test status
Simulation time 11615016957 ps
CPU time 176.42 seconds
Started Jul 01 11:50:30 AM PDT 24
Finished Jul 01 11:53:27 AM PDT 24
Peak memory 265896 kb
Host smart-03176833-60da-4a40-a128-6575142d5373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399729122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2399729122
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2689153191
Short name T262
Test name
Test status
Simulation time 19286842028 ps
CPU time 131.15 seconds
Started Jul 01 11:50:25 AM PDT 24
Finished Jul 01 11:52:37 AM PDT 24
Peak memory 257572 kb
Host smart-adc25f68-3d54-433b-90a2-a502138a7f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689153191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2689153191
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2632937883
Short name T383
Test name
Test status
Simulation time 78624136 ps
CPU time 1.01 seconds
Started Jul 01 11:50:16 AM PDT 24
Finished Jul 01 11:50:19 AM PDT 24
Peak memory 219064 kb
Host smart-d54abb76-4a60-4728-9f85-3d0f9d2ef063
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632937883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2632937883
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4021278696
Short name T176
Test name
Test status
Simulation time 10746514979 ps
CPU time 79.23 seconds
Started Jul 01 11:52:17 AM PDT 24
Finished Jul 01 11:53:38 AM PDT 24
Peak memory 260964 kb
Host smart-4952c52b-94b6-439d-b3ca-201b7c52f560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021278696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4021278696
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.62092456
Short name T21
Test name
Test status
Simulation time 126961640 ps
CPU time 1.01 seconds
Started Jul 01 11:48:16 AM PDT 24
Finished Jul 01 11:48:17 AM PDT 24
Peak memory 236692 kb
Host smart-65ac6db5-9b0b-43cb-8fcd-986705f3890a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62092456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.62092456
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1107621953
Short name T165
Test name
Test status
Simulation time 24313616923 ps
CPU time 220.38 seconds
Started Jul 01 11:48:11 AM PDT 24
Finished Jul 01 11:51:52 AM PDT 24
Peak memory 250460 kb
Host smart-a447c6eb-df80-4565-98f8-fa6e7bbc29f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107621953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1107621953
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3426012001
Short name T35
Test name
Test status
Simulation time 610686710196 ps
CPU time 1265.99 seconds
Started Jul 01 11:50:36 AM PDT 24
Finished Jul 01 12:11:42 PM PDT 24
Peak memory 291356 kb
Host smart-6002c162-73f3-472a-91a3-5ca83ef83c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426012001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3426012001
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1290270860
Short name T206
Test name
Test status
Simulation time 33515348916 ps
CPU time 322.31 seconds
Started Jul 01 11:51:02 AM PDT 24
Finished Jul 01 11:56:26 AM PDT 24
Peak memory 253740 kb
Host smart-5ec7ed0b-0839-4008-b8ee-bd0b85caa2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290270860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1290270860
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1343765775
Short name T43
Test name
Test status
Simulation time 6488398554 ps
CPU time 92.04 seconds
Started Jul 01 11:49:31 AM PDT 24
Finished Jul 01 11:51:04 AM PDT 24
Peak memory 258468 kb
Host smart-5f2a250e-aca5-416b-b7e8-bf6620d0526a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343765775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1343765775
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2939794799
Short name T63
Test name
Test status
Simulation time 28952084144 ps
CPU time 207.2 seconds
Started Jul 01 11:50:26 AM PDT 24
Finished Jul 01 11:53:55 AM PDT 24
Peak memory 250288 kb
Host smart-bf398b8f-36b5-4c63-b12a-f24321c11d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939794799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2939794799
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2437116016
Short name T190
Test name
Test status
Simulation time 22939120461 ps
CPU time 75.07 seconds
Started Jul 01 11:50:40 AM PDT 24
Finished Jul 01 11:51:55 AM PDT 24
Peak memory 263764 kb
Host smart-812da7db-021f-420f-856f-66823a36bfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437116016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2437116016
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2858399510
Short name T103
Test name
Test status
Simulation time 53549443 ps
CPU time 3.33 seconds
Started Jul 01 10:35:17 AM PDT 24
Finished Jul 01 10:35:25 AM PDT 24
Peak memory 215560 kb
Host smart-f17cf4f8-4e42-4768-9984-d6b4b67bb6bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858399510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2858399510
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.90000671
Short name T111
Test name
Test status
Simulation time 215381942 ps
CPU time 12.86 seconds
Started Jul 01 10:35:05 AM PDT 24
Finished Jul 01 10:35:24 AM PDT 24
Peak memory 215348 kb
Host smart-6c01858b-0984-46da-aea5-47b2934dd93a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90000671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_t
l_intg_err.90000671
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4108575792
Short name T219
Test name
Test status
Simulation time 5800233455 ps
CPU time 68.49 seconds
Started Jul 01 11:51:44 AM PDT 24
Finished Jul 01 11:52:54 AM PDT 24
Peak memory 272648 kb
Host smart-bf632ca2-ee6b-418c-bc9b-468575f9b0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108575792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4108575792
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1176909433
Short name T196
Test name
Test status
Simulation time 9910187239 ps
CPU time 153.67 seconds
Started Jul 01 11:52:44 AM PDT 24
Finished Jul 01 11:55:22 AM PDT 24
Peak memory 272808 kb
Host smart-0efdf104-a43f-4d14-8a88-839ef2303c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176909433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1176909433
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.936531861
Short name T160
Test name
Test status
Simulation time 314692926 ps
CPU time 19.02 seconds
Started Jul 01 10:35:08 AM PDT 24
Finished Jul 01 10:35:34 AM PDT 24
Peak memory 215368 kb
Host smart-8066c164-38c3-4b34-9e6b-a20439a78dad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936531861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.936531861
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1792926256
Short name T79
Test name
Test status
Simulation time 40178476208 ps
CPU time 359.98 seconds
Started Jul 01 11:50:07 AM PDT 24
Finished Jul 01 11:56:08 AM PDT 24
Peak memory 252648 kb
Host smart-9d3c65c6-5285-4c7e-b6b7-59a11254978e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792926256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1792926256
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3579255801
Short name T306
Test name
Test status
Simulation time 2602119439 ps
CPU time 5.34 seconds
Started Jul 01 11:50:53 AM PDT 24
Finished Jul 01 11:50:59 AM PDT 24
Peak memory 217428 kb
Host smart-70845ba5-5426-4a1d-94c4-ea47aaf3057e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579255801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3579255801
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.338423970
Short name T175
Test name
Test status
Simulation time 133782273180 ps
CPU time 412.48 seconds
Started Jul 01 11:52:11 AM PDT 24
Finished Jul 01 11:59:05 AM PDT 24
Peak memory 265472 kb
Host smart-5e0da1d7-5a41-4ad8-bb52-025d9183131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338423970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.338423970
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1355441107
Short name T847
Test name
Test status
Simulation time 5670261479 ps
CPU time 29.75 seconds
Started Jul 01 11:52:57 AM PDT 24
Finished Jul 01 11:53:29 AM PDT 24
Peak memory 225680 kb
Host smart-b19b66a0-7af3-453f-a7f8-9d762c3a2afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355441107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1355441107
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1346345665
Short name T899
Test name
Test status
Simulation time 1730311079 ps
CPU time 6.56 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:53:48 AM PDT 24
Peak memory 225604 kb
Host smart-53f6f3bc-e5ca-45ac-950e-3e54a97d4b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346345665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1346345665
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2135707623
Short name T883
Test name
Test status
Simulation time 108144498627 ps
CPU time 184.31 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:56:57 AM PDT 24
Peak memory 252924 kb
Host smart-1350b2bf-4a10-4f81-944b-1fff979c45f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135707623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2135707623
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.411216896
Short name T1003
Test name
Test status
Simulation time 1519821037 ps
CPU time 16.02 seconds
Started Jul 01 11:51:12 AM PDT 24
Finished Jul 01 11:51:29 AM PDT 24
Peak memory 233808 kb
Host smart-85306306-f53f-4ddd-b89f-93ba561d8823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411216896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.411216896
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2381856036
Short name T171
Test name
Test status
Simulation time 248320188 ps
CPU time 1.6 seconds
Started Jul 01 10:35:14 AM PDT 24
Finished Jul 01 10:35:21 AM PDT 24
Peak memory 215708 kb
Host smart-660caa09-71d7-4419-b675-05700289c3f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381856036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
381856036
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3625919093
Short name T300
Test name
Test status
Simulation time 44855028257 ps
CPU time 423.18 seconds
Started Jul 01 11:50:26 AM PDT 24
Finished Jul 01 11:57:30 AM PDT 24
Peak memory 258152 kb
Host smart-afe017a3-6ba3-48f0-8421-24c2ccb612ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625919093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3625919093
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3489324709
Short name T12
Test name
Test status
Simulation time 163957875772 ps
CPU time 132.23 seconds
Started Jul 01 11:52:50 AM PDT 24
Finished Jul 01 11:55:03 AM PDT 24
Peak memory 252164 kb
Host smart-76f85419-8026-433e-bdf6-5d00774eecd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489324709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3489324709
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4119104769
Short name T45
Test name
Test status
Simulation time 30672196438 ps
CPU time 13.6 seconds
Started Jul 01 11:53:43 AM PDT 24
Finished Jul 01 11:54:03 AM PDT 24
Peak memory 233856 kb
Host smart-e04e38a9-bfa6-4aac-91d1-abb161172674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119104769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4119104769
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1273625891
Short name T1
Test name
Test status
Simulation time 1512836706 ps
CPU time 5.2 seconds
Started Jul 01 11:51:42 AM PDT 24
Finished Jul 01 11:51:49 AM PDT 24
Peak memory 233836 kb
Host smart-097d0175-4254-4258-9bab-2af6678d69cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273625891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1273625891
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2847424788
Short name T84
Test name
Test status
Simulation time 46006815 ps
CPU time 1.11 seconds
Started Jul 01 10:35:43 AM PDT 24
Finished Jul 01 10:35:45 AM PDT 24
Peak memory 207132 kb
Host smart-e0849a72-68ed-44ca-8f0b-e3b00c7e7ab6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847424788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2847424788
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1378639206
Short name T1126
Test name
Test status
Simulation time 207099866 ps
CPU time 13.41 seconds
Started Jul 01 10:35:00 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 207112 kb
Host smart-c0555e45-46fc-4d69-b1c5-dcf51ef525bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378639206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1378639206
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2572703683
Short name T1055
Test name
Test status
Simulation time 637968764 ps
CPU time 11.68 seconds
Started Jul 01 10:35:03 AM PDT 24
Finished Jul 01 10:35:20 AM PDT 24
Peak memory 207148 kb
Host smart-12d01de3-c68c-4000-8f74-c6ffda070f8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572703683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2572703683
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3982747278
Short name T112
Test name
Test status
Simulation time 102576766 ps
CPU time 1.68 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 215832 kb
Host smart-cd66d546-954a-4f7f-a0dd-b9a4846b202b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982747278 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3982747278
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1120141353
Short name T140
Test name
Test status
Simulation time 35229012 ps
CPU time 1.13 seconds
Started Jul 01 10:35:04 AM PDT 24
Finished Jul 01 10:35:10 AM PDT 24
Peak memory 215376 kb
Host smart-0c1991bb-1fff-4067-808b-054da1b2c033
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120141353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
120141353
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3809681176
Short name T1031
Test name
Test status
Simulation time 13451521 ps
CPU time 0.69 seconds
Started Jul 01 10:35:02 AM PDT 24
Finished Jul 01 10:35:07 AM PDT 24
Peak memory 203816 kb
Host smart-5f72157a-4c55-4278-b249-b492168d778b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809681176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
809681176
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3382684841
Short name T114
Test name
Test status
Simulation time 54024776 ps
CPU time 1.21 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 215452 kb
Host smart-af2ae540-c870-4ab4-b111-447f263adad2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382684841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3382684841
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4176427103
Short name T1041
Test name
Test status
Simulation time 16162524 ps
CPU time 0.65 seconds
Started Jul 01 10:35:00 AM PDT 24
Finished Jul 01 10:35:04 AM PDT 24
Peak memory 203788 kb
Host smart-fdd6bb28-63b8-45a9-992e-dea065b8334e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176427103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4176427103
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1020212648
Short name T1059
Test name
Test status
Simulation time 216740514 ps
CPU time 2.97 seconds
Started Jul 01 10:34:59 AM PDT 24
Finished Jul 01 10:35:04 AM PDT 24
Peak memory 215400 kb
Host smart-00f3029a-4664-4818-b6f9-c16c8371c786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020212648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1020212648
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.183269184
Short name T98
Test name
Test status
Simulation time 1478937808 ps
CPU time 4.26 seconds
Started Jul 01 10:35:00 AM PDT 24
Finished Jul 01 10:35:08 AM PDT 24
Peak memory 215608 kb
Host smart-a8f660ed-ec94-42eb-bc20-5bc7b3594409
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183269184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.183269184
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.128241487
Short name T1084
Test name
Test status
Simulation time 413438509 ps
CPU time 14.08 seconds
Started Jul 01 10:35:01 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 215332 kb
Host smart-ea44b160-516d-4767-a882-990022327713
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128241487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.128241487
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3261080647
Short name T1051
Test name
Test status
Simulation time 617435639 ps
CPU time 12.62 seconds
Started Jul 01 10:35:04 AM PDT 24
Finished Jul 01 10:35:21 AM PDT 24
Peak memory 207100 kb
Host smart-f4fe64be-90e5-426f-97b7-8140e2675253
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261080647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3261080647
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2665868730
Short name T151
Test name
Test status
Simulation time 54478429 ps
CPU time 1.66 seconds
Started Jul 01 10:35:02 AM PDT 24
Finished Jul 01 10:35:08 AM PDT 24
Peak memory 215576 kb
Host smart-b4da9723-336f-45b8-9a51-5ef5c060745f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665868730 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2665868730
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.208904668
Short name T119
Test name
Test status
Simulation time 27851043 ps
CPU time 1.33 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 207172 kb
Host smart-4a567d20-da26-4bf1-852d-e15911db29cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208904668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.208904668
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.334148852
Short name T1108
Test name
Test status
Simulation time 14797112 ps
CPU time 0.74 seconds
Started Jul 01 10:35:10 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 204232 kb
Host smart-df642d9d-e03d-49c2-bbad-e75e723443e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334148852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.334148852
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.945736569
Short name T1150
Test name
Test status
Simulation time 72626586 ps
CPU time 2.19 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 215428 kb
Host smart-78d557e4-41c0-4f17-9d4b-e464efdfeabc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945736569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.945736569
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2152725305
Short name T1074
Test name
Test status
Simulation time 11471122 ps
CPU time 0.65 seconds
Started Jul 01 10:34:59 AM PDT 24
Finished Jul 01 10:35:03 AM PDT 24
Peak memory 203740 kb
Host smart-4178414b-1179-49ba-81bb-08b8ea76f3b9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152725305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2152725305
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1761520099
Short name T1046
Test name
Test status
Simulation time 77899026 ps
CPU time 2.61 seconds
Started Jul 01 10:35:15 AM PDT 24
Finished Jul 01 10:35:23 AM PDT 24
Peak memory 215304 kb
Host smart-93b388a6-8b3d-476c-90b9-61dbc5f581c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761520099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1761520099
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2586335792
Short name T1123
Test name
Test status
Simulation time 45928916 ps
CPU time 2.75 seconds
Started Jul 01 10:35:25 AM PDT 24
Finished Jul 01 10:35:29 AM PDT 24
Peak memory 215660 kb
Host smart-94c64831-2821-4b39-a96a-94f2130da0b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586335792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
586335792
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1624903387
Short name T1053
Test name
Test status
Simulation time 212165458 ps
CPU time 12.74 seconds
Started Jul 01 10:35:03 AM PDT 24
Finished Jul 01 10:35:21 AM PDT 24
Peak memory 215396 kb
Host smart-0a9948fd-6cd6-4205-b650-61d6b0a4e9a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624903387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1624903387
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1654947429
Short name T104
Test name
Test status
Simulation time 86002409 ps
CPU time 2.53 seconds
Started Jul 01 10:35:08 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 216484 kb
Host smart-538de36d-cac0-46cb-aa75-405b9bfc818b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654947429 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1654947429
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.318271393
Short name T117
Test name
Test status
Simulation time 163916490 ps
CPU time 2.49 seconds
Started Jul 01 10:35:02 AM PDT 24
Finished Jul 01 10:35:09 AM PDT 24
Peak memory 215372 kb
Host smart-290a2490-2e0f-4540-a9c4-45fa44c6eb5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318271393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.318271393
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.952028216
Short name T1095
Test name
Test status
Simulation time 18223258 ps
CPU time 0.73 seconds
Started Jul 01 10:35:30 AM PDT 24
Finished Jul 01 10:35:32 AM PDT 24
Peak memory 203896 kb
Host smart-30c81fe6-ad85-4dcf-903a-69b2ed233c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952028216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.952028216
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.628991614
Short name T1109
Test name
Test status
Simulation time 141727946 ps
CPU time 2.92 seconds
Started Jul 01 10:35:36 AM PDT 24
Finished Jul 01 10:35:41 AM PDT 24
Peak memory 215424 kb
Host smart-28b32a62-4da7-407f-a14f-895afe463d82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628991614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.628991614
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3395712571
Short name T107
Test name
Test status
Simulation time 517833145 ps
CPU time 2.92 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:19 AM PDT 24
Peak memory 216756 kb
Host smart-e1f79100-f666-4662-83cd-8c4d07107ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395712571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3395712571
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4038417843
Short name T1090
Test name
Test status
Simulation time 1017054524 ps
CPU time 6.77 seconds
Started Jul 01 10:35:08 AM PDT 24
Finished Jul 01 10:35:21 AM PDT 24
Peak memory 215444 kb
Host smart-f785b628-7cdc-4470-b7c0-cd7a5dd92218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038417843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4038417843
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3068829390
Short name T1099
Test name
Test status
Simulation time 115200624 ps
CPU time 3.57 seconds
Started Jul 01 10:35:20 AM PDT 24
Finished Jul 01 10:35:27 AM PDT 24
Peak memory 217260 kb
Host smart-64406ec8-2a3a-4660-adfe-2ba8c76a6865
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068829390 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3068829390
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4071339806
Short name T1129
Test name
Test status
Simulation time 824784413 ps
CPU time 2.79 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:19 AM PDT 24
Peak memory 207356 kb
Host smart-ad3b6d96-cea3-4759-9fe4-e912aa52ce5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071339806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4071339806
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1254911747
Short name T1086
Test name
Test status
Simulation time 76790177 ps
CPU time 0.73 seconds
Started Jul 01 10:35:19 AM PDT 24
Finished Jul 01 10:35:23 AM PDT 24
Peak memory 203944 kb
Host smart-d3ab518c-c325-4850-84f9-e79d6a409a8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254911747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1254911747
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.624954936
Short name T1067
Test name
Test status
Simulation time 87910674 ps
CPU time 2.62 seconds
Started Jul 01 10:35:06 AM PDT 24
Finished Jul 01 10:35:15 AM PDT 24
Peak memory 215980 kb
Host smart-8ef0c405-2e8a-43cd-a473-d6267f60d725
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624954936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.624954936
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.409051487
Short name T1125
Test name
Test status
Simulation time 38104676 ps
CPU time 2.39 seconds
Started Jul 01 10:35:23 AM PDT 24
Finished Jul 01 10:35:27 AM PDT 24
Peak memory 215656 kb
Host smart-93f7dc02-5a32-4c1c-862c-721f5ee3c5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409051487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.409051487
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2494137526
Short name T163
Test name
Test status
Simulation time 110982570 ps
CPU time 6.38 seconds
Started Jul 01 10:35:26 AM PDT 24
Finished Jul 01 10:35:33 AM PDT 24
Peak memory 215500 kb
Host smart-3fd7c292-da34-4ac2-b64d-23b25af94f79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494137526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2494137526
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4171143977
Short name T1135
Test name
Test status
Simulation time 341848053 ps
CPU time 2.88 seconds
Started Jul 01 10:37:12 AM PDT 24
Finished Jul 01 10:37:16 AM PDT 24
Peak memory 217196 kb
Host smart-03bb49ac-2fb3-435e-9a16-fe2791c6f828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171143977 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4171143977
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.899364095
Short name T152
Test name
Test status
Simulation time 87328902 ps
CPU time 1.37 seconds
Started Jul 01 10:35:04 AM PDT 24
Finished Jul 01 10:35:12 AM PDT 24
Peak memory 207344 kb
Host smart-fdaa15e2-1191-440c-9dbc-09dcb93e7f67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899364095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.899364095
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.570937129
Short name T1052
Test name
Test status
Simulation time 16875174 ps
CPU time 0.73 seconds
Started Jul 01 10:36:04 AM PDT 24
Finished Jul 01 10:36:07 AM PDT 24
Peak memory 204188 kb
Host smart-f2c6c7c8-bd96-4544-995b-2f1a82d98708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570937129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.570937129
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1773338157
Short name T1079
Test name
Test status
Simulation time 854047289 ps
CPU time 4.49 seconds
Started Jul 01 10:35:29 AM PDT 24
Finished Jul 01 10:35:34 AM PDT 24
Peak memory 215376 kb
Host smart-a0dbfd8b-6ec3-48f6-9ead-c95fd227b583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773338157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1773338157
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3557191005
Short name T102
Test name
Test status
Simulation time 374793354 ps
CPU time 4.55 seconds
Started Jul 01 10:35:16 AM PDT 24
Finished Jul 01 10:35:25 AM PDT 24
Peak memory 215672 kb
Host smart-06f4efbb-9cbc-4948-932c-c868cd7cb3ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557191005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3557191005
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1429294515
Short name T1075
Test name
Test status
Simulation time 588253690 ps
CPU time 16.92 seconds
Started Jul 01 10:35:23 AM PDT 24
Finished Jul 01 10:35:41 AM PDT 24
Peak memory 215628 kb
Host smart-1f9bd731-fcf3-4b45-8c14-a782c07b774b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429294515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1429294515
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3430526961
Short name T1110
Test name
Test status
Simulation time 23197801 ps
CPU time 1.53 seconds
Started Jul 01 10:35:42 AM PDT 24
Finished Jul 01 10:35:45 AM PDT 24
Peak memory 215476 kb
Host smart-1cd3e039-3ac7-437d-8121-ce8755575ebb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430526961 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3430526961
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1969718612
Short name T1088
Test name
Test status
Simulation time 30173008 ps
CPU time 1.91 seconds
Started Jul 01 10:35:44 AM PDT 24
Finished Jul 01 10:35:47 AM PDT 24
Peak memory 215372 kb
Host smart-f94dcb1b-9eec-4a51-9706-721a387d0e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969718612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1969718612
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2721545084
Short name T1038
Test name
Test status
Simulation time 28640068 ps
CPU time 0.71 seconds
Started Jul 01 10:35:12 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 203848 kb
Host smart-7869cf97-d018-49ae-a0da-35cb3c8493c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721545084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2721545084
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3066202504
Short name T1143
Test name
Test status
Simulation time 249442374 ps
CPU time 2.78 seconds
Started Jul 01 10:37:20 AM PDT 24
Finished Jul 01 10:37:23 AM PDT 24
Peak memory 215344 kb
Host smart-c4f7cdf3-2983-4149-9a5b-f59f79f75227
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066202504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3066202504
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.161750206
Short name T1149
Test name
Test status
Simulation time 213873246 ps
CPU time 1.34 seconds
Started Jul 01 10:35:11 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 215672 kb
Host smart-9b8a4a47-33a6-4ca3-8bf7-7c1c2f9259e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161750206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.161750206
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3092498790
Short name T1102
Test name
Test status
Simulation time 85359618 ps
CPU time 1.58 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 215404 kb
Host smart-4b41b36b-14c1-40b0-9478-1d2ad905cb1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092498790 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3092498790
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2659937286
Short name T1100
Test name
Test status
Simulation time 60681425 ps
CPU time 1.16 seconds
Started Jul 01 10:35:16 AM PDT 24
Finished Jul 01 10:35:22 AM PDT 24
Peak memory 207152 kb
Host smart-71dae2d1-9534-4ed7-984c-62c1ea9c64d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659937286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2659937286
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3356832426
Short name T1112
Test name
Test status
Simulation time 17316303 ps
CPU time 0.79 seconds
Started Jul 01 10:35:12 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 203904 kb
Host smart-e97a3b25-09d1-4072-8fc3-55f24855ea86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356832426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3356832426
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1811189176
Short name T1107
Test name
Test status
Simulation time 29563352 ps
CPU time 1.78 seconds
Started Jul 01 10:35:35 AM PDT 24
Finished Jul 01 10:35:39 AM PDT 24
Peak memory 215400 kb
Host smart-1b93577e-cec2-4d1b-b87a-70a8f649b2a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811189176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1811189176
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1233840878
Short name T95
Test name
Test status
Simulation time 137414955 ps
CPU time 3.99 seconds
Started Jul 01 10:35:12 AM PDT 24
Finished Jul 01 10:35:21 AM PDT 24
Peak memory 215724 kb
Host smart-6ec7a221-6ebc-4ae2-bbe3-64c0ba686134
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233840878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1233840878
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2397344706
Short name T1050
Test name
Test status
Simulation time 282848078 ps
CPU time 7.61 seconds
Started Jul 01 10:35:19 AM PDT 24
Finished Jul 01 10:35:30 AM PDT 24
Peak memory 216308 kb
Host smart-be3bc0ed-33ff-46dd-8341-eee408ac62ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397344706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2397344706
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1594877592
Short name T1070
Test name
Test status
Simulation time 134068563 ps
CPU time 1.7 seconds
Started Jul 01 10:35:13 AM PDT 24
Finished Jul 01 10:35:20 AM PDT 24
Peak memory 215376 kb
Host smart-5e6f02c5-8d17-4f17-a21e-128777eac98a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594877592 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1594877592
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2268665442
Short name T118
Test name
Test status
Simulation time 35153166 ps
CPU time 2.24 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 207256 kb
Host smart-1f6b2270-d911-4cab-9fbe-0f50bdc128df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268665442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2268665442
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4053377857
Short name T1072
Test name
Test status
Simulation time 31208266 ps
CPU time 0.72 seconds
Started Jul 01 10:35:42 AM PDT 24
Finished Jul 01 10:35:44 AM PDT 24
Peak memory 203896 kb
Host smart-123b6418-54f4-4461-8146-7f5f47e4ac81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053377857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4053377857
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1578964177
Short name T154
Test name
Test status
Simulation time 453362964 ps
CPU time 4.29 seconds
Started Jul 01 10:35:25 AM PDT 24
Finished Jul 01 10:35:35 AM PDT 24
Peak memory 215400 kb
Host smart-388b31fa-e11a-4bae-ae01-4ad0b9b8a8fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578964177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1578964177
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.915401615
Short name T96
Test name
Test status
Simulation time 1216873021 ps
CPU time 18.71 seconds
Started Jul 01 10:35:15 AM PDT 24
Finished Jul 01 10:35:39 AM PDT 24
Peak memory 215724 kb
Host smart-cd795ff6-84d2-4958-9379-7afbe3fd8176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915401615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.915401615
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4055254013
Short name T1127
Test name
Test status
Simulation time 204853463 ps
CPU time 2.86 seconds
Started Jul 01 10:35:11 AM PDT 24
Finished Jul 01 10:35:20 AM PDT 24
Peak memory 216532 kb
Host smart-888676a1-368b-4438-8078-6f1b5fbeb52f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055254013 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4055254013
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1718774178
Short name T1134
Test name
Test status
Simulation time 43970702 ps
CPU time 1.28 seconds
Started Jul 01 10:35:11 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 207232 kb
Host smart-bf282576-a5fd-4fe1-b5df-682456a12413
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718774178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1718774178
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.707109888
Short name T1146
Test name
Test status
Simulation time 40876736 ps
CPU time 0.69 seconds
Started Jul 01 10:35:16 AM PDT 24
Finished Jul 01 10:35:21 AM PDT 24
Peak memory 203772 kb
Host smart-41504370-f66c-48bb-83a4-ab76f0205979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707109888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.707109888
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2380237651
Short name T150
Test name
Test status
Simulation time 201414495 ps
CPU time 4.04 seconds
Started Jul 01 10:35:17 AM PDT 24
Finished Jul 01 10:35:26 AM PDT 24
Peak memory 215360 kb
Host smart-bc734cab-0f16-4c16-a4f0-a1335c03e68c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380237651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2380237651
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.788258436
Short name T1131
Test name
Test status
Simulation time 1009916761 ps
CPU time 7.63 seconds
Started Jul 01 10:35:45 AM PDT 24
Finished Jul 01 10:35:54 AM PDT 24
Peak memory 215612 kb
Host smart-4ee9ad73-3cc7-4f38-9101-2b7f7234379d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788258436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.788258436
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1337737742
Short name T106
Test name
Test status
Simulation time 168709298 ps
CPU time 2.71 seconds
Started Jul 01 10:35:14 AM PDT 24
Finished Jul 01 10:35:22 AM PDT 24
Peak memory 217708 kb
Host smart-57793801-3d8f-4c0d-b749-85f2e96b7433
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337737742 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1337737742
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4254890065
Short name T123
Test name
Test status
Simulation time 183593498 ps
CPU time 2.52 seconds
Started Jul 01 10:35:08 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 215384 kb
Host smart-9b9c6cef-ea78-49a5-a0f4-bf2ca202aa01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254890065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4254890065
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3494603878
Short name T1032
Test name
Test status
Simulation time 25886056 ps
CPU time 0.7 seconds
Started Jul 01 10:35:35 AM PDT 24
Finished Jul 01 10:35:38 AM PDT 24
Peak memory 203884 kb
Host smart-3c6269fe-d5c5-4c8c-b233-d515a6447f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494603878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3494603878
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1946163308
Short name T153
Test name
Test status
Simulation time 422190902 ps
CPU time 3.09 seconds
Started Jul 01 10:35:12 AM PDT 24
Finished Jul 01 10:35:21 AM PDT 24
Peak memory 215344 kb
Host smart-a315ceaf-c9f4-437f-a075-c6fbe82dcc1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946163308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1946163308
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2898027682
Short name T1128
Test name
Test status
Simulation time 118900006 ps
CPU time 1.9 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 215700 kb
Host smart-55f84398-a39f-49d1-8f13-98611a2a1f42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898027682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2898027682
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3873495289
Short name T109
Test name
Test status
Simulation time 468352703 ps
CPU time 6.03 seconds
Started Jul 01 10:35:12 AM PDT 24
Finished Jul 01 10:35:24 AM PDT 24
Peak memory 215392 kb
Host smart-898d7f99-c261-4e69-b399-7af574381bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873495289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3873495289
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.537006157
Short name T1077
Test name
Test status
Simulation time 941143476 ps
CPU time 1.6 seconds
Started Jul 01 10:35:25 AM PDT 24
Finished Jul 01 10:35:27 AM PDT 24
Peak memory 215796 kb
Host smart-35c4b2f4-cc60-4d8d-b6f8-11981ef67725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537006157 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.537006157
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1510598973
Short name T141
Test name
Test status
Simulation time 46784002 ps
CPU time 1.27 seconds
Started Jul 01 10:35:53 AM PDT 24
Finished Jul 01 10:35:57 AM PDT 24
Peak memory 207144 kb
Host smart-df6f070d-08d6-4b52-932f-873570fe8c4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510598973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1510598973
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.18981567
Short name T1139
Test name
Test status
Simulation time 12388083 ps
CPU time 0.74 seconds
Started Jul 01 10:35:25 AM PDT 24
Finished Jul 01 10:35:27 AM PDT 24
Peak memory 203940 kb
Host smart-2f773ec5-8265-433c-9a78-270ce2c2c67b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18981567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.18981567
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3054509084
Short name T1062
Test name
Test status
Simulation time 173650780 ps
CPU time 2.64 seconds
Started Jul 01 10:35:05 AM PDT 24
Finished Jul 01 10:35:14 AM PDT 24
Peak memory 215364 kb
Host smart-54405612-0cd1-449b-bc14-d89bb24f9a5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054509084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3054509084
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3766778318
Short name T1132
Test name
Test status
Simulation time 34921836 ps
CPU time 2.33 seconds
Started Jul 01 10:35:19 AM PDT 24
Finished Jul 01 10:35:25 AM PDT 24
Peak memory 215624 kb
Host smart-834a1fa3-eb01-4812-99e6-ff3c1d2a5490
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766778318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3766778318
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1010621562
Short name T1136
Test name
Test status
Simulation time 630710217 ps
CPU time 14.53 seconds
Started Jul 01 10:35:31 AM PDT 24
Finished Jul 01 10:35:47 AM PDT 24
Peak memory 215440 kb
Host smart-5650d751-f184-4b43-9109-d3e5d7b07448
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010621562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1010621562
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2877533904
Short name T1069
Test name
Test status
Simulation time 205493362 ps
CPU time 1.87 seconds
Started Jul 01 10:35:55 AM PDT 24
Finished Jul 01 10:36:00 AM PDT 24
Peak memory 216460 kb
Host smart-73656307-166f-40dc-bfb5-31db476ac3b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877533904 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2877533904
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3046525207
Short name T1151
Test name
Test status
Simulation time 88538561 ps
CPU time 1.93 seconds
Started Jul 01 10:35:07 AM PDT 24
Finished Jul 01 10:35:16 AM PDT 24
Peak memory 215400 kb
Host smart-1f91205e-12a8-4d20-9273-6b984a6cc5a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046525207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3046525207
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.832248818
Short name T1061
Test name
Test status
Simulation time 92070624 ps
CPU time 0.7 seconds
Started Jul 01 10:35:31 AM PDT 24
Finished Jul 01 10:35:33 AM PDT 24
Peak memory 204180 kb
Host smart-fd94b98a-5b67-40c3-81cd-807cb3404d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832248818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.832248818
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.156022653
Short name T1141
Test name
Test status
Simulation time 400477707 ps
CPU time 2.72 seconds
Started Jul 01 10:35:15 AM PDT 24
Finished Jul 01 10:35:23 AM PDT 24
Peak memory 215688 kb
Host smart-522154bc-ab99-4f10-95ea-c81fb88ecf7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156022653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.156022653
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2178869645
Short name T1138
Test name
Test status
Simulation time 77457124 ps
CPU time 2.64 seconds
Started Jul 01 10:35:10 AM PDT 24
Finished Jul 01 10:35:19 AM PDT 24
Peak memory 215776 kb
Host smart-5ec4701e-6627-4262-9b11-6b7992204aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178869645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2178869645
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2248814136
Short name T162
Test name
Test status
Simulation time 2637984005 ps
CPU time 7.63 seconds
Started Jul 01 10:35:21 AM PDT 24
Finished Jul 01 10:35:31 AM PDT 24
Peak memory 215648 kb
Host smart-6191b99a-63c0-4122-9b23-d44d29f78eda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248814136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2248814136
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3801273592
Short name T1106
Test name
Test status
Simulation time 201965218 ps
CPU time 14.43 seconds
Started Jul 01 10:35:10 AM PDT 24
Finished Jul 01 10:35:35 AM PDT 24
Peak memory 207244 kb
Host smart-67cd7e40-a133-49b8-831e-98df58c9f8f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801273592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3801273592
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3478298456
Short name T120
Test name
Test status
Simulation time 2444967934 ps
CPU time 32.76 seconds
Started Jul 01 10:35:08 AM PDT 24
Finished Jul 01 10:35:47 AM PDT 24
Peak memory 215468 kb
Host smart-fe0b5faa-c302-4bbd-8c67-9bbecad5c133
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478298456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3478298456
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4127817355
Short name T82
Test name
Test status
Simulation time 24352042 ps
CPU time 1.33 seconds
Started Jul 01 10:35:07 AM PDT 24
Finished Jul 01 10:35:15 AM PDT 24
Peak memory 207196 kb
Host smart-c2af17b6-5e09-45ad-800f-b67099a27354
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127817355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.4127817355
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2609276307
Short name T91
Test name
Test status
Simulation time 122382721 ps
CPU time 1.77 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 216404 kb
Host smart-38155cd0-2459-4598-b273-f2968acb8fa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609276307 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2609276307
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1401686978
Short name T1145
Test name
Test status
Simulation time 71651457 ps
CPU time 2.12 seconds
Started Jul 01 10:35:06 AM PDT 24
Finished Jul 01 10:35:15 AM PDT 24
Peak memory 215308 kb
Host smart-bb5eca1a-1c71-435a-ae71-de86ee45030d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401686978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
401686978
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3959678476
Short name T1035
Test name
Test status
Simulation time 29524312 ps
CPU time 0.73 seconds
Started Jul 01 10:35:06 AM PDT 24
Finished Jul 01 10:35:14 AM PDT 24
Peak memory 204148 kb
Host smart-6286c3c1-7da5-40bf-a464-c4673eb980de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959678476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
959678476
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.952921312
Short name T1068
Test name
Test status
Simulation time 28202233 ps
CPU time 2.04 seconds
Started Jul 01 10:35:11 AM PDT 24
Finished Jul 01 10:35:19 AM PDT 24
Peak memory 215372 kb
Host smart-58468cec-fd44-489a-aa7e-c231a68fd889
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952921312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.952921312
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3973285585
Short name T1116
Test name
Test status
Simulation time 30893751 ps
CPU time 0.64 seconds
Started Jul 01 10:35:04 AM PDT 24
Finished Jul 01 10:35:10 AM PDT 24
Peak memory 203784 kb
Host smart-38558ec2-f0b9-4c67-8807-dc05389b4fc4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973285585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3973285585
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.378665913
Short name T1096
Test name
Test status
Simulation time 102731111 ps
CPU time 2.57 seconds
Started Jul 01 10:35:03 AM PDT 24
Finished Jul 01 10:35:11 AM PDT 24
Peak memory 215444 kb
Host smart-9feddb39-d6b0-46f9-b625-231eb8daa1c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378665913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.378665913
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1339924374
Short name T101
Test name
Test status
Simulation time 84060786 ps
CPU time 2.7 seconds
Started Jul 01 10:35:39 AM PDT 24
Finished Jul 01 10:35:43 AM PDT 24
Peak memory 215792 kb
Host smart-dfbdb3af-07f8-465a-9a41-787d5f5222d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339924374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
339924374
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3327051290
Short name T1094
Test name
Test status
Simulation time 15821784 ps
CPU time 0.74 seconds
Started Jul 01 10:35:10 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 203916 kb
Host smart-812737a4-8c5f-40fd-9d2c-8a9e68d03e25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327051290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3327051290
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3939594934
Short name T1105
Test name
Test status
Simulation time 15050601 ps
CPU time 0.7 seconds
Started Jul 01 10:35:24 AM PDT 24
Finished Jul 01 10:35:26 AM PDT 24
Peak memory 203876 kb
Host smart-8bfd8ec1-c0c4-4551-83ca-ddc28059b846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939594934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3939594934
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3778293619
Short name T1036
Test name
Test status
Simulation time 33559611 ps
CPU time 0.69 seconds
Started Jul 01 10:35:17 AM PDT 24
Finished Jul 01 10:35:22 AM PDT 24
Peak memory 203884 kb
Host smart-bc7c4af5-1548-4e18-8144-9d96b8e73da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778293619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3778293619
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.43091133
Short name T1121
Test name
Test status
Simulation time 21914508 ps
CPU time 0.66 seconds
Started Jul 01 10:35:11 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 203816 kb
Host smart-c521e587-60c6-4207-9c03-4fcbaa6ec00e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43091133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.43091133
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1880657895
Short name T1064
Test name
Test status
Simulation time 14459388 ps
CPU time 0.73 seconds
Started Jul 01 10:35:38 AM PDT 24
Finished Jul 01 10:35:40 AM PDT 24
Peak memory 204228 kb
Host smart-9fe6978a-d9d9-42a8-bcee-7b2be993c15c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880657895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1880657895
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4225260573
Short name T1140
Test name
Test status
Simulation time 81059738 ps
CPU time 0.72 seconds
Started Jul 01 10:35:16 AM PDT 24
Finished Jul 01 10:35:21 AM PDT 24
Peak memory 203856 kb
Host smart-b36efffa-b605-43f8-a589-8d129cd458b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225260573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4225260573
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3630802347
Short name T1103
Test name
Test status
Simulation time 16445713 ps
CPU time 0.72 seconds
Started Jul 01 10:35:16 AM PDT 24
Finished Jul 01 10:35:22 AM PDT 24
Peak memory 203948 kb
Host smart-2b638175-9c24-4992-9638-c9c27770b28d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630802347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3630802347
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.516886398
Short name T1111
Test name
Test status
Simulation time 17427454 ps
CPU time 0.79 seconds
Started Jul 01 10:35:18 AM PDT 24
Finished Jul 01 10:35:23 AM PDT 24
Peak memory 204116 kb
Host smart-3f7b0cac-8e85-459f-9e7e-849c8c8d55d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516886398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.516886398
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1662772072
Short name T1130
Test name
Test status
Simulation time 13388900 ps
CPU time 0.76 seconds
Started Jul 01 10:35:40 AM PDT 24
Finished Jul 01 10:35:42 AM PDT 24
Peak memory 203936 kb
Host smart-76a9ffbd-a4d3-4070-ad15-b64423b0b9fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662772072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1662772072
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.185032046
Short name T1063
Test name
Test status
Simulation time 16845447 ps
CPU time 0.71 seconds
Started Jul 01 10:35:33 AM PDT 24
Finished Jul 01 10:35:40 AM PDT 24
Peak memory 204208 kb
Host smart-a6f06b8d-26a4-4a0a-9d9c-700833d6ae54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185032046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.185032046
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1967878269
Short name T1078
Test name
Test status
Simulation time 3219618377 ps
CPU time 15.02 seconds
Started Jul 01 10:35:02 AM PDT 24
Finished Jul 01 10:35:23 AM PDT 24
Peak memory 215344 kb
Host smart-3e8ef881-8c70-443e-be3b-0d9150a9b1c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967878269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1967878269
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2058452578
Short name T122
Test name
Test status
Simulation time 354229720 ps
CPU time 20.3 seconds
Started Jul 01 10:35:02 AM PDT 24
Finished Jul 01 10:35:27 AM PDT 24
Peak memory 207036 kb
Host smart-75cf0f5d-3da4-46d5-ac74-2954261a2490
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058452578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2058452578
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2799771001
Short name T83
Test name
Test status
Simulation time 71558618 ps
CPU time 1.15 seconds
Started Jul 01 10:35:04 AM PDT 24
Finished Jul 01 10:35:11 AM PDT 24
Peak memory 207220 kb
Host smart-0d5ae821-97b6-4e1e-972d-eee0fd8b8e78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799771001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2799771001
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4077889503
Short name T1092
Test name
Test status
Simulation time 58471324 ps
CPU time 1.79 seconds
Started Jul 01 10:35:37 AM PDT 24
Finished Jul 01 10:35:41 AM PDT 24
Peak memory 215504 kb
Host smart-b1c6704d-6e5c-4cc9-a427-3fd6bb951561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077889503 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4077889503
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1776283227
Short name T1137
Test name
Test status
Simulation time 50045537 ps
CPU time 1.91 seconds
Started Jul 01 10:35:08 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 215328 kb
Host smart-0038e0d1-ed3c-4216-8620-119c946f30df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776283227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
776283227
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3544843316
Short name T1124
Test name
Test status
Simulation time 17163605 ps
CPU time 0.68 seconds
Started Jul 01 10:35:13 AM PDT 24
Finished Jul 01 10:35:19 AM PDT 24
Peak memory 203880 kb
Host smart-5eb69867-fe02-498f-9b23-998464e39c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544843316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
544843316
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1658564214
Short name T121
Test name
Test status
Simulation time 132699766 ps
CPU time 1.25 seconds
Started Jul 01 10:35:04 AM PDT 24
Finished Jul 01 10:35:12 AM PDT 24
Peak memory 215456 kb
Host smart-9c7c35fc-782c-444b-93cb-5e738d216bea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658564214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1658564214
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1246345890
Short name T1058
Test name
Test status
Simulation time 22875582 ps
CPU time 0.67 seconds
Started Jul 01 10:35:14 AM PDT 24
Finished Jul 01 10:35:20 AM PDT 24
Peak memory 203776 kb
Host smart-03fa04f6-4b95-48b4-991a-8666a98805f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246345890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1246345890
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2068540194
Short name T1118
Test name
Test status
Simulation time 214995896 ps
CPU time 2.89 seconds
Started Jul 01 10:35:24 AM PDT 24
Finished Jul 01 10:35:27 AM PDT 24
Peak memory 215304 kb
Host smart-20ad5863-9f51-4c01-bfd9-da98c71b6b2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068540194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2068540194
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3387743861
Short name T99
Test name
Test status
Simulation time 64525177 ps
CPU time 1.84 seconds
Started Jul 01 10:35:04 AM PDT 24
Finished Jul 01 10:35:13 AM PDT 24
Peak memory 215704 kb
Host smart-341630cd-32e8-42eb-b5e6-22ba6f66aa1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387743861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
387743861
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2362002527
Short name T161
Test name
Test status
Simulation time 210493531 ps
CPU time 12.04 seconds
Started Jul 01 10:35:22 AM PDT 24
Finished Jul 01 10:35:36 AM PDT 24
Peak memory 215652 kb
Host smart-f3860391-38ea-4f0f-8721-28aa65211799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362002527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2362002527
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2238680518
Short name T1093
Test name
Test status
Simulation time 30143705 ps
CPU time 0.79 seconds
Started Jul 01 10:35:25 AM PDT 24
Finished Jul 01 10:35:26 AM PDT 24
Peak memory 203868 kb
Host smart-52039fe8-10d5-4e00-b849-9c7729f1c69c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238680518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2238680518
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1706173624
Short name T1065
Test name
Test status
Simulation time 12152550 ps
CPU time 0.75 seconds
Started Jul 01 10:35:41 AM PDT 24
Finished Jul 01 10:35:43 AM PDT 24
Peak memory 204220 kb
Host smart-b139f324-8faf-459c-9d9f-6420b62bc0fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706173624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1706173624
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3434466537
Short name T1113
Test name
Test status
Simulation time 45666625 ps
CPU time 0.8 seconds
Started Jul 01 10:35:46 AM PDT 24
Finished Jul 01 10:35:50 AM PDT 24
Peak memory 204216 kb
Host smart-de47927a-f160-4fe1-afca-2804b1206aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434466537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3434466537
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4179142455
Short name T1049
Test name
Test status
Simulation time 15989321 ps
CPU time 0.71 seconds
Started Jul 01 10:35:23 AM PDT 24
Finished Jul 01 10:35:25 AM PDT 24
Peak memory 203796 kb
Host smart-40d35409-3887-4352-b7cf-642a1043322b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179142455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4179142455
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.637639863
Short name T1066
Test name
Test status
Simulation time 14748037 ps
CPU time 0.69 seconds
Started Jul 01 10:35:18 AM PDT 24
Finished Jul 01 10:35:23 AM PDT 24
Peak memory 203852 kb
Host smart-58f9e2a9-fa4a-47de-b0e8-03a61d5ed980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637639863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.637639863
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1147467603
Short name T1122
Test name
Test status
Simulation time 31434596 ps
CPU time 0.73 seconds
Started Jul 01 10:35:19 AM PDT 24
Finished Jul 01 10:35:23 AM PDT 24
Peak memory 203952 kb
Host smart-2e4ab864-34de-46fc-81d7-55cd9a952b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147467603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1147467603
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1160707867
Short name T1045
Test name
Test status
Simulation time 16325655 ps
CPU time 0.82 seconds
Started Jul 01 10:35:30 AM PDT 24
Finished Jul 01 10:35:32 AM PDT 24
Peak memory 204148 kb
Host smart-6bafbd90-9181-4230-b420-53bcd3ca121c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160707867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1160707867
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3620477412
Short name T1044
Test name
Test status
Simulation time 28027976 ps
CPU time 0.7 seconds
Started Jul 01 10:35:58 AM PDT 24
Finished Jul 01 10:36:02 AM PDT 24
Peak memory 203904 kb
Host smart-a439cb44-bcce-4225-8415-b4a741f7308c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620477412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3620477412
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.967987036
Short name T1042
Test name
Test status
Simulation time 14023302 ps
CPU time 0.77 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:16 AM PDT 24
Peak memory 204228 kb
Host smart-08910aa6-352f-41a8-a8b3-48c6fc2d46e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967987036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.967987036
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1942072177
Short name T1047
Test name
Test status
Simulation time 16969507 ps
CPU time 0.72 seconds
Started Jul 01 10:35:14 AM PDT 24
Finished Jul 01 10:35:20 AM PDT 24
Peak memory 203912 kb
Host smart-7ba49e53-f235-43f9-a3c0-db6bdb377201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942072177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1942072177
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.652306916
Short name T115
Test name
Test status
Simulation time 777459790 ps
CPU time 16.3 seconds
Started Jul 01 10:34:59 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 207204 kb
Host smart-a033924b-38bc-45c7-bb2c-d4ae55aa27b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652306916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.652306916
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3581929353
Short name T1098
Test name
Test status
Simulation time 1701088836 ps
CPU time 12.53 seconds
Started Jul 01 10:35:17 AM PDT 24
Finished Jul 01 10:35:34 AM PDT 24
Peak memory 207216 kb
Host smart-26aaf9c9-9217-4614-a0dd-3a54448d2500
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581929353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3581929353
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1646619287
Short name T85
Test name
Test status
Simulation time 15456538 ps
CPU time 0.91 seconds
Started Jul 01 10:35:05 AM PDT 24
Finished Jul 01 10:35:14 AM PDT 24
Peak memory 206976 kb
Host smart-f2297363-64ed-4a2b-a876-801b33744f68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646619287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1646619287
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3586304713
Short name T110
Test name
Test status
Simulation time 133930931 ps
CPU time 2.53 seconds
Started Jul 01 10:35:04 AM PDT 24
Finished Jul 01 10:35:13 AM PDT 24
Peak memory 216464 kb
Host smart-c19a5d07-355f-48cd-8dc5-067c319e2275
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586304713 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3586304713
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3571585621
Short name T1037
Test name
Test status
Simulation time 102974972 ps
CPU time 1.82 seconds
Started Jul 01 10:35:06 AM PDT 24
Finished Jul 01 10:35:15 AM PDT 24
Peak memory 215412 kb
Host smart-53e101ad-3a44-4b58-91b6-f691cbce2489
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571585621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
571585621
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1277167180
Short name T1034
Test name
Test status
Simulation time 13474136 ps
CPU time 0.73 seconds
Started Jul 01 10:35:31 AM PDT 24
Finished Jul 01 10:35:33 AM PDT 24
Peak memory 204172 kb
Host smart-9a8dacf3-215a-486d-951f-3ec4ce3143c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277167180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
277167180
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3681508480
Short name T116
Test name
Test status
Simulation time 98646601 ps
CPU time 1.62 seconds
Started Jul 01 10:35:14 AM PDT 24
Finished Jul 01 10:35:21 AM PDT 24
Peak memory 215388 kb
Host smart-55f751e1-0048-46ca-9b3a-b8e7dc16a3d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681508480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3681508480
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.928587350
Short name T1133
Test name
Test status
Simulation time 39398956 ps
CPU time 0.71 seconds
Started Jul 01 10:35:37 AM PDT 24
Finished Jul 01 10:35:39 AM PDT 24
Peak memory 203804 kb
Host smart-658e134b-b6dd-4b83-9254-93de18695ae0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928587350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.928587350
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.990323865
Short name T1054
Test name
Test status
Simulation time 768406218 ps
CPU time 3.58 seconds
Started Jul 01 10:35:34 AM PDT 24
Finished Jul 01 10:35:40 AM PDT 24
Peak memory 215380 kb
Host smart-3db7104c-d971-4882-8bd6-639d86856b08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990323865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.990323865
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2332725453
Short name T94
Test name
Test status
Simulation time 85100516 ps
CPU time 1.58 seconds
Started Jul 01 10:35:11 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 216604 kb
Host smart-0cce3342-593c-4e54-aa11-c82a25f3ac4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332725453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
332725453
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2491468205
Short name T97
Test name
Test status
Simulation time 663954983 ps
CPU time 12.34 seconds
Started Jul 01 10:35:33 AM PDT 24
Finished Jul 01 10:35:46 AM PDT 24
Peak memory 216036 kb
Host smart-4f0e73d7-76a9-4496-be18-1771fac132c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491468205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2491468205
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4273930000
Short name T1083
Test name
Test status
Simulation time 51618555 ps
CPU time 0.7 seconds
Started Jul 01 10:35:18 AM PDT 24
Finished Jul 01 10:35:23 AM PDT 24
Peak memory 203828 kb
Host smart-458de3a0-862f-435a-8108-7f044429f6b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273930000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4273930000
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1068266660
Short name T1120
Test name
Test status
Simulation time 12147283 ps
CPU time 0.71 seconds
Started Jul 01 10:35:16 AM PDT 24
Finished Jul 01 10:35:22 AM PDT 24
Peak memory 203344 kb
Host smart-f6da661e-a2ab-4409-b5f0-57d1fd5546f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068266660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1068266660
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3231245307
Short name T1089
Test name
Test status
Simulation time 30940943 ps
CPU time 0.73 seconds
Started Jul 01 10:35:16 AM PDT 24
Finished Jul 01 10:35:22 AM PDT 24
Peak memory 203396 kb
Host smart-89c1eaf2-6e35-4222-9628-2d97622e624d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231245307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3231245307
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2384936975
Short name T1115
Test name
Test status
Simulation time 14664455 ps
CPU time 0.73 seconds
Started Jul 01 10:35:59 AM PDT 24
Finished Jul 01 10:36:03 AM PDT 24
Peak memory 204212 kb
Host smart-88d56185-a0f4-47e6-b556-93ac47e82607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384936975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2384936975
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.546530909
Short name T1073
Test name
Test status
Simulation time 13433371 ps
CPU time 0.69 seconds
Started Jul 01 10:35:10 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 204216 kb
Host smart-0afbaa04-9d8e-461c-9c83-507864c5870f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546530909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.546530909
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1738204310
Short name T1040
Test name
Test status
Simulation time 24041178 ps
CPU time 0.68 seconds
Started Jul 01 10:35:04 AM PDT 24
Finished Jul 01 10:35:16 AM PDT 24
Peak memory 203844 kb
Host smart-162741a6-5c25-4cd8-ba52-47abf893a0a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738204310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1738204310
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3407198441
Short name T1033
Test name
Test status
Simulation time 11098797 ps
CPU time 0.68 seconds
Started Jul 01 10:35:22 AM PDT 24
Finished Jul 01 10:35:24 AM PDT 24
Peak memory 203856 kb
Host smart-58c826f2-308c-429d-a4e0-e2eada78314c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407198441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3407198441
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2652739640
Short name T1030
Test name
Test status
Simulation time 16448237 ps
CPU time 0.75 seconds
Started Jul 01 10:35:25 AM PDT 24
Finished Jul 01 10:35:26 AM PDT 24
Peak memory 203900 kb
Host smart-410470d9-8104-4af8-a5e0-f0941c6700d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652739640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2652739640
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3576018229
Short name T1101
Test name
Test status
Simulation time 25213117 ps
CPU time 0.68 seconds
Started Jul 01 10:35:11 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 203884 kb
Host smart-02aa161c-9b14-4822-9d60-cd93c602044b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576018229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3576018229
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1329590924
Short name T1104
Test name
Test status
Simulation time 38332304 ps
CPU time 0.73 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 203832 kb
Host smart-401df822-b61f-4119-91fd-1ff50a25ddaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329590924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1329590924
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3223865948
Short name T1081
Test name
Test status
Simulation time 838879885 ps
CPU time 3.59 seconds
Started Jul 01 10:35:15 AM PDT 24
Finished Jul 01 10:35:24 AM PDT 24
Peak memory 217236 kb
Host smart-8c1daa21-30df-4413-a446-dbba110413fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223865948 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3223865948
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1028579756
Short name T1091
Test name
Test status
Simulation time 21633057 ps
CPU time 1.35 seconds
Started Jul 01 10:35:25 AM PDT 24
Finished Jul 01 10:35:27 AM PDT 24
Peak memory 207128 kb
Host smart-ff604520-ac50-4915-bb27-e3c91f1dbce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028579756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
028579756
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.522334371
Short name T1142
Test name
Test status
Simulation time 30527567 ps
CPU time 0.71 seconds
Started Jul 01 10:35:05 AM PDT 24
Finished Jul 01 10:35:13 AM PDT 24
Peak memory 203800 kb
Host smart-edf346f4-9921-473a-9091-3702400c03cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522334371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.522334371
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2178121586
Short name T1039
Test name
Test status
Simulation time 59630598 ps
CPU time 3.68 seconds
Started Jul 01 10:35:06 AM PDT 24
Finished Jul 01 10:35:16 AM PDT 24
Peak memory 215300 kb
Host smart-9bbfcc7c-dd46-41d9-8fa5-936e0ec2161a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178121586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2178121586
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1662357318
Short name T1114
Test name
Test status
Simulation time 122557608 ps
CPU time 3.35 seconds
Started Jul 01 10:35:35 AM PDT 24
Finished Jul 01 10:35:40 AM PDT 24
Peak memory 215620 kb
Host smart-d81ac0b3-8562-475e-8d04-e8797ccc46a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662357318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
662357318
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3463053100
Short name T149
Test name
Test status
Simulation time 4324349509 ps
CPU time 7.71 seconds
Started Jul 01 10:35:05 AM PDT 24
Finished Jul 01 10:35:19 AM PDT 24
Peak memory 215444 kb
Host smart-0982dddc-814f-4fc5-9d9a-2676c74c5627
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463053100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3463053100
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3114745277
Short name T1082
Test name
Test status
Simulation time 37649530 ps
CPU time 2.39 seconds
Started Jul 01 10:35:12 AM PDT 24
Finished Jul 01 10:35:20 AM PDT 24
Peak memory 216656 kb
Host smart-cc857586-59de-4490-8d9b-6583e447cb10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114745277 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3114745277
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.767184323
Short name T1060
Test name
Test status
Simulation time 37861151 ps
CPU time 1.33 seconds
Started Jul 01 10:35:05 AM PDT 24
Finished Jul 01 10:35:17 AM PDT 24
Peak memory 207148 kb
Host smart-c7b6049d-6144-4d52-8f32-31b015205678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767184323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.767184323
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3210646876
Short name T1057
Test name
Test status
Simulation time 14894914 ps
CPU time 0.77 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:16 AM PDT 24
Peak memory 204228 kb
Host smart-e25b3651-24a4-4de7-9325-ffec067423b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210646876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
210646876
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2403679939
Short name T1085
Test name
Test status
Simulation time 162672239 ps
CPU time 4.24 seconds
Started Jul 01 10:34:58 AM PDT 24
Finished Jul 01 10:35:05 AM PDT 24
Peak memory 215368 kb
Host smart-8e46d4d5-600d-42e3-b8d0-b9c7da9aebea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403679939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2403679939
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2121731006
Short name T100
Test name
Test status
Simulation time 258532235 ps
CPU time 5.26 seconds
Started Jul 01 10:35:13 AM PDT 24
Finished Jul 01 10:35:24 AM PDT 24
Peak memory 215660 kb
Host smart-94d0634b-5fa8-486c-a196-299d3dab486d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121731006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
121731006
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1017453194
Short name T1097
Test name
Test status
Simulation time 1036949127 ps
CPU time 14.05 seconds
Started Jul 01 10:35:21 AM PDT 24
Finished Jul 01 10:35:37 AM PDT 24
Peak memory 216120 kb
Host smart-a24a20a2-3c18-490c-9ed3-2d9133f8d018
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017453194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1017453194
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3138939333
Short name T108
Test name
Test status
Simulation time 153573787 ps
CPU time 2.94 seconds
Started Jul 01 10:35:30 AM PDT 24
Finished Jul 01 10:35:34 AM PDT 24
Peak memory 217076 kb
Host smart-565bbf30-118d-4aa9-9ef1-1b829da51a3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138939333 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3138939333
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2048900695
Short name T1144
Test name
Test status
Simulation time 40810654 ps
CPU time 1.28 seconds
Started Jul 01 10:35:17 AM PDT 24
Finished Jul 01 10:35:23 AM PDT 24
Peak memory 207176 kb
Host smart-a710fb54-100d-4232-a904-1529e68b4c9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048900695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
048900695
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3248052321
Short name T1029
Test name
Test status
Simulation time 12482984 ps
CPU time 0.68 seconds
Started Jul 01 10:35:02 AM PDT 24
Finished Jul 01 10:35:07 AM PDT 24
Peak memory 203848 kb
Host smart-d4d3b7fd-651f-48d6-9ba7-ef74a8c1aa82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248052321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
248052321
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2610121406
Short name T1043
Test name
Test status
Simulation time 420727891 ps
CPU time 2.84 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 215388 kb
Host smart-579ae8d0-18aa-4398-87be-7d8a4fb4a828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610121406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2610121406
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2636112545
Short name T105
Test name
Test status
Simulation time 2005067913 ps
CPU time 4.61 seconds
Started Jul 01 10:35:43 AM PDT 24
Finished Jul 01 10:35:48 AM PDT 24
Peak memory 216688 kb
Host smart-02e96200-80a4-4a0f-b9f3-e9aa8c17dea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636112545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
636112545
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4018538632
Short name T1148
Test name
Test status
Simulation time 542675241 ps
CPU time 6.18 seconds
Started Jul 01 10:35:08 AM PDT 24
Finished Jul 01 10:35:21 AM PDT 24
Peak memory 215452 kb
Host smart-6a56ed01-7737-4a42-8e9d-c605a10ef109
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018538632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4018538632
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1620790372
Short name T1056
Test name
Test status
Simulation time 46209086 ps
CPU time 1.73 seconds
Started Jul 01 10:35:30 AM PDT 24
Finished Jul 01 10:35:33 AM PDT 24
Peak memory 216464 kb
Host smart-66f7f8a9-39e4-4984-a9de-0f2cd6e3d499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620790372 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1620790372
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.944858161
Short name T1080
Test name
Test status
Simulation time 48350886 ps
CPU time 1.37 seconds
Started Jul 01 10:35:33 AM PDT 24
Finished Jul 01 10:35:40 AM PDT 24
Peak memory 207132 kb
Host smart-9619f85e-f15d-4a66-a81c-1e2d707bfebe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944858161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.944858161
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3133598328
Short name T1071
Test name
Test status
Simulation time 18157657 ps
CPU time 0.78 seconds
Started Jul 01 10:35:16 AM PDT 24
Finished Jul 01 10:35:22 AM PDT 24
Peak memory 203852 kb
Host smart-810b8b58-8769-43eb-a57a-795617ae7726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133598328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
133598328
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3710759522
Short name T1117
Test name
Test status
Simulation time 721263387 ps
CPU time 2.66 seconds
Started Jul 01 10:35:09 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 215404 kb
Host smart-2bed1360-1b35-45bb-903a-5bd6a4555ed2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710759522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3710759522
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3188475029
Short name T1076
Test name
Test status
Simulation time 108037384 ps
CPU time 6.76 seconds
Started Jul 01 10:35:02 AM PDT 24
Finished Jul 01 10:35:14 AM PDT 24
Peak memory 215432 kb
Host smart-92d2d152-97d2-4a47-b1aa-39540b193c55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188475029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3188475029
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1554291492
Short name T1087
Test name
Test status
Simulation time 79696427 ps
CPU time 1.61 seconds
Started Jul 01 10:35:03 AM PDT 24
Finished Jul 01 10:35:10 AM PDT 24
Peak memory 215436 kb
Host smart-2563e984-c57b-47e8-a991-5a9bf33aceb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554291492 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1554291492
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.247217499
Short name T1119
Test name
Test status
Simulation time 68807845 ps
CPU time 1.83 seconds
Started Jul 01 10:35:12 AM PDT 24
Finished Jul 01 10:35:20 AM PDT 24
Peak memory 215368 kb
Host smart-f02eb425-58f5-476d-bfce-9cacc9925ce4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247217499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.247217499
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.563724142
Short name T1048
Test name
Test status
Simulation time 20986668 ps
CPU time 0.68 seconds
Started Jul 01 10:35:13 AM PDT 24
Finished Jul 01 10:35:19 AM PDT 24
Peak memory 203804 kb
Host smart-baaa756f-ecb2-4502-a999-0068e8e18409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563724142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.563724142
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2182527181
Short name T139
Test name
Test status
Simulation time 217556430 ps
CPU time 3.03 seconds
Started Jul 01 10:35:46 AM PDT 24
Finished Jul 01 10:35:51 AM PDT 24
Peak memory 215444 kb
Host smart-92c03758-8b01-4bcd-8fc7-9e0d8d2168ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182527181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2182527181
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3406856220
Short name T1147
Test name
Test status
Simulation time 233953523 ps
CPU time 3.45 seconds
Started Jul 01 10:35:08 AM PDT 24
Finished Jul 01 10:35:18 AM PDT 24
Peak memory 215668 kb
Host smart-cdab8aa4-9e1e-4c0a-8c06-847c9edd3aec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406856220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
406856220
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3119533013
Short name T155
Test name
Test status
Simulation time 987360468 ps
CPU time 21 seconds
Started Jul 01 10:35:34 AM PDT 24
Finished Jul 01 10:35:55 AM PDT 24
Peak memory 215464 kb
Host smart-53723b8f-6aa0-4bee-b1e1-dccbe3ac6167
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119533013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3119533013
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.353623603
Short name T623
Test name
Test status
Simulation time 24699237 ps
CPU time 0.7 seconds
Started Jul 01 11:48:17 AM PDT 24
Finished Jul 01 11:48:18 AM PDT 24
Peak memory 206380 kb
Host smart-93e16cb6-fa1e-40ec-940f-1919d5f40e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353623603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.353623603
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2729327892
Short name T960
Test name
Test status
Simulation time 706932431 ps
CPU time 8.89 seconds
Started Jul 01 11:48:12 AM PDT 24
Finished Jul 01 11:48:21 AM PDT 24
Peak memory 225544 kb
Host smart-09a912cf-fedd-4b16-95b5-3c1a08c59b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729327892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2729327892
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3590840183
Short name T787
Test name
Test status
Simulation time 18385675 ps
CPU time 0.78 seconds
Started Jul 01 11:48:03 AM PDT 24
Finished Jul 01 11:48:05 AM PDT 24
Peak memory 206512 kb
Host smart-8ece7ed4-d866-4e09-94da-8ee261b01d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590840183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3590840183
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3544589757
Short name T551
Test name
Test status
Simulation time 134759202156 ps
CPU time 186.37 seconds
Started Jul 01 11:48:12 AM PDT 24
Finished Jul 01 11:51:19 AM PDT 24
Peak memory 256384 kb
Host smart-39e50070-ffbd-410e-9e29-ac366b91e801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544589757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3544589757
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1323392526
Short name T138
Test name
Test status
Simulation time 4604541115 ps
CPU time 67.77 seconds
Started Jul 01 11:48:13 AM PDT 24
Finished Jul 01 11:49:21 AM PDT 24
Peak memory 254300 kb
Host smart-f9cca782-9ec8-40f9-98a3-1073d2b72e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323392526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1323392526
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.164469748
Short name T143
Test name
Test status
Simulation time 198672552 ps
CPU time 7.74 seconds
Started Jul 01 11:48:13 AM PDT 24
Finished Jul 01 11:48:22 AM PDT 24
Peak memory 241900 kb
Host smart-1aea258b-39fb-4fd1-9e08-238a36001e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164469748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.164469748
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1800209238
Short name T88
Test name
Test status
Simulation time 7808062248 ps
CPU time 108.68 seconds
Started Jul 01 11:48:10 AM PDT 24
Finished Jul 01 11:49:59 AM PDT 24
Peak memory 254588 kb
Host smart-490e68b1-c8ad-4bdf-b6f0-36d7053cd791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800209238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1800209238
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.607069446
Short name T941
Test name
Test status
Simulation time 2240914212 ps
CPU time 7.01 seconds
Started Jul 01 11:48:09 AM PDT 24
Finished Jul 01 11:48:16 AM PDT 24
Peak memory 225608 kb
Host smart-2373f11a-ef6a-4b1a-aeba-657272a24bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607069446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.607069446
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3124671131
Short name T315
Test name
Test status
Simulation time 3434476997 ps
CPU time 22.72 seconds
Started Jul 01 11:48:06 AM PDT 24
Finished Jul 01 11:48:30 AM PDT 24
Peak memory 225720 kb
Host smart-9706964e-49a3-447d-83cf-e002a7bf2806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124671131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3124671131
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1213174241
Short name T801
Test name
Test status
Simulation time 25838428 ps
CPU time 1.08 seconds
Started Jul 01 11:48:01 AM PDT 24
Finished Jul 01 11:48:03 AM PDT 24
Peak memory 217648 kb
Host smart-1ce35fff-2b00-4807-8caf-7425cadf8365
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213174241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1213174241
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4227098016
Short name T557
Test name
Test status
Simulation time 1388667619 ps
CPU time 5.87 seconds
Started Jul 01 11:48:06 AM PDT 24
Finished Jul 01 11:48:13 AM PDT 24
Peak memory 233696 kb
Host smart-fb8090e1-c31d-4ab7-b2d5-2c1dda0047dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227098016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4227098016
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2513831210
Short name T630
Test name
Test status
Simulation time 1086887629 ps
CPU time 7.88 seconds
Started Jul 01 11:48:13 AM PDT 24
Finished Jul 01 11:48:21 AM PDT 24
Peak memory 225516 kb
Host smart-072bd5ce-8e00-46b2-86fd-04dde3695812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513831210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2513831210
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.158411306
Short name T839
Test name
Test status
Simulation time 1061726366 ps
CPU time 6.49 seconds
Started Jul 01 11:48:11 AM PDT 24
Finished Jul 01 11:48:18 AM PDT 24
Peak memory 221452 kb
Host smart-7a13dbf2-0487-4303-865a-ab7ab9e0c87a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=158411306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.158411306
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.306494439
Short name T164
Test name
Test status
Simulation time 114091805535 ps
CPU time 272.3 seconds
Started Jul 01 11:48:17 AM PDT 24
Finished Jul 01 11:52:50 AM PDT 24
Peak memory 250388 kb
Host smart-bb2086bd-ef7c-4836-a515-ae42c259e8e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306494439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.306494439
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.131849032
Short name T778
Test name
Test status
Simulation time 32806355602 ps
CPU time 27.34 seconds
Started Jul 01 11:48:01 AM PDT 24
Finished Jul 01 11:48:29 AM PDT 24
Peak memory 217400 kb
Host smart-900d76e1-ac38-4da7-bab6-a233113bdefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131849032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.131849032
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.889472418
Short name T71
Test name
Test status
Simulation time 18539631 ps
CPU time 0.8 seconds
Started Jul 01 11:48:01 AM PDT 24
Finished Jul 01 11:48:03 AM PDT 24
Peak memory 206644 kb
Host smart-9ca8ee2b-dad0-494c-bd1e-e0da86d75200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889472418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.889472418
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2315564974
Short name T556
Test name
Test status
Simulation time 152683785 ps
CPU time 2.62 seconds
Started Jul 01 11:48:02 AM PDT 24
Finished Jul 01 11:48:06 AM PDT 24
Peak memory 217420 kb
Host smart-b33dee06-8fd8-437f-aaa5-c4ee31d1e310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315564974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2315564974
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.349265432
Short name T873
Test name
Test status
Simulation time 12759249 ps
CPU time 0.82 seconds
Started Jul 01 11:48:02 AM PDT 24
Finished Jul 01 11:48:03 AM PDT 24
Peak memory 207064 kb
Host smart-2c2aca84-b49f-4a8c-8143-ff489e9c313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349265432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.349265432
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3070583315
Short name T727
Test name
Test status
Simulation time 423202776 ps
CPU time 6.22 seconds
Started Jul 01 11:48:06 AM PDT 24
Finished Jul 01 11:48:13 AM PDT 24
Peak memory 233736 kb
Host smart-ac93f4d3-8beb-46fe-a911-6b255e340186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070583315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3070583315
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.340409344
Short name T531
Test name
Test status
Simulation time 13024012 ps
CPU time 0.71 seconds
Started Jul 01 11:48:32 AM PDT 24
Finished Jul 01 11:48:34 AM PDT 24
Peak memory 205832 kb
Host smart-150cd9e6-cbec-405e-a1e9-d8d37f510cc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340409344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.340409344
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3920692198
Short name T664
Test name
Test status
Simulation time 149418844 ps
CPU time 2.67 seconds
Started Jul 01 11:48:26 AM PDT 24
Finished Jul 01 11:48:30 AM PDT 24
Peak memory 233840 kb
Host smart-2acc445b-2d2c-4ac1-b7e3-3dce31ea8846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920692198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3920692198
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1082121885
Short name T353
Test name
Test status
Simulation time 15414220 ps
CPU time 0.74 seconds
Started Jul 01 11:48:16 AM PDT 24
Finished Jul 01 11:48:18 AM PDT 24
Peak memory 206504 kb
Host smart-6d8210b4-ad73-4f47-897c-e4d112b7eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082121885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1082121885
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4094540011
Short name T226
Test name
Test status
Simulation time 1046423384 ps
CPU time 15.27 seconds
Started Jul 01 11:48:26 AM PDT 24
Finished Jul 01 11:48:43 AM PDT 24
Peak memory 236728 kb
Host smart-aa49f7ac-7db5-4b4b-a4d8-329da4602ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094540011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4094540011
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1021194268
Short name T705
Test name
Test status
Simulation time 4531250594 ps
CPU time 65.59 seconds
Started Jul 01 11:48:32 AM PDT 24
Finished Jul 01 11:49:39 AM PDT 24
Peak memory 251660 kb
Host smart-3f3255ab-aebd-47ce-82e2-173715761a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021194268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1021194268
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.325085266
Short name T923
Test name
Test status
Simulation time 12350422525 ps
CPU time 99.4 seconds
Started Jul 01 11:48:31 AM PDT 24
Finished Jul 01 11:50:12 AM PDT 24
Peak memory 271688 kb
Host smart-b3906f18-60af-4621-8e27-edd3df92eba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325085266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
325085266
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1687386934
Short name T279
Test name
Test status
Simulation time 4934768731 ps
CPU time 84.96 seconds
Started Jul 01 11:48:26 AM PDT 24
Finished Jul 01 11:49:52 AM PDT 24
Peak memory 241560 kb
Host smart-4c81f48e-51c5-44b7-9e5f-0a6082da5227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687386934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1687386934
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.513502531
Short name T166
Test name
Test status
Simulation time 19269772418 ps
CPU time 62.58 seconds
Started Jul 01 11:48:27 AM PDT 24
Finished Jul 01 11:49:31 AM PDT 24
Peak memory 252432 kb
Host smart-932c278a-6270-4f58-a61f-df742526f09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513502531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
513502531
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.594985882
Short name T346
Test name
Test status
Simulation time 64511093 ps
CPU time 2.24 seconds
Started Jul 01 11:48:25 AM PDT 24
Finished Jul 01 11:48:29 AM PDT 24
Peak memory 233484 kb
Host smart-ceb189d9-beab-4e73-9513-17c29325a92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594985882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.594985882
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.72747073
Short name T179
Test name
Test status
Simulation time 54249208531 ps
CPU time 60.28 seconds
Started Jul 01 11:48:28 AM PDT 24
Finished Jul 01 11:49:29 AM PDT 24
Peak memory 241628 kb
Host smart-d53b0ca0-1d44-43da-8b27-c0150e2e0272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72747073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.72747073
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3295803287
Short name T729
Test name
Test status
Simulation time 50851933 ps
CPU time 1.03 seconds
Started Jul 01 11:48:21 AM PDT 24
Finished Jul 01 11:48:25 AM PDT 24
Peak memory 218884 kb
Host smart-1549a10c-3925-4194-bfec-e059f1df90b1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295803287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3295803287
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4211482135
Short name T824
Test name
Test status
Simulation time 64109944 ps
CPU time 2.64 seconds
Started Jul 01 11:48:26 AM PDT 24
Finished Jul 01 11:48:30 AM PDT 24
Peak memory 233440 kb
Host smart-7f146100-0b92-4bfa-910e-a2b53da1f8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211482135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4211482135
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3228920898
Short name T567
Test name
Test status
Simulation time 12533517757 ps
CPU time 27.25 seconds
Started Jul 01 11:48:22 AM PDT 24
Finished Jul 01 11:48:52 AM PDT 24
Peak memory 233928 kb
Host smart-ba0d0a29-5893-45b4-af90-d107f797439b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228920898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3228920898
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3013275599
Short name T782
Test name
Test status
Simulation time 351889638 ps
CPU time 5.42 seconds
Started Jul 01 11:48:26 AM PDT 24
Finished Jul 01 11:48:33 AM PDT 24
Peak memory 222036 kb
Host smart-b9001b3e-03be-4965-90a0-3d1971da76a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3013275599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3013275599
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2448714071
Short name T66
Test name
Test status
Simulation time 36670762 ps
CPU time 0.96 seconds
Started Jul 01 11:48:31 AM PDT 24
Finished Jul 01 11:48:33 AM PDT 24
Peak memory 236272 kb
Host smart-c4add31b-ed43-402f-9c94-8aee4dea7689
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448714071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2448714071
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3153898536
Short name T5
Test name
Test status
Simulation time 7947825930 ps
CPU time 26.25 seconds
Started Jul 01 11:48:22 AM PDT 24
Finished Jul 01 11:48:51 AM PDT 24
Peak memory 217540 kb
Host smart-5099dc2a-3a19-4bdc-aeb3-bc90b9dc8d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153898536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3153898536
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3559025170
Short name T375
Test name
Test status
Simulation time 2442981257 ps
CPU time 1.97 seconds
Started Jul 01 11:48:21 AM PDT 24
Finished Jul 01 11:48:26 AM PDT 24
Peak memory 209000 kb
Host smart-53adaf07-301d-42d8-ac3e-6fe5c1aca707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559025170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3559025170
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3932843751
Short name T969
Test name
Test status
Simulation time 332646263 ps
CPU time 5.21 seconds
Started Jul 01 11:48:22 AM PDT 24
Finished Jul 01 11:48:30 AM PDT 24
Peak memory 217360 kb
Host smart-2aea5e66-1040-4a32-9860-235a177aa2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932843751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3932843751
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1761787791
Short name T505
Test name
Test status
Simulation time 901244764 ps
CPU time 0.87 seconds
Started Jul 01 11:48:20 AM PDT 24
Finished Jul 01 11:48:25 AM PDT 24
Peak memory 206984 kb
Host smart-11c2e0ce-4635-499f-afb7-18803d447743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761787791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1761787791
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2752523529
Short name T1013
Test name
Test status
Simulation time 604371647 ps
CPU time 2.49 seconds
Started Jul 01 11:48:27 AM PDT 24
Finished Jul 01 11:48:31 AM PDT 24
Peak memory 225544 kb
Host smart-5f2eb2f2-f9ff-4300-8d1d-4e2f2b5b0a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752523529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2752523529
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2826453349
Short name T667
Test name
Test status
Simulation time 14842532 ps
CPU time 0.76 seconds
Started Jul 01 11:50:07 AM PDT 24
Finished Jul 01 11:50:08 AM PDT 24
Peak memory 206328 kb
Host smart-8786ca8f-f777-4628-87c3-e9bdcad312af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826453349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2826453349
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3758884613
Short name T718
Test name
Test status
Simulation time 2161183403 ps
CPU time 12.38 seconds
Started Jul 01 11:50:00 AM PDT 24
Finished Jul 01 11:50:13 AM PDT 24
Peak memory 233796 kb
Host smart-e62234db-8624-47b8-b836-af2999c2c90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758884613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3758884613
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1164570709
Short name T980
Test name
Test status
Simulation time 132782457 ps
CPU time 0.77 seconds
Started Jul 01 11:49:55 AM PDT 24
Finished Jul 01 11:49:56 AM PDT 24
Peak memory 207872 kb
Host smart-dd6c333d-904f-4f66-aaa4-1a2f040dae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164570709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1164570709
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1940419048
Short name T78
Test name
Test status
Simulation time 31276558138 ps
CPU time 234.02 seconds
Started Jul 01 11:50:06 AM PDT 24
Finished Jul 01 11:54:01 AM PDT 24
Peak memory 265384 kb
Host smart-9bd17d86-2950-4621-ac20-a5cb4b79b372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940419048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1940419048
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3017216546
Short name T947
Test name
Test status
Simulation time 8581731333 ps
CPU time 37.53 seconds
Started Jul 01 11:50:06 AM PDT 24
Finished Jul 01 11:50:45 AM PDT 24
Peak memory 242176 kb
Host smart-49e6cd91-6865-4828-a88b-ddb39411d7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017216546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3017216546
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3005940835
Short name T34
Test name
Test status
Simulation time 8544261801 ps
CPU time 26.84 seconds
Started Jul 01 11:50:00 AM PDT 24
Finished Jul 01 11:50:28 AM PDT 24
Peak memory 238376 kb
Host smart-b56e23a2-6228-4a2b-a16d-a2a210101ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005940835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3005940835
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.257411725
Short name T865
Test name
Test status
Simulation time 205343142576 ps
CPU time 374.08 seconds
Started Jul 01 11:50:05 AM PDT 24
Finished Jul 01 11:56:19 AM PDT 24
Peak memory 250280 kb
Host smart-64a0cd8f-ed8a-4a2d-9f94-35f07ad8395e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257411725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.257411725
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.217684740
Short name T388
Test name
Test status
Simulation time 1288208634 ps
CPU time 12.93 seconds
Started Jul 01 11:50:00 AM PDT 24
Finished Jul 01 11:50:14 AM PDT 24
Peak memory 233780 kb
Host smart-fa7d8dfb-f26f-467c-b055-328319f84269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217684740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.217684740
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3706532010
Short name T495
Test name
Test status
Simulation time 690950689 ps
CPU time 4.26 seconds
Started Jul 01 11:50:02 AM PDT 24
Finished Jul 01 11:50:06 AM PDT 24
Peak memory 225548 kb
Host smart-d70c8106-ab42-4187-a5b0-9328519406e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706532010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3706532010
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1235862194
Short name T842
Test name
Test status
Simulation time 15564554 ps
CPU time 1.06 seconds
Started Jul 01 11:49:56 AM PDT 24
Finished Jul 01 11:49:58 AM PDT 24
Peak memory 218976 kb
Host smart-79c64c7e-08fe-4f5a-b156-8412d876adbd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235862194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1235862194
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.802204794
Short name T895
Test name
Test status
Simulation time 7374277485 ps
CPU time 22.77 seconds
Started Jul 01 11:50:00 AM PDT 24
Finished Jul 01 11:50:23 AM PDT 24
Peak memory 237244 kb
Host smart-7ec0ac3d-7194-4a2b-ac64-7f2844de1068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802204794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.802204794
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4257908386
Short name T89
Test name
Test status
Simulation time 8225211256 ps
CPU time 11.8 seconds
Started Jul 01 11:50:02 AM PDT 24
Finished Jul 01 11:50:14 AM PDT 24
Peak memory 233868 kb
Host smart-e9409daa-b03a-426f-8353-f968c7befdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257908386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4257908386
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1953015205
Short name T984
Test name
Test status
Simulation time 117268612 ps
CPU time 4.11 seconds
Started Jul 01 11:50:06 AM PDT 24
Finished Jul 01 11:50:11 AM PDT 24
Peak memory 224192 kb
Host smart-2c0a8362-ce6b-445f-a18a-9e9474ed819d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1953015205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1953015205
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3460562900
Short name T892
Test name
Test status
Simulation time 56285670 ps
CPU time 1.16 seconds
Started Jul 01 11:50:06 AM PDT 24
Finished Jul 01 11:50:08 AM PDT 24
Peak memory 208116 kb
Host smart-3a8cbf9c-8d02-44e0-bf73-ef16cda05bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460562900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3460562900
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2312842666
Short name T988
Test name
Test status
Simulation time 5348061667 ps
CPU time 25.98 seconds
Started Jul 01 11:49:57 AM PDT 24
Finished Jul 01 11:50:24 AM PDT 24
Peak memory 217432 kb
Host smart-cee2b697-e9fa-4292-a4b9-42e440cf7c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312842666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2312842666
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3715303467
Short name T525
Test name
Test status
Simulation time 3131036133 ps
CPU time 11.25 seconds
Started Jul 01 11:49:59 AM PDT 24
Finished Jul 01 11:50:12 AM PDT 24
Peak memory 217512 kb
Host smart-df628129-9de1-42a9-b8f7-a2dae4525683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715303467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3715303467
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2644538951
Short name T408
Test name
Test status
Simulation time 24972655 ps
CPU time 0.87 seconds
Started Jul 01 11:50:01 AM PDT 24
Finished Jul 01 11:50:03 AM PDT 24
Peak memory 206936 kb
Host smart-cf70a130-da09-47ec-af92-4c70ff88658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644538951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2644538951
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.806560809
Short name T875
Test name
Test status
Simulation time 67136602 ps
CPU time 0.77 seconds
Started Jul 01 11:49:58 AM PDT 24
Finished Jul 01 11:49:59 AM PDT 24
Peak memory 206960 kb
Host smart-902ccabb-a8b1-400e-aa55-aa34f661f089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806560809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.806560809
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.140419312
Short name T256
Test name
Test status
Simulation time 2402300128 ps
CPU time 4.7 seconds
Started Jul 01 11:50:01 AM PDT 24
Finished Jul 01 11:50:06 AM PDT 24
Peak memory 233828 kb
Host smart-8215f2a6-228e-42c3-a5e1-07fe31c26aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140419312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.140419312
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.799553948
Short name T313
Test name
Test status
Simulation time 24195749 ps
CPU time 0.74 seconds
Started Jul 01 11:50:19 AM PDT 24
Finished Jul 01 11:50:21 AM PDT 24
Peak memory 205796 kb
Host smart-0e50d70b-d031-470d-9394-22aad04f9200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799553948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.799553948
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3892855223
Short name T502
Test name
Test status
Simulation time 625572251 ps
CPU time 3.86 seconds
Started Jul 01 11:50:10 AM PDT 24
Finished Jul 01 11:50:15 AM PDT 24
Peak memory 225556 kb
Host smart-98126e71-5166-4bac-9b30-e018b5229395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892855223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3892855223
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1934516286
Short name T1018
Test name
Test status
Simulation time 16054539 ps
CPU time 0.77 seconds
Started Jul 01 11:50:05 AM PDT 24
Finished Jul 01 11:50:06 AM PDT 24
Peak memory 206676 kb
Host smart-7a6336f2-3ddd-4448-9c31-655321916afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934516286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1934516286
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.725664920
Short name T185
Test name
Test status
Simulation time 63496263917 ps
CPU time 165.49 seconds
Started Jul 01 11:50:13 AM PDT 24
Finished Jul 01 11:53:00 AM PDT 24
Peak memory 268284 kb
Host smart-583258ce-7ebc-4ee3-8db7-ab7885e70818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725664920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.725664920
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.472144635
Short name T334
Test name
Test status
Simulation time 405252575 ps
CPU time 4.47 seconds
Started Jul 01 11:50:12 AM PDT 24
Finished Jul 01 11:50:17 AM PDT 24
Peak memory 225528 kb
Host smart-d590c242-f8b0-4707-ac9b-15642db66a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472144635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.472144635
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1901934127
Short name T982
Test name
Test status
Simulation time 3971491942 ps
CPU time 12.92 seconds
Started Jul 01 11:50:10 AM PDT 24
Finished Jul 01 11:50:24 AM PDT 24
Peak memory 224124 kb
Host smart-9ef80575-dc52-4181-9d75-3ae3fae0390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901934127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1901934127
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4294125556
Short name T543
Test name
Test status
Simulation time 475381441 ps
CPU time 4.15 seconds
Started Jul 01 11:50:11 AM PDT 24
Finished Jul 01 11:50:16 AM PDT 24
Peak memory 233728 kb
Host smart-8eccd9cd-6fa3-4b30-90ae-5da5add3f7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294125556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4294125556
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3221540987
Short name T221
Test name
Test status
Simulation time 120894649400 ps
CPU time 94.39 seconds
Started Jul 01 11:50:11 AM PDT 24
Finished Jul 01 11:51:47 AM PDT 24
Peak memory 240000 kb
Host smart-83e38d79-bb12-421e-8a0c-ec6f4e6800cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221540987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3221540987
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.337632513
Short name T860
Test name
Test status
Simulation time 2137229952 ps
CPU time 18.14 seconds
Started Jul 01 11:50:10 AM PDT 24
Finished Jul 01 11:50:29 AM PDT 24
Peak memory 225528 kb
Host smart-7386fde9-c40d-49d2-b7e8-8890c790b1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337632513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.337632513
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2196554532
Short name T926
Test name
Test status
Simulation time 326530636 ps
CPU time 3.99 seconds
Started Jul 01 11:50:11 AM PDT 24
Finished Jul 01 11:50:16 AM PDT 24
Peak memory 225512 kb
Host smart-2aff2400-2dc2-4671-8acf-6e9d673e9591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196554532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2196554532
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.316019423
Short name T665
Test name
Test status
Simulation time 159780051 ps
CPU time 1.01 seconds
Started Jul 01 11:50:05 AM PDT 24
Finished Jul 01 11:50:07 AM PDT 24
Peak memory 217652 kb
Host smart-87015710-cf82-45ab-b76f-19de011a32c4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316019423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.316019423
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2259146259
Short name T60
Test name
Test status
Simulation time 30531094 ps
CPU time 2.44 seconds
Started Jul 01 11:50:11 AM PDT 24
Finished Jul 01 11:50:15 AM PDT 24
Peak memory 233516 kb
Host smart-d9868944-2761-4f3e-a531-56bbb4a60fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259146259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2259146259
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1450431116
Short name T641
Test name
Test status
Simulation time 39802339 ps
CPU time 2.54 seconds
Started Jul 01 11:50:13 AM PDT 24
Finished Jul 01 11:50:17 AM PDT 24
Peak memory 233736 kb
Host smart-3be9ce92-9b52-444f-898d-6a7321c36a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450431116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1450431116
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2450810497
Short name T877
Test name
Test status
Simulation time 838290208 ps
CPU time 4.66 seconds
Started Jul 01 11:50:11 AM PDT 24
Finished Jul 01 11:50:17 AM PDT 24
Peak memory 221764 kb
Host smart-e3ebe7a8-a122-4f37-bf35-23552c7a8ff7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2450810497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2450810497
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1997176956
Short name T17
Test name
Test status
Simulation time 1119621432466 ps
CPU time 555.87 seconds
Started Jul 01 11:50:15 AM PDT 24
Finished Jul 01 11:59:34 AM PDT 24
Peak memory 263840 kb
Host smart-5a3377f0-9058-4d60-a49f-993cb06c5d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997176956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1997176956
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.708121218
Short name T713
Test name
Test status
Simulation time 2856320210 ps
CPU time 30.95 seconds
Started Jul 01 11:50:04 AM PDT 24
Finished Jul 01 11:50:36 AM PDT 24
Peak memory 217400 kb
Host smart-ab1aaca5-7bde-4699-b4bf-55fae0f32484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708121218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.708121218
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.134614719
Short name T973
Test name
Test status
Simulation time 328079047 ps
CPU time 1.86 seconds
Started Jul 01 11:50:05 AM PDT 24
Finished Jul 01 11:50:08 AM PDT 24
Peak memory 208960 kb
Host smart-e80bf3c6-4689-4431-a075-62428af46a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134614719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.134614719
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3928364036
Short name T719
Test name
Test status
Simulation time 101614849 ps
CPU time 1.06 seconds
Started Jul 01 11:50:11 AM PDT 24
Finished Jul 01 11:50:13 AM PDT 24
Peak memory 217156 kb
Host smart-b12d7b24-cb13-4a9a-b38a-5e5a9d72daea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928364036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3928364036
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3436804840
Short name T642
Test name
Test status
Simulation time 140044337 ps
CPU time 0.88 seconds
Started Jul 01 11:50:09 AM PDT 24
Finished Jul 01 11:50:11 AM PDT 24
Peak memory 207360 kb
Host smart-aa0d0d3d-50ee-4e28-b510-690c890ffebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436804840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3436804840
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3692068378
Short name T360
Test name
Test status
Simulation time 2557098750 ps
CPU time 7.18 seconds
Started Jul 01 11:50:09 AM PDT 24
Finished Jul 01 11:50:17 AM PDT 24
Peak memory 225692 kb
Host smart-3945e633-6c89-4dba-9be3-24e5885e4761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692068378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3692068378
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1561634938
Short name T552
Test name
Test status
Simulation time 32418528 ps
CPU time 0.78 seconds
Started Jul 01 11:50:21 AM PDT 24
Finished Jul 01 11:50:23 AM PDT 24
Peak memory 206796 kb
Host smart-1adbf8b3-4fa5-4689-b3e2-d42653383d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561634938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1561634938
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3463327785
Short name T650
Test name
Test status
Simulation time 717672113 ps
CPU time 2.38 seconds
Started Jul 01 11:50:17 AM PDT 24
Finished Jul 01 11:50:22 AM PDT 24
Peak memory 225200 kb
Host smart-028f08ee-bff6-4385-9be8-cdf406afd48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463327785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3463327785
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3654907048
Short name T438
Test name
Test status
Simulation time 34519466 ps
CPU time 0.78 seconds
Started Jul 01 11:50:17 AM PDT 24
Finished Jul 01 11:50:20 AM PDT 24
Peak memory 207496 kb
Host smart-bfcf76c6-9c0d-4dca-a090-5082194586b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654907048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3654907048
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.486582489
Short name T930
Test name
Test status
Simulation time 7928829237 ps
CPU time 54.31 seconds
Started Jul 01 11:50:23 AM PDT 24
Finished Jul 01 11:51:18 AM PDT 24
Peak memory 233824 kb
Host smart-c6b9de06-e9a5-4bd7-b60f-29f9faf2fc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486582489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.486582489
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4161886585
Short name T181
Test name
Test status
Simulation time 102563394729 ps
CPU time 244.53 seconds
Started Jul 01 11:50:19 AM PDT 24
Finished Jul 01 11:54:25 AM PDT 24
Peak memory 256484 kb
Host smart-dc395d75-deb6-4b1c-9c4e-3049d5885f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161886585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4161886585
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2791985614
Short name T244
Test name
Test status
Simulation time 294202339370 ps
CPU time 232.39 seconds
Started Jul 01 11:50:19 AM PDT 24
Finished Jul 01 11:54:13 AM PDT 24
Peak memory 250312 kb
Host smart-2bd6a6ef-eeee-43d2-9012-0a1c8fa3e268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791985614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2791985614
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1874471353
Short name T310
Test name
Test status
Simulation time 279222233 ps
CPU time 7.12 seconds
Started Jul 01 11:50:15 AM PDT 24
Finished Jul 01 11:50:25 AM PDT 24
Peak memory 225540 kb
Host smart-e71b40fa-f554-4c47-b123-48a252bd38e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874471353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1874471353
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3652231707
Short name T685
Test name
Test status
Simulation time 185696607146 ps
CPU time 175.36 seconds
Started Jul 01 11:50:20 AM PDT 24
Finished Jul 01 11:53:17 AM PDT 24
Peak memory 250232 kb
Host smart-5b2c53cf-4ff0-4304-bb37-c1995c32180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652231707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3652231707
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2506382819
Short name T516
Test name
Test status
Simulation time 1746450097 ps
CPU time 18.23 seconds
Started Jul 01 11:50:16 AM PDT 24
Finished Jul 01 11:50:36 AM PDT 24
Peak memory 233688 kb
Host smart-a71af001-dcbc-4436-85d3-c07f343a858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506382819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2506382819
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3574736781
Short name T751
Test name
Test status
Simulation time 1814814646 ps
CPU time 3.89 seconds
Started Jul 01 11:50:14 AM PDT 24
Finished Jul 01 11:50:19 AM PDT 24
Peak memory 233732 kb
Host smart-23fcdc48-33c5-4c60-95ba-1657dffd97fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574736781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3574736781
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3596252318
Short name T247
Test name
Test status
Simulation time 1738540864 ps
CPU time 5.31 seconds
Started Jul 01 11:50:17 AM PDT 24
Finished Jul 01 11:50:24 AM PDT 24
Peak memory 234728 kb
Host smart-7c23ca9b-a670-45aa-bd36-1cccbffcb8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596252318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3596252318
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2750153367
Short name T876
Test name
Test status
Simulation time 629087656 ps
CPU time 8.38 seconds
Started Jul 01 11:50:16 AM PDT 24
Finished Jul 01 11:50:27 AM PDT 24
Peak memory 233676 kb
Host smart-12c9f329-019e-488b-bc2c-89aff0e65a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750153367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2750153367
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.692654662
Short name T344
Test name
Test status
Simulation time 2861044123 ps
CPU time 3.6 seconds
Started Jul 01 11:50:24 AM PDT 24
Finished Jul 01 11:50:28 AM PDT 24
Peak memory 221564 kb
Host smart-bfe4e701-54b6-42b8-8d66-7e661649e3cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=692654662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.692654662
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.111820162
Short name T130
Test name
Test status
Simulation time 129281225092 ps
CPU time 348.75 seconds
Started Jul 01 11:50:22 AM PDT 24
Finished Jul 01 11:56:12 AM PDT 24
Peak memory 258564 kb
Host smart-38f6fa3d-67f9-4047-ad4e-7cda6e72ff4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111820162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.111820162
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1393187608
Short name T651
Test name
Test status
Simulation time 1677149233 ps
CPU time 10.2 seconds
Started Jul 01 11:50:15 AM PDT 24
Finished Jul 01 11:50:27 AM PDT 24
Peak memory 217392 kb
Host smart-4e02c100-dc92-4e77-9135-4193096912a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393187608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1393187608
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4238655291
Short name T584
Test name
Test status
Simulation time 730296881 ps
CPU time 4.62 seconds
Started Jul 01 11:50:15 AM PDT 24
Finished Jul 01 11:50:22 AM PDT 24
Peak memory 217348 kb
Host smart-389a5dae-6985-4e37-815b-09e0a9a768b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238655291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4238655291
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2971049027
Short name T999
Test name
Test status
Simulation time 54086889 ps
CPU time 1.66 seconds
Started Jul 01 11:50:15 AM PDT 24
Finished Jul 01 11:50:18 AM PDT 24
Peak memory 217344 kb
Host smart-95ddd6bb-5356-4daa-af78-f42103b54350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971049027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2971049027
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1820955881
Short name T587
Test name
Test status
Simulation time 120463951 ps
CPU time 0.88 seconds
Started Jul 01 11:50:15 AM PDT 24
Finished Jul 01 11:50:18 AM PDT 24
Peak memory 206956 kb
Host smart-2dbcc658-ccfa-49b6-ba1a-77bcd8325ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820955881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1820955881
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3078895258
Short name T257
Test name
Test status
Simulation time 3657452299 ps
CPU time 14.76 seconds
Started Jul 01 11:50:15 AM PDT 24
Finished Jul 01 11:50:31 AM PDT 24
Peak memory 233880 kb
Host smart-a63e3bb2-77ab-4d77-9d93-48c848c841a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078895258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3078895258
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.854195647
Short name T632
Test name
Test status
Simulation time 22919340 ps
CPU time 0.7 seconds
Started Jul 01 11:50:31 AM PDT 24
Finished Jul 01 11:50:33 AM PDT 24
Peak memory 206408 kb
Host smart-73d1d35b-21a0-4d82-a54c-caaf7f9e98e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854195647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.854195647
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2697716049
Short name T381
Test name
Test status
Simulation time 1041300049 ps
CPU time 6.05 seconds
Started Jul 01 11:50:27 AM PDT 24
Finished Jul 01 11:50:34 AM PDT 24
Peak memory 225512 kb
Host smart-cdafb2ae-aa8c-4e83-a9d5-90785dbf320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697716049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2697716049
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.428726063
Short name T772
Test name
Test status
Simulation time 19262910 ps
CPU time 0.78 seconds
Started Jul 01 11:50:21 AM PDT 24
Finished Jul 01 11:50:23 AM PDT 24
Peak memory 207832 kb
Host smart-68bde70c-f453-4598-a144-2a24324b59be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428726063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.428726063
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2510534888
Short name T953
Test name
Test status
Simulation time 217272687320 ps
CPU time 510.82 seconds
Started Jul 01 11:50:25 AM PDT 24
Finished Jul 01 11:58:57 AM PDT 24
Peak memory 266768 kb
Host smart-adf6e1b6-80af-46df-9281-8f0cbdba6077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510534888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2510534888
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3231338087
Short name T758
Test name
Test status
Simulation time 955182199 ps
CPU time 13.22 seconds
Started Jul 01 11:50:26 AM PDT 24
Finished Jul 01 11:50:40 AM PDT 24
Peak memory 225560 kb
Host smart-0674a671-8b85-43ae-9690-e5ddebae27d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231338087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3231338087
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3661827585
Short name T232
Test name
Test status
Simulation time 582807477 ps
CPU time 3.29 seconds
Started Jul 01 11:50:23 AM PDT 24
Finished Jul 01 11:50:27 AM PDT 24
Peak memory 225504 kb
Host smart-843111cf-4968-4b08-809e-bc184f16c07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661827585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3661827585
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3470510965
Short name T532
Test name
Test status
Simulation time 1173014694 ps
CPU time 16.31 seconds
Started Jul 01 11:50:28 AM PDT 24
Finished Jul 01 11:50:45 AM PDT 24
Peak memory 241656 kb
Host smart-248fff2a-e53d-4b7b-a93b-50595839208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470510965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3470510965
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1684356681
Short name T38
Test name
Test status
Simulation time 90332455 ps
CPU time 1.03 seconds
Started Jul 01 11:50:20 AM PDT 24
Finished Jul 01 11:50:23 AM PDT 24
Peak memory 218868 kb
Host smart-befc0c23-6f38-406b-8e6e-74dba1c79687
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684356681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1684356681
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3145401840
Short name T1016
Test name
Test status
Simulation time 2782753692 ps
CPU time 13.09 seconds
Started Jul 01 11:50:19 AM PDT 24
Finished Jul 01 11:50:34 AM PDT 24
Peak memory 241508 kb
Host smart-f02493a0-c4df-4e86-a80b-2ced98f3453f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145401840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3145401840
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.793964648
Short name T328
Test name
Test status
Simulation time 3564555904 ps
CPU time 12.26 seconds
Started Jul 01 11:50:21 AM PDT 24
Finished Jul 01 11:50:34 AM PDT 24
Peak memory 233908 kb
Host smart-6ecc365a-27e7-4217-943c-1252f0fa25a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793964648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.793964648
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2496198023
Short name T766
Test name
Test status
Simulation time 2190096372 ps
CPU time 5.63 seconds
Started Jul 01 11:50:25 AM PDT 24
Finished Jul 01 11:50:31 AM PDT 24
Peak memory 220896 kb
Host smart-e38edbf4-61fa-4cef-a3aa-975440a524c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2496198023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2496198023
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3722482894
Short name T811
Test name
Test status
Simulation time 4545191818 ps
CPU time 13.92 seconds
Started Jul 01 11:50:19 AM PDT 24
Finished Jul 01 11:50:35 AM PDT 24
Peak memory 217508 kb
Host smart-b5cc749d-4802-46d6-be1c-2306b327e04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722482894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3722482894
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.370371615
Short name T415
Test name
Test status
Simulation time 7776429557 ps
CPU time 12.92 seconds
Started Jul 01 11:50:20 AM PDT 24
Finished Jul 01 11:50:34 AM PDT 24
Peak memory 217412 kb
Host smart-d4098be9-5038-4a75-b857-2dc51ce77089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370371615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.370371615
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3153535694
Short name T997
Test name
Test status
Simulation time 326615226 ps
CPU time 3.66 seconds
Started Jul 01 11:50:21 AM PDT 24
Finished Jul 01 11:50:26 AM PDT 24
Peak memory 217344 kb
Host smart-554d8f17-9607-4a9e-9d0a-83c68d0355e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153535694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3153535694
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3686035773
Short name T398
Test name
Test status
Simulation time 62707416 ps
CPU time 0.76 seconds
Started Jul 01 11:50:25 AM PDT 24
Finished Jul 01 11:50:27 AM PDT 24
Peak memory 207000 kb
Host smart-dba637ee-0e3c-4c41-aa93-eae690d14241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686035773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3686035773
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1117624157
Short name T1005
Test name
Test status
Simulation time 6325303456 ps
CPU time 19.09 seconds
Started Jul 01 11:50:27 AM PDT 24
Finished Jul 01 11:50:47 AM PDT 24
Peak memory 233776 kb
Host smart-b1806ec6-3e1e-45d7-8c48-89831849699a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117624157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1117624157
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.675071754
Short name T1015
Test name
Test status
Simulation time 34297307 ps
CPU time 0.75 seconds
Started Jul 01 11:50:38 AM PDT 24
Finished Jul 01 11:50:39 AM PDT 24
Peak memory 206692 kb
Host smart-cadf6273-9be3-4f70-bbdc-3ad350d055f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675071754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.675071754
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.318482178
Short name T533
Test name
Test status
Simulation time 110545772 ps
CPU time 2.39 seconds
Started Jul 01 11:50:32 AM PDT 24
Finished Jul 01 11:50:35 AM PDT 24
Peak memory 225576 kb
Host smart-0502e9fc-0a00-458c-b5d9-ec6108559fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318482178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.318482178
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.753074225
Short name T647
Test name
Test status
Simulation time 20615826 ps
CPU time 0.82 seconds
Started Jul 01 11:50:24 AM PDT 24
Finished Jul 01 11:50:26 AM PDT 24
Peak memory 207808 kb
Host smart-ad42cbfe-d84e-4ef9-818b-68c868463c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753074225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.753074225
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2168494966
Short name T62
Test name
Test status
Simulation time 15260986782 ps
CPU time 138.14 seconds
Started Jul 01 11:50:31 AM PDT 24
Finished Jul 01 11:52:51 AM PDT 24
Peak memory 256624 kb
Host smart-5f0eb184-edb4-473f-9057-c551c3e5ecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168494966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2168494966
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3483700581
Short name T137
Test name
Test status
Simulation time 15254024012 ps
CPU time 103.95 seconds
Started Jul 01 11:50:36 AM PDT 24
Finished Jul 01 11:52:21 AM PDT 24
Peak memory 250388 kb
Host smart-6e9c921e-23bd-4036-b991-6d72b5f543e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483700581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3483700581
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3022265260
Short name T866
Test name
Test status
Simulation time 38999780776 ps
CPU time 35.82 seconds
Started Jul 01 11:50:35 AM PDT 24
Finished Jul 01 11:51:11 AM PDT 24
Peak memory 241160 kb
Host smart-4395dab2-ce07-4ab4-94c2-fee5e76e3b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022265260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3022265260
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2334407246
Short name T826
Test name
Test status
Simulation time 383000537 ps
CPU time 3.36 seconds
Started Jul 01 11:50:31 AM PDT 24
Finished Jul 01 11:50:35 AM PDT 24
Peak memory 225568 kb
Host smart-6c7a9ed7-c445-4281-ab08-048587878952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334407246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2334407246
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2623109581
Short name T570
Test name
Test status
Simulation time 24137939371 ps
CPU time 49.45 seconds
Started Jul 01 11:50:31 AM PDT 24
Finished Jul 01 11:51:22 AM PDT 24
Peak memory 250256 kb
Host smart-8dc4de58-15ea-4693-b8ff-88cf86a56435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623109581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2623109581
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3414799487
Short name T580
Test name
Test status
Simulation time 30567680 ps
CPU time 2.09 seconds
Started Jul 01 11:50:31 AM PDT 24
Finished Jul 01 11:50:34 AM PDT 24
Peak memory 224916 kb
Host smart-73a4cbe4-1f0d-4a7d-a5dd-570720a6222c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414799487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3414799487
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2615819029
Short name T209
Test name
Test status
Simulation time 1439405334 ps
CPU time 14.95 seconds
Started Jul 01 11:50:30 AM PDT 24
Finished Jul 01 11:50:45 AM PDT 24
Peak memory 233780 kb
Host smart-f7f479f2-6640-4d8f-9e4a-3d76297c400d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615819029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2615819029
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.777253649
Short name T363
Test name
Test status
Simulation time 390920527 ps
CPU time 1.14 seconds
Started Jul 01 11:50:26 AM PDT 24
Finished Jul 01 11:50:28 AM PDT 24
Peak memory 217672 kb
Host smart-44d46b97-d8e6-422a-b329-e14a7ea13929
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777253649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.777253649
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.576366776
Short name T479
Test name
Test status
Simulation time 1426604088 ps
CPU time 5.3 seconds
Started Jul 01 11:50:31 AM PDT 24
Finished Jul 01 11:50:37 AM PDT 24
Peak memory 225772 kb
Host smart-e0fec092-15ab-4260-b4c9-4d30fa2bb53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576366776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.576366776
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3765742389
Short name T637
Test name
Test status
Simulation time 699835886 ps
CPU time 11.24 seconds
Started Jul 01 11:50:26 AM PDT 24
Finished Jul 01 11:50:38 AM PDT 24
Peak memory 250088 kb
Host smart-e80814d0-5ee8-48d8-9da7-435d2708ce0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765742389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3765742389
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3176551114
Short name T145
Test name
Test status
Simulation time 126600929 ps
CPU time 4.29 seconds
Started Jul 01 11:50:31 AM PDT 24
Finished Jul 01 11:50:36 AM PDT 24
Peak memory 224172 kb
Host smart-95bbb149-e55f-4f02-b4e8-f3d697083677
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3176551114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3176551114
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1194709241
Short name T289
Test name
Test status
Simulation time 58535510597 ps
CPU time 37.65 seconds
Started Jul 01 11:50:30 AM PDT 24
Finished Jul 01 11:51:09 AM PDT 24
Peak memory 217468 kb
Host smart-d013fad5-1e17-4365-81d4-b042b2e93184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194709241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1194709241
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4100677019
Short name T695
Test name
Test status
Simulation time 4468711902 ps
CPU time 7.71 seconds
Started Jul 01 11:50:28 AM PDT 24
Finished Jul 01 11:50:37 AM PDT 24
Peak memory 217500 kb
Host smart-bd41f4d8-f462-4595-81b0-9f710c5992bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100677019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4100677019
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3648673391
Short name T1010
Test name
Test status
Simulation time 242550155 ps
CPU time 1.41 seconds
Started Jul 01 11:50:31 AM PDT 24
Finished Jul 01 11:50:34 AM PDT 24
Peak memory 217380 kb
Host smart-45232628-8f5d-48a3-be98-69d25290efa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648673391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3648673391
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.858090548
Short name T717
Test name
Test status
Simulation time 987032434 ps
CPU time 1.08 seconds
Started Jul 01 11:50:24 AM PDT 24
Finished Jul 01 11:50:26 AM PDT 24
Peak memory 207972 kb
Host smart-3c13e3a9-a7df-453e-8a41-0b966e967495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858090548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.858090548
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2818040336
Short name T851
Test name
Test status
Simulation time 694597840 ps
CPU time 6.69 seconds
Started Jul 01 11:50:31 AM PDT 24
Finished Jul 01 11:50:39 AM PDT 24
Peak memory 233676 kb
Host smart-cfcc6138-bf92-496d-b085-21419b4ee1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818040336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2818040336
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.847856896
Short name T26
Test name
Test status
Simulation time 36170616 ps
CPU time 0.73 seconds
Started Jul 01 11:50:46 AM PDT 24
Finished Jul 01 11:50:47 AM PDT 24
Peak memory 206412 kb
Host smart-3cce5c92-e43d-4e0a-a48e-b0403a7a1ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847856896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.847856896
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3136483955
Short name T445
Test name
Test status
Simulation time 1200256620 ps
CPU time 5.44 seconds
Started Jul 01 11:50:45 AM PDT 24
Finished Jul 01 11:50:51 AM PDT 24
Peak memory 225568 kb
Host smart-3eaec1ee-a0ad-4aff-9ec0-2a9b34e3488d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136483955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3136483955
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3345956593
Short name T741
Test name
Test status
Simulation time 27244194 ps
CPU time 0.78 seconds
Started Jul 01 11:50:36 AM PDT 24
Finished Jul 01 11:50:37 AM PDT 24
Peak memory 206760 kb
Host smart-96d0ffc2-60e1-4480-aa13-8dc5047426b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345956593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3345956593
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.455499370
Short name T214
Test name
Test status
Simulation time 3807921431 ps
CPU time 62.48 seconds
Started Jul 01 11:50:40 AM PDT 24
Finished Jul 01 11:51:43 AM PDT 24
Peak memory 253496 kb
Host smart-1afaeb84-e4e5-4113-bb17-a98b07274b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455499370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.455499370
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1249698108
Short name T500
Test name
Test status
Simulation time 10971946988 ps
CPU time 84.4 seconds
Started Jul 01 11:50:41 AM PDT 24
Finished Jul 01 11:52:07 AM PDT 24
Peak memory 250396 kb
Host smart-2f313e22-c5cf-4822-ac4c-d4bc0ea88dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249698108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1249698108
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3307229245
Short name T657
Test name
Test status
Simulation time 5006972428 ps
CPU time 37.2 seconds
Started Jul 01 11:50:45 AM PDT 24
Finished Jul 01 11:51:23 AM PDT 24
Peak memory 250312 kb
Host smart-a5ef06b0-47fb-4934-bad3-c4e326c359ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307229245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3307229245
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.4059726371
Short name T400
Test name
Test status
Simulation time 1110448402 ps
CPU time 23.5 seconds
Started Jul 01 11:50:41 AM PDT 24
Finished Jul 01 11:51:05 AM PDT 24
Peak memory 250024 kb
Host smart-1f537036-cbcc-4328-8fc4-6f0d13be6545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059726371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.4059726371
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2052027854
Short name T228
Test name
Test status
Simulation time 543464071 ps
CPU time 8.99 seconds
Started Jul 01 11:50:40 AM PDT 24
Finished Jul 01 11:50:49 AM PDT 24
Peak memory 233760 kb
Host smart-d0782cb1-d666-444c-977d-580259b956ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052027854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2052027854
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4018995323
Short name T681
Test name
Test status
Simulation time 862050933 ps
CPU time 14.77 seconds
Started Jul 01 11:50:45 AM PDT 24
Finished Jul 01 11:51:00 AM PDT 24
Peak memory 241532 kb
Host smart-ce99878a-67f2-4975-ad97-179ac313054b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018995323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4018995323
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.4029633027
Short name T440
Test name
Test status
Simulation time 29132139 ps
CPU time 1.08 seconds
Started Jul 01 11:50:37 AM PDT 24
Finished Jul 01 11:50:39 AM PDT 24
Peak memory 217656 kb
Host smart-db93ad8b-ba95-4a87-9fa2-358be7398cf8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029633027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.4029633027
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2012634698
Short name T492
Test name
Test status
Simulation time 25187100756 ps
CPU time 20.2 seconds
Started Jul 01 11:50:40 AM PDT 24
Finished Jul 01 11:51:01 AM PDT 24
Peak memory 241744 kb
Host smart-90efda1a-2a56-4285-86f7-afa014b1c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012634698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2012634698
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1380615920
Short name T928
Test name
Test status
Simulation time 4199655474 ps
CPU time 8.31 seconds
Started Jul 01 11:50:35 AM PDT 24
Finished Jul 01 11:50:44 AM PDT 24
Peak memory 233816 kb
Host smart-7559343e-15f9-4693-8d69-814f82b44ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380615920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1380615920
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.10968797
Short name T148
Test name
Test status
Simulation time 409968171 ps
CPU time 6.94 seconds
Started Jul 01 11:50:40 AM PDT 24
Finished Jul 01 11:50:48 AM PDT 24
Peak memory 224224 kb
Host smart-53d2fe51-289e-4d3c-9d86-c460d3fba5cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=10968797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direc
t.10968797
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.426201292
Short name T503
Test name
Test status
Simulation time 98473955 ps
CPU time 1.05 seconds
Started Jul 01 11:50:44 AM PDT 24
Finished Jul 01 11:50:46 AM PDT 24
Peak memory 208060 kb
Host smart-c05a370d-71b3-4710-9e9e-61e515c599f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426201292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.426201292
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3768536117
Short name T489
Test name
Test status
Simulation time 2756167989 ps
CPU time 19.39 seconds
Started Jul 01 11:50:38 AM PDT 24
Finished Jul 01 11:50:58 AM PDT 24
Peak memory 217636 kb
Host smart-fe92fbdd-e1c8-499e-afd3-29e1b86a619b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768536117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3768536117
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.745922964
Short name T514
Test name
Test status
Simulation time 806181737 ps
CPU time 5.45 seconds
Started Jul 01 11:50:37 AM PDT 24
Finished Jul 01 11:50:44 AM PDT 24
Peak memory 217444 kb
Host smart-d4a7f686-3eb4-4494-8a86-375dcd76f504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745922964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.745922964
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.61804323
Short name T808
Test name
Test status
Simulation time 43898175 ps
CPU time 0.91 seconds
Started Jul 01 11:50:36 AM PDT 24
Finished Jul 01 11:50:38 AM PDT 24
Peak memory 207996 kb
Host smart-420ce1c7-1de2-47d3-82c5-7e64958e5391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61804323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.61804323
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2246426835
Short name T484
Test name
Test status
Simulation time 68788070 ps
CPU time 0.92 seconds
Started Jul 01 11:50:37 AM PDT 24
Finished Jul 01 11:50:38 AM PDT 24
Peak memory 206996 kb
Host smart-511310c8-e68e-4f0b-84f7-8e98f2f95181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246426835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2246426835
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3422455655
Short name T738
Test name
Test status
Simulation time 19109532081 ps
CPU time 9.52 seconds
Started Jul 01 11:50:40 AM PDT 24
Finished Jul 01 11:50:50 AM PDT 24
Peak memory 225672 kb
Host smart-7e9f8337-7d98-490f-a268-bb1919b6e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422455655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3422455655
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2462800459
Short name T723
Test name
Test status
Simulation time 13499098 ps
CPU time 0.77 seconds
Started Jul 01 11:50:53 AM PDT 24
Finished Jul 01 11:50:55 AM PDT 24
Peak memory 206400 kb
Host smart-30583226-c1b9-4ce9-ab0f-ffdffe2e2ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462800459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2462800459
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1497121997
Short name T253
Test name
Test status
Simulation time 5742031167 ps
CPU time 15.92 seconds
Started Jul 01 11:50:53 AM PDT 24
Finished Jul 01 11:51:09 AM PDT 24
Peak memory 233896 kb
Host smart-e6aefbaa-4d6f-4cfc-9e3d-9102a0cb6174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497121997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1497121997
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.190170643
Short name T769
Test name
Test status
Simulation time 15546643 ps
CPU time 0.77 seconds
Started Jul 01 11:50:46 AM PDT 24
Finished Jul 01 11:50:48 AM PDT 24
Peak memory 208040 kb
Host smart-362d18f4-4d97-4ca1-a903-b70faff318e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190170643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.190170643
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.300072534
Short name T192
Test name
Test status
Simulation time 3355824825 ps
CPU time 78.79 seconds
Started Jul 01 11:50:51 AM PDT 24
Finished Jul 01 11:52:10 AM PDT 24
Peak memory 258016 kb
Host smart-73bd55f0-17c8-4238-9110-f51cc7bc7ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300072534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.300072534
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1216550101
Short name T53
Test name
Test status
Simulation time 30513869354 ps
CPU time 127.59 seconds
Started Jul 01 11:50:51 AM PDT 24
Finished Jul 01 11:52:59 AM PDT 24
Peak memory 265168 kb
Host smart-526ebf7c-b87d-4aa2-8c8e-a8fa1adac741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216550101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1216550101
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3960708680
Short name T169
Test name
Test status
Simulation time 3651415774 ps
CPU time 54.16 seconds
Started Jul 01 11:50:52 AM PDT 24
Finished Jul 01 11:51:47 AM PDT 24
Peak memory 250400 kb
Host smart-6ba5ced2-fd1d-4cdd-9c62-348e2ea71ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960708680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3960708680
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3201835310
Short name T825
Test name
Test status
Simulation time 1375977597 ps
CPU time 10.25 seconds
Started Jul 01 11:50:51 AM PDT 24
Finished Jul 01 11:51:02 AM PDT 24
Peak memory 233804 kb
Host smart-6e0e90dc-7217-43be-b3fb-7823ef33621f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201835310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3201835310
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2973996241
Short name T189
Test name
Test status
Simulation time 69184966235 ps
CPU time 144.43 seconds
Started Jul 01 11:50:52 AM PDT 24
Finished Jul 01 11:53:17 AM PDT 24
Peak memory 252668 kb
Host smart-384664ff-6119-4ffd-8888-5c7862c3e819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973996241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2973996241
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1008135724
Short name T236
Test name
Test status
Simulation time 2809320394 ps
CPU time 7.91 seconds
Started Jul 01 11:50:50 AM PDT 24
Finished Jul 01 11:50:59 AM PDT 24
Peak memory 225696 kb
Host smart-455e38d5-cb78-4cef-a323-58beb91bcdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008135724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1008135724
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3497004265
Short name T396
Test name
Test status
Simulation time 6953857196 ps
CPU time 84.74 seconds
Started Jul 01 11:50:49 AM PDT 24
Finished Jul 01 11:52:14 AM PDT 24
Peak memory 233876 kb
Host smart-29e0bc72-26fa-41a6-8382-ebe313767ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497004265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3497004265
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.482769743
Short name T699
Test name
Test status
Simulation time 48939927 ps
CPU time 1.11 seconds
Started Jul 01 11:50:49 AM PDT 24
Finished Jul 01 11:50:51 AM PDT 24
Peak memory 217660 kb
Host smart-46a2df6f-187f-4612-a106-c88495e2d3a8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482769743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.482769743
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1767651902
Short name T395
Test name
Test status
Simulation time 1004390372 ps
CPU time 5.54 seconds
Started Jul 01 11:50:50 AM PDT 24
Finished Jul 01 11:50:57 AM PDT 24
Peak memory 233776 kb
Host smart-868932a5-b489-4220-a34a-1fd2fe9d0d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767651902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1767651902
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1556008443
Short name T493
Test name
Test status
Simulation time 6287080264 ps
CPU time 15.1 seconds
Started Jul 01 11:50:50 AM PDT 24
Finished Jul 01 11:51:06 AM PDT 24
Peak memory 242040 kb
Host smart-3a397c63-5889-4b89-a7f6-282a22a21a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556008443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1556008443
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1217052663
Short name T144
Test name
Test status
Simulation time 446376932 ps
CPU time 3.58 seconds
Started Jul 01 11:50:49 AM PDT 24
Finished Jul 01 11:50:53 AM PDT 24
Peak memory 223600 kb
Host smart-84ea7216-2642-44d5-a952-c7f4e3979cab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1217052663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1217052663
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.864451645
Short name T442
Test name
Test status
Simulation time 24879716163 ps
CPU time 256.74 seconds
Started Jul 01 11:50:52 AM PDT 24
Finished Jul 01 11:55:10 AM PDT 24
Peak memory 274204 kb
Host smart-a6d833b4-170e-4f67-9a95-10f4040fa313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864451645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.864451645
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1832499380
Short name T918
Test name
Test status
Simulation time 3966717114 ps
CPU time 23.71 seconds
Started Jul 01 11:50:48 AM PDT 24
Finished Jul 01 11:51:12 AM PDT 24
Peak memory 217596 kb
Host smart-24f6dfe8-9fea-4926-bf09-2022858d4b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832499380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1832499380
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3854260678
Short name T627
Test name
Test status
Simulation time 253072593 ps
CPU time 2.29 seconds
Started Jul 01 11:50:46 AM PDT 24
Finished Jul 01 11:50:49 AM PDT 24
Peak memory 217120 kb
Host smart-9bec9b91-dfa1-4f6e-81c6-8b3e66c9d896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854260678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3854260678
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2562558783
Short name T891
Test name
Test status
Simulation time 22551062 ps
CPU time 0.84 seconds
Started Jul 01 11:50:48 AM PDT 24
Finished Jul 01 11:50:49 AM PDT 24
Peak memory 207152 kb
Host smart-fab7c226-96b1-49d4-884a-03c0fe185991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562558783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2562558783
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1477662624
Short name T596
Test name
Test status
Simulation time 1328955040 ps
CPU time 1.05 seconds
Started Jul 01 11:50:48 AM PDT 24
Finished Jul 01 11:50:50 AM PDT 24
Peak memory 207984 kb
Host smart-6ffcb9aa-3161-49c6-89d9-5b8eeb2e52af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477662624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1477662624
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.435065526
Short name T762
Test name
Test status
Simulation time 447605916 ps
CPU time 6.5 seconds
Started Jul 01 11:50:52 AM PDT 24
Finished Jul 01 11:50:59 AM PDT 24
Peak memory 225544 kb
Host smart-2b0ee0ec-ce9d-41d6-a145-ac4baac01606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435065526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.435065526
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1798436391
Short name T443
Test name
Test status
Simulation time 14212285 ps
CPU time 0.76 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:03 AM PDT 24
Peak memory 206396 kb
Host smart-17ad479d-e25d-46d7-b92d-4658ae51ee4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798436391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1798436391
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2279582138
Short name T449
Test name
Test status
Simulation time 276522254 ps
CPU time 2.85 seconds
Started Jul 01 11:51:02 AM PDT 24
Finished Jul 01 11:51:05 AM PDT 24
Peak memory 233692 kb
Host smart-d84c0e2f-f4cc-4192-9b38-74acbb99cf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279582138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2279582138
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1863048651
Short name T308
Test name
Test status
Simulation time 42024988 ps
CPU time 0.8 seconds
Started Jul 01 11:50:53 AM PDT 24
Finished Jul 01 11:50:55 AM PDT 24
Peak memory 206488 kb
Host smart-6bc31a9c-7dea-4bd0-bcf0-e53c8d813014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863048651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1863048651
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1967280604
Short name T995
Test name
Test status
Simulation time 10715444476 ps
CPU time 55.39 seconds
Started Jul 01 11:50:58 AM PDT 24
Finished Jul 01 11:51:54 AM PDT 24
Peak memory 250372 kb
Host smart-4bbf1d8d-bb30-4d58-8e13-99dbb43bb73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967280604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1967280604
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.922294139
Short name T942
Test name
Test status
Simulation time 77819727126 ps
CPU time 383.96 seconds
Started Jul 01 11:50:56 AM PDT 24
Finished Jul 01 11:57:20 AM PDT 24
Peak memory 270340 kb
Host smart-9855848c-a044-4d6b-9709-b5681235cb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922294139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.922294139
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3802776590
Short name T245
Test name
Test status
Simulation time 42920184995 ps
CPU time 301.5 seconds
Started Jul 01 11:50:56 AM PDT 24
Finished Jul 01 11:55:59 AM PDT 24
Peak memory 251920 kb
Host smart-08918154-a992-4eda-8bfa-b268e7dfbfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802776590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3802776590
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3003476128
Short name T761
Test name
Test status
Simulation time 6218125110 ps
CPU time 18.84 seconds
Started Jul 01 11:50:56 AM PDT 24
Finished Jul 01 11:51:16 AM PDT 24
Peak memory 238444 kb
Host smart-5e2cb5f3-b0f6-4780-bf4f-11d9fdd04cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003476128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3003476128
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1895572581
Short name T125
Test name
Test status
Simulation time 4381466491 ps
CPU time 39.82 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:42 AM PDT 24
Peak memory 225620 kb
Host smart-d6f0092d-f02f-4e99-8500-a8e9bec2067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895572581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1895572581
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2278434419
Short name T888
Test name
Test status
Simulation time 3882927799 ps
CPU time 22.96 seconds
Started Jul 01 11:50:57 AM PDT 24
Finished Jul 01 11:51:21 AM PDT 24
Peak memory 225596 kb
Host smart-fd9819ad-2877-4474-9246-3f8e3366fd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278434419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2278434419
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.78637561
Short name T591
Test name
Test status
Simulation time 3130627357 ps
CPU time 6.72 seconds
Started Jul 01 11:50:57 AM PDT 24
Finished Jul 01 11:51:05 AM PDT 24
Peak memory 225628 kb
Host smart-000056a0-178b-42c4-9c6a-562e90b67353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78637561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.78637561
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1336094640
Short name T386
Test name
Test status
Simulation time 33492460 ps
CPU time 1.14 seconds
Started Jul 01 11:50:52 AM PDT 24
Finished Jul 01 11:50:54 AM PDT 24
Peak memory 217656 kb
Host smart-4f179d05-2b9f-4536-8720-7066da382b15
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336094640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1336094640
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.932574403
Short name T243
Test name
Test status
Simulation time 3328333756 ps
CPU time 9.31 seconds
Started Jul 01 11:50:57 AM PDT 24
Finished Jul 01 11:51:07 AM PDT 24
Peak memory 233852 kb
Host smart-888d51bc-0228-4f0a-b9b4-048fe0d83046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932574403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.932574403
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1011980302
Short name T254
Test name
Test status
Simulation time 31463768409 ps
CPU time 20.58 seconds
Started Jul 01 11:50:56 AM PDT 24
Finished Jul 01 11:51:17 AM PDT 24
Peak memory 225720 kb
Host smart-04b40515-9555-4d09-968e-277b9b890da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011980302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1011980302
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1990528429
Short name T526
Test name
Test status
Simulation time 2713811063 ps
CPU time 7.15 seconds
Started Jul 01 11:50:57 AM PDT 24
Finished Jul 01 11:51:05 AM PDT 24
Peak memory 220432 kb
Host smart-b613fea3-33ad-4e7c-96f0-003d7942099a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1990528429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1990528429
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.30096465
Short name T745
Test name
Test status
Simulation time 102456253163 ps
CPU time 232.36 seconds
Started Jul 01 11:50:57 AM PDT 24
Finished Jul 01 11:54:50 AM PDT 24
Peak memory 258536 kb
Host smart-50cd7d05-d57e-449f-879b-008513be5b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30096465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress
_all.30096465
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3156528237
Short name T327
Test name
Test status
Simulation time 292184289 ps
CPU time 3.24 seconds
Started Jul 01 11:50:50 AM PDT 24
Finished Jul 01 11:50:54 AM PDT 24
Peak memory 219052 kb
Host smart-bac21030-986e-45b3-96a4-37332371a0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156528237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3156528237
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4197173087
Short name T635
Test name
Test status
Simulation time 136874001 ps
CPU time 2.18 seconds
Started Jul 01 11:50:58 AM PDT 24
Finished Jul 01 11:51:01 AM PDT 24
Peak memory 217312 kb
Host smart-2f9633b1-6ceb-4cd9-8893-71d1a9da822a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197173087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4197173087
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2263958435
Short name T704
Test name
Test status
Simulation time 70592188 ps
CPU time 0.76 seconds
Started Jul 01 11:50:58 AM PDT 24
Finished Jul 01 11:51:00 AM PDT 24
Peak memory 206944 kb
Host smart-a39fa0ac-f417-4d22-ae43-d7d62913d879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263958435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2263958435
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3623900898
Short name T364
Test name
Test status
Simulation time 66400310592 ps
CPU time 21.57 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:24 AM PDT 24
Peak memory 242052 kb
Host smart-3801a175-f53c-46c7-baff-53b7c473f0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623900898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3623900898
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4284001833
Short name T781
Test name
Test status
Simulation time 22393572 ps
CPU time 0.74 seconds
Started Jul 01 11:51:07 AM PDT 24
Finished Jul 01 11:51:09 AM PDT 24
Peak memory 206372 kb
Host smart-0b94d026-60d4-4ea1-97ba-6d286cfbf919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284001833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4284001833
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3983312125
Short name T47
Test name
Test status
Simulation time 175763143 ps
CPU time 2.8 seconds
Started Jul 01 11:51:03 AM PDT 24
Finished Jul 01 11:51:07 AM PDT 24
Peak memory 233720 kb
Host smart-9f585751-dd31-4942-ab10-d25208dbe1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983312125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3983312125
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.41528589
Short name T832
Test name
Test status
Simulation time 13693961 ps
CPU time 0.79 seconds
Started Jul 01 11:51:02 AM PDT 24
Finished Jul 01 11:51:03 AM PDT 24
Peak memory 207612 kb
Host smart-a81b688a-ac50-422d-bb20-79e4d6cfca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41528589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.41528589
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.267415329
Short name T491
Test name
Test status
Simulation time 977221963 ps
CPU time 19.88 seconds
Started Jul 01 11:51:05 AM PDT 24
Finished Jul 01 11:51:25 AM PDT 24
Peak memory 241968 kb
Host smart-34a8f509-8883-4b68-9734-47fa4f61e45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267415329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.267415329
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3534510226
Short name T907
Test name
Test status
Simulation time 194670880502 ps
CPU time 108.95 seconds
Started Jul 01 11:51:02 AM PDT 24
Finished Jul 01 11:52:52 AM PDT 24
Peak memory 272028 kb
Host smart-de9e4663-007f-4162-b3d0-ebede24ffbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534510226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3534510226
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1937996194
Short name T611
Test name
Test status
Simulation time 207921236 ps
CPU time 6.47 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:09 AM PDT 24
Peak memory 241992 kb
Host smart-f7882282-1d84-4fc1-b0c3-1ed5ca6d22dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937996194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1937996194
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3058832419
Short name T870
Test name
Test status
Simulation time 1003515347 ps
CPU time 25.79 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:28 AM PDT 24
Peak memory 252572 kb
Host smart-369693c9-f54c-4a63-aa08-09c72c790c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058832419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3058832419
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.309567547
Short name T763
Test name
Test status
Simulation time 160655643 ps
CPU time 3.92 seconds
Started Jul 01 11:51:03 AM PDT 24
Finished Jul 01 11:51:08 AM PDT 24
Peak memory 233812 kb
Host smart-4a1408b5-75c8-4dfe-bb2a-1a875bbff5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309567547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.309567547
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.427958750
Short name T698
Test name
Test status
Simulation time 7441190753 ps
CPU time 17.3 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:19 AM PDT 24
Peak memory 233884 kb
Host smart-af520a9b-93d3-47c8-af73-2b18b32a206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427958750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.427958750
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.187949375
Short name T959
Test name
Test status
Simulation time 53477333 ps
CPU time 0.99 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:03 AM PDT 24
Peak memory 217664 kb
Host smart-761b5609-4fc1-47ed-bd29-21b6335d8987
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187949375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.187949375
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.24248434
Short name T712
Test name
Test status
Simulation time 36832644 ps
CPU time 2.56 seconds
Started Jul 01 11:51:03 AM PDT 24
Finished Jul 01 11:51:07 AM PDT 24
Peak memory 233716 kb
Host smart-5dc82108-3f36-45c9-8294-d6761b7ee4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24248434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.24248434
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.352933832
Short name T732
Test name
Test status
Simulation time 4497146576 ps
CPU time 17.46 seconds
Started Jul 01 11:51:03 AM PDT 24
Finished Jul 01 11:51:21 AM PDT 24
Peak memory 242060 kb
Host smart-5bd0167f-a2ef-499f-8f25-8fee348a646f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352933832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.352933832
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2401319914
Short name T991
Test name
Test status
Simulation time 238331050 ps
CPU time 5.3 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:07 AM PDT 24
Peak memory 223632 kb
Host smart-5cc593b9-d07c-4b54-bdd8-f6bd8a8f4204
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2401319914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2401319914
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2610500020
Short name T878
Test name
Test status
Simulation time 159372005660 ps
CPU time 395.84 seconds
Started Jul 01 11:51:03 AM PDT 24
Finished Jul 01 11:57:40 AM PDT 24
Peak memory 253140 kb
Host smart-f0542461-1c25-4e22-93c8-6e20a38588b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610500020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2610500020
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1164787822
Short name T287
Test name
Test status
Simulation time 2924003865 ps
CPU time 17.49 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:19 AM PDT 24
Peak memory 217524 kb
Host smart-76b209f9-353e-4ba3-b891-507c2246b1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164787822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1164787822
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.558628670
Short name T321
Test name
Test status
Simulation time 4823160670 ps
CPU time 7.96 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:11 AM PDT 24
Peak memory 217480 kb
Host smart-e8ff2766-65d0-4327-8f2a-d37b489c260e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558628670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.558628670
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.280446820
Short name T475
Test name
Test status
Simulation time 193861013 ps
CPU time 1.3 seconds
Started Jul 01 11:51:02 AM PDT 24
Finished Jul 01 11:51:05 AM PDT 24
Peak memory 217336 kb
Host smart-5e848b41-1f09-460c-be0b-869c732212a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280446820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.280446820
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1966574004
Short name T32
Test name
Test status
Simulation time 21474521 ps
CPU time 0.77 seconds
Started Jul 01 11:51:01 AM PDT 24
Finished Jul 01 11:51:03 AM PDT 24
Peak memory 206948 kb
Host smart-f230042e-9a42-4e99-b156-7acb583fdb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966574004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1966574004
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2057818939
Short name T380
Test name
Test status
Simulation time 5704111996 ps
CPU time 10.11 seconds
Started Jul 01 11:51:02 AM PDT 24
Finished Jul 01 11:51:13 AM PDT 24
Peak memory 233884 kb
Host smart-77b76b2f-8257-4d39-8e19-f231fb1d99f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057818939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2057818939
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2337425021
Short name T352
Test name
Test status
Simulation time 47934279 ps
CPU time 0.74 seconds
Started Jul 01 11:51:12 AM PDT 24
Finished Jul 01 11:51:15 AM PDT 24
Peak memory 206720 kb
Host smart-5e033021-917f-4190-9747-2a0c6d8d3184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337425021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2337425021
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.775849105
Short name T890
Test name
Test status
Simulation time 257809975 ps
CPU time 3.31 seconds
Started Jul 01 11:51:07 AM PDT 24
Finished Jul 01 11:51:12 AM PDT 24
Peak memory 233780 kb
Host smart-0320d567-7582-482c-a4b6-e92c70257668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775849105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.775849105
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4025868040
Short name T994
Test name
Test status
Simulation time 15492110 ps
CPU time 0.82 seconds
Started Jul 01 11:51:07 AM PDT 24
Finished Jul 01 11:51:09 AM PDT 24
Peak memory 207736 kb
Host smart-c261fa9b-c6db-4596-a078-19ef7e5e028a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025868040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4025868040
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3993139452
Short name T178
Test name
Test status
Simulation time 30418948638 ps
CPU time 150.78 seconds
Started Jul 01 11:51:19 AM PDT 24
Finished Jul 01 11:53:51 AM PDT 24
Peak memory 254016 kb
Host smart-8feeb08f-46d7-43f8-95fc-55e748944c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993139452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3993139452
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2521331557
Short name T284
Test name
Test status
Simulation time 6804282753 ps
CPU time 34.07 seconds
Started Jul 01 11:51:15 AM PDT 24
Finished Jul 01 11:51:50 AM PDT 24
Peak memory 225768 kb
Host smart-7bee630d-3791-44a7-b328-4f9a67e6d48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521331557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2521331557
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2191072143
Short name T759
Test name
Test status
Simulation time 4022408171 ps
CPU time 32.46 seconds
Started Jul 01 11:51:11 AM PDT 24
Finished Jul 01 11:51:44 AM PDT 24
Peak memory 233904 kb
Host smart-89fbef8f-0d2b-484b-833b-f9ac4167fc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191072143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2191072143
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3842737887
Short name T263
Test name
Test status
Simulation time 3975978214 ps
CPU time 52.7 seconds
Started Jul 01 11:51:07 AM PDT 24
Finished Jul 01 11:52:01 AM PDT 24
Peak memory 242072 kb
Host smart-9caab122-a57e-484f-ac8b-ff3411c05990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842737887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3842737887
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1345147199
Short name T513
Test name
Test status
Simulation time 7094456513 ps
CPU time 17.79 seconds
Started Jul 01 11:51:06 AM PDT 24
Finished Jul 01 11:51:25 AM PDT 24
Peak memory 233920 kb
Host smart-ba5d7548-9d06-44bc-ae8e-f7135cc8f00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345147199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1345147199
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1791991424
Short name T76
Test name
Test status
Simulation time 621849332 ps
CPU time 5.89 seconds
Started Jul 01 11:51:14 AM PDT 24
Finished Jul 01 11:51:21 AM PDT 24
Peak memory 225536 kb
Host smart-500d9f17-6775-4257-b005-f337cf23303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791991424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1791991424
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2073078820
Short name T964
Test name
Test status
Simulation time 18091669 ps
CPU time 1.05 seconds
Started Jul 01 11:51:09 AM PDT 24
Finished Jul 01 11:51:10 AM PDT 24
Peak memory 217624 kb
Host smart-48717e5c-4ec7-4228-80e1-d4521680d6db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073078820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2073078820
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3381975859
Short name T939
Test name
Test status
Simulation time 965839863 ps
CPU time 4.48 seconds
Started Jul 01 11:51:06 AM PDT 24
Finished Jul 01 11:51:12 AM PDT 24
Peak memory 233708 kb
Host smart-1f08012c-2242-4b47-ac51-c9bfe1f612ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381975859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3381975859
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2172498554
Short name T887
Test name
Test status
Simulation time 371173271 ps
CPU time 4.4 seconds
Started Jul 01 11:51:06 AM PDT 24
Finished Jul 01 11:51:12 AM PDT 24
Peak memory 233756 kb
Host smart-437539b3-9d60-4afd-ab4b-b194ecb28e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172498554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2172498554
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2318534018
Short name T373
Test name
Test status
Simulation time 344727198 ps
CPU time 3.33 seconds
Started Jul 01 11:51:07 AM PDT 24
Finished Jul 01 11:51:11 AM PDT 24
Peak memory 221856 kb
Host smart-56742706-b07d-4df0-bfbb-7b494a6d6b45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2318534018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2318534018
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3630792748
Short name T136
Test name
Test status
Simulation time 146990437513 ps
CPU time 103.44 seconds
Started Jul 01 11:51:12 AM PDT 24
Finished Jul 01 11:52:58 AM PDT 24
Peak memory 238844 kb
Host smart-844714b8-147a-412e-854b-6ae39d99ec2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630792748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3630792748
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2809667258
Short name T9
Test name
Test status
Simulation time 5502322730 ps
CPU time 28.27 seconds
Started Jul 01 11:51:08 AM PDT 24
Finished Jul 01 11:51:37 AM PDT 24
Peak memory 217664 kb
Host smart-95c3c55d-9b58-45ea-bacc-5a9642a888e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809667258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2809667258
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1162278959
Short name T676
Test name
Test status
Simulation time 1565045166 ps
CPU time 9.76 seconds
Started Jul 01 11:51:14 AM PDT 24
Finished Jul 01 11:51:25 AM PDT 24
Peak memory 217296 kb
Host smart-ba031bb6-7a77-4d62-9ced-585a04166411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162278959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1162278959
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1807867253
Short name T603
Test name
Test status
Simulation time 105401476 ps
CPU time 1.37 seconds
Started Jul 01 11:51:08 AM PDT 24
Finished Jul 01 11:51:10 AM PDT 24
Peak memory 217352 kb
Host smart-2242d084-c8b9-4dd4-9ffb-6523c91d64fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807867253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1807867253
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4001480253
Short name T716
Test name
Test status
Simulation time 56075807 ps
CPU time 0.8 seconds
Started Jul 01 11:51:06 AM PDT 24
Finished Jul 01 11:51:08 AM PDT 24
Peak memory 206964 kb
Host smart-0735ea19-5d2b-42bc-a0ac-f8e57e61e6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001480253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4001480253
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.154618348
Short name T227
Test name
Test status
Simulation time 1783016261 ps
CPU time 9.09 seconds
Started Jul 01 11:51:08 AM PDT 24
Finished Jul 01 11:51:18 AM PDT 24
Peak memory 233760 kb
Host smart-c6ba239e-a8f6-4b84-a1ab-48ab28cd2ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154618348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.154618348
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.97067699
Short name T593
Test name
Test status
Simulation time 11305565 ps
CPU time 0.71 seconds
Started Jul 01 11:48:43 AM PDT 24
Finished Jul 01 11:48:45 AM PDT 24
Peak memory 206736 kb
Host smart-beb2f575-4e53-46b5-a835-46d5230cd324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97067699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.97067699
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.663915110
Short name T927
Test name
Test status
Simulation time 3112707343 ps
CPU time 9.09 seconds
Started Jul 01 11:48:38 AM PDT 24
Finished Jul 01 11:48:48 AM PDT 24
Peak memory 233908 kb
Host smart-167067f4-7cbb-486d-b31a-91e50f1aa04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663915110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.663915110
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.422334920
Short name T746
Test name
Test status
Simulation time 14754872 ps
CPU time 0.77 seconds
Started Jul 01 11:48:30 AM PDT 24
Finished Jul 01 11:48:32 AM PDT 24
Peak memory 207532 kb
Host smart-4a48b40d-ef53-48d5-b257-a73de95ce561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422334920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.422334920
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1637972227
Short name T946
Test name
Test status
Simulation time 18677816 ps
CPU time 0.75 seconds
Started Jul 01 11:48:37 AM PDT 24
Finished Jul 01 11:48:39 AM PDT 24
Peak memory 216932 kb
Host smart-d979bd28-5d79-4411-bae3-0f1aaaa549a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637972227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1637972227
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.439920724
Short name T831
Test name
Test status
Simulation time 44755143597 ps
CPU time 23.82 seconds
Started Jul 01 11:48:41 AM PDT 24
Finished Jul 01 11:49:05 AM PDT 24
Peak memory 242072 kb
Host smart-0d970bec-37d2-4509-9a36-eeeaefddc6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439920724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.439920724
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2092870985
Short name T74
Test name
Test status
Simulation time 73529941661 ps
CPU time 192.37 seconds
Started Jul 01 11:48:38 AM PDT 24
Finished Jul 01 11:51:51 AM PDT 24
Peak memory 250092 kb
Host smart-f30c917f-1c5f-475b-bcef-7359e04b0798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092870985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2092870985
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3720755143
Short name T755
Test name
Test status
Simulation time 896190976 ps
CPU time 6.59 seconds
Started Jul 01 11:48:40 AM PDT 24
Finished Jul 01 11:48:48 AM PDT 24
Peak memory 237656 kb
Host smart-cca55d99-d26a-46a8-bdd0-d6ad00571997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720755143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3720755143
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2575948650
Short name T776
Test name
Test status
Simulation time 64078362498 ps
CPU time 63.51 seconds
Started Jul 01 11:48:41 AM PDT 24
Finished Jul 01 11:49:45 AM PDT 24
Peak memory 242076 kb
Host smart-9515536c-e65d-4df0-be4f-0b43a2f2c8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575948650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2575948650
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3426746744
Short name T770
Test name
Test status
Simulation time 1032464910 ps
CPU time 7.47 seconds
Started Jul 01 11:48:38 AM PDT 24
Finished Jul 01 11:48:46 AM PDT 24
Peak memory 233820 kb
Host smart-2e46b862-958f-42ea-8975-1dbb1b581d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426746744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3426746744
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2544720425
Short name T750
Test name
Test status
Simulation time 31744216637 ps
CPU time 25.89 seconds
Started Jul 01 11:48:36 AM PDT 24
Finished Jul 01 11:49:03 AM PDT 24
Peak memory 233852 kb
Host smart-7816b225-2a5d-4336-96ed-225fac7b89e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544720425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2544720425
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1131330848
Short name T558
Test name
Test status
Simulation time 16165764 ps
CPU time 1.07 seconds
Started Jul 01 11:48:31 AM PDT 24
Finished Jul 01 11:48:33 AM PDT 24
Peak memory 217668 kb
Host smart-eb1c09ee-d8cd-4132-bcef-ab2c0ad9258c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131330848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1131330848
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3877481656
Short name T863
Test name
Test status
Simulation time 76004841 ps
CPU time 2.21 seconds
Started Jul 01 11:48:37 AM PDT 24
Finished Jul 01 11:48:40 AM PDT 24
Peak memory 224040 kb
Host smart-6927ffb5-2c27-448c-a66d-3430d57951e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877481656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3877481656
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1300865606
Short name T828
Test name
Test status
Simulation time 7434541169 ps
CPU time 12.59 seconds
Started Jul 01 11:48:35 AM PDT 24
Finished Jul 01 11:48:49 AM PDT 24
Peak memory 225668 kb
Host smart-8961d483-6772-4e9f-9d5c-70f564525733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300865606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1300865606
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2412633092
Short name T457
Test name
Test status
Simulation time 1308500409 ps
CPU time 13.53 seconds
Started Jul 01 11:48:37 AM PDT 24
Finished Jul 01 11:48:52 AM PDT 24
Peak memory 223448 kb
Host smart-8abe3eb4-e6df-4b3b-b8ff-9bd156e4fb7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2412633092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2412633092
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3286909619
Short name T68
Test name
Test status
Simulation time 348733690 ps
CPU time 1.17 seconds
Started Jul 01 11:48:43 AM PDT 24
Finished Jul 01 11:48:44 AM PDT 24
Peak memory 236780 kb
Host smart-50ea01d7-1314-4026-b220-2beb5267fceb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286909619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3286909619
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3119041991
Short name T683
Test name
Test status
Simulation time 31284096360 ps
CPU time 119.5 seconds
Started Jul 01 11:48:44 AM PDT 24
Finished Jul 01 11:50:44 AM PDT 24
Peak memory 254428 kb
Host smart-18175064-a96c-4836-949f-b6510b1d85a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119041991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3119041991
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3750348338
Short name T407
Test name
Test status
Simulation time 9686799393 ps
CPU time 49.64 seconds
Started Jul 01 11:48:32 AM PDT 24
Finished Jul 01 11:49:23 AM PDT 24
Peak memory 217464 kb
Host smart-b77ef666-8dda-40dc-9183-99a760aa218d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750348338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3750348338
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1182827512
Short name T815
Test name
Test status
Simulation time 9570003490 ps
CPU time 9.06 seconds
Started Jul 01 11:48:32 AM PDT 24
Finished Jul 01 11:48:42 AM PDT 24
Peak memory 217448 kb
Host smart-866e5d5d-e7db-496c-8c5e-329b4ea2b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182827512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1182827512
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.87058524
Short name T347
Test name
Test status
Simulation time 697347936 ps
CPU time 2.34 seconds
Started Jul 01 11:48:37 AM PDT 24
Finished Jul 01 11:48:40 AM PDT 24
Peak memory 217288 kb
Host smart-f0eb5fde-6583-44e2-b15d-cef899dac5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87058524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.87058524
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3621801403
Short name T309
Test name
Test status
Simulation time 147988375 ps
CPU time 0.81 seconds
Started Jul 01 11:48:32 AM PDT 24
Finished Jul 01 11:48:34 AM PDT 24
Peak memory 206960 kb
Host smart-1f4b2c8a-0f62-4c9a-a4f3-5949aecfd9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621801403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3621801403
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1567789651
Short name T913
Test name
Test status
Simulation time 6931175713 ps
CPU time 22.75 seconds
Started Jul 01 11:48:36 AM PDT 24
Finished Jul 01 11:48:59 AM PDT 24
Peak memory 238092 kb
Host smart-b9e2ed7f-b031-41b5-ace0-5a14a376e96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567789651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1567789651
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3554172779
Short name T753
Test name
Test status
Simulation time 13498994 ps
CPU time 0.7 seconds
Started Jul 01 11:51:18 AM PDT 24
Finished Jul 01 11:51:20 AM PDT 24
Peak memory 205800 kb
Host smart-c4b8ced2-abbf-4893-9440-43d9f86bbfcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554172779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3554172779
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2754958012
Short name T323
Test name
Test status
Simulation time 374564760 ps
CPU time 3.74 seconds
Started Jul 01 11:51:13 AM PDT 24
Finished Jul 01 11:51:19 AM PDT 24
Peak memory 225532 kb
Host smart-4f88c0ad-e1db-4705-898a-3b823c7f792c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754958012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2754958012
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1116570312
Short name T345
Test name
Test status
Simulation time 15268826 ps
CPU time 0.79 seconds
Started Jul 01 11:51:13 AM PDT 24
Finished Jul 01 11:51:15 AM PDT 24
Peak memory 207520 kb
Host smart-83f21814-ca01-47ce-99d1-339a6e60b543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116570312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1116570312
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3740506976
Short name T968
Test name
Test status
Simulation time 48534413414 ps
CPU time 89.3 seconds
Started Jul 01 11:51:18 AM PDT 24
Finished Jul 01 11:52:49 AM PDT 24
Peak memory 238216 kb
Host smart-11f3cd57-85aa-43aa-9fd0-4b6550de5b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740506976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3740506976
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.250445296
Short name T765
Test name
Test status
Simulation time 2487852164 ps
CPU time 64.4 seconds
Started Jul 01 11:51:17 AM PDT 24
Finished Jul 01 11:52:22 AM PDT 24
Peak memory 258580 kb
Host smart-b219573d-49b1-4263-ac07-659fc8a375e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250445296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.250445296
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4087542034
Short name T208
Test name
Test status
Simulation time 5176878495 ps
CPU time 78.6 seconds
Started Jul 01 11:51:17 AM PDT 24
Finished Jul 01 11:52:37 AM PDT 24
Peak memory 257060 kb
Host smart-c4fca36b-2f16-47b5-84e7-abb24f093447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087542034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4087542034
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.4118244192
Short name T976
Test name
Test status
Simulation time 52014068956 ps
CPU time 112.61 seconds
Started Jul 01 11:51:14 AM PDT 24
Finished Jul 01 11:53:08 AM PDT 24
Peak memory 256696 kb
Host smart-faaacd18-6e26-4f7a-8258-25fcf949bb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118244192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.4118244192
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.150215246
Short name T230
Test name
Test status
Simulation time 375300030 ps
CPU time 3.27 seconds
Started Jul 01 11:51:12 AM PDT 24
Finished Jul 01 11:51:16 AM PDT 24
Peak memory 225520 kb
Host smart-2f0c3fcd-853b-4610-8626-b65436af3515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150215246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.150215246
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2585319913
Short name T421
Test name
Test status
Simulation time 1357737088 ps
CPU time 12.31 seconds
Started Jul 01 11:51:13 AM PDT 24
Finished Jul 01 11:51:27 AM PDT 24
Peak memory 225580 kb
Host smart-ceacd7df-60f9-4564-80f0-274677bfcc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585319913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2585319913
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2646459145
Short name T246
Test name
Test status
Simulation time 3668669868 ps
CPU time 6.8 seconds
Started Jul 01 11:51:12 AM PDT 24
Finished Jul 01 11:51:20 AM PDT 24
Peak memory 233844 kb
Host smart-05e9389e-b3e2-4134-ade1-ed2555f3b8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646459145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2646459145
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2055724919
Short name T921
Test name
Test status
Simulation time 1988445719 ps
CPU time 5.29 seconds
Started Jul 01 11:51:13 AM PDT 24
Finished Jul 01 11:51:20 AM PDT 24
Peak memory 233820 kb
Host smart-4046b282-baf6-4ab5-9721-cc84086f3718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055724919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2055724919
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1189699305
Short name T411
Test name
Test status
Simulation time 748786256 ps
CPU time 3.98 seconds
Started Jul 01 11:51:12 AM PDT 24
Finished Jul 01 11:51:17 AM PDT 24
Peak memory 219788 kb
Host smart-c7a782a0-6dd8-4324-9d47-8306bd5f61cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1189699305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1189699305
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1654609280
Short name T36
Test name
Test status
Simulation time 137730258524 ps
CPU time 205.39 seconds
Started Jul 01 11:51:18 AM PDT 24
Finished Jul 01 11:54:45 AM PDT 24
Peak memory 283236 kb
Host smart-bc30e536-bf7a-4288-ad3b-5e5844b3174e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654609280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1654609280
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2894135231
Short name T293
Test name
Test status
Simulation time 5755341600 ps
CPU time 21.31 seconds
Started Jul 01 11:51:15 AM PDT 24
Finished Jul 01 11:51:37 AM PDT 24
Peak memory 217484 kb
Host smart-50cbedcc-db0f-40be-b6f0-2d64d857cc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894135231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2894135231
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3643880664
Short name T376
Test name
Test status
Simulation time 66169092507 ps
CPU time 16.3 seconds
Started Jul 01 11:51:12 AM PDT 24
Finished Jul 01 11:51:30 AM PDT 24
Peak memory 217420 kb
Host smart-c3e05b71-32a1-4e58-82dc-10792901c433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643880664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3643880664
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.842326049
Short name T469
Test name
Test status
Simulation time 40078535 ps
CPU time 1.06 seconds
Started Jul 01 11:51:12 AM PDT 24
Finished Jul 01 11:51:15 AM PDT 24
Peak memory 208904 kb
Host smart-aa8c7721-424e-4dbb-8bf2-793e3318291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842326049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.842326049
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.575593317
Short name T539
Test name
Test status
Simulation time 121019915 ps
CPU time 0.82 seconds
Started Jul 01 11:51:12 AM PDT 24
Finished Jul 01 11:51:15 AM PDT 24
Peak memory 206904 kb
Host smart-9e7a3adc-ab01-4481-9945-7b02c4876674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575593317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.575593317
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2387758720
Short name T187
Test name
Test status
Simulation time 4142370025 ps
CPU time 15.51 seconds
Started Jul 01 11:51:11 AM PDT 24
Finished Jul 01 11:51:28 AM PDT 24
Peak memory 225700 kb
Host smart-41922896-27ed-411b-bb04-2050590a2b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387758720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2387758720
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2035285833
Short name T75
Test name
Test status
Simulation time 30062788 ps
CPU time 0.72 seconds
Started Jul 01 11:51:23 AM PDT 24
Finished Jul 01 11:51:24 AM PDT 24
Peak memory 206384 kb
Host smart-41539793-2d50-4e27-976e-43eadd53194f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035285833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2035285833
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1250195377
Short name T77
Test name
Test status
Simulation time 382069010 ps
CPU time 3.39 seconds
Started Jul 01 11:51:24 AM PDT 24
Finished Jul 01 11:51:28 AM PDT 24
Peak memory 225560 kb
Host smart-e4f0f185-589b-4134-a3db-e79abc87f869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250195377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1250195377
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2578737383
Short name T342
Test name
Test status
Simulation time 18473039 ps
CPU time 0.79 seconds
Started Jul 01 11:51:17 AM PDT 24
Finished Jul 01 11:51:19 AM PDT 24
Peak memory 207472 kb
Host smart-e9fef94e-da87-4c76-9297-c14424152286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578737383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2578737383
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1399376715
Short name T916
Test name
Test status
Simulation time 70402551799 ps
CPU time 165.34 seconds
Started Jul 01 11:51:24 AM PDT 24
Finished Jul 01 11:54:11 AM PDT 24
Peak memory 256912 kb
Host smart-44fb1bc1-2b33-4c8c-ae5c-6837c93a5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399376715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1399376715
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4255181288
Short name T693
Test name
Test status
Simulation time 174448008812 ps
CPU time 241.11 seconds
Started Jul 01 11:51:23 AM PDT 24
Finished Jul 01 11:55:25 AM PDT 24
Peak memory 251392 kb
Host smart-b61b7f8f-ce9d-4823-9767-5b5185d3cb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255181288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4255181288
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2047847303
Short name T436
Test name
Test status
Simulation time 53050062 ps
CPU time 3.62 seconds
Started Jul 01 11:51:31 AM PDT 24
Finished Jul 01 11:51:36 AM PDT 24
Peak memory 233744 kb
Host smart-24379396-6336-43a7-8f04-e2f995fcd943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047847303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2047847303
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1732154973
Short name T956
Test name
Test status
Simulation time 93181030268 ps
CPU time 78.59 seconds
Started Jul 01 11:51:23 AM PDT 24
Finished Jul 01 11:52:43 AM PDT 24
Peak memory 258472 kb
Host smart-c9c8f9e8-6302-49ca-919a-e86079a60416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732154973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1732154973
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3922718461
Short name T361
Test name
Test status
Simulation time 101965581 ps
CPU time 3.46 seconds
Started Jul 01 11:51:24 AM PDT 24
Finished Jul 01 11:51:29 AM PDT 24
Peak memory 225780 kb
Host smart-4a192273-e5c5-47c1-8010-1360df738c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922718461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3922718461
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.313206329
Short name T203
Test name
Test status
Simulation time 10701399783 ps
CPU time 82.3 seconds
Started Jul 01 11:51:26 AM PDT 24
Finished Jul 01 11:52:50 AM PDT 24
Peak memory 251012 kb
Host smart-f05c508c-e3ef-46f3-90e9-aa5dfcb9e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313206329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.313206329
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.282808563
Short name T188
Test name
Test status
Simulation time 1868619424 ps
CPU time 7.67 seconds
Started Jul 01 11:51:23 AM PDT 24
Finished Jul 01 11:51:31 AM PDT 24
Peak memory 225576 kb
Host smart-16870327-c46a-4ac9-8613-8b546b84d40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282808563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.282808563
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2052829155
Short name T42
Test name
Test status
Simulation time 17908935970 ps
CPU time 25.75 seconds
Started Jul 01 11:51:25 AM PDT 24
Finished Jul 01 11:51:52 AM PDT 24
Peak memory 234504 kb
Host smart-67556e66-1cbc-4b48-8d27-e61ce367fca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052829155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2052829155
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1394279884
Short name T574
Test name
Test status
Simulation time 2796979030 ps
CPU time 6.7 seconds
Started Jul 01 11:51:25 AM PDT 24
Finished Jul 01 11:51:33 AM PDT 24
Peak memory 223864 kb
Host smart-502a22a9-1b08-417a-ae9a-fe2725af9623
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1394279884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1394279884
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2370651141
Short name T785
Test name
Test status
Simulation time 6951946368 ps
CPU time 118.1 seconds
Started Jul 01 11:51:24 AM PDT 24
Finished Jul 01 11:53:23 AM PDT 24
Peak memory 250500 kb
Host smart-b1a2c013-e32c-4054-948c-b902fc312f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370651141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2370651141
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3212104697
Short name T31
Test name
Test status
Simulation time 471278143 ps
CPU time 6.27 seconds
Started Jul 01 11:51:18 AM PDT 24
Finished Jul 01 11:51:26 AM PDT 24
Peak memory 217356 kb
Host smart-ad7fafd3-cca9-4f65-8d62-dbc14530f668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212104697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3212104697
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2713218
Short name T933
Test name
Test status
Simulation time 11543994033 ps
CPU time 5.78 seconds
Started Jul 01 11:51:19 AM PDT 24
Finished Jul 01 11:51:26 AM PDT 24
Peak memory 217384 kb
Host smart-1b136076-d6a5-4831-9e6f-e59314fb7f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2713218
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.417765019
Short name T645
Test name
Test status
Simulation time 665264473 ps
CPU time 3.89 seconds
Started Jul 01 11:51:22 AM PDT 24
Finished Jul 01 11:51:27 AM PDT 24
Peak memory 217332 kb
Host smart-d6a49c84-7d46-4159-b8ec-5091fec1b011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417765019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.417765019
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.314184935
Short name T986
Test name
Test status
Simulation time 405081783 ps
CPU time 0.98 seconds
Started Jul 01 11:51:23 AM PDT 24
Finished Jul 01 11:51:25 AM PDT 24
Peak memory 207984 kb
Host smart-2a1044e0-a575-498b-9743-cd6eaa860571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314184935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.314184935
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3614095903
Short name T925
Test name
Test status
Simulation time 12075614909 ps
CPU time 8.41 seconds
Started Jul 01 11:51:24 AM PDT 24
Finished Jul 01 11:51:33 AM PDT 24
Peak memory 241564 kb
Host smart-49341016-7f50-4d58-9767-56b2936b3371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614095903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3614095903
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3045323522
Short name T806
Test name
Test status
Simulation time 14476612 ps
CPU time 0.73 seconds
Started Jul 01 11:51:34 AM PDT 24
Finished Jul 01 11:51:37 AM PDT 24
Peak memory 206296 kb
Host smart-b41bfe7d-2478-4170-819e-106e18f339d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045323522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3045323522
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.701665100
Short name T919
Test name
Test status
Simulation time 234448277 ps
CPU time 2.43 seconds
Started Jul 01 11:51:36 AM PDT 24
Finished Jul 01 11:51:41 AM PDT 24
Peak memory 225496 kb
Host smart-7e818a84-b1fb-48bf-a223-7ebbb22706fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701665100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.701665100
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1490681841
Short name T904
Test name
Test status
Simulation time 32141598 ps
CPU time 0.83 seconds
Started Jul 01 11:51:28 AM PDT 24
Finished Jul 01 11:51:29 AM PDT 24
Peak memory 207840 kb
Host smart-52041bf6-9a4f-46a9-82e8-e59a127b6b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490681841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1490681841
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2955002869
Short name T970
Test name
Test status
Simulation time 28331130391 ps
CPU time 42.19 seconds
Started Jul 01 11:51:35 AM PDT 24
Finished Jul 01 11:52:20 AM PDT 24
Peak memory 253188 kb
Host smart-f9417e8f-deb8-4df3-b9c6-c3f1dc8000f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955002869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2955002869
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4064173037
Short name T286
Test name
Test status
Simulation time 18673279475 ps
CPU time 198.74 seconds
Started Jul 01 11:51:33 AM PDT 24
Finished Jul 01 11:54:54 AM PDT 24
Peak memory 251276 kb
Host smart-799e6227-155d-4394-8de6-796c81977442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064173037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4064173037
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4092824824
Short name T391
Test name
Test status
Simulation time 127632805890 ps
CPU time 153.06 seconds
Started Jul 01 11:51:38 AM PDT 24
Finished Jul 01 11:54:13 AM PDT 24
Peak memory 253604 kb
Host smart-99648648-2896-4536-9853-a6895ae17b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092824824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4092824824
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.969759321
Short name T1000
Test name
Test status
Simulation time 3421362080 ps
CPU time 14.92 seconds
Started Jul 01 11:51:31 AM PDT 24
Finished Jul 01 11:51:47 AM PDT 24
Peak memory 225732 kb
Host smart-a8761776-dd50-4bf0-98c5-300ecf5932dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969759321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.969759321
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1821882107
Short name T172
Test name
Test status
Simulation time 56953292923 ps
CPU time 126.74 seconds
Started Jul 01 11:51:31 AM PDT 24
Finished Jul 01 11:53:39 AM PDT 24
Peak memory 257872 kb
Host smart-c5267882-fd4d-4810-80e5-afa4c86631c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821882107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1821882107
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.208538221
Short name T640
Test name
Test status
Simulation time 66399294 ps
CPU time 2.68 seconds
Started Jul 01 11:51:27 AM PDT 24
Finished Jul 01 11:51:31 AM PDT 24
Peak memory 233804 kb
Host smart-2978bc1f-b641-44a8-9728-2dc1d0f5b19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208538221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.208538221
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1047387299
Short name T1011
Test name
Test status
Simulation time 273135553 ps
CPU time 3.47 seconds
Started Jul 01 11:51:36 AM PDT 24
Finished Jul 01 11:51:42 AM PDT 24
Peak memory 225544 kb
Host smart-9f07d0c3-251c-49f2-aabf-9254c7b83bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047387299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1047387299
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.415055566
Short name T497
Test name
Test status
Simulation time 6240296223 ps
CPU time 18.26 seconds
Started Jul 01 11:51:28 AM PDT 24
Finished Jul 01 11:51:47 AM PDT 24
Peak memory 241632 kb
Host smart-3db68df7-2274-473e-a618-da0525130b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415055566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.415055566
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.383475190
Short name T223
Test name
Test status
Simulation time 312684804 ps
CPU time 4.13 seconds
Started Jul 01 11:51:29 AM PDT 24
Finished Jul 01 11:51:34 AM PDT 24
Peak memory 233832 kb
Host smart-7dec063d-27e4-4424-8bf1-fdc339d91128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383475190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.383475190
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1263983647
Short name T444
Test name
Test status
Simulation time 776350287 ps
CPU time 3.83 seconds
Started Jul 01 11:51:38 AM PDT 24
Finished Jul 01 11:51:44 AM PDT 24
Peak memory 221776 kb
Host smart-14e14720-20b4-41fc-af41-377cafcbf36a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1263983647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1263983647
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.514645067
Short name T957
Test name
Test status
Simulation time 5240684875 ps
CPU time 37.12 seconds
Started Jul 01 11:51:38 AM PDT 24
Finished Jul 01 11:52:17 AM PDT 24
Peak memory 250344 kb
Host smart-74dd5124-cb2f-414e-a19b-686d1b54d65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514645067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.514645067
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.443925083
Short name T914
Test name
Test status
Simulation time 8118299216 ps
CPU time 15.6 seconds
Started Jul 01 11:51:28 AM PDT 24
Finished Jul 01 11:51:45 AM PDT 24
Peak memory 217436 kb
Host smart-c776e5d8-1800-41dc-ba25-27d25e99f0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443925083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.443925083
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.627732449
Short name T340
Test name
Test status
Simulation time 2645930499 ps
CPU time 4.48 seconds
Started Jul 01 11:51:27 AM PDT 24
Finished Jul 01 11:51:33 AM PDT 24
Peak memory 217476 kb
Host smart-755091c1-b103-48cb-ac92-99e13812d487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627732449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.627732449
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2095913275
Short name T864
Test name
Test status
Simulation time 30990665 ps
CPU time 1.05 seconds
Started Jul 01 11:51:30 AM PDT 24
Finished Jul 01 11:51:32 AM PDT 24
Peak memory 208052 kb
Host smart-73096492-c4b0-4e77-9bd9-3479b6895045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095913275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2095913275
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1244110597
Short name T314
Test name
Test status
Simulation time 115204117 ps
CPU time 0.84 seconds
Started Jul 01 11:51:28 AM PDT 24
Finished Jul 01 11:51:30 AM PDT 24
Peak memory 206976 kb
Host smart-ea6eda63-d91c-4a85-93cc-4839900e69e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244110597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1244110597
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2404008282
Short name T833
Test name
Test status
Simulation time 1398270615 ps
CPU time 6.99 seconds
Started Jul 01 11:51:36 AM PDT 24
Finished Jul 01 11:51:45 AM PDT 24
Peak memory 241996 kb
Host smart-651ef23e-29b8-44d6-bd09-a1ca1c265d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404008282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2404008282
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3295486500
Short name T486
Test name
Test status
Simulation time 15456818 ps
CPU time 0.8 seconds
Started Jul 01 11:51:39 AM PDT 24
Finished Jul 01 11:51:43 AM PDT 24
Peak memory 206380 kb
Host smart-9edcc61e-27ca-410e-b9b5-f07883a6bcfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295486500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3295486500
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3108258649
Short name T903
Test name
Test status
Simulation time 892469660 ps
CPU time 3.14 seconds
Started Jul 01 11:51:41 AM PDT 24
Finished Jul 01 11:51:47 AM PDT 24
Peak memory 233708 kb
Host smart-0c8ab093-b486-4cf8-83eb-7f989334d651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108258649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3108258649
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2261876099
Short name T817
Test name
Test status
Simulation time 28632522 ps
CPU time 0.77 seconds
Started Jul 01 11:51:34 AM PDT 24
Finished Jul 01 11:51:37 AM PDT 24
Peak memory 207536 kb
Host smart-9ddaf3c0-d2eb-4c8e-9142-343461c7e155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261876099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2261876099
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2901608767
Short name T728
Test name
Test status
Simulation time 1701150010 ps
CPU time 25.87 seconds
Started Jul 01 11:51:38 AM PDT 24
Finished Jul 01 11:52:06 AM PDT 24
Peak memory 242268 kb
Host smart-5c2f8c8a-ba05-4343-be25-2b7b45ae8334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901608767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2901608767
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3083194186
Short name T910
Test name
Test status
Simulation time 14043928927 ps
CPU time 68.95 seconds
Started Jul 01 11:51:41 AM PDT 24
Finished Jul 01 11:52:52 AM PDT 24
Peak memory 258468 kb
Host smart-ada8cc0f-b3ba-46a0-8c7e-79e72ee9317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083194186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3083194186
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.485984850
Short name T535
Test name
Test status
Simulation time 20054476532 ps
CPU time 145.24 seconds
Started Jul 01 11:51:39 AM PDT 24
Finished Jul 01 11:54:06 AM PDT 24
Peak memory 250796 kb
Host smart-4b277bb9-6297-4bd3-b62f-e0d8c0d71cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485984850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.485984850
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1962317077
Short name T646
Test name
Test status
Simulation time 399458376 ps
CPU time 4.94 seconds
Started Jul 01 11:51:38 AM PDT 24
Finished Jul 01 11:51:45 AM PDT 24
Peak memory 233720 kb
Host smart-6fc72537-6cec-4b96-a90d-44bb9e096100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962317077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1962317077
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1967812504
Short name T410
Test name
Test status
Simulation time 17555154478 ps
CPU time 114.37 seconds
Started Jul 01 11:51:41 AM PDT 24
Finished Jul 01 11:53:38 AM PDT 24
Peak memory 250300 kb
Host smart-726ebfe2-46e9-472a-aeb4-98f2b3e31966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967812504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1967812504
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3062394815
Short name T625
Test name
Test status
Simulation time 582185403 ps
CPU time 5.87 seconds
Started Jul 01 11:51:41 AM PDT 24
Finished Jul 01 11:51:49 AM PDT 24
Peak memory 241532 kb
Host smart-a3450912-909a-48f9-a724-6d14e9f66a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062394815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3062394815
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1666755741
Short name T458
Test name
Test status
Simulation time 2480654242 ps
CPU time 7.16 seconds
Started Jul 01 11:51:38 AM PDT 24
Finished Jul 01 11:51:47 AM PDT 24
Peak memory 228388 kb
Host smart-25764ba6-28f0-4b85-8031-523bb97579b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666755741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1666755741
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1836924529
Short name T490
Test name
Test status
Simulation time 1899370494 ps
CPU time 6.91 seconds
Started Jul 01 11:51:34 AM PDT 24
Finished Jul 01 11:51:42 AM PDT 24
Peak memory 233748 kb
Host smart-2884ff5c-7af3-489e-a4f9-70237721b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836924529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1836924529
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2089144883
Short name T24
Test name
Test status
Simulation time 1266030062 ps
CPU time 12.96 seconds
Started Jul 01 11:51:42 AM PDT 24
Finished Jul 01 11:51:57 AM PDT 24
Peak memory 220164 kb
Host smart-676c9044-8161-412c-8799-66bfb7ac8c63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2089144883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2089144883
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3938107464
Short name T555
Test name
Test status
Simulation time 28834631902 ps
CPU time 257.77 seconds
Started Jul 01 11:51:40 AM PDT 24
Finished Jul 01 11:56:01 AM PDT 24
Peak memory 255964 kb
Host smart-f74d869f-0637-458b-aae2-075779c5007e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938107464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3938107464
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1752337710
Short name T341
Test name
Test status
Simulation time 57321263 ps
CPU time 0.71 seconds
Started Jul 01 11:51:34 AM PDT 24
Finished Jul 01 11:51:37 AM PDT 24
Peak memory 206636 kb
Host smart-f04c827c-b429-4954-87a4-734a93252824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752337710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1752337710
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.313386406
Short name T4
Test name
Test status
Simulation time 12560704 ps
CPU time 0.71 seconds
Started Jul 01 11:51:34 AM PDT 24
Finished Jul 01 11:51:36 AM PDT 24
Peak memory 206636 kb
Host smart-9357016f-dd69-4f70-be7f-417a0aa25016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313386406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.313386406
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4040727590
Short name T992
Test name
Test status
Simulation time 25837614 ps
CPU time 0.88 seconds
Started Jul 01 11:51:35 AM PDT 24
Finished Jul 01 11:51:38 AM PDT 24
Peak memory 206996 kb
Host smart-53261e7e-78eb-414c-9e0d-40d35aac615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040727590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4040727590
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.931230336
Short name T1014
Test name
Test status
Simulation time 58256417 ps
CPU time 0.8 seconds
Started Jul 01 11:51:34 AM PDT 24
Finished Jul 01 11:51:36 AM PDT 24
Peak memory 206988 kb
Host smart-7e8f6158-287f-437d-9c16-e290bf6c804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931230336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.931230336
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4099739333
Short name T680
Test name
Test status
Simulation time 11925925860 ps
CPU time 18.98 seconds
Started Jul 01 11:51:40 AM PDT 24
Finished Jul 01 11:52:02 AM PDT 24
Peak memory 225700 kb
Host smart-2f9fc74d-b029-480b-8825-bad21810ec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099739333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4099739333
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3357087943
Short name T461
Test name
Test status
Simulation time 25988970 ps
CPU time 0.77 seconds
Started Jul 01 11:51:47 AM PDT 24
Finished Jul 01 11:51:50 AM PDT 24
Peak memory 206276 kb
Host smart-8a8b9786-f535-4c30-aa64-d9645bd50a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357087943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3357087943
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3060380874
Short name T688
Test name
Test status
Simulation time 114600207 ps
CPU time 2.37 seconds
Started Jul 01 11:51:45 AM PDT 24
Finished Jul 01 11:51:49 AM PDT 24
Peak memory 233344 kb
Host smart-72eb9311-2ec1-4080-b7cd-f20d97e0e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060380874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3060380874
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2764083798
Short name T422
Test name
Test status
Simulation time 72211597 ps
CPU time 0.8 seconds
Started Jul 01 11:51:38 AM PDT 24
Finished Jul 01 11:51:41 AM PDT 24
Peak memory 207460 kb
Host smart-c5a35b09-f57b-45f4-98e7-342687acfc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764083798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2764083798
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.646353744
Short name T202
Test name
Test status
Simulation time 80129989864 ps
CPU time 555.6 seconds
Started Jul 01 11:51:45 AM PDT 24
Finished Jul 01 12:01:02 PM PDT 24
Peak memory 264896 kb
Host smart-0dab95e9-0b68-4faa-bb0f-266610ba8ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646353744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.646353744
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1458323674
Short name T940
Test name
Test status
Simulation time 251469787102 ps
CPU time 270.62 seconds
Started Jul 01 11:51:46 AM PDT 24
Finished Jul 01 11:56:18 AM PDT 24
Peak memory 266008 kb
Host smart-77d08310-bbf6-4a54-98cc-29d502ab3db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458323674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1458323674
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2574332913
Short name T6
Test name
Test status
Simulation time 1302865848 ps
CPU time 17.64 seconds
Started Jul 01 11:51:46 AM PDT 24
Finished Jul 01 11:52:05 AM PDT 24
Peak memory 235532 kb
Host smart-2ec749bf-02a9-4e29-9ce8-9fb614edd01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574332913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2574332913
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3677754616
Short name T348
Test name
Test status
Simulation time 3665480981 ps
CPU time 29.52 seconds
Started Jul 01 11:51:46 AM PDT 24
Finished Jul 01 11:52:17 AM PDT 24
Peak memory 253712 kb
Host smart-b64cf0b7-ced3-4634-89c6-b32ffcf8086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677754616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3677754616
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3805160239
Short name T215
Test name
Test status
Simulation time 397532927 ps
CPU time 4.21 seconds
Started Jul 01 11:51:44 AM PDT 24
Finished Jul 01 11:51:50 AM PDT 24
Peak memory 225528 kb
Host smart-9a8989b5-1d6d-4ca0-99c1-45e05bf64d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805160239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3805160239
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2715747351
Short name T307
Test name
Test status
Simulation time 5616998823 ps
CPU time 12.57 seconds
Started Jul 01 11:51:45 AM PDT 24
Finished Jul 01 11:51:59 AM PDT 24
Peak memory 225716 kb
Host smart-ca6101fd-a1b3-4b83-be60-a1cff9249b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715747351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2715747351
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3806769364
Short name T737
Test name
Test status
Simulation time 621848232 ps
CPU time 5.58 seconds
Started Jul 01 11:51:48 AM PDT 24
Finished Jul 01 11:51:55 AM PDT 24
Peak memory 233812 kb
Host smart-609b30b5-01c7-45fd-82a1-c0772508d634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806769364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3806769364
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1081997340
Short name T351
Test name
Test status
Simulation time 694588557 ps
CPU time 2.6 seconds
Started Jul 01 11:51:45 AM PDT 24
Finished Jul 01 11:51:49 AM PDT 24
Peak memory 225536 kb
Host smart-2d90de02-edc9-4125-a285-7adf48074480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081997340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1081997340
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3493765232
Short name T7
Test name
Test status
Simulation time 241649948 ps
CPU time 4.44 seconds
Started Jul 01 11:51:44 AM PDT 24
Finished Jul 01 11:51:50 AM PDT 24
Peak memory 224132 kb
Host smart-3499d68d-d229-4f2f-8ca6-80ef719c2121
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3493765232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3493765232
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2989945419
Short name T809
Test name
Test status
Simulation time 4236280211 ps
CPU time 53.54 seconds
Started Jul 01 11:51:44 AM PDT 24
Finished Jul 01 11:52:39 AM PDT 24
Peak memory 258576 kb
Host smart-ee824924-daa6-4d7b-8468-6af333c18045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989945419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2989945419
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1230988734
Short name T297
Test name
Test status
Simulation time 4826665507 ps
CPU time 27.41 seconds
Started Jul 01 11:51:42 AM PDT 24
Finished Jul 01 11:52:12 AM PDT 24
Peak memory 217604 kb
Host smart-0ee7ed0b-d31b-4cd4-9b47-3362f375679c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230988734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1230988734
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4032687257
Short name T385
Test name
Test status
Simulation time 1098125889 ps
CPU time 5.26 seconds
Started Jul 01 11:51:38 AM PDT 24
Finished Jul 01 11:51:46 AM PDT 24
Peak memory 217332 kb
Host smart-f60ef82e-859c-463a-a263-842d74e47951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032687257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4032687257
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4215542251
Short name T488
Test name
Test status
Simulation time 148415071 ps
CPU time 1.41 seconds
Started Jul 01 11:51:40 AM PDT 24
Finished Jul 01 11:51:45 AM PDT 24
Peak memory 217376 kb
Host smart-faae4b9a-d764-4e98-832a-cc81d02d9724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215542251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4215542251
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.425277126
Short name T298
Test name
Test status
Simulation time 49925397 ps
CPU time 0.84 seconds
Started Jul 01 11:51:38 AM PDT 24
Finished Jul 01 11:51:41 AM PDT 24
Peak memory 206968 kb
Host smart-de3af0bf-c17d-4231-83f1-bfb24c676d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425277126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.425277126
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3641270999
Short name T409
Test name
Test status
Simulation time 14673102711 ps
CPU time 14.18 seconds
Started Jul 01 11:51:45 AM PDT 24
Finished Jul 01 11:52:01 AM PDT 24
Peak memory 233912 kb
Host smart-61499792-8c62-4cf8-a154-c76035a56764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641270999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3641270999
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4115338952
Short name T378
Test name
Test status
Simulation time 14427910 ps
CPU time 0.74 seconds
Started Jul 01 11:51:57 AM PDT 24
Finished Jul 01 11:51:59 AM PDT 24
Peak memory 206404 kb
Host smart-2c5cc314-f0fc-427d-9f4b-ca28355553ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115338952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4115338952
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.399242501
Short name T414
Test name
Test status
Simulation time 1040227105 ps
CPU time 6.4 seconds
Started Jul 01 11:51:49 AM PDT 24
Finished Jul 01 11:51:57 AM PDT 24
Peak memory 225508 kb
Host smart-2456fe05-ea2d-4356-a0fc-e0f10a40612e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399242501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.399242501
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.320557581
Short name T777
Test name
Test status
Simulation time 19178927 ps
CPU time 0.75 seconds
Started Jul 01 11:51:48 AM PDT 24
Finished Jul 01 11:51:51 AM PDT 24
Peak memory 206488 kb
Host smart-29247387-fc5f-402c-91bb-64a1e2038ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320557581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.320557581
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3976620961
Short name T675
Test name
Test status
Simulation time 4315904284 ps
CPU time 58.94 seconds
Started Jul 01 11:51:48 AM PDT 24
Finished Jul 01 11:52:49 AM PDT 24
Peak memory 250180 kb
Host smart-2807e2f4-c2e7-4b2e-a632-ffd9283c3c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976620961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3976620961
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.755548087
Short name T1027
Test name
Test status
Simulation time 95094171625 ps
CPU time 59.64 seconds
Started Jul 01 11:51:50 AM PDT 24
Finished Jul 01 11:52:52 AM PDT 24
Peak memory 224956 kb
Host smart-cfdc6473-8c9c-4691-9bf6-b530cdbe1a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755548087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.755548087
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1702470334
Short name T954
Test name
Test status
Simulation time 8205148526 ps
CPU time 73.52 seconds
Started Jul 01 11:51:50 AM PDT 24
Finished Jul 01 11:53:05 AM PDT 24
Peak memory 250412 kb
Host smart-dceec92b-13d4-4db6-a197-310a91819b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702470334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1702470334
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3010215193
Short name T387
Test name
Test status
Simulation time 488922161 ps
CPU time 6.76 seconds
Started Jul 01 11:51:50 AM PDT 24
Finished Jul 01 11:51:58 AM PDT 24
Peak memory 235012 kb
Host smart-60da5b81-d731-4c17-b884-9b486c7503cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010215193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3010215193
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3774503850
Short name T844
Test name
Test status
Simulation time 23443981203 ps
CPU time 244.73 seconds
Started Jul 01 11:51:50 AM PDT 24
Finished Jul 01 11:55:57 AM PDT 24
Peak memory 266044 kb
Host smart-3339d7f3-8d55-434d-8a14-7c7cfc3e1f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774503850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3774503850
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1018786146
Short name T703
Test name
Test status
Simulation time 497106301 ps
CPU time 6.74 seconds
Started Jul 01 11:51:49 AM PDT 24
Finished Jul 01 11:51:58 AM PDT 24
Peak memory 225552 kb
Host smart-cc334846-7743-4c3a-b6db-1b98995c0d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018786146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1018786146
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.726493673
Short name T536
Test name
Test status
Simulation time 92956820 ps
CPU time 2.22 seconds
Started Jul 01 11:51:48 AM PDT 24
Finished Jul 01 11:51:52 AM PDT 24
Peak memory 225504 kb
Host smart-3259c153-7284-4f26-9ccf-9c00f5bddc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726493673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.726493673
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3863245654
Short name T742
Test name
Test status
Simulation time 3962726873 ps
CPU time 13.84 seconds
Started Jul 01 11:51:50 AM PDT 24
Finished Jul 01 11:52:06 AM PDT 24
Peak memory 233868 kb
Host smart-2c3cf83a-35c3-48f4-b16d-8e8d0ec3d465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863245654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3863245654
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3168899988
Short name T606
Test name
Test status
Simulation time 7489238584 ps
CPU time 21.08 seconds
Started Jul 01 11:51:51 AM PDT 24
Finished Jul 01 11:52:13 AM PDT 24
Peak memory 242044 kb
Host smart-573e352a-299c-4b10-baee-6674d01a5aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168899988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3168899988
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2860482874
Short name T521
Test name
Test status
Simulation time 2090567414 ps
CPU time 4.62 seconds
Started Jul 01 11:51:51 AM PDT 24
Finished Jul 01 11:51:57 AM PDT 24
Peak memory 223652 kb
Host smart-515fb3a0-3d3c-451a-99e2-5fad48339c25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2860482874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2860482874
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3475473174
Short name T133
Test name
Test status
Simulation time 47107420403 ps
CPU time 438.53 seconds
Started Jul 01 11:52:00 AM PDT 24
Finished Jul 01 11:59:20 AM PDT 24
Peak memory 268876 kb
Host smart-40f8b232-cc67-41d4-b49f-81b70cd345d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475473174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3475473174
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3401104473
Short name T292
Test name
Test status
Simulation time 85656197819 ps
CPU time 32.6 seconds
Started Jul 01 11:51:43 AM PDT 24
Finished Jul 01 11:52:18 AM PDT 24
Peak memory 217672 kb
Host smart-5532a14f-f010-4a4e-a681-f8419f61aa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401104473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3401104473
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.935600709
Short name T435
Test name
Test status
Simulation time 282085111 ps
CPU time 1.62 seconds
Started Jul 01 11:51:47 AM PDT 24
Finished Jul 01 11:51:50 AM PDT 24
Peak memory 208852 kb
Host smart-34ba5dfa-7472-4076-b3e3-7c83d8917abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935600709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.935600709
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3059848072
Short name T404
Test name
Test status
Simulation time 604348318 ps
CPU time 2.38 seconds
Started Jul 01 11:51:49 AM PDT 24
Finished Jul 01 11:51:53 AM PDT 24
Peak memory 217328 kb
Host smart-f60dd29b-d157-4578-99ef-104bbee0a01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059848072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3059848072
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3633802645
Short name T447
Test name
Test status
Simulation time 185772434 ps
CPU time 0.86 seconds
Started Jul 01 11:51:46 AM PDT 24
Finished Jul 01 11:51:48 AM PDT 24
Peak memory 206996 kb
Host smart-3cc727c5-164e-41f1-8af5-c2f53dcd40ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633802645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3633802645
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.347045092
Short name T429
Test name
Test status
Simulation time 79345156 ps
CPU time 3.79 seconds
Started Jul 01 11:51:50 AM PDT 24
Finished Jul 01 11:51:56 AM PDT 24
Peak memory 233752 kb
Host smart-9204e9a9-1b97-4a30-8bd9-a768ec999575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347045092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.347045092
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3363938295
Short name T653
Test name
Test status
Simulation time 40819917 ps
CPU time 0.76 seconds
Started Jul 01 11:51:59 AM PDT 24
Finished Jul 01 11:52:01 AM PDT 24
Peak memory 205820 kb
Host smart-477fa112-1fe6-46ec-8acb-d452f74e20a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363938295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3363938295
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1921769268
Short name T915
Test name
Test status
Simulation time 1488500468 ps
CPU time 7.28 seconds
Started Jul 01 11:51:54 AM PDT 24
Finished Jul 01 11:52:02 AM PDT 24
Peak memory 233712 kb
Host smart-8e169258-7d2e-462f-b324-0d0822a11191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921769268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1921769268
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3253671048
Short name T465
Test name
Test status
Simulation time 46414051 ps
CPU time 0.81 seconds
Started Jul 01 11:51:54 AM PDT 24
Finished Jul 01 11:51:56 AM PDT 24
Peak memory 207540 kb
Host smart-95443acb-88c9-41b8-81ef-8020c3af3935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253671048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3253671048
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2511673844
Short name T654
Test name
Test status
Simulation time 8146200174 ps
CPU time 33.83 seconds
Started Jul 01 11:51:54 AM PDT 24
Finished Jul 01 11:52:29 AM PDT 24
Peak memory 239964 kb
Host smart-62dce06d-37a1-4069-9893-1db0eb5a9554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511673844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2511673844
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.4238912479
Short name T684
Test name
Test status
Simulation time 8593039580 ps
CPU time 48.77 seconds
Started Jul 01 11:52:01 AM PDT 24
Finished Jul 01 11:52:51 AM PDT 24
Peak memory 253708 kb
Host smart-c8eb2700-7b8d-4132-b9e5-8f50ccdd36fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238912479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.4238912479
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.401704714
Short name T972
Test name
Test status
Simulation time 4330341330 ps
CPU time 26.26 seconds
Started Jul 01 11:51:56 AM PDT 24
Finished Jul 01 11:52:23 AM PDT 24
Peak memory 236332 kb
Host smart-acf54e7c-7411-42e0-b2ed-7e82c71adaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401704714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.401704714
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.4047382914
Short name T439
Test name
Test status
Simulation time 3318953921 ps
CPU time 15.23 seconds
Started Jul 01 11:51:55 AM PDT 24
Finished Jul 01 11:52:11 AM PDT 24
Peak memory 235900 kb
Host smart-44f65040-0cd9-4deb-a1c8-4606e7888680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047382914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.4047382914
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2432601798
Short name T909
Test name
Test status
Simulation time 1879805640 ps
CPU time 13.15 seconds
Started Jul 01 11:51:57 AM PDT 24
Finished Jul 01 11:52:12 AM PDT 24
Peak memory 233708 kb
Host smart-97f3b1d4-87c7-49a9-b9e0-a2bf89a1ea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432601798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2432601798
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1364413869
Short name T234
Test name
Test status
Simulation time 7148552294 ps
CPU time 6.72 seconds
Started Jul 01 11:51:57 AM PDT 24
Finished Jul 01 11:52:04 AM PDT 24
Peak memory 225592 kb
Host smart-ae79cdf0-5f25-469f-9eb0-5f55c64371ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364413869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1364413869
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3839669587
Short name T571
Test name
Test status
Simulation time 10964211169 ps
CPU time 9.62 seconds
Started Jul 01 11:51:56 AM PDT 24
Finished Jul 01 11:52:06 AM PDT 24
Peak memory 225808 kb
Host smart-61fc841c-96d7-4ce1-b970-af724839cece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839669587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3839669587
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.253837511
Short name T240
Test name
Test status
Simulation time 1599271483 ps
CPU time 3.33 seconds
Started Jul 01 11:51:54 AM PDT 24
Finished Jul 01 11:51:58 AM PDT 24
Peak memory 233680 kb
Host smart-6581bc88-6fec-4555-bc05-cb3462e1d61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253837511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.253837511
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4068578878
Short name T764
Test name
Test status
Simulation time 137035885 ps
CPU time 3.24 seconds
Started Jul 01 11:51:53 AM PDT 24
Finished Jul 01 11:51:58 AM PDT 24
Peak memory 219696 kb
Host smart-e65ff11a-cb46-47c1-874c-693bd92e1fe2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4068578878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4068578878
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2254233113
Short name T159
Test name
Test status
Simulation time 1403068586 ps
CPU time 32.46 seconds
Started Jul 01 11:52:01 AM PDT 24
Finished Jul 01 11:52:35 AM PDT 24
Peak memory 250276 kb
Host smart-fe6e601b-e831-4f61-ae1e-551f230f248c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254233113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2254233113
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.998079234
Short name T295
Test name
Test status
Simulation time 7771672074 ps
CPU time 11.15 seconds
Started Jul 01 11:51:55 AM PDT 24
Finished Jul 01 11:52:07 AM PDT 24
Peak memory 217444 kb
Host smart-1c55345d-1e9b-4e5f-809d-c37aac514de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998079234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.998079234
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1594353274
Short name T583
Test name
Test status
Simulation time 1295865337 ps
CPU time 2.83 seconds
Started Jul 01 11:51:57 AM PDT 24
Finished Jul 01 11:52:02 AM PDT 24
Peak memory 217376 kb
Host smart-470695cb-ee84-4ff9-a9a6-7a381e04db82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594353274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1594353274
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1330301559
Short name T30
Test name
Test status
Simulation time 60417186 ps
CPU time 1.51 seconds
Started Jul 01 11:51:57 AM PDT 24
Finished Jul 01 11:52:00 AM PDT 24
Peak memory 217404 kb
Host smart-d14688f5-1fba-4d47-860e-15bef2eab438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330301559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1330301559
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2618672741
Short name T985
Test name
Test status
Simulation time 83231406 ps
CPU time 0.97 seconds
Started Jul 01 11:51:57 AM PDT 24
Finished Jul 01 11:52:00 AM PDT 24
Peak memory 208068 kb
Host smart-a8120e64-c4f6-4680-bca5-bceea764b572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618672741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2618672741
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.481179959
Short name T403
Test name
Test status
Simulation time 7027620260 ps
CPU time 14.44 seconds
Started Jul 01 11:51:57 AM PDT 24
Finished Jul 01 11:52:13 AM PDT 24
Peak memory 233864 kb
Host smart-4896c42b-9aa5-48bc-b800-feba9b9d2572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481179959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.481179959
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.383441344
Short name T474
Test name
Test status
Simulation time 37098285 ps
CPU time 0.78 seconds
Started Jul 01 11:52:08 AM PDT 24
Finished Jul 01 11:52:10 AM PDT 24
Peak memory 206388 kb
Host smart-dd28703d-788e-4ca2-aa6a-7de94a391a6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383441344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.383441344
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3935710375
Short name T597
Test name
Test status
Simulation time 85084984 ps
CPU time 2.64 seconds
Started Jul 01 11:52:06 AM PDT 24
Finished Jul 01 11:52:10 AM PDT 24
Peak memory 233728 kb
Host smart-cb724fb2-62e6-403a-bb9d-aefaaff14659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935710375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3935710375
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.908754702
Short name T330
Test name
Test status
Simulation time 82485208 ps
CPU time 0.85 seconds
Started Jul 01 11:52:03 AM PDT 24
Finished Jul 01 11:52:05 AM PDT 24
Peak memory 207512 kb
Host smart-06c80fb2-6ff8-4e99-862a-6dbfd9c60589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908754702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.908754702
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.4280109554
Short name T965
Test name
Test status
Simulation time 11409991302 ps
CPU time 100.51 seconds
Started Jul 01 11:52:08 AM PDT 24
Finished Jul 01 11:53:49 AM PDT 24
Peak memory 250300 kb
Host smart-21aeac09-5a39-4074-abf3-f63f567bdc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280109554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.4280109554
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1472640677
Short name T604
Test name
Test status
Simulation time 3019085206 ps
CPU time 39.58 seconds
Started Jul 01 11:52:09 AM PDT 24
Finished Jul 01 11:52:49 AM PDT 24
Peak memory 241008 kb
Host smart-055b8443-7604-4901-b8be-5e02ba355077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472640677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1472640677
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2295994945
Short name T663
Test name
Test status
Simulation time 140280391157 ps
CPU time 198.45 seconds
Started Jul 01 11:52:06 AM PDT 24
Finished Jul 01 11:55:26 AM PDT 24
Peak memory 250320 kb
Host smart-82477670-b60e-4e28-ad7e-557bb0717a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295994945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2295994945
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2145821636
Short name T113
Test name
Test status
Simulation time 337303200 ps
CPU time 4.83 seconds
Started Jul 01 11:52:06 AM PDT 24
Finished Jul 01 11:52:12 AM PDT 24
Peak memory 234532 kb
Host smart-045ba72d-a63a-453d-9a74-66e96792c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145821636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2145821636
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.260244386
Short name T213
Test name
Test status
Simulation time 15073628782 ps
CPU time 38.86 seconds
Started Jul 01 11:52:13 AM PDT 24
Finished Jul 01 11:52:54 AM PDT 24
Peak memory 225692 kb
Host smart-1f67c9ff-d338-48e0-ad71-8e1d4227b7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260244386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.260244386
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3565016412
Short name T582
Test name
Test status
Simulation time 11373673302 ps
CPU time 22.81 seconds
Started Jul 01 11:52:00 AM PDT 24
Finished Jul 01 11:52:24 AM PDT 24
Peak memory 233876 kb
Host smart-7123c43d-8f0e-492f-b2ac-116c9db6d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565016412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3565016412
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3785621278
Short name T191
Test name
Test status
Simulation time 7752352389 ps
CPU time 66.38 seconds
Started Jul 01 11:52:05 AM PDT 24
Finished Jul 01 11:53:12 AM PDT 24
Peak memory 233840 kb
Host smart-7498450a-9a8f-4956-a602-99c32dd706e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785621278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3785621278
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3171658578
Short name T783
Test name
Test status
Simulation time 114589141083 ps
CPU time 33.82 seconds
Started Jul 01 11:52:01 AM PDT 24
Finished Jul 01 11:52:37 AM PDT 24
Peak memory 233224 kb
Host smart-ef116371-2a14-4284-aacc-03b17dbe30f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171658578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3171658578
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.353108288
Short name T11
Test name
Test status
Simulation time 82188546 ps
CPU time 2.2 seconds
Started Jul 01 11:52:00 AM PDT 24
Finished Jul 01 11:52:03 AM PDT 24
Peak memory 225560 kb
Host smart-c6915945-f138-4dd9-98a1-8d3593f0d660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353108288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.353108288
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2534778361
Short name T602
Test name
Test status
Simulation time 6091854543 ps
CPU time 18.41 seconds
Started Jul 01 11:52:06 AM PDT 24
Finished Jul 01 11:52:26 AM PDT 24
Peak memory 221684 kb
Host smart-fb32c25b-0903-4a42-a1ac-373de06d0785
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2534778361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2534778361
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2201075726
Short name T673
Test name
Test status
Simulation time 2134776846 ps
CPU time 31.74 seconds
Started Jul 01 11:52:07 AM PDT 24
Finished Jul 01 11:52:40 AM PDT 24
Peak memory 242108 kb
Host smart-2acd1ffd-e7d3-4c64-83a8-2a54b5838d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201075726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2201075726
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.194033802
Short name T609
Test name
Test status
Simulation time 1353954390 ps
CPU time 10.61 seconds
Started Jul 01 11:52:00 AM PDT 24
Finished Jul 01 11:52:12 AM PDT 24
Peak memory 217492 kb
Host smart-0627297d-4ec3-40ba-8e73-cda56abf3317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194033802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.194033802
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1589012619
Short name T881
Test name
Test status
Simulation time 12012394530 ps
CPU time 6.07 seconds
Started Jul 01 11:52:02 AM PDT 24
Finished Jul 01 11:52:09 AM PDT 24
Peak memory 217496 kb
Host smart-7b6106a5-bccf-47d3-b0da-5cd20c6e4d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589012619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1589012619
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4007184080
Short name T971
Test name
Test status
Simulation time 60827891 ps
CPU time 1.23 seconds
Started Jul 01 11:52:00 AM PDT 24
Finished Jul 01 11:52:03 AM PDT 24
Peak memory 217416 kb
Host smart-763b61f6-d266-4bf4-ab6a-3426b0799821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007184080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4007184080
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1363402709
Short name T33
Test name
Test status
Simulation time 48830893 ps
CPU time 0.73 seconds
Started Jul 01 11:52:00 AM PDT 24
Finished Jul 01 11:52:02 AM PDT 24
Peak memory 206936 kb
Host smart-c5921667-0b2b-43eb-83da-1bea6629902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363402709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1363402709
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.655277905
Short name T671
Test name
Test status
Simulation time 2317296893 ps
CPU time 3.88 seconds
Started Jul 01 11:52:05 AM PDT 24
Finished Jul 01 11:52:10 AM PDT 24
Peak memory 233864 kb
Host smart-61dab0de-34e2-4e1e-bade-4fcf6d770070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655277905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.655277905
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4243076769
Short name T450
Test name
Test status
Simulation time 14292274 ps
CPU time 0.75 seconds
Started Jul 01 11:52:10 AM PDT 24
Finished Jul 01 11:52:13 AM PDT 24
Peak memory 206312 kb
Host smart-e6958c83-1ed0-433e-88ae-b0de472b4a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243076769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4243076769
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2409520882
Short name T639
Test name
Test status
Simulation time 3730796776 ps
CPU time 10.07 seconds
Started Jul 01 11:52:11 AM PDT 24
Finished Jul 01 11:52:22 AM PDT 24
Peak memory 225696 kb
Host smart-a8302598-929b-4a35-920d-ae04171da160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409520882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2409520882
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.676932419
Short name T384
Test name
Test status
Simulation time 16060824 ps
CPU time 0.81 seconds
Started Jul 01 11:52:08 AM PDT 24
Finished Jul 01 11:52:10 AM PDT 24
Peak memory 207840 kb
Host smart-03d3f284-7310-4d5c-83b7-a902cf691b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676932419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.676932419
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3339613315
Short name T523
Test name
Test status
Simulation time 372114072901 ps
CPU time 240.15 seconds
Started Jul 01 11:52:16 AM PDT 24
Finished Jul 01 11:56:18 AM PDT 24
Peak memory 254828 kb
Host smart-dff7c8f1-4354-4578-bf0b-6046a8a84551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339613315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3339613315
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4135836461
Short name T249
Test name
Test status
Simulation time 23331330145 ps
CPU time 180.83 seconds
Started Jul 01 11:52:12 AM PDT 24
Finished Jul 01 11:55:14 AM PDT 24
Peak memory 269052 kb
Host smart-d8220121-f350-42c0-9825-1f9c85b2ab24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135836461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4135836461
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4106160302
Short name T276
Test name
Test status
Simulation time 2518306425 ps
CPU time 15.82 seconds
Started Jul 01 11:52:12 AM PDT 24
Finished Jul 01 11:52:30 AM PDT 24
Peak memory 225912 kb
Host smart-ca6d56eb-867d-4da0-bd71-ff7d31028f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106160302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4106160302
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3884745499
Short name T423
Test name
Test status
Simulation time 52858283 ps
CPU time 0.82 seconds
Started Jul 01 11:52:11 AM PDT 24
Finished Jul 01 11:52:14 AM PDT 24
Peak memory 216912 kb
Host smart-6cc2fc6a-1f1a-4368-ae67-5452bdd2304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884745499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3884745499
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.660006702
Short name T302
Test name
Test status
Simulation time 377027356 ps
CPU time 2.36 seconds
Started Jul 01 11:52:16 AM PDT 24
Finished Jul 01 11:52:20 AM PDT 24
Peak memory 224016 kb
Host smart-8e803982-4edb-41a1-b63a-99ec7fa66da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660006702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.660006702
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.177396037
Short name T1008
Test name
Test status
Simulation time 1750751836 ps
CPU time 9.29 seconds
Started Jul 01 11:52:11 AM PDT 24
Finished Jul 01 11:52:22 AM PDT 24
Peak memory 225524 kb
Host smart-3f22e02b-dfb5-4224-a648-0f4ae3293ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177396037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.177396037
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2603690158
Short name T510
Test name
Test status
Simulation time 4499556397 ps
CPU time 4.82 seconds
Started Jul 01 11:52:10 AM PDT 24
Finished Jul 01 11:52:16 AM PDT 24
Peak memory 233864 kb
Host smart-a33713b7-9009-450a-a3d6-4f76893eadc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603690158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2603690158
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2601347987
Short name T90
Test name
Test status
Simulation time 1519428206 ps
CPU time 9.18 seconds
Started Jul 01 11:52:05 AM PDT 24
Finished Jul 01 11:52:16 AM PDT 24
Peak memory 241220 kb
Host smart-7505a11b-5a7a-49c5-be15-4fd549a84352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601347987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2601347987
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2790390476
Short name T369
Test name
Test status
Simulation time 7665945066 ps
CPU time 20.96 seconds
Started Jul 01 11:52:11 AM PDT 24
Finished Jul 01 11:52:34 AM PDT 24
Peak memory 223504 kb
Host smart-84635403-510d-4c9b-a764-dd6d3a678689
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2790390476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2790390476
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.655023064
Short name T818
Test name
Test status
Simulation time 145682352 ps
CPU time 0.99 seconds
Started Jul 01 11:52:11 AM PDT 24
Finished Jul 01 11:52:14 AM PDT 24
Peak memory 207908 kb
Host smart-1b3e2019-2f7d-42b8-876f-fc36be6a9293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655023064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.655023064
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2403851190
Short name T796
Test name
Test status
Simulation time 7061247481 ps
CPU time 33.02 seconds
Started Jul 01 11:52:05 AM PDT 24
Finished Jul 01 11:52:40 AM PDT 24
Peak memory 220992 kb
Host smart-ba3be942-3cee-4d7d-bddb-8534e5c3156e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403851190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2403851190
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1673332749
Short name T725
Test name
Test status
Simulation time 3398296137 ps
CPU time 4.55 seconds
Started Jul 01 11:52:06 AM PDT 24
Finished Jul 01 11:52:11 AM PDT 24
Peak memory 217516 kb
Host smart-39b7e90d-7d17-4f0f-8d52-9986cdf02f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673332749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1673332749
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.638996120
Short name T649
Test name
Test status
Simulation time 1605143662 ps
CPU time 5.16 seconds
Started Jul 01 11:52:05 AM PDT 24
Finished Jul 01 11:52:12 AM PDT 24
Peak memory 217516 kb
Host smart-47731364-30b8-4633-a49d-448bdeed5df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638996120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.638996120
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.619343104
Short name T628
Test name
Test status
Simulation time 70754973 ps
CPU time 0.9 seconds
Started Jul 01 11:52:05 AM PDT 24
Finished Jul 01 11:52:07 AM PDT 24
Peak memory 207212 kb
Host smart-7ae25de0-405b-4c53-a56d-13018bd7e68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619343104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.619343104
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3017923458
Short name T803
Test name
Test status
Simulation time 3057963309 ps
CPU time 7.2 seconds
Started Jul 01 11:52:13 AM PDT 24
Finished Jul 01 11:52:22 AM PDT 24
Peak memory 239504 kb
Host smart-d4196eda-db0d-4871-b041-7972ce694b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017923458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3017923458
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3519554540
Short name T843
Test name
Test status
Simulation time 19679477 ps
CPU time 0.73 seconds
Started Jul 01 11:52:15 AM PDT 24
Finished Jul 01 11:52:17 AM PDT 24
Peak memory 206404 kb
Host smart-1fc121ac-00b9-40c1-bf2c-79c9a0a1cb82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519554540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3519554540
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.442590867
Short name T697
Test name
Test status
Simulation time 2195826697 ps
CPU time 6.04 seconds
Started Jul 01 11:52:16 AM PDT 24
Finished Jul 01 11:52:24 AM PDT 24
Peak memory 233920 kb
Host smart-b95a3cce-de09-4cf2-a5dd-db653e2cc8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442590867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.442590867
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1744194292
Short name T996
Test name
Test status
Simulation time 102746849 ps
CPU time 0.73 seconds
Started Jul 01 11:52:11 AM PDT 24
Finished Jul 01 11:52:14 AM PDT 24
Peak memory 206468 kb
Host smart-c6307e91-2901-42db-86c9-79e3fb8dbce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744194292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1744194292
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.251750479
Short name T40
Test name
Test status
Simulation time 9484799199 ps
CPU time 85.76 seconds
Started Jul 01 11:52:15 AM PDT 24
Finished Jul 01 11:53:43 AM PDT 24
Peak memory 250312 kb
Host smart-450b755b-7adc-48a8-bc49-0301b64b1256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251750479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.251750479
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2982260711
Short name T174
Test name
Test status
Simulation time 48228288899 ps
CPU time 313.91 seconds
Started Jul 01 11:52:14 AM PDT 24
Finished Jul 01 11:57:29 AM PDT 24
Peak memory 266996 kb
Host smart-15ed09c4-6e5d-474f-ad18-7f20ce845388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982260711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2982260711
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.955405551
Short name T278
Test name
Test status
Simulation time 1321801337 ps
CPU time 22.64 seconds
Started Jul 01 11:52:14 AM PDT 24
Finished Jul 01 11:52:38 AM PDT 24
Peak memory 241628 kb
Host smart-595e6cc9-f2b2-48d1-825c-5573bcafe679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955405551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.955405551
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2716893229
Short name T55
Test name
Test status
Simulation time 1344757631 ps
CPU time 12.43 seconds
Started Jul 01 11:52:16 AM PDT 24
Finished Jul 01 11:52:30 AM PDT 24
Peak memory 238716 kb
Host smart-2e67afa8-9a8e-4cf1-9a6c-a0666222592f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716893229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2716893229
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1093810643
Short name T621
Test name
Test status
Simulation time 546482569 ps
CPU time 2.75 seconds
Started Jul 01 11:52:16 AM PDT 24
Finished Jul 01 11:52:21 AM PDT 24
Peak memory 225532 kb
Host smart-b322ea5b-51cb-49f1-b962-8e18ec927eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093810643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1093810643
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.549582485
Short name T792
Test name
Test status
Simulation time 258146255 ps
CPU time 4.8 seconds
Started Jul 01 11:52:16 AM PDT 24
Finished Jul 01 11:52:22 AM PDT 24
Peak memory 225560 kb
Host smart-b3735b62-eac2-4009-a132-01c7e63f7fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549582485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.549582485
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.997826341
Short name T70
Test name
Test status
Simulation time 7059848441 ps
CPU time 5.56 seconds
Started Jul 01 11:52:16 AM PDT 24
Finished Jul 01 11:52:23 AM PDT 24
Peak memory 225744 kb
Host smart-42a99059-5878-48fa-a655-f1bba3f4ea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997826341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.997826341
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.169896602
Short name T389
Test name
Test status
Simulation time 609784894 ps
CPU time 2.04 seconds
Started Jul 01 11:52:16 AM PDT 24
Finished Jul 01 11:52:20 AM PDT 24
Peak memory 225064 kb
Host smart-1ae70139-06e1-491a-89bb-020a89e0b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169896602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.169896602
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2533953895
Short name T392
Test name
Test status
Simulation time 1402180058 ps
CPU time 11.19 seconds
Started Jul 01 11:52:14 AM PDT 24
Finished Jul 01 11:52:27 AM PDT 24
Peak memory 220724 kb
Host smart-031b3ac8-4f67-4a49-ba97-be73af098e87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2533953895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2533953895
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3334168174
Short name T180
Test name
Test status
Simulation time 13130991041 ps
CPU time 93.78 seconds
Started Jul 01 11:52:16 AM PDT 24
Finished Jul 01 11:53:52 AM PDT 24
Peak memory 257640 kb
Host smart-1fa84ed9-0e95-442d-b8c2-d4116311ca90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334168174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3334168174
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.457131027
Short name T850
Test name
Test status
Simulation time 62390068692 ps
CPU time 33.04 seconds
Started Jul 01 11:52:16 AM PDT 24
Finished Jul 01 11:52:51 AM PDT 24
Peak memory 221276 kb
Host smart-e3277c58-f08e-41bf-b866-a2c09aa754a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457131027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.457131027
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1132367467
Short name T538
Test name
Test status
Simulation time 374127880 ps
CPU time 2.8 seconds
Started Jul 01 11:52:18 AM PDT 24
Finished Jul 01 11:52:22 AM PDT 24
Peak memory 217304 kb
Host smart-5177ac8e-ed84-4399-add0-e4105ac72431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132367467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1132367467
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1431702470
Short name T613
Test name
Test status
Simulation time 31506024 ps
CPU time 1.73 seconds
Started Jul 01 11:52:15 AM PDT 24
Finished Jul 01 11:52:19 AM PDT 24
Peak memory 217280 kb
Host smart-cff709b5-fecc-4c1e-9f1c-708989e51448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431702470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1431702470
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2631809503
Short name T362
Test name
Test status
Simulation time 96911648 ps
CPU time 0.76 seconds
Started Jul 01 11:52:17 AM PDT 24
Finished Jul 01 11:52:20 AM PDT 24
Peak memory 206944 kb
Host smart-6dbe73a1-75e6-41bf-a3ba-4676af5ebb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631809503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2631809503
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3162784814
Short name T446
Test name
Test status
Simulation time 372976366 ps
CPU time 2.99 seconds
Started Jul 01 11:52:17 AM PDT 24
Finished Jul 01 11:52:21 AM PDT 24
Peak memory 225544 kb
Host smart-77640d50-766f-4a4a-a435-78e707ac0c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162784814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3162784814
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4130639881
Short name T814
Test name
Test status
Simulation time 26246612 ps
CPU time 0.8 seconds
Started Jul 01 11:48:56 AM PDT 24
Finished Jul 01 11:48:58 AM PDT 24
Peak memory 206296 kb
Host smart-827facee-de67-486d-9ce0-c5412b8c1c9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130639881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
130639881
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1657699946
Short name T906
Test name
Test status
Simulation time 576759814 ps
CPU time 4.64 seconds
Started Jul 01 11:48:52 AM PDT 24
Finished Jul 01 11:48:58 AM PDT 24
Peak memory 225544 kb
Host smart-76129dab-79a4-4b8c-aaaf-1019d5d0b62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657699946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1657699946
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3481923436
Short name T56
Test name
Test status
Simulation time 15144480 ps
CPU time 0.8 seconds
Started Jul 01 11:48:43 AM PDT 24
Finished Jul 01 11:48:45 AM PDT 24
Peak memory 207848 kb
Host smart-1773a9b0-6fe5-4950-87b9-9f0a5c37c838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481923436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3481923436
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3679848788
Short name T41
Test name
Test status
Simulation time 28638908003 ps
CPU time 128.91 seconds
Started Jul 01 11:48:51 AM PDT 24
Finished Jul 01 11:51:01 AM PDT 24
Peak memory 266916 kb
Host smart-d52a93e7-5a07-4365-85c2-ff1a2342f65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679848788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3679848788
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1456373970
Short name T430
Test name
Test status
Simulation time 8703710503 ps
CPU time 57.67 seconds
Started Jul 01 11:48:53 AM PDT 24
Finished Jul 01 11:49:52 AM PDT 24
Peak memory 250776 kb
Host smart-52343651-3f28-4586-b4f6-15edc152a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456373970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1456373970
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3938703970
Short name T905
Test name
Test status
Simulation time 14800091102 ps
CPU time 120.2 seconds
Started Jul 01 11:48:56 AM PDT 24
Finished Jul 01 11:50:58 AM PDT 24
Peak memory 225804 kb
Host smart-7ced4e54-1708-48fb-ac76-3e7ba2b0406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938703970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3938703970
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.534602486
Short name T599
Test name
Test status
Simulation time 3218118085 ps
CPU time 31.81 seconds
Started Jul 01 11:48:52 AM PDT 24
Finished Jul 01 11:49:24 AM PDT 24
Peak memory 233928 kb
Host smart-84474f97-93ca-4c9d-a7c3-5199747f9412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534602486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.534602486
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1525790757
Short name T795
Test name
Test status
Simulation time 31842420685 ps
CPU time 223.42 seconds
Started Jul 01 11:48:51 AM PDT 24
Finished Jul 01 11:52:36 AM PDT 24
Peak memory 256136 kb
Host smart-2af9406e-67b8-4b78-be39-1b6992ab7eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525790757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1525790757
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1205479360
Short name T629
Test name
Test status
Simulation time 2836455668 ps
CPU time 9.03 seconds
Started Jul 01 11:48:50 AM PDT 24
Finished Jul 01 11:49:01 AM PDT 24
Peak memory 233884 kb
Host smart-27acfd0f-e65b-4821-bbbf-6f5d673d9d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205479360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1205479360
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1538861228
Short name T856
Test name
Test status
Simulation time 5302353371 ps
CPU time 22.15 seconds
Started Jul 01 11:48:52 AM PDT 24
Finished Jul 01 11:49:16 AM PDT 24
Peak memory 250072 kb
Host smart-5f56e411-c86e-49d0-b6a5-e686e4bdaab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538861228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1538861228
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1259417369
Short name T132
Test name
Test status
Simulation time 98939695 ps
CPU time 1.06 seconds
Started Jul 01 11:48:43 AM PDT 24
Finished Jul 01 11:48:45 AM PDT 24
Peak memory 218996 kb
Host smart-97da8009-f750-48f4-93ed-e215ba976e5d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259417369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1259417369
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2109765597
Short name T605
Test name
Test status
Simulation time 10987161333 ps
CPU time 8.14 seconds
Started Jul 01 11:48:48 AM PDT 24
Finished Jul 01 11:48:58 AM PDT 24
Peak memory 225640 kb
Host smart-f638b5db-ab76-48d3-9236-9a5bd4d970d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109765597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2109765597
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2478413317
Short name T318
Test name
Test status
Simulation time 60469308 ps
CPU time 2.51 seconds
Started Jul 01 11:48:48 AM PDT 24
Finished Jul 01 11:48:51 AM PDT 24
Peak memory 233492 kb
Host smart-db598378-eeac-4b69-9cfa-2b16c5b97d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478413317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2478413317
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2071374929
Short name T757
Test name
Test status
Simulation time 4564643769 ps
CPU time 13.26 seconds
Started Jul 01 11:48:52 AM PDT 24
Finished Jul 01 11:49:07 AM PDT 24
Peak memory 223684 kb
Host smart-e2d8ae5f-f329-4750-a254-5b6fd40f44ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071374929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2071374929
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2406442872
Short name T67
Test name
Test status
Simulation time 38443127 ps
CPU time 1 seconds
Started Jul 01 11:48:57 AM PDT 24
Finished Jul 01 11:49:00 AM PDT 24
Peak memory 236380 kb
Host smart-bf5a8a94-4bb8-4d0e-b739-3930ee5aafe7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406442872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2406442872
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2116508985
Short name T158
Test name
Test status
Simulation time 75125018231 ps
CPU time 654.87 seconds
Started Jul 01 11:48:57 AM PDT 24
Finished Jul 01 11:59:53 AM PDT 24
Peak memory 273660 kb
Host smart-5f018866-e910-4ba4-8886-b623c48be3f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116508985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2116508985
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3747344688
Short name T793
Test name
Test status
Simulation time 2869300684 ps
CPU time 15.99 seconds
Started Jul 01 11:48:47 AM PDT 24
Finished Jul 01 11:49:05 AM PDT 24
Peak memory 217596 kb
Host smart-c96ced39-02ef-4b8d-869d-ebc648916fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747344688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3747344688
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3916540939
Short name T427
Test name
Test status
Simulation time 1514987920 ps
CPU time 4.22 seconds
Started Jul 01 11:48:47 AM PDT 24
Finished Jul 01 11:48:53 AM PDT 24
Peak memory 217572 kb
Host smart-307ff063-1c26-4581-b06a-de667a5c6e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916540939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3916540939
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1997690309
Short name T377
Test name
Test status
Simulation time 20739641 ps
CPU time 0.86 seconds
Started Jul 01 11:48:46 AM PDT 24
Finished Jul 01 11:48:48 AM PDT 24
Peak memory 207972 kb
Host smart-1b85dccb-d368-41de-8473-a554d21a73eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997690309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1997690309
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1566362541
Short name T819
Test name
Test status
Simulation time 30531048 ps
CPU time 0.81 seconds
Started Jul 01 11:48:47 AM PDT 24
Finished Jul 01 11:48:49 AM PDT 24
Peak memory 206908 kb
Host smart-01fd7e86-889f-434d-badf-6a65fd66e7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566362541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1566362541
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1450662021
Short name T547
Test name
Test status
Simulation time 863478480 ps
CPU time 4.55 seconds
Started Jul 01 11:48:52 AM PDT 24
Finished Jul 01 11:48:58 AM PDT 24
Peak memory 233780 kb
Host smart-a93b40f3-4cde-4ace-a9d2-3354d5484df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450662021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1450662021
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2677220989
Short name T744
Test name
Test status
Simulation time 13694874 ps
CPU time 0.73 seconds
Started Jul 01 11:52:26 AM PDT 24
Finished Jul 01 11:52:34 AM PDT 24
Peak memory 205796 kb
Host smart-886c34d5-261b-4dbf-aa1c-937468841f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677220989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2677220989
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3551124003
Short name T724
Test name
Test status
Simulation time 113413526 ps
CPU time 3.3 seconds
Started Jul 01 11:52:21 AM PDT 24
Finished Jul 01 11:52:27 AM PDT 24
Peak memory 233768 kb
Host smart-abc70615-e85b-42a4-ae56-1630e42706c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551124003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3551124003
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2925347479
Short name T542
Test name
Test status
Simulation time 21299859 ps
CPU time 0.81 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:52:35 AM PDT 24
Peak memory 207844 kb
Host smart-ee8f70dd-7e01-4c5c-a0bf-3c6f512f1235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925347479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2925347479
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.617730266
Short name T813
Test name
Test status
Simulation time 182697413 ps
CPU time 4.61 seconds
Started Jul 01 11:52:21 AM PDT 24
Finished Jul 01 11:52:30 AM PDT 24
Peak memory 235228 kb
Host smart-a94eff2d-5b56-4d94-9d54-4d4f25b3d909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617730266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.617730266
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1704741465
Short name T931
Test name
Test status
Simulation time 9053696631 ps
CPU time 43.25 seconds
Started Jul 01 11:52:20 AM PDT 24
Finished Jul 01 11:53:06 AM PDT 24
Peak memory 250348 kb
Host smart-759ae297-a279-41cc-8781-1e982646ead2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704741465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1704741465
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3448574820
Short name T269
Test name
Test status
Simulation time 59586538871 ps
CPU time 316.71 seconds
Started Jul 01 11:52:20 AM PDT 24
Finished Jul 01 11:57:40 AM PDT 24
Peak memory 251280 kb
Host smart-40161bf6-f6f5-4af5-85a6-e385197ec237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448574820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3448574820
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3690398395
Short name T874
Test name
Test status
Simulation time 747128296 ps
CPU time 6.25 seconds
Started Jul 01 11:52:21 AM PDT 24
Finished Jul 01 11:52:30 AM PDT 24
Peak memory 225576 kb
Host smart-1521d4b7-7832-435f-b74c-37a854e1d1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690398395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3690398395
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3974389908
Short name T476
Test name
Test status
Simulation time 66617420539 ps
CPU time 145.46 seconds
Started Jul 01 11:52:21 AM PDT 24
Finished Jul 01 11:54:50 AM PDT 24
Peak memory 266580 kb
Host smart-5e6fdc2f-e7cb-4597-9ee6-1265bb00d9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974389908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3974389908
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2598905083
Short name T944
Test name
Test status
Simulation time 661441437 ps
CPU time 3.75 seconds
Started Jul 01 11:52:20 AM PDT 24
Finished Jul 01 11:52:27 AM PDT 24
Peak memory 233728 kb
Host smart-23a90952-5e59-4205-b7ab-5dbf1671de62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598905083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2598905083
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3039764011
Short name T715
Test name
Test status
Simulation time 3222540844 ps
CPU time 14.16 seconds
Started Jul 01 11:52:21 AM PDT 24
Finished Jul 01 11:52:38 AM PDT 24
Peak memory 233884 kb
Host smart-bb6cf5dc-0a6f-4924-ba26-91a2ed680193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039764011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3039764011
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4258238798
Short name T272
Test name
Test status
Simulation time 2493106187 ps
CPU time 6.41 seconds
Started Jul 01 11:52:21 AM PDT 24
Finished Jul 01 11:52:30 AM PDT 24
Peak memory 233788 kb
Host smart-b102d8bf-a9da-4495-862e-ca301f144d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258238798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4258238798
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2756974270
Short name T212
Test name
Test status
Simulation time 799648234 ps
CPU time 7.62 seconds
Started Jul 01 11:52:21 AM PDT 24
Finished Jul 01 11:52:31 AM PDT 24
Peak memory 233788 kb
Host smart-e7a93f28-0182-4d0b-ad69-b3a7c725de29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756974270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2756974270
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2064760664
Short name T324
Test name
Test status
Simulation time 1312863348 ps
CPU time 12.88 seconds
Started Jul 01 11:52:21 AM PDT 24
Finished Jul 01 11:52:38 AM PDT 24
Peak memory 223216 kb
Host smart-e9c2bccc-eb4c-4b3e-af61-397aa741b30a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2064760664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2064760664
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1425807041
Short name T977
Test name
Test status
Simulation time 8882281869 ps
CPU time 33.46 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:53:08 AM PDT 24
Peak memory 242160 kb
Host smart-47491d3a-81ba-4e58-977c-e6aae91cf231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425807041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1425807041
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1237311586
Short name T827
Test name
Test status
Simulation time 9787160422 ps
CPU time 14.24 seconds
Started Jul 01 11:52:21 AM PDT 24
Finished Jul 01 11:52:38 AM PDT 24
Peak memory 217476 kb
Host smart-57129c78-eaf6-43ca-aa69-061b66e12aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237311586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1237311586
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3643638177
Short name T368
Test name
Test status
Simulation time 2641416773 ps
CPU time 10.16 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:52:44 AM PDT 24
Peak memory 217512 kb
Host smart-b446ee47-b806-4123-883b-0a1712d459ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643638177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3643638177
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3277275436
Short name T975
Test name
Test status
Simulation time 156974010 ps
CPU time 1.03 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:52:35 AM PDT 24
Peak memory 208000 kb
Host smart-110203d0-8473-4511-a609-6ecf59655459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277275436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3277275436
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3306980069
Short name T355
Test name
Test status
Simulation time 55284502 ps
CPU time 0.8 seconds
Started Jul 01 11:52:21 AM PDT 24
Finished Jul 01 11:52:26 AM PDT 24
Peak memory 207152 kb
Host smart-794b1b81-c87c-43e8-b7c7-2a7dc5369952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306980069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3306980069
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2638009753
Short name T356
Test name
Test status
Simulation time 630992319 ps
CPU time 4.71 seconds
Started Jul 01 11:52:19 AM PDT 24
Finished Jul 01 11:52:26 AM PDT 24
Peak memory 233728 kb
Host smart-543a5357-635a-44d9-8723-415cd27ded68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638009753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2638009753
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.748916513
Short name T740
Test name
Test status
Simulation time 37570782 ps
CPU time 0.74 seconds
Started Jul 01 11:52:26 AM PDT 24
Finished Jul 01 11:52:33 AM PDT 24
Peak memory 206372 kb
Host smart-3317e3af-cae2-462f-9919-c8d77ec9d057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748916513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.748916513
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4066271671
Short name T575
Test name
Test status
Simulation time 56334052 ps
CPU time 2.46 seconds
Started Jul 01 11:52:28 AM PDT 24
Finished Jul 01 11:52:39 AM PDT 24
Peak memory 233760 kb
Host smart-b26b6e72-e490-415d-b151-6c84639a370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066271671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4066271671
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.60994444
Short name T456
Test name
Test status
Simulation time 24291412 ps
CPU time 0.82 seconds
Started Jul 01 11:52:29 AM PDT 24
Finished Jul 01 11:52:38 AM PDT 24
Peak memory 207480 kb
Host smart-255dbd97-a84a-4c2a-b393-e023fdc1fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60994444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.60994444
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2515963618
Short name T794
Test name
Test status
Simulation time 17866720732 ps
CPU time 37.46 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:53:12 AM PDT 24
Peak memory 250268 kb
Host smart-c2cdecae-6ebd-4830-977a-7236b000a4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515963618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2515963618
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3751740959
Short name T170
Test name
Test status
Simulation time 4932942039 ps
CPU time 31.04 seconds
Started Jul 01 11:52:28 AM PDT 24
Finished Jul 01 11:53:06 AM PDT 24
Peak memory 250260 kb
Host smart-3ac0d530-b465-4071-82fb-2955fa299c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751740959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3751740959
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3315976155
Short name T205
Test name
Test status
Simulation time 24389855010 ps
CPU time 126.76 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:54:42 AM PDT 24
Peak memory 250384 kb
Host smart-1663b2c6-63c3-4b5c-b1b4-341dae3be022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315976155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3315976155
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.580276506
Short name T282
Test name
Test status
Simulation time 294893430 ps
CPU time 6.13 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:52:40 AM PDT 24
Peak memory 241956 kb
Host smart-f6f12a4d-84ea-4d25-a42d-724c64f2b098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580276506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.580276506
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.4078352227
Short name T177
Test name
Test status
Simulation time 48126758687 ps
CPU time 103.38 seconds
Started Jul 01 11:52:26 AM PDT 24
Finished Jul 01 11:54:15 AM PDT 24
Peak memory 250312 kb
Host smart-ff45065f-9754-48c5-be30-2fcb5da8f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078352227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.4078352227
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2640972276
Short name T210
Test name
Test status
Simulation time 168182031 ps
CPU time 2.27 seconds
Started Jul 01 11:52:28 AM PDT 24
Finished Jul 01 11:52:38 AM PDT 24
Peak memory 225596 kb
Host smart-91c2e7e5-16f6-41a4-955c-f024d86d9dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640972276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2640972276
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.839385502
Short name T468
Test name
Test status
Simulation time 2547876536 ps
CPU time 9.77 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:52:44 AM PDT 24
Peak memory 225640 kb
Host smart-24cff31c-5560-4bc1-8c32-68cc3b798c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839385502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.839385502
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3735776149
Short name T898
Test name
Test status
Simulation time 5266701095 ps
CPU time 7.25 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:52:42 AM PDT 24
Peak memory 233824 kb
Host smart-0c2deb1d-bd54-4453-8cf7-035428432939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735776149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3735776149
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1159696211
Short name T235
Test name
Test status
Simulation time 31042036414 ps
CPU time 24.73 seconds
Started Jul 01 11:52:28 AM PDT 24
Finished Jul 01 11:53:01 AM PDT 24
Peak memory 242076 kb
Host smart-f885cae9-619f-4721-8001-36a5606144e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159696211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1159696211
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2777786718
Short name T885
Test name
Test status
Simulation time 2994078394 ps
CPU time 4.43 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:52:40 AM PDT 24
Peak memory 220348 kb
Host smart-ad4313dd-de25-4342-b863-b560bb96c7e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2777786718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2777786718
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3322308939
Short name T211
Test name
Test status
Simulation time 34600922362 ps
CPU time 125.1 seconds
Started Jul 01 11:52:26 AM PDT 24
Finished Jul 01 11:54:37 AM PDT 24
Peak memory 250400 kb
Host smart-7b0176a1-b58b-4cd2-b4f8-f4460847dadd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322308939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3322308939
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3555709714
Short name T296
Test name
Test status
Simulation time 736689573 ps
CPU time 10.62 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:52:45 AM PDT 24
Peak memory 217368 kb
Host smart-dd659242-727b-4381-b21a-442731a322d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555709714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3555709714
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2657094043
Short name T428
Test name
Test status
Simulation time 17391577732 ps
CPU time 13.28 seconds
Started Jul 01 11:52:29 AM PDT 24
Finished Jul 01 11:52:51 AM PDT 24
Peak memory 217500 kb
Host smart-1afbe882-c7cc-41f0-ad33-8ad5b4857f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657094043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2657094043
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1562105926
Short name T835
Test name
Test status
Simulation time 343431657 ps
CPU time 1.89 seconds
Started Jul 01 11:52:28 AM PDT 24
Finished Jul 01 11:52:38 AM PDT 24
Peak memory 217372 kb
Host smart-98d17ccc-045b-4328-90e0-6c1ac4b600c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562105926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1562105926
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4185310270
Short name T624
Test name
Test status
Simulation time 131636587 ps
CPU time 0.81 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:52:35 AM PDT 24
Peak memory 206928 kb
Host smart-4a6997ca-ab88-4c84-896b-0d016b7aa5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185310270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4185310270
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.67722835
Short name T418
Test name
Test status
Simulation time 44124426 ps
CPU time 2.38 seconds
Started Jul 01 11:52:27 AM PDT 24
Finished Jul 01 11:52:36 AM PDT 24
Peak memory 233776 kb
Host smart-47ecf6a1-f31f-49e7-ba10-0bd0f0891ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67722835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.67722835
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2626455688
Short name T483
Test name
Test status
Simulation time 14166979 ps
CPU time 0.73 seconds
Started Jul 01 11:52:36 AM PDT 24
Finished Jul 01 11:52:45 AM PDT 24
Peak memory 206388 kb
Host smart-f1529244-cd9d-42b2-9a54-44558f5dadfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626455688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2626455688
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2595450377
Short name T541
Test name
Test status
Simulation time 3912129321 ps
CPU time 19.06 seconds
Started Jul 01 11:52:31 AM PDT 24
Finished Jul 01 11:53:00 AM PDT 24
Peak memory 225728 kb
Host smart-b9d90980-5199-4d7b-9d0e-4680eee82eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595450377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2595450377
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4155726603
Short name T773
Test name
Test status
Simulation time 18683393 ps
CPU time 0.76 seconds
Started Jul 01 11:52:26 AM PDT 24
Finished Jul 01 11:52:33 AM PDT 24
Peak memory 206820 kb
Host smart-d65503d9-3efe-43ec-a196-bc3bcdf3ecec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155726603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4155726603
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2361124772
Short name T610
Test name
Test status
Simulation time 11174136 ps
CPU time 0.76 seconds
Started Jul 01 11:52:37 AM PDT 24
Finished Jul 01 11:52:46 AM PDT 24
Peak memory 216996 kb
Host smart-7d792334-a040-46df-9a2c-3a64a48573f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361124772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2361124772
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2005724477
Short name T54
Test name
Test status
Simulation time 6146304184 ps
CPU time 103 seconds
Started Jul 01 11:52:37 AM PDT 24
Finished Jul 01 11:54:28 AM PDT 24
Peak memory 252964 kb
Host smart-8b512c92-dd58-4059-a331-bbfb70170649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005724477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2005724477
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.636739007
Short name T233
Test name
Test status
Simulation time 4182311089 ps
CPU time 108.44 seconds
Started Jul 01 11:52:36 AM PDT 24
Finished Jul 01 11:54:33 AM PDT 24
Peak memory 255528 kb
Host smart-5952790e-4c97-44b7-a4ce-c69dd55ae2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636739007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.636739007
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2404749088
Short name T3
Test name
Test status
Simulation time 218930472 ps
CPU time 5.37 seconds
Started Jul 01 11:52:33 AM PDT 24
Finished Jul 01 11:52:48 AM PDT 24
Peak memory 233812 kb
Host smart-c55a8518-9596-43f5-9181-7ca1b5ced6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404749088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2404749088
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3495694198
Short name T222
Test name
Test status
Simulation time 9148137943 ps
CPU time 20.22 seconds
Started Jul 01 11:52:33 AM PDT 24
Finished Jul 01 11:53:03 AM PDT 24
Peak memory 225612 kb
Host smart-b9721ccb-a184-474f-957e-5987d480dcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495694198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3495694198
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.990056509
Short name T225
Test name
Test status
Simulation time 2366269022 ps
CPU time 12.43 seconds
Started Jul 01 11:52:30 AM PDT 24
Finished Jul 01 11:52:50 AM PDT 24
Peak memory 234028 kb
Host smart-e6b15422-840f-49ab-8b2b-59ee3adf980f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990056509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.990056509
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2155091285
Short name T87
Test name
Test status
Simulation time 401911777 ps
CPU time 7.83 seconds
Started Jul 01 11:52:33 AM PDT 24
Finished Jul 01 11:52:50 AM PDT 24
Peak memory 233804 kb
Host smart-2ca3e9bf-1415-46aa-b686-973b3ef2b8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155091285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2155091285
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.627807600
Short name T586
Test name
Test status
Simulation time 7388895127 ps
CPU time 13.93 seconds
Started Jul 01 11:52:32 AM PDT 24
Finished Jul 01 11:52:55 AM PDT 24
Peak memory 233896 kb
Host smart-3c2718cc-b5c2-4283-b35d-2ba893d6a544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627807600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.627807600
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2800052842
Short name T1025
Test name
Test status
Simulation time 448855760 ps
CPU time 3.78 seconds
Started Jul 01 11:52:32 AM PDT 24
Finished Jul 01 11:52:46 AM PDT 24
Peak memory 225476 kb
Host smart-3be92fa7-148b-4ccd-9334-e9e66512c9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800052842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2800052842
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2923771366
Short name T412
Test name
Test status
Simulation time 3127999409 ps
CPU time 7.97 seconds
Started Jul 01 11:52:37 AM PDT 24
Finished Jul 01 11:52:53 AM PDT 24
Peak memory 221740 kb
Host smart-37552ec2-8d91-4728-8b39-17d4c392924f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2923771366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2923771366
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.292170150
Short name T967
Test name
Test status
Simulation time 192236879 ps
CPU time 0.97 seconds
Started Jul 01 11:52:36 AM PDT 24
Finished Jul 01 11:52:45 AM PDT 24
Peak memory 207480 kb
Host smart-001935e9-c8e1-4e84-a51d-3b5df2d89dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292170150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.292170150
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3671058666
Short name T981
Test name
Test status
Simulation time 8007721182 ps
CPU time 22.2 seconds
Started Jul 01 11:52:31 AM PDT 24
Finished Jul 01 11:53:03 AM PDT 24
Peak memory 221416 kb
Host smart-d1181263-a150-4a4c-9a75-811a7e68a773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671058666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3671058666
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1959703655
Short name T27
Test name
Test status
Simulation time 744109383 ps
CPU time 5.2 seconds
Started Jul 01 11:52:26 AM PDT 24
Finished Jul 01 11:52:38 AM PDT 24
Peak memory 217416 kb
Host smart-9c459a2d-4de6-4c1d-9562-d220b35bb54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959703655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1959703655
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2814222371
Short name T774
Test name
Test status
Simulation time 1815512724 ps
CPU time 1.43 seconds
Started Jul 01 11:52:31 AM PDT 24
Finished Jul 01 11:52:41 AM PDT 24
Peak memory 217280 kb
Host smart-f98d177e-305e-4d4b-a428-23826df58a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814222371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2814222371
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1085102515
Short name T595
Test name
Test status
Simulation time 110992099 ps
CPU time 0.96 seconds
Started Jul 01 11:52:32 AM PDT 24
Finished Jul 01 11:52:42 AM PDT 24
Peak memory 207448 kb
Host smart-2aac6722-73da-4ca7-bbf8-804e42d02d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085102515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1085102515
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.247678450
Short name T338
Test name
Test status
Simulation time 7989830201 ps
CPU time 5.75 seconds
Started Jul 01 11:52:34 AM PDT 24
Finished Jul 01 11:52:48 AM PDT 24
Peak memory 225604 kb
Host smart-55e2e0c4-38f0-4507-abcd-b31eebdf1d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247678450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.247678450
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3061804638
Short name T963
Test name
Test status
Simulation time 25579054 ps
CPU time 0.74 seconds
Started Jul 01 11:52:40 AM PDT 24
Finished Jul 01 11:52:47 AM PDT 24
Peak memory 206572 kb
Host smart-8bb27445-e10d-48fd-8793-a7ae7622d585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061804638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3061804638
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2442134027
Short name T522
Test name
Test status
Simulation time 500329276 ps
CPU time 2.72 seconds
Started Jul 01 11:52:35 AM PDT 24
Finished Jul 01 11:52:47 AM PDT 24
Peak memory 233732 kb
Host smart-28010978-7e61-4ec8-97e5-707ba6410a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442134027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2442134027
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2661824086
Short name T424
Test name
Test status
Simulation time 17575656 ps
CPU time 0.84 seconds
Started Jul 01 11:52:36 AM PDT 24
Finished Jul 01 11:52:45 AM PDT 24
Peak memory 206468 kb
Host smart-02c799a4-b002-48b8-83e1-e66b6f4ebd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661824086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2661824086
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1678093648
Short name T494
Test name
Test status
Simulation time 729434964 ps
CPU time 11.49 seconds
Started Jul 01 11:52:45 AM PDT 24
Finished Jul 01 11:53:00 AM PDT 24
Peak memory 238368 kb
Host smart-d7a19f49-27c2-43f6-8bf8-461b841e1b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678093648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1678093648
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1341441661
Short name T268
Test name
Test status
Simulation time 40402062560 ps
CPU time 411.6 seconds
Started Jul 01 11:52:43 AM PDT 24
Finished Jul 01 11:59:40 AM PDT 24
Peak memory 256736 kb
Host smart-aa0640b3-69d4-4eb6-bedb-391703c05e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341441661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1341441661
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2972415982
Short name T482
Test name
Test status
Simulation time 1180423276 ps
CPU time 8.68 seconds
Started Jul 01 11:52:39 AM PDT 24
Finished Jul 01 11:52:54 AM PDT 24
Peak memory 225572 kb
Host smart-a589b428-bfc2-42ec-b641-51e9e79bf2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972415982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2972415982
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1116587828
Short name T802
Test name
Test status
Simulation time 1963507723 ps
CPU time 28.21 seconds
Started Jul 01 11:52:34 AM PDT 24
Finished Jul 01 11:53:11 AM PDT 24
Peak memory 250144 kb
Host smart-b4c8ad1d-39e1-47f2-abbb-eceda34c230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116587828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1116587828
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3554322472
Short name T922
Test name
Test status
Simulation time 581006064 ps
CPU time 3.11 seconds
Started Jul 01 11:52:35 AM PDT 24
Finished Jul 01 11:52:47 AM PDT 24
Peak memory 225512 kb
Host smart-3a8b0ee5-c7cd-46d2-a503-3a9b1e664fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554322472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3554322472
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.806717558
Short name T644
Test name
Test status
Simulation time 365332472 ps
CPU time 7.68 seconds
Started Jul 01 11:52:37 AM PDT 24
Finished Jul 01 11:52:52 AM PDT 24
Peak memory 225432 kb
Host smart-c956c91c-16cc-4763-baa4-713328845de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806717558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.806717558
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2165323467
Short name T852
Test name
Test status
Simulation time 3346861606 ps
CPU time 4.73 seconds
Started Jul 01 11:52:36 AM PDT 24
Finished Jul 01 11:52:49 AM PDT 24
Peak memory 233844 kb
Host smart-dc014a32-d491-4b01-87e2-cd017eb0fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165323467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2165323467
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2300546515
Short name T259
Test name
Test status
Simulation time 26639749860 ps
CPU time 17.71 seconds
Started Jul 01 11:52:41 AM PDT 24
Finished Jul 01 11:53:04 AM PDT 24
Peak memory 225668 kb
Host smart-ae86a7e4-a45e-4c19-9be1-b15d6a06bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300546515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2300546515
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2822139888
Short name T858
Test name
Test status
Simulation time 3742446104 ps
CPU time 8.41 seconds
Started Jul 01 11:52:41 AM PDT 24
Finished Jul 01 11:52:55 AM PDT 24
Peak memory 223356 kb
Host smart-6f9d8ce9-460d-456f-9a49-1461f0959215
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2822139888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2822139888
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2857980067
Short name T472
Test name
Test status
Simulation time 169292324221 ps
CPU time 832.58 seconds
Started Jul 01 11:52:43 AM PDT 24
Finished Jul 01 12:06:41 PM PDT 24
Peak memory 283196 kb
Host smart-6f264ccc-8c21-4e96-8eb9-01396ceb7cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857980067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2857980067
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.584355527
Short name T823
Test name
Test status
Simulation time 31208422 ps
CPU time 0.73 seconds
Started Jul 01 11:52:36 AM PDT 24
Finished Jul 01 11:52:45 AM PDT 24
Peak memory 206936 kb
Host smart-a18499ae-f6ce-4106-857f-2fc484252603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584355527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.584355527
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2286890168
Short name T379
Test name
Test status
Simulation time 3444015150 ps
CPU time 12.12 seconds
Started Jul 01 11:52:40 AM PDT 24
Finished Jul 01 11:52:59 AM PDT 24
Peak memory 217536 kb
Host smart-8e7bb729-a6ed-40a8-95a5-86fe9dfda8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286890168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2286890168
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.413105655
Short name T496
Test name
Test status
Simulation time 323470419 ps
CPU time 1.44 seconds
Started Jul 01 11:52:35 AM PDT 24
Finished Jul 01 11:52:45 AM PDT 24
Peak memory 217120 kb
Host smart-982a2344-fbda-43d4-b613-884507ae9c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413105655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.413105655
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3913143886
Short name T708
Test name
Test status
Simulation time 148497683 ps
CPU time 0.78 seconds
Started Jul 01 11:52:36 AM PDT 24
Finished Jul 01 11:52:45 AM PDT 24
Peak memory 206968 kb
Host smart-e7223666-714b-40ee-b7d5-34356721de24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913143886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3913143886
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2752844309
Short name T894
Test name
Test status
Simulation time 2843860276 ps
CPU time 13.1 seconds
Started Jul 01 11:52:38 AM PDT 24
Finished Jul 01 11:52:58 AM PDT 24
Peak memory 237816 kb
Host smart-bbd47f96-010a-4082-bfb5-378c0758163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752844309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2752844309
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2913501707
Short name T337
Test name
Test status
Simulation time 80650019 ps
CPU time 0.67 seconds
Started Jul 01 11:52:46 AM PDT 24
Finished Jul 01 11:52:50 AM PDT 24
Peak memory 206640 kb
Host smart-d7aa2af4-c3e7-454b-b2d5-b1f6b2b2bed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913501707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2913501707
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.601650608
Short name T848
Test name
Test status
Simulation time 73997761 ps
CPU time 2.05 seconds
Started Jul 01 11:52:48 AM PDT 24
Finished Jul 01 11:52:53 AM PDT 24
Peak memory 224692 kb
Host smart-e656686b-d6c2-49bd-aa84-58985a55279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601650608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.601650608
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3935871733
Short name T406
Test name
Test status
Simulation time 65436986 ps
CPU time 0.78 seconds
Started Jul 01 11:52:43 AM PDT 24
Finished Jul 01 11:52:49 AM PDT 24
Peak memory 207844 kb
Host smart-a4ba70a5-7cad-4b06-ab56-03807dbd526e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935871733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3935871733
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1033601490
Short name T207
Test name
Test status
Simulation time 66722821938 ps
CPU time 224.38 seconds
Started Jul 01 11:52:47 AM PDT 24
Finished Jul 01 11:56:34 AM PDT 24
Peak memory 252376 kb
Host smart-59314de5-d172-4fbb-8658-bfe6da24fce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033601490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1033601490
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1563402852
Short name T544
Test name
Test status
Simulation time 30713547292 ps
CPU time 188.69 seconds
Started Jul 01 11:52:47 AM PDT 24
Finished Jul 01 11:55:59 AM PDT 24
Peak memory 251444 kb
Host smart-db250275-be94-432c-8d42-13131f932c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563402852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1563402852
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1942579897
Short name T454
Test name
Test status
Simulation time 23808119372 ps
CPU time 126.5 seconds
Started Jul 01 11:52:47 AM PDT 24
Finished Jul 01 11:54:56 AM PDT 24
Peak memory 266060 kb
Host smart-9f5f0223-f1ae-4969-b77e-b646ff0a375e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942579897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1942579897
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2105475507
Short name T420
Test name
Test status
Simulation time 141448501 ps
CPU time 2.73 seconds
Started Jul 01 11:52:47 AM PDT 24
Finished Jul 01 11:52:52 AM PDT 24
Peak memory 233728 kb
Host smart-2e90d7df-7b40-44eb-ba81-413116625390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105475507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2105475507
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.80289946
Short name T841
Test name
Test status
Simulation time 6997428995 ps
CPU time 5.36 seconds
Started Jul 01 11:52:42 AM PDT 24
Finished Jul 01 11:52:53 AM PDT 24
Peak memory 225632 kb
Host smart-55fa34bc-11c1-4d12-b6cf-0921e6ae0bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80289946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.80289946
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.323547458
Short name T661
Test name
Test status
Simulation time 38769450519 ps
CPU time 128.91 seconds
Started Jul 01 11:52:42 AM PDT 24
Finished Jul 01 11:54:56 AM PDT 24
Peak memory 250276 kb
Host smart-f2df8d23-394c-4186-b429-6c45ff553181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323547458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.323547458
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3137757477
Short name T1004
Test name
Test status
Simulation time 4645324394 ps
CPU time 10.9 seconds
Started Jul 01 11:52:41 AM PDT 24
Finished Jul 01 11:52:58 AM PDT 24
Peak memory 225720 kb
Host smart-f6c71c1c-8894-4030-b9c4-f3f1602d3d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137757477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3137757477
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2256127198
Short name T452
Test name
Test status
Simulation time 572171180 ps
CPU time 4.54 seconds
Started Jul 01 11:52:45 AM PDT 24
Finished Jul 01 11:52:53 AM PDT 24
Peak memory 241976 kb
Host smart-61fad1eb-41c6-4e96-bd58-6d019f4754bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256127198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2256127198
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3790273613
Short name T1007
Test name
Test status
Simulation time 656128950 ps
CPU time 6.22 seconds
Started Jul 01 11:52:47 AM PDT 24
Finished Jul 01 11:52:56 AM PDT 24
Peak memory 223592 kb
Host smart-b21140fa-8026-4ed8-a613-7e13e0d35997
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3790273613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3790273613
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1646034981
Short name T271
Test name
Test status
Simulation time 191510795095 ps
CPU time 429.9 seconds
Started Jul 01 11:52:46 AM PDT 24
Finished Jul 01 11:59:59 AM PDT 24
Peak memory 268200 kb
Host smart-cf384827-1424-4a7a-ae9e-03cfa1943cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646034981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1646034981
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.596576631
Short name T666
Test name
Test status
Simulation time 3144843719 ps
CPU time 5.57 seconds
Started Jul 01 11:52:41 AM PDT 24
Finished Jul 01 11:52:52 AM PDT 24
Peak memory 217504 kb
Host smart-12b7416d-98e8-43a7-8917-5a51a252e3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596576631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.596576631
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1597978948
Short name T504
Test name
Test status
Simulation time 1440509726 ps
CPU time 2.51 seconds
Started Jul 01 11:52:42 AM PDT 24
Finished Jul 01 11:52:50 AM PDT 24
Peak memory 217352 kb
Host smart-f14dd63a-34dc-4d37-b58b-35882d4520f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597978948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1597978948
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2252618461
Short name T689
Test name
Test status
Simulation time 35623698 ps
CPU time 1.16 seconds
Started Jul 01 11:52:44 AM PDT 24
Finished Jul 01 11:52:49 AM PDT 24
Peak memory 208972 kb
Host smart-f2c7b1df-f119-45b1-aa07-ffc812dfc590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252618461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2252618461
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.677472203
Short name T316
Test name
Test status
Simulation time 64720291 ps
CPU time 0.72 seconds
Started Jul 01 11:52:45 AM PDT 24
Finished Jul 01 11:52:49 AM PDT 24
Peak memory 206996 kb
Host smart-22564ba9-36fc-4a99-9e08-8419836a0d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677472203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.677472203
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3369728621
Short name T791
Test name
Test status
Simulation time 11223104555 ps
CPU time 17.17 seconds
Started Jul 01 11:52:47 AM PDT 24
Finished Jul 01 11:53:07 AM PDT 24
Peak memory 233888 kb
Host smart-eec48481-4365-4557-a8c4-85d0151c2d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369728621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3369728621
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3528377493
Short name T820
Test name
Test status
Simulation time 38544384 ps
CPU time 0.67 seconds
Started Jul 01 11:52:50 AM PDT 24
Finished Jul 01 11:52:52 AM PDT 24
Peak memory 205792 kb
Host smart-2b120fb5-da64-457f-85eb-1b0553c38a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528377493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3528377493
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1401729569
Short name T1024
Test name
Test status
Simulation time 242974939 ps
CPU time 4.08 seconds
Started Jul 01 11:52:54 AM PDT 24
Finished Jul 01 11:52:59 AM PDT 24
Peak memory 233836 kb
Host smart-daf2db44-2139-40c5-9945-2b728a24890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401729569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1401729569
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3465371241
Short name T325
Test name
Test status
Simulation time 23368049 ps
CPU time 0.79 seconds
Started Jul 01 11:52:49 AM PDT 24
Finished Jul 01 11:52:52 AM PDT 24
Peak memory 207516 kb
Host smart-5e35ec32-a157-418e-bb49-9681b5597e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465371241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3465371241
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3540126823
Short name T126
Test name
Test status
Simulation time 31751588699 ps
CPU time 273.36 seconds
Started Jul 01 11:52:52 AM PDT 24
Finished Jul 01 11:57:27 AM PDT 24
Peak memory 268068 kb
Host smart-bc18f2f8-6b94-4fe3-bd34-3cd54c5c078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540126823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3540126823
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.507972008
Short name T786
Test name
Test status
Simulation time 8508939546 ps
CPU time 24.92 seconds
Started Jul 01 11:52:53 AM PDT 24
Finished Jul 01 11:53:20 AM PDT 24
Peak memory 218732 kb
Host smart-cf5bafb2-e701-44eb-8e82-eddafece0f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507972008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.507972008
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2287657816
Short name T195
Test name
Test status
Simulation time 41303295476 ps
CPU time 376.1 seconds
Started Jul 01 11:52:52 AM PDT 24
Finished Jul 01 11:59:09 AM PDT 24
Peak memory 266408 kb
Host smart-9118dc22-86be-4674-a04b-12a72cc2a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287657816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2287657816
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1557093394
Short name T700
Test name
Test status
Simulation time 10373237076 ps
CPU time 34.39 seconds
Started Jul 01 11:52:52 AM PDT 24
Finished Jul 01 11:53:29 AM PDT 24
Peak memory 233836 kb
Host smart-4bb3208e-0c1c-4a4b-b7cc-9a532cfb2a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557093394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1557093394
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.111653430
Short name T168
Test name
Test status
Simulation time 13803020917 ps
CPU time 19.07 seconds
Started Jul 01 11:52:53 AM PDT 24
Finished Jul 01 11:53:14 AM PDT 24
Peak memory 250296 kb
Host smart-fd613c05-b045-4cff-856e-68735298e730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111653430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.111653430
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1298307769
Short name T251
Test name
Test status
Simulation time 205676651 ps
CPU time 4.75 seconds
Started Jul 01 11:52:49 AM PDT 24
Finished Jul 01 11:52:56 AM PDT 24
Peak memory 225568 kb
Host smart-9725f6d6-38ec-4c42-a950-d552faf08e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298307769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1298307769
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1700155581
Short name T932
Test name
Test status
Simulation time 31830504 ps
CPU time 2.23 seconds
Started Jul 01 11:52:52 AM PDT 24
Finished Jul 01 11:52:56 AM PDT 24
Peak memory 225208 kb
Host smart-93a6d66e-49bd-4e41-8300-0018ddeb417e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700155581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1700155581
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3989285547
Short name T329
Test name
Test status
Simulation time 14353723076 ps
CPU time 5.96 seconds
Started Jul 01 11:52:47 AM PDT 24
Finished Jul 01 11:52:56 AM PDT 24
Peak memory 225668 kb
Host smart-6c3330d1-f6f0-416d-a05c-d8af1e90283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989285547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3989285547
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.334688168
Short name T229
Test name
Test status
Simulation time 2262532675 ps
CPU time 5.09 seconds
Started Jul 01 11:52:47 AM PDT 24
Finished Jul 01 11:52:55 AM PDT 24
Peak memory 233916 kb
Host smart-d05e427b-48c0-4e2b-a2cf-98aafef6db70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334688168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.334688168
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.863723808
Short name T615
Test name
Test status
Simulation time 119550018 ps
CPU time 3.26 seconds
Started Jul 01 11:52:51 AM PDT 24
Finished Jul 01 11:52:56 AM PDT 24
Peak memory 224176 kb
Host smart-58b2ad3c-ed8d-4c0d-ae06-c7697cb7fee9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=863723808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.863723808
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.111718740
Short name T157
Test name
Test status
Simulation time 4988684664 ps
CPU time 77.24 seconds
Started Jul 01 11:52:52 AM PDT 24
Finished Jul 01 11:54:10 AM PDT 24
Peak memory 250572 kb
Host smart-512a2de0-261c-4faf-8ff9-ac3552bea576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111718740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.111718740
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3677387684
Short name T655
Test name
Test status
Simulation time 40061559 ps
CPU time 0.7 seconds
Started Jul 01 11:52:47 AM PDT 24
Finished Jul 01 11:52:50 AM PDT 24
Peak memory 206664 kb
Host smart-63015afa-fbb5-4ec1-bdde-71e38dbdc30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677387684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3677387684
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.615022898
Short name T57
Test name
Test status
Simulation time 2521758460 ps
CPU time 4.97 seconds
Started Jul 01 11:52:48 AM PDT 24
Finished Jul 01 11:52:56 AM PDT 24
Peak memory 217452 kb
Host smart-94cd90fb-b7e9-47a1-84a8-6ed9f33b3558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615022898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.615022898
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4220058285
Short name T358
Test name
Test status
Simulation time 60209895 ps
CPU time 0.79 seconds
Started Jul 01 11:52:47 AM PDT 24
Finished Jul 01 11:52:51 AM PDT 24
Peak memory 206912 kb
Host smart-c449cd5d-e266-41a0-9d8b-0d481d49dc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220058285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4220058285
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2961789669
Short name T950
Test name
Test status
Simulation time 188323649 ps
CPU time 0.88 seconds
Started Jul 01 11:52:46 AM PDT 24
Finished Jul 01 11:52:50 AM PDT 24
Peak memory 206984 kb
Host smart-fc73d21c-14c4-4b5a-b9dd-3c37876516e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961789669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2961789669
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.422908010
Short name T478
Test name
Test status
Simulation time 29214504780 ps
CPU time 21.16 seconds
Started Jul 01 11:52:52 AM PDT 24
Finished Jul 01 11:53:15 AM PDT 24
Peak memory 225688 kb
Host smart-7ebc5acb-037f-44de-8ec5-d98f75cf6201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422908010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.422908010
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3349489927
Short name T879
Test name
Test status
Simulation time 31737057 ps
CPU time 0.76 seconds
Started Jul 01 11:52:59 AM PDT 24
Finished Jul 01 11:53:02 AM PDT 24
Peak memory 206352 kb
Host smart-f55656be-9cb0-4ef1-83f6-437bbdee0a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349489927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3349489927
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.118438431
Short name T869
Test name
Test status
Simulation time 802853934 ps
CPU time 9.39 seconds
Started Jul 01 11:52:59 AM PDT 24
Finished Jul 01 11:53:11 AM PDT 24
Peak memory 233772 kb
Host smart-7a018f82-8683-4c11-92b0-8aab0c8c82da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118438431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.118438431
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1911459975
Short name T638
Test name
Test status
Simulation time 12941474 ps
CPU time 0.76 seconds
Started Jul 01 11:52:51 AM PDT 24
Finished Jul 01 11:52:54 AM PDT 24
Peak memory 207756 kb
Host smart-42ff736f-5327-440a-bcfe-8bdbe6353f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911459975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1911459975
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1665916765
Short name T1022
Test name
Test status
Simulation time 33680636881 ps
CPU time 40.82 seconds
Started Jul 01 11:52:57 AM PDT 24
Finished Jul 01 11:53:40 AM PDT 24
Peak memory 257960 kb
Host smart-0f7831df-7d62-4072-ba10-a2e1da4c18d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665916765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1665916765
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2920353784
Short name T52
Test name
Test status
Simulation time 22227632619 ps
CPU time 161.78 seconds
Started Jul 01 11:52:58 AM PDT 24
Finished Jul 01 11:55:42 AM PDT 24
Peak memory 272848 kb
Host smart-299ce11f-526d-4ccb-a62b-de8b608a3ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920353784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2920353784
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3281546339
Short name T840
Test name
Test status
Simulation time 63381270403 ps
CPU time 124.11 seconds
Started Jul 01 11:52:58 AM PDT 24
Finished Jul 01 11:55:04 AM PDT 24
Peak memory 250756 kb
Host smart-16e8905e-2b05-4c06-b51b-d17d4db02080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281546339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3281546339
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2997730338
Short name T267
Test name
Test status
Simulation time 29363257835 ps
CPU time 103.02 seconds
Started Jul 01 11:52:59 AM PDT 24
Finished Jul 01 11:54:44 AM PDT 24
Peak memory 250196 kb
Host smart-aa6a2881-11bb-464d-80ef-7e70b3645dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997730338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2997730338
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3765895092
Short name T546
Test name
Test status
Simulation time 8640901898 ps
CPU time 8.15 seconds
Started Jul 01 11:52:56 AM PDT 24
Finished Jul 01 11:53:05 AM PDT 24
Peak memory 233976 kb
Host smart-b7f7aba4-b024-472c-9bcf-f4660ec2963f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765895092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3765895092
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1589914648
Short name T530
Test name
Test status
Simulation time 525660369 ps
CPU time 14.61 seconds
Started Jul 01 11:52:58 AM PDT 24
Finished Jul 01 11:53:15 AM PDT 24
Peak memory 233792 kb
Host smart-04586817-ffa5-4e78-9c6e-1c5384058866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589914648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1589914648
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3832779852
Short name T217
Test name
Test status
Simulation time 33332261746 ps
CPU time 9.63 seconds
Started Jul 01 11:52:58 AM PDT 24
Finished Jul 01 11:53:10 AM PDT 24
Peak memory 233808 kb
Host smart-fb62d811-c872-4281-9486-c4bdd1ff1012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832779852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3832779852
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1476455677
Short name T255
Test name
Test status
Simulation time 1004240186 ps
CPU time 3.72 seconds
Started Jul 01 11:52:57 AM PDT 24
Finished Jul 01 11:53:02 AM PDT 24
Peak memory 225568 kb
Host smart-684175dc-e8d0-48fa-8eff-b064f43a324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476455677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1476455677
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.415484718
Short name T768
Test name
Test status
Simulation time 701669288 ps
CPU time 4.35 seconds
Started Jul 01 11:53:01 AM PDT 24
Finished Jul 01 11:53:09 AM PDT 24
Peak memory 223984 kb
Host smart-6bb73dcd-b95b-49d7-9064-ab07b05b36fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=415484718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.415484718
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2820325957
Short name T291
Test name
Test status
Simulation time 780839488 ps
CPU time 4.29 seconds
Started Jul 01 11:52:52 AM PDT 24
Finished Jul 01 11:52:58 AM PDT 24
Peak memory 217496 kb
Host smart-c705160b-06a3-4a36-9f1f-70df98e3aa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820325957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2820325957
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4160337819
Short name T365
Test name
Test status
Simulation time 949280298 ps
CPU time 3.46 seconds
Started Jul 01 11:52:50 AM PDT 24
Finished Jul 01 11:52:55 AM PDT 24
Peak memory 217276 kb
Host smart-fbe072e2-13aa-4440-97d3-bbdadc4d1432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160337819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4160337819
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.400223170
Short name T677
Test name
Test status
Simulation time 241578278 ps
CPU time 1.28 seconds
Started Jul 01 11:52:58 AM PDT 24
Finished Jul 01 11:53:01 AM PDT 24
Peak memory 208952 kb
Host smart-abb3cff8-8e88-49aa-ad5c-130dd5712112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400223170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.400223170
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.281723784
Short name T86
Test name
Test status
Simulation time 426219715 ps
CPU time 0.95 seconds
Started Jul 01 11:52:57 AM PDT 24
Finished Jul 01 11:53:00 AM PDT 24
Peak memory 207984 kb
Host smart-21377b84-1c50-4b65-84ee-2464d6a75530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281723784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.281723784
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3142894884
Short name T239
Test name
Test status
Simulation time 903164748 ps
CPU time 5.25 seconds
Started Jul 01 11:53:00 AM PDT 24
Finished Jul 01 11:53:07 AM PDT 24
Peak memory 225532 kb
Host smart-361c589c-4659-4249-9def-8615a7656e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142894884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3142894884
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2755056125
Short name T463
Test name
Test status
Simulation time 24226544 ps
CPU time 0.74 seconds
Started Jul 01 11:53:08 AM PDT 24
Finished Jul 01 11:53:11 AM PDT 24
Peak memory 205812 kb
Host smart-6f34c775-1dd2-4af9-b904-c30935066862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755056125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2755056125
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1823446420
Short name T471
Test name
Test status
Simulation time 415195383 ps
CPU time 5.26 seconds
Started Jul 01 11:53:02 AM PDT 24
Finished Jul 01 11:53:10 AM PDT 24
Peak memory 225568 kb
Host smart-036e5d9f-c50b-4b94-a9f4-86a7fa378094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823446420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1823446420
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.931755666
Short name T678
Test name
Test status
Simulation time 19792442 ps
CPU time 0.81 seconds
Started Jul 01 11:52:58 AM PDT 24
Finished Jul 01 11:53:01 AM PDT 24
Peak memory 207480 kb
Host smart-a40debaa-547f-4d4a-9de8-fb35c0494817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931755666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.931755666
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3506851990
Short name T652
Test name
Test status
Simulation time 2079971535 ps
CPU time 54.15 seconds
Started Jul 01 11:53:09 AM PDT 24
Finished Jul 01 11:54:05 AM PDT 24
Peak memory 256212 kb
Host smart-a25beb97-7c65-428c-8adf-5d3ed4a6ba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506851990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3506851990
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1205981170
Short name T285
Test name
Test status
Simulation time 2015956234 ps
CPU time 17.65 seconds
Started Jul 01 11:53:10 AM PDT 24
Finished Jul 01 11:53:30 AM PDT 24
Peak memory 220676 kb
Host smart-c55b5104-51d5-4579-8dbc-1476a1690a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205981170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1205981170
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1568583580
Short name T131
Test name
Test status
Simulation time 1153296384 ps
CPU time 15.64 seconds
Started Jul 01 11:53:01 AM PDT 24
Finished Jul 01 11:53:20 AM PDT 24
Peak memory 238652 kb
Host smart-563eefa9-73ed-47a5-a458-183c68c278c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568583580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1568583580
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.594649596
Short name T198
Test name
Test status
Simulation time 19621065450 ps
CPU time 94.58 seconds
Started Jul 01 11:53:01 AM PDT 24
Finished Jul 01 11:54:38 AM PDT 24
Peak memory 250600 kb
Host smart-22757c6b-397e-412b-8f3f-5a9f8d110eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594649596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.594649596
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.227925357
Short name T731
Test name
Test status
Simulation time 774567482 ps
CPU time 5.83 seconds
Started Jul 01 11:53:02 AM PDT 24
Finished Jul 01 11:53:11 AM PDT 24
Peak memory 225544 kb
Host smart-45282365-c533-4e9f-a21c-b4ed070a385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227925357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.227925357
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3959331367
Short name T949
Test name
Test status
Simulation time 6949486315 ps
CPU time 16.51 seconds
Started Jul 01 11:53:01 AM PDT 24
Finished Jul 01 11:53:21 AM PDT 24
Peak memory 233860 kb
Host smart-4bcc54ec-60a2-497a-a8c4-210f1d2cf21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959331367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3959331367
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1767515031
Short name T594
Test name
Test status
Simulation time 1175761983 ps
CPU time 3.03 seconds
Started Jul 01 11:53:03 AM PDT 24
Finished Jul 01 11:53:09 AM PDT 24
Peak memory 225520 kb
Host smart-ede6238a-583c-47ff-8b79-5501202d3e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767515031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1767515031
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3803421477
Short name T1001
Test name
Test status
Simulation time 1835164229 ps
CPU time 3.83 seconds
Started Jul 01 11:53:02 AM PDT 24
Finished Jul 01 11:53:09 AM PDT 24
Peak memory 233676 kb
Host smart-9c69a18d-3356-4fc7-9928-756b1c2f3d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803421477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3803421477
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3695925286
Short name T1020
Test name
Test status
Simulation time 149499750 ps
CPU time 3.39 seconds
Started Jul 01 11:53:05 AM PDT 24
Finished Jul 01 11:53:11 AM PDT 24
Peak memory 219764 kb
Host smart-25c80727-c3da-469f-8d1d-ee40bfb0b712
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3695925286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3695925286
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1456282791
Short name T370
Test name
Test status
Simulation time 15396251133 ps
CPU time 19.09 seconds
Started Jul 01 11:53:00 AM PDT 24
Finished Jul 01 11:53:22 AM PDT 24
Peak memory 217508 kb
Host smart-a974a4a4-c3d4-4ff7-922d-71cdc08c415d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456282791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1456282791
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.199037065
Short name T588
Test name
Test status
Simulation time 7207113155 ps
CPU time 10.4 seconds
Started Jul 01 11:52:57 AM PDT 24
Finished Jul 01 11:53:10 AM PDT 24
Peak memory 217492 kb
Host smart-e2f829b2-a48d-4967-8af6-6ae95cb049f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199037065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.199037065
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2089301193
Short name T805
Test name
Test status
Simulation time 266997155 ps
CPU time 2.33 seconds
Started Jul 01 11:53:02 AM PDT 24
Finished Jul 01 11:53:08 AM PDT 24
Peak memory 217512 kb
Host smart-56c7de26-ba36-426f-949d-fd08c9635848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089301193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2089301193
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1168308020
Short name T72
Test name
Test status
Simulation time 496341150 ps
CPU time 1.1 seconds
Started Jul 01 11:53:03 AM PDT 24
Finished Jul 01 11:53:07 AM PDT 24
Peak memory 207980 kb
Host smart-9d64d3f6-cda7-4864-bfcb-541c8ad13074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168308020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1168308020
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1180710529
Short name T499
Test name
Test status
Simulation time 6704465817 ps
CPU time 8.41 seconds
Started Jul 01 11:53:00 AM PDT 24
Finished Jul 01 11:53:11 AM PDT 24
Peak memory 225692 kb
Host smart-695cd57f-cfd4-4b5d-b8f2-14bad8da5a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180710529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1180710529
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4191662500
Short name T349
Test name
Test status
Simulation time 25488402 ps
CPU time 0.76 seconds
Started Jul 01 11:53:12 AM PDT 24
Finished Jul 01 11:53:14 AM PDT 24
Peak memory 206380 kb
Host smart-72ef76ce-c984-4f67-a0bc-869da8e2d3e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191662500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4191662500
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.78537956
Short name T619
Test name
Test status
Simulation time 616882238 ps
CPU time 4.1 seconds
Started Jul 01 11:53:15 AM PDT 24
Finished Jul 01 11:53:21 AM PDT 24
Peak memory 225548 kb
Host smart-6110f496-38cb-4e9d-a912-dae5fbf23a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78537956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.78537956
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3499867966
Short name T822
Test name
Test status
Simulation time 12776379 ps
CPU time 0.76 seconds
Started Jul 01 11:53:08 AM PDT 24
Finished Jul 01 11:53:11 AM PDT 24
Peak memory 206472 kb
Host smart-30455485-2d30-4328-8d13-36f83f98928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499867966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3499867966
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2558374602
Short name T193
Test name
Test status
Simulation time 13556834835 ps
CPU time 134.37 seconds
Started Jul 01 11:53:13 AM PDT 24
Finished Jul 01 11:55:29 AM PDT 24
Peak memory 257996 kb
Host smart-4ea47dbb-3ee6-4600-aedb-f176e6aa4a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558374602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2558374602
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.848161629
Short name T51
Test name
Test status
Simulation time 33621818906 ps
CPU time 313.14 seconds
Started Jul 01 11:53:12 AM PDT 24
Finished Jul 01 11:58:26 AM PDT 24
Peak memory 250864 kb
Host smart-37cbbcd6-3a7c-4563-8498-5417b4a53152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848161629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.848161629
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1666304097
Short name T194
Test name
Test status
Simulation time 29493590344 ps
CPU time 150 seconds
Started Jul 01 11:53:14 AM PDT 24
Finished Jul 01 11:55:45 AM PDT 24
Peak memory 267796 kb
Host smart-ce70554d-aef5-4bc5-bd9a-bd7456c7dd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666304097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1666304097
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1401198641
Short name T659
Test name
Test status
Simulation time 742987379 ps
CPU time 11.54 seconds
Started Jul 01 11:53:20 AM PDT 24
Finished Jul 01 11:53:33 AM PDT 24
Peak memory 242016 kb
Host smart-c4f3aab7-a5d9-4acd-bf11-49bc1686d835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401198641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1401198641
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1173267215
Short name T983
Test name
Test status
Simulation time 29844234862 ps
CPU time 114.61 seconds
Started Jul 01 11:53:15 AM PDT 24
Finished Jul 01 11:55:12 AM PDT 24
Peak memory 253280 kb
Host smart-fada4911-0169-4f9f-a65a-00942083b691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173267215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1173267215
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2393817895
Short name T966
Test name
Test status
Simulation time 42638070 ps
CPU time 2.76 seconds
Started Jul 01 11:53:07 AM PDT 24
Finished Jul 01 11:53:13 AM PDT 24
Peak memory 233784 kb
Host smart-fd34a7d2-1c5a-4ef2-8fea-fe4ae1f77c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393817895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2393817895
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3085082904
Short name T882
Test name
Test status
Simulation time 314296529 ps
CPU time 6.31 seconds
Started Jul 01 11:53:08 AM PDT 24
Finished Jul 01 11:53:18 AM PDT 24
Peak memory 233752 kb
Host smart-7124d9d6-46b5-447a-a815-517bb44f04fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085082904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3085082904
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3821900251
Short name T534
Test name
Test status
Simulation time 3848004515 ps
CPU time 12.37 seconds
Started Jul 01 11:53:07 AM PDT 24
Finished Jul 01 11:53:22 AM PDT 24
Peak memory 233692 kb
Host smart-cfe1db04-6d43-4ba5-81a7-c630a728466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821900251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3821900251
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2515788567
Short name T836
Test name
Test status
Simulation time 22214584691 ps
CPU time 17.31 seconds
Started Jul 01 11:53:07 AM PDT 24
Finished Jul 01 11:53:27 AM PDT 24
Peak memory 233856 kb
Host smart-8372a890-afc2-4791-bea9-5368a651efc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515788567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2515788567
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.925310509
Short name T319
Test name
Test status
Simulation time 4155038616 ps
CPU time 5.15 seconds
Started Jul 01 11:53:14 AM PDT 24
Finished Jul 01 11:53:21 AM PDT 24
Peak memory 220544 kb
Host smart-e5901246-94f8-4bcc-b661-d52afb4746a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=925310509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.925310509
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1842276221
Short name T722
Test name
Test status
Simulation time 31258041107 ps
CPU time 369.34 seconds
Started Jul 01 11:53:20 AM PDT 24
Finished Jul 01 11:59:31 AM PDT 24
Peak memory 266852 kb
Host smart-7cefbe86-51ad-40d5-b5a1-993dc77f62ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842276221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1842276221
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4094147074
Short name T294
Test name
Test status
Simulation time 6296739922 ps
CPU time 31.3 seconds
Started Jul 01 11:53:08 AM PDT 24
Finished Jul 01 11:53:42 AM PDT 24
Peak memory 217688 kb
Host smart-f5f8d19c-091f-4e73-b224-8e3071c6e2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094147074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4094147074
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3897941046
Short name T128
Test name
Test status
Simulation time 2299360496 ps
CPU time 10.04 seconds
Started Jul 01 11:53:09 AM PDT 24
Finished Jul 01 11:53:21 AM PDT 24
Peak memory 217440 kb
Host smart-f32862c2-dfc7-47cd-829c-f15f1a51cc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897941046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3897941046
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1623073482
Short name T331
Test name
Test status
Simulation time 43977282 ps
CPU time 0.89 seconds
Started Jul 01 11:53:08 AM PDT 24
Finished Jul 01 11:53:11 AM PDT 24
Peak memory 207444 kb
Host smart-9bab6cfe-df63-476a-9ca0-760e3dbf2be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623073482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1623073482
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3354791836
Short name T322
Test name
Test status
Simulation time 71392299 ps
CPU time 0.89 seconds
Started Jul 01 11:53:09 AM PDT 24
Finished Jul 01 11:53:13 AM PDT 24
Peak memory 207196 kb
Host smart-2d1fc7b7-f161-45cd-8cff-72ad6cf0e012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354791836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3354791836
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.641507372
Short name T565
Test name
Test status
Simulation time 4734177840 ps
CPU time 18.28 seconds
Started Jul 01 11:53:16 AM PDT 24
Finished Jul 01 11:53:36 AM PDT 24
Peak memory 233820 kb
Host smart-30acffa3-425e-4a02-b1a5-634258115ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641507372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.641507372
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2385997887
Short name T64
Test name
Test status
Simulation time 15228989 ps
CPU time 0.73 seconds
Started Jul 01 11:53:18 AM PDT 24
Finished Jul 01 11:53:20 AM PDT 24
Peak memory 206372 kb
Host smart-48c168ff-9743-4d8e-9ba7-3f8d576306bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385997887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2385997887
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2120689515
Short name T720
Test name
Test status
Simulation time 807027106 ps
CPU time 7.77 seconds
Started Jul 01 11:53:14 AM PDT 24
Finished Jul 01 11:53:24 AM PDT 24
Peak memory 233752 kb
Host smart-9e828956-fda4-4f31-af9f-0bd15eecbc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120689515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2120689515
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4215395103
Short name T332
Test name
Test status
Simulation time 225555857 ps
CPU time 0.8 seconds
Started Jul 01 11:53:13 AM PDT 24
Finished Jul 01 11:53:15 AM PDT 24
Peak memory 207524 kb
Host smart-ca6aa21b-86da-463f-bc9d-bf5236b557bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215395103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4215395103
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3535241045
Short name T134
Test name
Test status
Simulation time 47785223583 ps
CPU time 329.26 seconds
Started Jul 01 11:53:18 AM PDT 24
Finished Jul 01 11:58:49 AM PDT 24
Peak memory 274104 kb
Host smart-73adbdf3-4866-4fa0-a770-81d0c019067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535241045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3535241045
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2623202726
Short name T908
Test name
Test status
Simulation time 19492002816 ps
CPU time 38.18 seconds
Started Jul 01 11:53:18 AM PDT 24
Finished Jul 01 11:53:58 AM PDT 24
Peak memory 242184 kb
Host smart-56e0a79d-4a4d-48c1-af18-88990aad7fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623202726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2623202726
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3056072178
Short name T183
Test name
Test status
Simulation time 19128306583 ps
CPU time 48.1 seconds
Started Jul 01 11:53:19 AM PDT 24
Finished Jul 01 11:54:08 AM PDT 24
Peak memory 233904 kb
Host smart-e997aa4f-f100-443f-9ede-e42f6cd1ffae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056072178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3056072178
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3548895408
Short name T13
Test name
Test status
Simulation time 4220409748 ps
CPU time 12.76 seconds
Started Jul 01 11:53:13 AM PDT 24
Finished Jul 01 11:53:27 AM PDT 24
Peak memory 225700 kb
Host smart-3bd46f41-f81b-4046-91f9-c84b1e8b7416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548895408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3548895408
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2081498182
Short name T672
Test name
Test status
Simulation time 4388551101 ps
CPU time 57.89 seconds
Started Jul 01 11:53:14 AM PDT 24
Finished Jul 01 11:54:14 AM PDT 24
Peak memory 252352 kb
Host smart-8da28205-7543-4362-9618-bc895c99bbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081498182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2081498182
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2085338225
Short name T238
Test name
Test status
Simulation time 3112509512 ps
CPU time 6.38 seconds
Started Jul 01 11:53:15 AM PDT 24
Finished Jul 01 11:53:23 AM PDT 24
Peak memory 225700 kb
Host smart-70e3b6ce-0faa-4750-89df-f22b3c6447da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085338225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2085338225
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2656000600
Short name T859
Test name
Test status
Simulation time 551554545 ps
CPU time 5.74 seconds
Started Jul 01 11:53:14 AM PDT 24
Finished Jul 01 11:53:21 AM PDT 24
Peak memory 233812 kb
Host smart-3332fc88-1976-4c47-9133-c51435f1edbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656000600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2656000600
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1918948095
Short name T607
Test name
Test status
Simulation time 137071549602 ps
CPU time 19.34 seconds
Started Jul 01 11:53:14 AM PDT 24
Finished Jul 01 11:53:36 AM PDT 24
Peak memory 225656 kb
Host smart-4ac546b6-32d4-4f61-b589-debd7878d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918948095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1918948095
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2032117128
Short name T545
Test name
Test status
Simulation time 3060123377 ps
CPU time 11.17 seconds
Started Jul 01 11:53:20 AM PDT 24
Finished Jul 01 11:53:33 AM PDT 24
Peak memory 233932 kb
Host smart-8e1f0084-ce75-44c4-8bba-3c7772d830f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032117128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2032117128
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1275231397
Short name T600
Test name
Test status
Simulation time 367928966 ps
CPU time 5.79 seconds
Started Jul 01 11:53:17 AM PDT 24
Finished Jul 01 11:53:24 AM PDT 24
Peak memory 224204 kb
Host smart-c7c53490-6009-4992-a6be-347ee2704fa9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1275231397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1275231397
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4244308617
Short name T952
Test name
Test status
Simulation time 3386148691 ps
CPU time 38.8 seconds
Started Jul 01 11:53:19 AM PDT 24
Finished Jul 01 11:53:59 AM PDT 24
Peak memory 225844 kb
Host smart-da284a56-8faa-410c-9c47-0ee496b90cf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244308617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4244308617
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1225942885
Short name T448
Test name
Test status
Simulation time 206077814 ps
CPU time 5.09 seconds
Started Jul 01 11:53:14 AM PDT 24
Finished Jul 01 11:53:22 AM PDT 24
Peak memory 217520 kb
Host smart-204b9ff1-7117-4328-b8ca-8507d6a5b273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225942885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1225942885
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.502551175
Short name T620
Test name
Test status
Simulation time 349308777 ps
CPU time 2.44 seconds
Started Jul 01 11:53:14 AM PDT 24
Finished Jul 01 11:53:17 AM PDT 24
Peak memory 217544 kb
Host smart-c5805ede-eb3c-4b68-a130-87c0ef3a27ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502551175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.502551175
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.767713695
Short name T441
Test name
Test status
Simulation time 217149674 ps
CPU time 4.06 seconds
Started Jul 01 11:53:13 AM PDT 24
Finished Jul 01 11:53:18 AM PDT 24
Peak memory 217428 kb
Host smart-c286fec2-e2fe-4f80-875f-4a4ac8c81bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767713695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.767713695
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1621465182
Short name T598
Test name
Test status
Simulation time 59905960 ps
CPU time 0.71 seconds
Started Jul 01 11:53:14 AM PDT 24
Finished Jul 01 11:53:17 AM PDT 24
Peak memory 206500 kb
Host smart-17c4f02d-dbfd-43d3-857e-a8fd087fc62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621465182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1621465182
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2709186135
Short name T520
Test name
Test status
Simulation time 13832625960 ps
CPU time 11.02 seconds
Started Jul 01 11:53:14 AM PDT 24
Finished Jul 01 11:53:27 AM PDT 24
Peak memory 242044 kb
Host smart-5749973d-5718-49e5-87f1-cc7a2437fd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709186135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2709186135
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3670403800
Short name T537
Test name
Test status
Simulation time 12911136 ps
CPU time 0.76 seconds
Started Jul 01 11:49:07 AM PDT 24
Finished Jul 01 11:49:09 AM PDT 24
Peak memory 205816 kb
Host smart-2598b603-9af9-45b8-8601-1b8a1407f5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670403800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
670403800
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4048878680
Short name T648
Test name
Test status
Simulation time 114994678 ps
CPU time 3.7 seconds
Started Jul 01 11:49:01 AM PDT 24
Finished Jul 01 11:49:06 AM PDT 24
Peak memory 233804 kb
Host smart-b51fda5b-7906-4e4e-aa8d-dc448a3757c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048878680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4048878680
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3889165434
Short name T1021
Test name
Test status
Simulation time 70838498 ps
CPU time 0.8 seconds
Started Jul 01 11:48:57 AM PDT 24
Finished Jul 01 11:48:59 AM PDT 24
Peak memory 207836 kb
Host smart-cb1abb19-d20e-4d1b-bc8f-1d828d5510b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889165434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3889165434
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3207647534
Short name T431
Test name
Test status
Simulation time 8297230851 ps
CPU time 85.84 seconds
Started Jul 01 11:49:04 AM PDT 24
Finished Jul 01 11:50:31 AM PDT 24
Peak memory 255156 kb
Host smart-ad03c52e-8f96-490e-907d-42cf834e919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207647534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3207647534
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.493713541
Short name T50
Test name
Test status
Simulation time 26296318403 ps
CPU time 298.33 seconds
Started Jul 01 11:49:02 AM PDT 24
Finished Jul 01 11:54:01 AM PDT 24
Peak memory 269792 kb
Host smart-59202db3-d3b3-44dd-90fa-4bd345a58d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493713541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.493713541
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3826902104
Short name T917
Test name
Test status
Simulation time 195252465774 ps
CPU time 477.28 seconds
Started Jul 01 11:49:03 AM PDT 24
Finished Jul 01 11:57:01 AM PDT 24
Peak memory 266832 kb
Host smart-9f050a81-9481-440a-8833-088757f8d8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826902104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3826902104
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2421448717
Short name T280
Test name
Test status
Simulation time 1757726320 ps
CPU time 13.58 seconds
Started Jul 01 11:49:02 AM PDT 24
Finished Jul 01 11:49:16 AM PDT 24
Peak memory 236276 kb
Host smart-db0175cf-a4c6-4e71-b0ce-ee79177a1958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421448717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2421448717
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2397886850
Short name T270
Test name
Test status
Simulation time 46628479081 ps
CPU time 158.48 seconds
Started Jul 01 11:49:03 AM PDT 24
Finished Jul 01 11:51:42 AM PDT 24
Peak memory 269004 kb
Host smart-8ef39cc9-df16-44e0-9de2-7dbdfb77bd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397886850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2397886850
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2337351810
Short name T554
Test name
Test status
Simulation time 616894613 ps
CPU time 8.94 seconds
Started Jul 01 11:49:02 AM PDT 24
Finished Jul 01 11:49:12 AM PDT 24
Peak memory 233740 kb
Host smart-ab6f95eb-9048-4b1e-be5c-5684e98bb6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337351810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2337351810
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.529557262
Short name T951
Test name
Test status
Simulation time 1148350440 ps
CPU time 14.77 seconds
Started Jul 01 11:49:05 AM PDT 24
Finished Jul 01 11:49:20 AM PDT 24
Peak memory 233784 kb
Host smart-e4b50066-019d-49b0-9cd6-41af801d1f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529557262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.529557262
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2542597145
Short name T39
Test name
Test status
Simulation time 32617761 ps
CPU time 1.1 seconds
Started Jul 01 11:48:56 AM PDT 24
Finished Jul 01 11:48:58 AM PDT 24
Peak memory 218912 kb
Host smart-a30941e5-c67a-474a-b679-dab2de1f1ee7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542597145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2542597145
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3738132585
Short name T1023
Test name
Test status
Simulation time 516526837 ps
CPU time 2.89 seconds
Started Jul 01 11:49:03 AM PDT 24
Finished Jul 01 11:49:07 AM PDT 24
Peak memory 225496 kb
Host smart-4c53e73f-a8c6-420e-9eb1-276c73648cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738132585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3738132585
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.712034458
Short name T961
Test name
Test status
Simulation time 20246923342 ps
CPU time 33.31 seconds
Started Jul 01 11:48:57 AM PDT 24
Finished Jul 01 11:49:32 AM PDT 24
Peak memory 250192 kb
Host smart-8087bdab-e3ed-4231-8aa8-c331b1c626b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712034458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.712034458
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3408305672
Short name T399
Test name
Test status
Simulation time 1238329379 ps
CPU time 12.94 seconds
Started Jul 01 11:49:01 AM PDT 24
Finished Jul 01 11:49:15 AM PDT 24
Peak memory 223184 kb
Host smart-316728fb-173d-4eb2-8639-0f0f06dfb25c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3408305672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3408305672
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3633385893
Short name T18
Test name
Test status
Simulation time 3464268534 ps
CPU time 1.82 seconds
Started Jul 01 11:49:01 AM PDT 24
Finished Jul 01 11:49:04 AM PDT 24
Peak memory 236508 kb
Host smart-ce6c2f73-5a3b-4020-826c-05aef6041778
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633385893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3633385893
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2478901210
Short name T1017
Test name
Test status
Simulation time 12978160 ps
CPU time 0.74 seconds
Started Jul 01 11:48:57 AM PDT 24
Finished Jul 01 11:48:59 AM PDT 24
Peak memory 206596 kb
Host smart-e24987ed-e9a7-4da0-b527-8f5aee089e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478901210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2478901210
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2597388280
Short name T343
Test name
Test status
Simulation time 33951851 ps
CPU time 0.72 seconds
Started Jul 01 11:48:58 AM PDT 24
Finished Jul 01 11:49:00 AM PDT 24
Peak memory 206628 kb
Host smart-ca2373ba-9aaf-4e01-8e2c-0b3aa5efee4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597388280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2597388280
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2950503348
Short name T634
Test name
Test status
Simulation time 45979647 ps
CPU time 1.38 seconds
Started Jul 01 11:48:57 AM PDT 24
Finished Jul 01 11:49:00 AM PDT 24
Peak memory 209068 kb
Host smart-608fea53-f039-4323-aea4-bb9f950f892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950503348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2950503348
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4211628710
Short name T585
Test name
Test status
Simulation time 254855032 ps
CPU time 0.79 seconds
Started Jul 01 11:48:57 AM PDT 24
Finished Jul 01 11:48:59 AM PDT 24
Peak memory 206960 kb
Host smart-2698a93a-a82b-47e1-a164-6374aec5e517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211628710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4211628710
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4009476238
Short name T569
Test name
Test status
Simulation time 12745384857 ps
CPU time 5.95 seconds
Started Jul 01 11:49:03 AM PDT 24
Finished Jul 01 11:49:10 AM PDT 24
Peak memory 233876 kb
Host smart-de939784-c24a-48d2-a999-2fde20e66356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009476238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4009476238
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3016214773
Short name T401
Test name
Test status
Simulation time 12721330 ps
CPU time 0.76 seconds
Started Jul 01 11:53:28 AM PDT 24
Finished Jul 01 11:53:33 AM PDT 24
Peak memory 206720 kb
Host smart-e4982e73-37fb-4878-9e2a-e30071bf2ef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016214773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3016214773
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4035260007
Short name T374
Test name
Test status
Simulation time 1814951087 ps
CPU time 9.96 seconds
Started Jul 01 11:53:29 AM PDT 24
Finished Jul 01 11:53:44 AM PDT 24
Peak memory 225576 kb
Host smart-64cc7caa-62f8-4c2b-bcb0-9da36ffd4715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035260007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4035260007
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3283893978
Short name T978
Test name
Test status
Simulation time 60270216 ps
CPU time 0.81 seconds
Started Jul 01 11:53:18 AM PDT 24
Finished Jul 01 11:53:19 AM PDT 24
Peak memory 207772 kb
Host smart-722fef0d-e8c8-4a5f-ac01-92615d9e9362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283893978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3283893978
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1166137336
Short name T242
Test name
Test status
Simulation time 6000648383 ps
CPU time 102.36 seconds
Started Jul 01 11:53:28 AM PDT 24
Finished Jul 01 11:55:14 AM PDT 24
Peak memory 255252 kb
Host smart-e2944c23-6867-40ec-a73a-16fb8adac9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166137336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1166137336
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1100570186
Short name T248
Test name
Test status
Simulation time 41196035819 ps
CPU time 85.63 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:54:56 AM PDT 24
Peak memory 236252 kb
Host smart-6c2dc6fa-dd1d-4617-8d94-3062d5f39ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100570186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1100570186
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1289284204
Short name T687
Test name
Test status
Simulation time 45340007425 ps
CPU time 420.62 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 12:00:31 PM PDT 24
Peak memory 266412 kb
Host smart-e5ab6b60-46ee-4220-8e28-d98b7926cdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289284204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1289284204
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3994673374
Short name T416
Test name
Test status
Simulation time 1693600648 ps
CPU time 21.25 seconds
Started Jul 01 11:53:19 AM PDT 24
Finished Jul 01 11:53:42 AM PDT 24
Peak memory 237348 kb
Host smart-f75881bb-15f8-45b6-acef-c06af026f932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994673374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3994673374
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.329570560
Short name T354
Test name
Test status
Simulation time 19486176 ps
CPU time 0.78 seconds
Started Jul 01 11:53:28 AM PDT 24
Finished Jul 01 11:53:32 AM PDT 24
Peak memory 216776 kb
Host smart-2e0bb686-7022-4f60-8f95-f84c43ef1262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329570560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.329570560
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.522389111
Short name T631
Test name
Test status
Simulation time 313092648 ps
CPU time 3.71 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:53:33 AM PDT 24
Peak memory 225500 kb
Host smart-3724439d-ca2e-4211-a4fc-ba952f5357f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522389111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.522389111
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3121939331
Short name T800
Test name
Test status
Simulation time 1955852712 ps
CPU time 8.38 seconds
Started Jul 01 11:53:19 AM PDT 24
Finished Jul 01 11:53:29 AM PDT 24
Peak memory 233936 kb
Host smart-92c4515d-1efd-41de-9c13-ab4edec17219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121939331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3121939331
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1969664376
Short name T402
Test name
Test status
Simulation time 57667404 ps
CPU time 2.21 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:53:31 AM PDT 24
Peak memory 233464 kb
Host smart-ed5b7e60-9256-4582-a8c1-0a340613bfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969664376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1969664376
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2908066977
Short name T359
Test name
Test status
Simulation time 8123553948 ps
CPU time 23.39 seconds
Started Jul 01 11:53:19 AM PDT 24
Finished Jul 01 11:53:43 AM PDT 24
Peak memory 233892 kb
Host smart-12cc6ad0-650e-4d2c-b732-7e1291459cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908066977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2908066977
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2374654616
Short name T936
Test name
Test status
Simulation time 447716008 ps
CPU time 4.35 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:53:35 AM PDT 24
Peak memory 221208 kb
Host smart-a99fc58d-5ed2-46cc-a0f4-2c4a59e7d3a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2374654616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2374654616
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.872085991
Short name T660
Test name
Test status
Simulation time 282624530 ps
CPU time 1.17 seconds
Started Jul 01 11:53:28 AM PDT 24
Finished Jul 01 11:53:33 AM PDT 24
Peak memory 207792 kb
Host smart-e03fd80f-1a63-434d-ab33-60e4121f0e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872085991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.872085991
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.575359722
Short name T674
Test name
Test status
Simulation time 69379813 ps
CPU time 0.74 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:53:29 AM PDT 24
Peak memory 206604 kb
Host smart-e427fe60-2e0a-463d-886d-760669233167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575359722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.575359722
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2448761101
Short name T335
Test name
Test status
Simulation time 16444852 ps
CPU time 0.74 seconds
Started Jul 01 11:53:19 AM PDT 24
Finished Jul 01 11:53:21 AM PDT 24
Peak memory 206628 kb
Host smart-60a070d0-8edd-4553-8ab7-415ff34248ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448761101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2448761101
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3122458016
Short name T124
Test name
Test status
Simulation time 78705254 ps
CPU time 1.41 seconds
Started Jul 01 11:53:18 AM PDT 24
Finished Jul 01 11:53:20 AM PDT 24
Peak memory 217376 kb
Host smart-d85ceb57-004c-4b4e-9a91-d7fa626fcd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122458016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3122458016
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3861552219
Short name T413
Test name
Test status
Simulation time 314772288 ps
CPU time 0.9 seconds
Started Jul 01 11:53:19 AM PDT 24
Finished Jul 01 11:53:21 AM PDT 24
Peak memory 207952 kb
Host smart-8df95cb8-3bae-4698-bd9f-8a8181b5982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861552219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3861552219
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1871217331
Short name T129
Test name
Test status
Simulation time 2764315085 ps
CPU time 4.85 seconds
Started Jul 01 11:53:19 AM PDT 24
Finished Jul 01 11:53:25 AM PDT 24
Peak memory 233872 kb
Host smart-26a87e67-8e7f-494c-a5af-dd1a698ad965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871217331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1871217331
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1730762093
Short name T572
Test name
Test status
Simulation time 13671430 ps
CPU time 0.72 seconds
Started Jul 01 11:53:30 AM PDT 24
Finished Jul 01 11:53:35 AM PDT 24
Peak memory 206440 kb
Host smart-52819e36-0a2d-429d-bb9e-82f3cd98d1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730762093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1730762093
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.111434190
Short name T962
Test name
Test status
Simulation time 409974586 ps
CPU time 4.69 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:53:35 AM PDT 24
Peak memory 233752 kb
Host smart-78ede356-4cb3-42c3-aa1f-9c9a53e06a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111434190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.111434190
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1553144358
Short name T617
Test name
Test status
Simulation time 46977187 ps
CPU time 0.79 seconds
Started Jul 01 11:53:26 AM PDT 24
Finished Jul 01 11:53:27 AM PDT 24
Peak memory 207508 kb
Host smart-4abec7f3-8c65-4850-9c2a-88b785e674d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553144358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1553144358
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.241000494
Short name T186
Test name
Test status
Simulation time 26168845262 ps
CPU time 89.86 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:55:00 AM PDT 24
Peak memory 250476 kb
Host smart-01d095ae-f51b-4f5b-90db-86c2b22f6883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241000494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.241000494
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3964692369
Short name T998
Test name
Test status
Simulation time 1962784319 ps
CPU time 29.41 seconds
Started Jul 01 11:53:26 AM PDT 24
Finished Jul 01 11:53:57 AM PDT 24
Peak memory 236396 kb
Host smart-2384cd8f-5645-4159-8222-0e044f3e9ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964692369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3964692369
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.947087717
Short name T920
Test name
Test status
Simulation time 58513410059 ps
CPU time 560.73 seconds
Started Jul 01 11:53:32 AM PDT 24
Finished Jul 01 12:02:58 PM PDT 24
Peak memory 258516 kb
Host smart-3a19db20-3c08-406c-9dca-3586bf2b7d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947087717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.947087717
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.830662485
Short name T810
Test name
Test status
Simulation time 2305501353 ps
CPU time 14.52 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:53:43 AM PDT 24
Peak memory 250300 kb
Host smart-cc377968-e136-41c6-a69a-78d51aa2a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830662485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.830662485
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1002869877
Short name T682
Test name
Test status
Simulation time 11337429894 ps
CPU time 63.43 seconds
Started Jul 01 11:53:28 AM PDT 24
Finished Jul 01 11:54:35 AM PDT 24
Peak memory 225684 kb
Host smart-7bf6e73f-45ad-468e-bb93-d892d8b2d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002869877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1002869877
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2051624229
Short name T1019
Test name
Test status
Simulation time 6514625229 ps
CPU time 10.86 seconds
Started Jul 01 11:53:30 AM PDT 24
Finished Jul 01 11:53:45 AM PDT 24
Peak memory 233960 kb
Host smart-035f9579-6267-4242-9317-8ff9865f2ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051624229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2051624229
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3609241557
Short name T837
Test name
Test status
Simulation time 3226865714 ps
CPU time 39.97 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:54:10 AM PDT 24
Peak memory 233904 kb
Host smart-1598c736-9c7d-42bd-9bb6-8776c3d054c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609241557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3609241557
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2093406864
Short name T690
Test name
Test status
Simulation time 1834051852 ps
CPU time 4.48 seconds
Started Jul 01 11:53:26 AM PDT 24
Finished Jul 01 11:53:33 AM PDT 24
Peak memory 233772 kb
Host smart-6f4553ae-b5c6-40af-9296-036ddcfdc565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093406864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2093406864
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4032706896
Short name T901
Test name
Test status
Simulation time 6264717293 ps
CPU time 9.5 seconds
Started Jul 01 11:53:26 AM PDT 24
Finished Jul 01 11:53:37 AM PDT 24
Peak memory 239100 kb
Host smart-93d30abc-4152-4f75-b044-44c5fb0e19e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032706896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4032706896
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1741537157
Short name T326
Test name
Test status
Simulation time 1115226530 ps
CPU time 6.8 seconds
Started Jul 01 11:53:28 AM PDT 24
Finished Jul 01 11:53:38 AM PDT 24
Peak memory 220408 kb
Host smart-ce23b4a0-94e0-4f84-b125-033c9e769054
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1741537157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1741537157
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1955819013
Short name T548
Test name
Test status
Simulation time 53070972903 ps
CPU time 33.68 seconds
Started Jul 01 11:53:29 AM PDT 24
Finished Jul 01 11:54:07 AM PDT 24
Peak memory 217440 kb
Host smart-0a186834-e386-4481-92ef-7e3eca53a0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955819013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1955819013
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2234942262
Short name T481
Test name
Test status
Simulation time 1537827367 ps
CPU time 5.23 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:53:34 AM PDT 24
Peak memory 217364 kb
Host smart-26d323cb-243d-42b8-94c5-798a869773e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234942262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2234942262
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1826384046
Short name T473
Test name
Test status
Simulation time 21722806 ps
CPU time 0.89 seconds
Started Jul 01 11:53:28 AM PDT 24
Finished Jul 01 11:53:32 AM PDT 24
Peak memory 207584 kb
Host smart-874e628c-d0e8-459f-9126-44f5bb345d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826384046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1826384046
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3342850886
Short name T464
Test name
Test status
Simulation time 14628276 ps
CPU time 0.72 seconds
Started Jul 01 11:53:27 AM PDT 24
Finished Jul 01 11:53:30 AM PDT 24
Peak memory 206944 kb
Host smart-9502cdb8-01e6-4329-9e8c-1c1e1d0fe4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342850886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3342850886
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2945285547
Short name T241
Test name
Test status
Simulation time 210550746 ps
CPU time 4.93 seconds
Started Jul 01 11:53:26 AM PDT 24
Finished Jul 01 11:53:33 AM PDT 24
Peak memory 241652 kb
Host smart-a2e9d3ab-538d-4786-b224-43068adeceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945285547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2945285547
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.511850546
Short name T779
Test name
Test status
Simulation time 68341268 ps
CPU time 0.77 seconds
Started Jul 01 11:53:31 AM PDT 24
Finished Jul 01 11:53:36 AM PDT 24
Peak memory 205800 kb
Host smart-3e85de6a-013e-42da-b23d-a2cd35ef839d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511850546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.511850546
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.786028924
Short name T707
Test name
Test status
Simulation time 1421574337 ps
CPU time 5.84 seconds
Started Jul 01 11:53:31 AM PDT 24
Finished Jul 01 11:53:42 AM PDT 24
Peak memory 225440 kb
Host smart-7dd7ff7e-5b95-4403-beed-5de54208cc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786028924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.786028924
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2931431524
Short name T317
Test name
Test status
Simulation time 25901409 ps
CPU time 0.74 seconds
Started Jul 01 11:53:34 AM PDT 24
Finished Jul 01 11:53:41 AM PDT 24
Peak memory 206484 kb
Host smart-f622919b-7201-45fb-89a1-158f1b3544b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931431524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2931431524
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1364239198
Short name T44
Test name
Test status
Simulation time 62609307705 ps
CPU time 256.89 seconds
Started Jul 01 11:53:31 AM PDT 24
Finished Jul 01 11:57:53 AM PDT 24
Peak memory 268492 kb
Host smart-704c826c-d3bc-4047-a227-466f64a6bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364239198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1364239198
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1971990487
Short name T498
Test name
Test status
Simulation time 24822919 ps
CPU time 0.81 seconds
Started Jul 01 11:53:34 AM PDT 24
Finished Jul 01 11:53:41 AM PDT 24
Peak memory 216928 kb
Host smart-51f896eb-49a9-406b-abe0-439a00449154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971990487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1971990487
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4111423669
Short name T540
Test name
Test status
Simulation time 457981330 ps
CPU time 4.88 seconds
Started Jul 01 11:53:31 AM PDT 24
Finished Jul 01 11:53:41 AM PDT 24
Peak memory 218620 kb
Host smart-58a12a82-f0a4-4ba7-98b9-71f8930132ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111423669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4111423669
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4267478895
Short name T275
Test name
Test status
Simulation time 755000190 ps
CPU time 7.21 seconds
Started Jul 01 11:53:34 AM PDT 24
Finished Jul 01 11:53:47 AM PDT 24
Peak memory 233852 kb
Host smart-267abbf1-6ea3-4f70-b697-2e95d2af95e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267478895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4267478895
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1534319193
Short name T470
Test name
Test status
Simulation time 19825368356 ps
CPU time 146.05 seconds
Started Jul 01 11:53:33 AM PDT 24
Finished Jul 01 11:56:04 AM PDT 24
Peak memory 250320 kb
Host smart-ee6dfe98-3568-4062-8cb5-40f43368a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534319193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1534319193
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3242414238
Short name T382
Test name
Test status
Simulation time 662777775 ps
CPU time 8.74 seconds
Started Jul 01 11:53:32 AM PDT 24
Finished Jul 01 11:53:46 AM PDT 24
Peak memory 233700 kb
Host smart-11bcd5dc-fd99-4eb5-a8da-1f3a216c1f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242414238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3242414238
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2959653024
Short name T512
Test name
Test status
Simulation time 353962954 ps
CPU time 6.27 seconds
Started Jul 01 11:53:32 AM PDT 24
Finished Jul 01 11:53:44 AM PDT 24
Peak memory 241940 kb
Host smart-086d8499-6690-4ef5-ab25-43e6e23eb001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959653024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2959653024
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.526491547
Short name T518
Test name
Test status
Simulation time 7194427971 ps
CPU time 17.09 seconds
Started Jul 01 11:53:31 AM PDT 24
Finished Jul 01 11:53:53 AM PDT 24
Peak memory 250080 kb
Host smart-02b0e258-6aa3-4da8-b49c-6ed66dadc9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526491547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.526491547
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1898070147
Short name T679
Test name
Test status
Simulation time 3656964825 ps
CPU time 11.87 seconds
Started Jul 01 11:53:32 AM PDT 24
Finished Jul 01 11:53:48 AM PDT 24
Peak memory 233964 kb
Host smart-0f036a9a-0cae-4ad1-940a-2e167ef014e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898070147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1898070147
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.73438256
Short name T501
Test name
Test status
Simulation time 3148472887 ps
CPU time 11.39 seconds
Started Jul 01 11:53:31 AM PDT 24
Finished Jul 01 11:53:47 AM PDT 24
Peak memory 223208 kb
Host smart-df5a603c-e057-4321-a650-be222365a35c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=73438256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direc
t.73438256
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3466880149
Short name T156
Test name
Test status
Simulation time 2639488107 ps
CPU time 30.94 seconds
Started Jul 01 11:53:37 AM PDT 24
Finished Jul 01 11:54:13 AM PDT 24
Peak memory 234092 kb
Host smart-8f09fd2a-ef05-4189-9ad6-dd6c0b74728d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466880149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3466880149
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.751343643
Short name T290
Test name
Test status
Simulation time 1241722301 ps
CPU time 4.08 seconds
Started Jul 01 11:53:31 AM PDT 24
Finished Jul 01 11:53:40 AM PDT 24
Peak memory 217572 kb
Host smart-65b809e2-6a7a-45b3-a1d1-b666840f03a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751343643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.751343643
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.505714897
Short name T304
Test name
Test status
Simulation time 5113103791 ps
CPU time 3.7 seconds
Started Jul 01 11:53:30 AM PDT 24
Finished Jul 01 11:53:39 AM PDT 24
Peak memory 217516 kb
Host smart-ba18c933-f86f-431d-a167-adc47fdd7c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505714897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.505714897
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2492554204
Short name T333
Test name
Test status
Simulation time 103290153 ps
CPU time 2.15 seconds
Started Jul 01 11:53:30 AM PDT 24
Finished Jul 01 11:53:37 AM PDT 24
Peak memory 217320 kb
Host smart-9a091598-b35f-4dcc-8494-c390651b5ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492554204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2492554204
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4127826997
Short name T816
Test name
Test status
Simulation time 245259566 ps
CPU time 0.84 seconds
Started Jul 01 11:53:34 AM PDT 24
Finished Jul 01 11:53:41 AM PDT 24
Peak memory 208012 kb
Host smart-698abff8-f947-4643-b961-c8150492641c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127826997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4127826997
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1414675475
Short name T1012
Test name
Test status
Simulation time 153956134 ps
CPU time 2.3 seconds
Started Jul 01 11:53:33 AM PDT 24
Finished Jul 01 11:53:41 AM PDT 24
Peak memory 225536 kb
Host smart-2c6b81cf-7873-41ca-87cb-19acccbac491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414675475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1414675475
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.956251702
Short name T69
Test name
Test status
Simulation time 15625523 ps
CPU time 0.81 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:53:43 AM PDT 24
Peak memory 205892 kb
Host smart-6e1beed3-78e0-4139-a3e1-52692feb1c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956251702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.956251702
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.285228099
Short name T73
Test name
Test status
Simulation time 281869868 ps
CPU time 4.93 seconds
Started Jul 01 11:53:34 AM PDT 24
Finished Jul 01 11:53:45 AM PDT 24
Peak memory 233708 kb
Host smart-3ce7ff25-1aa0-44f3-8f29-3dcb2a366e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285228099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.285228099
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.541217769
Short name T853
Test name
Test status
Simulation time 30791844 ps
CPU time 0.84 seconds
Started Jul 01 11:53:30 AM PDT 24
Finished Jul 01 11:53:35 AM PDT 24
Peak memory 207860 kb
Host smart-05bd9866-f878-4f8e-9518-6d30f2093ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541217769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.541217769
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1693706880
Short name T736
Test name
Test status
Simulation time 10165992830 ps
CPU time 72.43 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:54:54 AM PDT 24
Peak memory 250288 kb
Host smart-6f4cad5e-7e09-4585-b18c-fa30b4eb2f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693706880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1693706880
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4161894494
Short name T1026
Test name
Test status
Simulation time 8731145530 ps
CPU time 11.42 seconds
Started Jul 01 11:53:37 AM PDT 24
Finished Jul 01 11:53:54 AM PDT 24
Peak memory 219072 kb
Host smart-de48dfed-1e4b-418a-a3e8-acebbc0aa5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161894494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4161894494
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.820751440
Short name T80
Test name
Test status
Simulation time 30937603008 ps
CPU time 137.36 seconds
Started Jul 01 11:53:35 AM PDT 24
Finished Jul 01 11:55:59 AM PDT 24
Peak memory 264820 kb
Host smart-0b904f39-d693-4c68-b0a9-faf4e354028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820751440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.820751440
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.928324929
Short name T283
Test name
Test status
Simulation time 84114669 ps
CPU time 4.93 seconds
Started Jul 01 11:53:37 AM PDT 24
Finished Jul 01 11:53:47 AM PDT 24
Peak memory 241952 kb
Host smart-1f6ae935-c764-4397-aece-a11f94ab10f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928324929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.928324929
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.4161913364
Short name T508
Test name
Test status
Simulation time 57878923450 ps
CPU time 104.09 seconds
Started Jul 01 11:53:32 AM PDT 24
Finished Jul 01 11:55:21 AM PDT 24
Peak memory 242020 kb
Host smart-4e42a5fb-6be9-4a8a-abde-7ba0c834622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161913364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.4161913364
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2733742810
Short name T258
Test name
Test status
Simulation time 1100624179 ps
CPU time 4.46 seconds
Started Jul 01 11:53:35 AM PDT 24
Finished Jul 01 11:53:45 AM PDT 24
Peak memory 225516 kb
Host smart-1a9a8c90-0694-44e6-bb95-ef4788336517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733742810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2733742810
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3909307106
Short name T204
Test name
Test status
Simulation time 485420501 ps
CPU time 8.43 seconds
Started Jul 01 11:53:30 AM PDT 24
Finished Jul 01 11:53:43 AM PDT 24
Peak memory 229468 kb
Host smart-9d58e826-5549-450a-b5ba-b5a3a242886f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909307106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3909307106
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3784483218
Short name T519
Test name
Test status
Simulation time 516218626 ps
CPU time 6.15 seconds
Started Jul 01 11:53:33 AM PDT 24
Finished Jul 01 11:53:45 AM PDT 24
Peak memory 233816 kb
Host smart-aaafa5b0-a604-4f1f-af3f-9e11b6173603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784483218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3784483218
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.209571325
Short name T834
Test name
Test status
Simulation time 1656121005 ps
CPU time 7.6 seconds
Started Jul 01 11:53:37 AM PDT 24
Finished Jul 01 11:53:50 AM PDT 24
Peak memory 240316 kb
Host smart-5f270a4f-c747-418d-9f69-dc4959e82156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209571325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.209571325
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3653808334
Short name T367
Test name
Test status
Simulation time 1848271996 ps
CPU time 4.35 seconds
Started Jul 01 11:53:30 AM PDT 24
Finished Jul 01 11:53:39 AM PDT 24
Peak memory 220304 kb
Host smart-7e681991-a553-4e35-be73-1fd5f946cbea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3653808334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3653808334
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4227827870
Short name T896
Test name
Test status
Simulation time 3901423337 ps
CPU time 24.08 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:54:06 AM PDT 24
Peak memory 225720 kb
Host smart-d240b9d1-d71d-4843-a5c5-067d5c790c13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227827870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4227827870
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4150023758
Short name T61
Test name
Test status
Simulation time 9409716722 ps
CPU time 53.85 seconds
Started Jul 01 11:53:31 AM PDT 24
Finished Jul 01 11:54:29 AM PDT 24
Peak memory 217424 kb
Host smart-21c0268b-e9ce-4551-a740-c5146ddc4198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150023758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4150023758
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2528826155
Short name T459
Test name
Test status
Simulation time 2626386353 ps
CPU time 8.27 seconds
Started Jul 01 11:53:31 AM PDT 24
Finished Jul 01 11:53:43 AM PDT 24
Peak memory 217576 kb
Host smart-803dce88-6e42-4140-8e74-80ac3ecfeb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528826155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2528826155
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1174869599
Short name T807
Test name
Test status
Simulation time 74021776 ps
CPU time 3.38 seconds
Started Jul 01 11:53:34 AM PDT 24
Finished Jul 01 11:53:43 AM PDT 24
Peak memory 217376 kb
Host smart-59b42775-8313-4512-b8b8-823c187a05ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174869599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1174869599
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1355415145
Short name T549
Test name
Test status
Simulation time 98172086 ps
CPU time 0.68 seconds
Started Jul 01 11:53:33 AM PDT 24
Finished Jul 01 11:53:39 AM PDT 24
Peak memory 206904 kb
Host smart-9f177749-768a-4cdb-a1c6-615956c77352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355415145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1355415145
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3308971573
Short name T614
Test name
Test status
Simulation time 1259087931 ps
CPU time 7.77 seconds
Started Jul 01 11:53:30 AM PDT 24
Finished Jul 01 11:53:42 AM PDT 24
Peak memory 233740 kb
Host smart-87059aea-b571-43fd-8e48-c14d9585094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308971573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3308971573
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2114243506
Short name T636
Test name
Test status
Simulation time 14844752 ps
CPU time 0.74 seconds
Started Jul 01 11:53:41 AM PDT 24
Finished Jul 01 11:53:45 AM PDT 24
Peak memory 206360 kb
Host smart-a3d77687-fa46-4af3-a54a-264fd1fcd9e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114243506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2114243506
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2003134540
Short name T958
Test name
Test status
Simulation time 2724916087 ps
CPU time 24.18 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:54:06 AM PDT 24
Peak memory 225668 kb
Host smart-0319a701-9531-43c1-812c-8bac59a28887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003134540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2003134540
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.885823382
Short name T726
Test name
Test status
Simulation time 46631375 ps
CPU time 0.78 seconds
Started Jul 01 11:53:35 AM PDT 24
Finished Jul 01 11:53:41 AM PDT 24
Peak memory 206680 kb
Host smart-7cc2dc81-975d-4677-baf2-c6dfad4e6a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885823382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.885823382
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2956430272
Short name T264
Test name
Test status
Simulation time 254243498209 ps
CPU time 191.03 seconds
Started Jul 01 11:53:41 AM PDT 24
Finished Jul 01 11:56:55 AM PDT 24
Peak memory 254504 kb
Host smart-5d653bdb-01db-4eda-b264-32dbda5bc04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956430272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2956430272
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3960613163
Short name T912
Test name
Test status
Simulation time 5627867195 ps
CPU time 68.48 seconds
Started Jul 01 11:53:44 AM PDT 24
Finished Jul 01 11:54:59 AM PDT 24
Peak memory 266800 kb
Host smart-ca46b89d-837b-418e-8884-d78614ea2cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960613163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3960613163
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3391605881
Short name T49
Test name
Test status
Simulation time 187064351957 ps
CPU time 228.78 seconds
Started Jul 01 11:53:40 AM PDT 24
Finished Jul 01 11:57:33 AM PDT 24
Peak memory 258560 kb
Host smart-18e70128-a486-402b-9fc6-36927cd73295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391605881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3391605881
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2229132072
Short name T281
Test name
Test status
Simulation time 312498034 ps
CPU time 9.09 seconds
Started Jul 01 11:53:35 AM PDT 24
Finished Jul 01 11:53:50 AM PDT 24
Peak memory 241916 kb
Host smart-2d6d6e87-b4a8-4fa0-a02f-a4c1dbbbd705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229132072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2229132072
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1342499975
Short name T830
Test name
Test status
Simulation time 16361487520 ps
CPU time 65.4 seconds
Started Jul 01 11:53:43 AM PDT 24
Finished Jul 01 11:54:53 AM PDT 24
Peak memory 254780 kb
Host smart-c758061d-5667-45d9-91a4-e6b3c8e13c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342499975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1342499975
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.671544585
Short name T656
Test name
Test status
Simulation time 1249964480 ps
CPU time 10.47 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:53:52 AM PDT 24
Peak memory 225596 kb
Host smart-ac8a5845-8809-4c01-94ed-bdf01299a8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671544585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.671544585
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1185713530
Short name T938
Test name
Test status
Simulation time 17625427053 ps
CPU time 68.03 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:54:50 AM PDT 24
Peak memory 240460 kb
Host smart-67b13c7b-2b49-433b-9eaa-19845670ad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185713530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1185713530
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.803057043
Short name T220
Test name
Test status
Simulation time 17564571437 ps
CPU time 26.34 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:54:08 AM PDT 24
Peak memory 233940 kb
Host smart-1cf499e0-907a-46c5-a483-3796fe70fdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803057043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.803057043
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.736280577
Short name T948
Test name
Test status
Simulation time 3473367988 ps
CPU time 18.86 seconds
Started Jul 01 11:53:42 AM PDT 24
Finished Jul 01 11:54:06 AM PDT 24
Peak memory 223152 kb
Host smart-3dc88b55-f732-4187-9813-6ecaa9f2da0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=736280577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.736280577
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.166419437
Short name T857
Test name
Test status
Simulation time 10696829395 ps
CPU time 53.63 seconds
Started Jul 01 11:53:42 AM PDT 24
Finished Jul 01 11:54:39 AM PDT 24
Peak memory 251416 kb
Host smart-c1d3fbb3-1bed-4de3-a880-1e41c4af8f14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166419437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.166419437
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1107443073
Short name T788
Test name
Test status
Simulation time 2345643051 ps
CPU time 25.36 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:54:07 AM PDT 24
Peak memory 217580 kb
Host smart-d368a7b3-005b-44dc-82d5-ab10a6f54e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107443073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1107443073
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.822210650
Short name T366
Test name
Test status
Simulation time 17502903719 ps
CPU time 7.22 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:53:49 AM PDT 24
Peak memory 217484 kb
Host smart-1fcc914d-f59a-4fde-9168-8a58223cadcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822210650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.822210650
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2685102433
Short name T566
Test name
Test status
Simulation time 416197120 ps
CPU time 1.72 seconds
Started Jul 01 11:53:35 AM PDT 24
Finished Jul 01 11:53:43 AM PDT 24
Peak memory 217304 kb
Host smart-52eb759d-4d6f-4c93-a933-1b90818c8211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685102433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2685102433
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3640572640
Short name T804
Test name
Test status
Simulation time 70665627 ps
CPU time 0.77 seconds
Started Jul 01 11:53:36 AM PDT 24
Finished Jul 01 11:53:43 AM PDT 24
Peak memory 206968 kb
Host smart-97406d3e-04eb-414d-8cee-990a0c37469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640572640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3640572640
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.563870778
Short name T216
Test name
Test status
Simulation time 11126020837 ps
CPU time 4.19 seconds
Started Jul 01 11:53:35 AM PDT 24
Finished Jul 01 11:53:45 AM PDT 24
Peak memory 225732 kb
Host smart-31f68d79-c6f8-4bc5-9a5b-8ee4f433730f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563870778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.563870778
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.611136355
Short name T301
Test name
Test status
Simulation time 46982593 ps
CPU time 0.75 seconds
Started Jul 01 11:53:46 AM PDT 24
Finished Jul 01 11:53:52 AM PDT 24
Peak memory 205808 kb
Host smart-7618bc18-997e-41c5-a4c6-e7b89662e864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611136355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.611136355
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1728571467
Short name T902
Test name
Test status
Simulation time 127390068 ps
CPU time 2.32 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:53:54 AM PDT 24
Peak memory 225468 kb
Host smart-b4977776-1056-48e8-a55b-9f4f2ac794e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728571467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1728571467
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2467703511
Short name T577
Test name
Test status
Simulation time 18836286 ps
CPU time 0.77 seconds
Started Jul 01 11:53:39 AM PDT 24
Finished Jul 01 11:53:44 AM PDT 24
Peak memory 207508 kb
Host smart-3f063dd3-68ac-47b6-aac1-2b889d31858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467703511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2467703511
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1588151601
Short name T911
Test name
Test status
Simulation time 5297832652 ps
CPU time 81.21 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:55:13 AM PDT 24
Peak memory 250356 kb
Host smart-ca8252a4-5326-41c0-a01f-324495b5c5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588151601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1588151601
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1803518681
Short name T669
Test name
Test status
Simulation time 6299980749 ps
CPU time 74.88 seconds
Started Jul 01 11:53:48 AM PDT 24
Finished Jul 01 11:55:07 AM PDT 24
Peak memory 250600 kb
Host smart-30640976-e12c-44e2-82d6-15831f49ccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803518681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1803518681
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.715858863
Short name T467
Test name
Test status
Simulation time 3136500526 ps
CPU time 14.96 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:54:07 AM PDT 24
Peak memory 233992 kb
Host smart-3c0dafd8-c663-463e-8dc0-ffb5ae555df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715858863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.715858863
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2168168338
Short name T10
Test name
Test status
Simulation time 15027810886 ps
CPU time 22.81 seconds
Started Jul 01 11:53:49 AM PDT 24
Finished Jul 01 11:54:16 AM PDT 24
Peak memory 236124 kb
Host smart-906fa578-1b24-462c-9be3-dfc9b5336623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168168338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2168168338
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3146718867
Short name T218
Test name
Test status
Simulation time 1880148199 ps
CPU time 9.71 seconds
Started Jul 01 11:53:44 AM PDT 24
Finished Jul 01 11:54:00 AM PDT 24
Peak memory 225528 kb
Host smart-90b8cf02-0ce7-4be0-b2ce-249e602fe8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146718867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3146718867
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3598766509
Short name T897
Test name
Test status
Simulation time 2403611473 ps
CPU time 17.25 seconds
Started Jul 01 11:53:44 AM PDT 24
Finished Jul 01 11:54:07 AM PDT 24
Peak memory 233824 kb
Host smart-0a3196de-64d3-444f-9e4e-650b79b9404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598766509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3598766509
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2809473852
Short name T668
Test name
Test status
Simulation time 443125101 ps
CPU time 4.47 seconds
Started Jul 01 11:53:40 AM PDT 24
Finished Jul 01 11:53:48 AM PDT 24
Peak memory 225592 kb
Host smart-271094ee-d329-4b03-a285-42def09588e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809473852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2809473852
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3900878231
Short name T350
Test name
Test status
Simulation time 1334791124 ps
CPU time 15.4 seconds
Started Jul 01 11:53:45 AM PDT 24
Finished Jul 01 11:54:06 AM PDT 24
Peak memory 223488 kb
Host smart-a9a81a16-b055-4afa-b758-92584979530f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3900878231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3900878231
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2411250576
Short name T1009
Test name
Test status
Simulation time 9720226268 ps
CPU time 98.24 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:55:30 AM PDT 24
Peak memory 250436 kb
Host smart-a36370a9-3ce3-4ee0-b501-c331b982b3d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411250576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2411250576
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2600868029
Short name T780
Test name
Test status
Simulation time 13583525 ps
CPU time 0.74 seconds
Started Jul 01 11:53:43 AM PDT 24
Finished Jul 01 11:53:48 AM PDT 24
Peak memory 206644 kb
Host smart-0915c42d-e512-4380-8fad-07e6a9ccc4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600868029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2600868029
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.363408734
Short name T868
Test name
Test status
Simulation time 1625071206 ps
CPU time 5.78 seconds
Started Jul 01 11:53:40 AM PDT 24
Finished Jul 01 11:53:50 AM PDT 24
Peak memory 217352 kb
Host smart-6716837a-7a92-4ac5-81d2-b42faff608ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363408734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.363408734
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1373255491
Short name T658
Test name
Test status
Simulation time 240572634 ps
CPU time 1.9 seconds
Started Jul 01 11:53:43 AM PDT 24
Finished Jul 01 11:53:51 AM PDT 24
Peak memory 217352 kb
Host smart-fdf34ae4-621c-4f2c-85a0-571b31f57276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373255491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1373255491
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.286920407
Short name T872
Test name
Test status
Simulation time 44973834 ps
CPU time 0.81 seconds
Started Jul 01 11:53:43 AM PDT 24
Finished Jul 01 11:53:48 AM PDT 24
Peak memory 206972 kb
Host smart-e4d8a03e-0625-4c22-a4d0-6ec7e31264e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286920407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.286920407
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3766968487
Short name T767
Test name
Test status
Simulation time 7326117328 ps
CPU time 17.09 seconds
Started Jul 01 11:53:46 AM PDT 24
Finished Jul 01 11:54:09 AM PDT 24
Peak memory 233860 kb
Host smart-5cea8b18-62eb-4ccb-813e-31ab6ae61ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766968487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3766968487
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3508835896
Short name T670
Test name
Test status
Simulation time 28906283 ps
CPU time 0.71 seconds
Started Jul 01 11:53:51 AM PDT 24
Finished Jul 01 11:53:55 AM PDT 24
Peak memory 205824 kb
Host smart-19bcc308-e977-4c3b-b5d8-305bea92711a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508835896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3508835896
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2432584767
Short name T59
Test name
Test status
Simulation time 237183086 ps
CPU time 3.09 seconds
Started Jul 01 11:53:51 AM PDT 24
Finished Jul 01 11:53:57 AM PDT 24
Peak memory 233752 kb
Host smart-36ddd24a-5507-4f06-ba32-ee5293af116c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432584767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2432584767
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2079197348
Short name T426
Test name
Test status
Simulation time 40761197 ps
CPU time 0.8 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:53:53 AM PDT 24
Peak memory 206836 kb
Host smart-b4e6dc31-ae2c-4ff4-a974-c505a52d34c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079197348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2079197348
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2270933923
Short name T405
Test name
Test status
Simulation time 833138304 ps
CPU time 11.54 seconds
Started Jul 01 11:53:53 AM PDT 24
Finished Jul 01 11:54:07 AM PDT 24
Peak memory 225552 kb
Host smart-c2cd1ef9-a030-44c7-a5ac-56bcc3cc5b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270933923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2270933923
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2426467006
Short name T200
Test name
Test status
Simulation time 6967552727 ps
CPU time 96.36 seconds
Started Jul 01 11:53:51 AM PDT 24
Finished Jul 01 11:55:30 AM PDT 24
Peak memory 257696 kb
Host smart-e9537ac0-6a17-4d35-acb3-81f9e232252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426467006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2426467006
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3783405528
Short name T935
Test name
Test status
Simulation time 689786227 ps
CPU time 7.77 seconds
Started Jul 01 11:53:53 AM PDT 24
Finished Jul 01 11:54:03 AM PDT 24
Peak memory 240456 kb
Host smart-9e20ba2e-e5b1-4745-9685-50b54404bc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783405528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3783405528
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1499083540
Short name T390
Test name
Test status
Simulation time 837709848 ps
CPU time 11.72 seconds
Started Jul 01 11:53:46 AM PDT 24
Finished Jul 01 11:54:03 AM PDT 24
Peak memory 233732 kb
Host smart-1393964f-2c4b-45c1-b5fb-b75c8cfe7ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499083540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1499083540
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.874836484
Short name T955
Test name
Test status
Simulation time 975647539 ps
CPU time 11.8 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:54:04 AM PDT 24
Peak memory 225468 kb
Host smart-49fbb837-305c-41f7-8143-f204e0dbd185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874836484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.874836484
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1996725827
Short name T184
Test name
Test status
Simulation time 15829725399 ps
CPU time 13.41 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:54:05 AM PDT 24
Peak memory 241980 kb
Host smart-eef033eb-8b36-4fa5-9db9-9d73fe0d9d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996725827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1996725827
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2651703533
Short name T509
Test name
Test status
Simulation time 7050058777 ps
CPU time 23.31 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:54:15 AM PDT 24
Peak memory 225740 kb
Host smart-90433934-63e3-44bd-9d93-dd9e8ae3b044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651703533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2651703533
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2636550374
Short name T462
Test name
Test status
Simulation time 13322396629 ps
CPU time 11.43 seconds
Started Jul 01 11:53:52 AM PDT 24
Finished Jul 01 11:54:06 AM PDT 24
Peak memory 221844 kb
Host smart-e112cdaf-8f5d-4ea7-8de4-37a4eeff64b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2636550374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2636550374
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3733980699
Short name T433
Test name
Test status
Simulation time 155850417 ps
CPU time 1.12 seconds
Started Jul 01 11:53:51 AM PDT 24
Finished Jul 01 11:53:55 AM PDT 24
Peak memory 208452 kb
Host smart-610f21c0-1bb2-4a20-8629-8a370b86a3cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733980699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3733980699
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1717888752
Short name T838
Test name
Test status
Simulation time 1681153711 ps
CPU time 16.7 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:54:09 AM PDT 24
Peak memory 217612 kb
Host smart-fede0973-8694-4411-93fa-04765dda261a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717888752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1717888752
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2504229483
Short name T515
Test name
Test status
Simulation time 65173402641 ps
CPU time 15.96 seconds
Started Jul 01 11:53:49 AM PDT 24
Finished Jul 01 11:54:09 AM PDT 24
Peak memory 217464 kb
Host smart-34e59a2a-c948-467a-9153-015e7bd54d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504229483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2504229483
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2675204656
Short name T889
Test name
Test status
Simulation time 377723320 ps
CPU time 2.26 seconds
Started Jul 01 11:53:47 AM PDT 24
Finished Jul 01 11:53:54 AM PDT 24
Peak memory 217368 kb
Host smart-721e7757-4de8-40af-95e7-be9a7adc0700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675204656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2675204656
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.182572645
Short name T524
Test name
Test status
Simulation time 177688840 ps
CPU time 0.75 seconds
Started Jul 01 11:53:48 AM PDT 24
Finished Jul 01 11:53:53 AM PDT 24
Peak memory 206944 kb
Host smart-ecc4a9bb-7a91-43ac-aed7-4d22732d64ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182572645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.182572645
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1381281731
Short name T709
Test name
Test status
Simulation time 1046017788 ps
CPU time 4.4 seconds
Started Jul 01 11:53:48 AM PDT 24
Finished Jul 01 11:53:57 AM PDT 24
Peak memory 225460 kb
Host smart-82e117e3-a38c-443b-96a9-239e4d937692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381281731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1381281731
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3781855941
Short name T305
Test name
Test status
Simulation time 11339129 ps
CPU time 0.7 seconds
Started Jul 01 11:53:59 AM PDT 24
Finished Jul 01 11:54:02 AM PDT 24
Peak memory 206412 kb
Host smart-a801b5ed-f140-432c-9253-a523c776cda9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781855941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3781855941
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3332486792
Short name T559
Test name
Test status
Simulation time 2145622415 ps
CPU time 20.71 seconds
Started Jul 01 11:53:58 AM PDT 24
Finished Jul 01 11:54:20 AM PDT 24
Peak memory 225592 kb
Host smart-e107c288-7958-416a-8cb6-0f8d7a8fecce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332486792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3332486792
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3453049335
Short name T568
Test name
Test status
Simulation time 19209373 ps
CPU time 0.83 seconds
Started Jul 01 11:53:53 AM PDT 24
Finished Jul 01 11:53:56 AM PDT 24
Peak memory 206460 kb
Host smart-2dbe1bea-2850-4144-b13e-69de2ac0f21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453049335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3453049335
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2367082123
Short name T25
Test name
Test status
Simulation time 11769889237 ps
CPU time 38.56 seconds
Started Jul 01 11:53:57 AM PDT 24
Finished Jul 01 11:54:36 AM PDT 24
Peak memory 250256 kb
Host smart-f5ea04c1-56e5-4de1-bd92-9801f8936e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367082123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2367082123
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.821615177
Short name T702
Test name
Test status
Simulation time 4185659806 ps
CPU time 64.15 seconds
Started Jul 01 11:53:58 AM PDT 24
Finished Jul 01 11:55:04 AM PDT 24
Peak memory 253872 kb
Host smart-0cb16872-4791-4e4e-8f63-f15ed1d1d7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821615177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.821615177
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3217912612
Short name T266
Test name
Test status
Simulation time 4929561768 ps
CPU time 79.2 seconds
Started Jul 01 11:53:59 AM PDT 24
Finished Jul 01 11:55:20 AM PDT 24
Peak memory 256156 kb
Host smart-02907715-1b96-40ae-b7d8-a95a9cc61334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217912612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3217912612
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4099857084
Short name T643
Test name
Test status
Simulation time 846208382 ps
CPU time 6.06 seconds
Started Jul 01 11:53:58 AM PDT 24
Finished Jul 01 11:54:05 AM PDT 24
Peak memory 225584 kb
Host smart-88a80220-c7d1-47fe-a805-36bca218844d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099857084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4099857084
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.781740355
Short name T579
Test name
Test status
Simulation time 929871602 ps
CPU time 17.22 seconds
Started Jul 01 11:53:57 AM PDT 24
Finished Jul 01 11:54:16 AM PDT 24
Peak memory 241916 kb
Host smart-b3a1d0a2-a0cf-4eef-8838-d88feb0544ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781740355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.781740355
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4125357900
Short name T419
Test name
Test status
Simulation time 158705364 ps
CPU time 3.73 seconds
Started Jul 01 11:53:56 AM PDT 24
Finished Jul 01 11:54:01 AM PDT 24
Peak memory 233788 kb
Host smart-97731f79-f688-4615-a5ae-b59d18fc06c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125357900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4125357900
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3318348588
Short name T821
Test name
Test status
Simulation time 5372647321 ps
CPU time 35.06 seconds
Started Jul 01 11:53:56 AM PDT 24
Finished Jul 01 11:54:32 AM PDT 24
Peak memory 225720 kb
Host smart-841d15b6-3c67-41da-acd4-1020937749ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318348588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3318348588
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.944784544
Short name T692
Test name
Test status
Simulation time 895614170 ps
CPU time 4.02 seconds
Started Jul 01 11:53:57 AM PDT 24
Finished Jul 01 11:54:03 AM PDT 24
Peak memory 225512 kb
Host smart-777b8f85-9873-4d79-b680-7cf21dcfac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944784544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.944784544
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3384634382
Short name T752
Test name
Test status
Simulation time 11388851380 ps
CPU time 11.41 seconds
Started Jul 01 11:53:59 AM PDT 24
Finished Jul 01 11:54:12 AM PDT 24
Peak memory 233924 kb
Host smart-18f11d9b-ed8f-47e4-aea2-65e794507d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384634382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3384634382
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2724848809
Short name T147
Test name
Test status
Simulation time 988587726 ps
CPU time 5.24 seconds
Started Jul 01 11:54:00 AM PDT 24
Finished Jul 01 11:54:07 AM PDT 24
Peak memory 224004 kb
Host smart-3455dae2-eda0-4cf8-906e-b5b7625b47f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2724848809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2724848809
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3738898233
Short name T974
Test name
Test status
Simulation time 41655442 ps
CPU time 0.93 seconds
Started Jul 01 11:53:59 AM PDT 24
Finished Jul 01 11:54:01 AM PDT 24
Peak memory 208420 kb
Host smart-8d4245e4-0249-404e-9767-7d05c3a6e972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738898233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3738898233
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3942269781
Short name T900
Test name
Test status
Simulation time 3585402190 ps
CPU time 21.61 seconds
Started Jul 01 11:53:52 AM PDT 24
Finished Jul 01 11:54:16 AM PDT 24
Peak memory 217504 kb
Host smart-4b06a603-802c-4a22-92f7-0215d49e6048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942269781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3942269781
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.335842774
Short name T749
Test name
Test status
Simulation time 5820897300 ps
CPU time 16.18 seconds
Started Jul 01 11:53:52 AM PDT 24
Finished Jul 01 11:54:11 AM PDT 24
Peak memory 217524 kb
Host smart-e2816bcc-b8cb-42b7-91b7-36fd364c6d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335842774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.335842774
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4229321738
Short name T993
Test name
Test status
Simulation time 148022199 ps
CPU time 2.15 seconds
Started Jul 01 11:53:56 AM PDT 24
Finished Jul 01 11:53:59 AM PDT 24
Peak memory 217308 kb
Host smart-fa4e4a91-d638-461d-a06e-786fc082da2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229321738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4229321738
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.295166
Short name T563
Test name
Test status
Simulation time 20490053 ps
CPU time 0.74 seconds
Started Jul 01 11:53:54 AM PDT 24
Finished Jul 01 11:53:56 AM PDT 24
Peak memory 206988 kb
Host smart-86861ab0-16b2-4552-8436-39ef4ff580fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.295166
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2808883012
Short name T735
Test name
Test status
Simulation time 2660483638 ps
CPU time 14.22 seconds
Started Jul 01 11:53:59 AM PDT 24
Finished Jul 01 11:54:15 AM PDT 24
Peak memory 225700 kb
Host smart-d9359873-6c1a-4cae-96a5-e564c94ac358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808883012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2808883012
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1682835125
Short name T312
Test name
Test status
Simulation time 12596884 ps
CPU time 0.73 seconds
Started Jul 01 11:54:09 AM PDT 24
Finished Jul 01 11:54:11 AM PDT 24
Peak memory 206360 kb
Host smart-4a2e5411-97ee-4e71-a444-70342a90f1f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682835125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1682835125
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3279851918
Short name T760
Test name
Test status
Simulation time 50930194 ps
CPU time 2.64 seconds
Started Jul 01 11:54:03 AM PDT 24
Finished Jul 01 11:54:07 AM PDT 24
Peak memory 233748 kb
Host smart-3c88dbab-573b-4c8d-bd8a-025e3177554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279851918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3279851918
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2682204425
Short name T1002
Test name
Test status
Simulation time 195628732 ps
CPU time 0.82 seconds
Started Jul 01 11:53:59 AM PDT 24
Finished Jul 01 11:54:01 AM PDT 24
Peak memory 207504 kb
Host smart-455770ab-1450-4bd7-b608-bc509099c7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682204425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2682204425
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3366843916
Short name T945
Test name
Test status
Simulation time 14869472984 ps
CPU time 105.41 seconds
Started Jul 01 11:54:02 AM PDT 24
Finished Jul 01 11:55:49 AM PDT 24
Peak memory 250316 kb
Host smart-a9cc9a75-d7f8-4af2-ae50-c9503a4743ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366843916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3366843916
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2796770741
Short name T1006
Test name
Test status
Simulation time 27006550435 ps
CPU time 59.74 seconds
Started Jul 01 11:54:04 AM PDT 24
Finished Jul 01 11:55:04 AM PDT 24
Peak memory 225832 kb
Host smart-2da6d651-43e9-46ce-84e3-7e5cd9aaea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796770741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2796770741
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1510110055
Short name T460
Test name
Test status
Simulation time 4854699380 ps
CPU time 60.92 seconds
Started Jul 01 11:54:09 AM PDT 24
Finished Jul 01 11:55:12 AM PDT 24
Peak memory 255372 kb
Host smart-b6dcb5b4-b4cd-457d-bc8c-5dc49e475027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510110055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1510110055
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.15711306
Short name T274
Test name
Test status
Simulation time 5405869529 ps
CPU time 43.95 seconds
Started Jul 01 11:54:05 AM PDT 24
Finished Jul 01 11:54:50 AM PDT 24
Peak memory 234896 kb
Host smart-074c1210-1b5c-4929-b81d-becf2bf27598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15711306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.15711306
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.561290951
Short name T561
Test name
Test status
Simulation time 5072800477 ps
CPU time 12.34 seconds
Started Jul 01 11:54:02 AM PDT 24
Finished Jul 01 11:54:16 AM PDT 24
Peak memory 225620 kb
Host smart-54f0be9b-b2bf-4f4b-aa7f-7c08c6e9e7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561290951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.561290951
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3551285214
Short name T528
Test name
Test status
Simulation time 149375193 ps
CPU time 3.18 seconds
Started Jul 01 11:54:05 AM PDT 24
Finished Jul 01 11:54:09 AM PDT 24
Peak memory 233892 kb
Host smart-198b3610-b6f7-43a0-a653-e6462960eb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551285214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3551285214
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.760012672
Short name T797
Test name
Test status
Simulation time 4345924605 ps
CPU time 13.53 seconds
Started Jul 01 11:54:04 AM PDT 24
Finished Jul 01 11:54:19 AM PDT 24
Peak memory 242116 kb
Host smart-49e4f499-f53e-42ae-9347-11dbfdad91d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760012672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.760012672
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2437952096
Short name T937
Test name
Test status
Simulation time 544365676 ps
CPU time 4.2 seconds
Started Jul 01 11:54:04 AM PDT 24
Finished Jul 01 11:54:09 AM PDT 24
Peak memory 241484 kb
Host smart-b3cf692d-5741-498b-b7d2-38fefae24a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437952096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2437952096
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1271928619
Short name T453
Test name
Test status
Simulation time 132778230 ps
CPU time 2.99 seconds
Started Jul 01 11:54:04 AM PDT 24
Finished Jul 01 11:54:08 AM PDT 24
Peak memory 225552 kb
Host smart-146c4c9f-8df1-4c77-b84f-dbe205772d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271928619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1271928619
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1142414769
Short name T142
Test name
Test status
Simulation time 75848244 ps
CPU time 3.62 seconds
Started Jul 01 11:54:03 AM PDT 24
Finished Jul 01 11:54:08 AM PDT 24
Peak memory 220348 kb
Host smart-90adcdf2-4ed2-4c57-98f3-ed73d0fdb774
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1142414769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1142414769
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4218369095
Short name T798
Test name
Test status
Simulation time 50564714899 ps
CPU time 157.87 seconds
Started Jul 01 11:54:09 AM PDT 24
Finished Jul 01 11:56:49 AM PDT 24
Peak memory 256004 kb
Host smart-ddc1264c-05c4-4f9b-b359-d397d95ad8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218369095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4218369095
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2400202155
Short name T1028
Test name
Test status
Simulation time 8246657453 ps
CPU time 43.12 seconds
Started Jul 01 11:53:56 AM PDT 24
Finished Jul 01 11:54:40 AM PDT 24
Peak memory 217416 kb
Host smart-d8987d79-ba54-495f-ab40-f0b3b20817b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400202155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2400202155
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3682944771
Short name T694
Test name
Test status
Simulation time 32308996 ps
CPU time 0.73 seconds
Started Jul 01 11:53:57 AM PDT 24
Finished Jul 01 11:53:59 AM PDT 24
Peak memory 206816 kb
Host smart-612d59ad-b646-475d-8073-9c50bacddc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682944771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3682944771
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3557759223
Short name T578
Test name
Test status
Simulation time 166107144 ps
CPU time 1.5 seconds
Started Jul 01 11:54:02 AM PDT 24
Finished Jul 01 11:54:05 AM PDT 24
Peak memory 217356 kb
Host smart-db176560-d7a7-4e58-82c2-00ff57796e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557759223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3557759223
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2496413426
Short name T487
Test name
Test status
Simulation time 435940452 ps
CPU time 0.83 seconds
Started Jul 01 11:53:59 AM PDT 24
Finished Jul 01 11:54:02 AM PDT 24
Peak memory 206928 kb
Host smart-d3e5a372-6ba9-4417-9415-8cd5686d77b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496413426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2496413426
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2470773368
Short name T589
Test name
Test status
Simulation time 309202031 ps
CPU time 3.91 seconds
Started Jul 01 11:54:03 AM PDT 24
Finished Jul 01 11:54:08 AM PDT 24
Peak memory 233736 kb
Host smart-24e51a78-b950-4af1-b6d7-8dbd3a69348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470773368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2470773368
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1289934777
Short name T987
Test name
Test status
Simulation time 620852992 ps
CPU time 9.25 seconds
Started Jul 01 11:54:08 AM PDT 24
Finished Jul 01 11:54:19 AM PDT 24
Peak memory 233744 kb
Host smart-f5c46f8f-2ea6-4569-9f0e-f202b6c607a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289934777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1289934777
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1944423488
Short name T701
Test name
Test status
Simulation time 29462888 ps
CPU time 0.8 seconds
Started Jul 01 11:54:09 AM PDT 24
Finished Jul 01 11:54:11 AM PDT 24
Peak memory 207372 kb
Host smart-04db8167-cb68-479b-8416-cad95672d2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944423488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1944423488
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1391066775
Short name T979
Test name
Test status
Simulation time 248611573331 ps
CPU time 219.03 seconds
Started Jul 01 11:54:16 AM PDT 24
Finished Jul 01 11:57:57 AM PDT 24
Peak memory 250308 kb
Host smart-a8ce1d19-10d4-4392-8085-3fa2e9bbe4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391066775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1391066775
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2769461582
Short name T480
Test name
Test status
Simulation time 7903870415 ps
CPU time 55.62 seconds
Started Jul 01 11:54:14 AM PDT 24
Finished Jul 01 11:55:11 AM PDT 24
Peak memory 255816 kb
Host smart-b4937cea-1311-4367-a77c-2d96b1106ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769461582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2769461582
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.233555156
Short name T135
Test name
Test status
Simulation time 38765897907 ps
CPU time 156.65 seconds
Started Jul 01 11:54:17 AM PDT 24
Finished Jul 01 11:56:55 AM PDT 24
Peak memory 253168 kb
Host smart-48694964-c346-4c99-acd0-81b7733ba216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233555156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.233555156
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.268621262
Short name T273
Test name
Test status
Simulation time 1101731427 ps
CPU time 7.91 seconds
Started Jul 01 11:54:08 AM PDT 24
Finished Jul 01 11:54:18 AM PDT 24
Peak memory 225516 kb
Host smart-b293e615-6600-44e2-88fd-4af996c74fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268621262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.268621262
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.134888796
Short name T771
Test name
Test status
Simulation time 136168557466 ps
CPU time 237.75 seconds
Started Jul 01 11:54:10 AM PDT 24
Finished Jul 01 11:58:09 AM PDT 24
Peak memory 253516 kb
Host smart-e40f2081-915d-44ca-ba97-c69eacda2a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134888796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.134888796
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.107808692
Short name T733
Test name
Test status
Simulation time 578500255 ps
CPU time 2.94 seconds
Started Jul 01 11:54:10 AM PDT 24
Finished Jul 01 11:54:14 AM PDT 24
Peak memory 225484 kb
Host smart-052cc370-13fc-4729-bff3-5aca3e85f274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107808692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.107808692
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.250085947
Short name T662
Test name
Test status
Simulation time 33940280 ps
CPU time 2.43 seconds
Started Jul 01 11:54:10 AM PDT 24
Finished Jul 01 11:54:14 AM PDT 24
Peak memory 233516 kb
Host smart-71f67eb0-aa0a-443b-8731-abaff3b24472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250085947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.250085947
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.856012834
Short name T58
Test name
Test status
Simulation time 193371841 ps
CPU time 3.94 seconds
Started Jul 01 11:54:08 AM PDT 24
Finished Jul 01 11:54:13 AM PDT 24
Peak memory 225520 kb
Host smart-b6e581df-fb70-4a04-83aa-c965c68bbe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856012834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.856012834
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3095532088
Short name T224
Test name
Test status
Simulation time 498695258 ps
CPU time 4.66 seconds
Started Jul 01 11:54:10 AM PDT 24
Finished Jul 01 11:54:16 AM PDT 24
Peak memory 233724 kb
Host smart-aa488284-f5e4-43ef-bf00-3e1a673605b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095532088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3095532088
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2271454765
Short name T616
Test name
Test status
Simulation time 3279354965 ps
CPU time 10.32 seconds
Started Jul 01 11:54:08 AM PDT 24
Finished Jul 01 11:54:20 AM PDT 24
Peak memory 223272 kb
Host smart-d6cfc21c-80ad-466b-972f-b45c14ed21b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2271454765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2271454765
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.989259326
Short name T417
Test name
Test status
Simulation time 14090970428 ps
CPU time 20.4 seconds
Started Jul 01 11:54:09 AM PDT 24
Finished Jul 01 11:54:31 AM PDT 24
Peak memory 217424 kb
Host smart-bebcf42a-ba0c-497c-bca5-0fdb68cef923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989259326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.989259326
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3294529725
Short name T529
Test name
Test status
Simulation time 1906058383 ps
CPU time 4.69 seconds
Started Jul 01 11:54:08 AM PDT 24
Finished Jul 01 11:54:14 AM PDT 24
Peak memory 217364 kb
Host smart-161306f3-2348-4649-9af1-ebe14addda8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294529725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3294529725
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1411705044
Short name T622
Test name
Test status
Simulation time 421080061 ps
CPU time 3.9 seconds
Started Jul 01 11:54:10 AM PDT 24
Finished Jul 01 11:54:15 AM PDT 24
Peak memory 217376 kb
Host smart-fdfec4c5-b113-441e-9edd-a11e592df854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411705044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1411705044
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2034182986
Short name T748
Test name
Test status
Simulation time 48246682 ps
CPU time 0.87 seconds
Started Jul 01 11:54:09 AM PDT 24
Finished Jul 01 11:54:11 AM PDT 24
Peak memory 206964 kb
Host smart-7f6720c5-a1b7-4f8b-aadc-79d836b41c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034182986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2034182986
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3407290888
Short name T706
Test name
Test status
Simulation time 126617170 ps
CPU time 2.47 seconds
Started Jul 01 11:54:10 AM PDT 24
Finished Jul 01 11:54:13 AM PDT 24
Peak memory 225276 kb
Host smart-5e4d846c-2def-4f6d-a9f5-314c778634e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407290888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3407290888
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3395367742
Short name T849
Test name
Test status
Simulation time 14546789 ps
CPU time 0.72 seconds
Started Jul 01 11:49:18 AM PDT 24
Finished Jul 01 11:49:20 AM PDT 24
Peak memory 206736 kb
Host smart-c25470f2-c175-438a-80a1-576ace170d1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395367742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
395367742
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2088637670
Short name T855
Test name
Test status
Simulation time 778135316 ps
CPU time 3.81 seconds
Started Jul 01 11:49:14 AM PDT 24
Finished Jul 01 11:49:18 AM PDT 24
Peak memory 225552 kb
Host smart-9bc530bc-562b-4aca-b984-d72acfebe320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088637670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2088637670
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1215966869
Short name T590
Test name
Test status
Simulation time 15089281 ps
CPU time 0.79 seconds
Started Jul 01 11:49:08 AM PDT 24
Finished Jul 01 11:49:09 AM PDT 24
Peak memory 207828 kb
Host smart-ddb2dc9a-31bd-4dfa-bbd3-1592e393515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215966869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1215966869
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1137478688
Short name T924
Test name
Test status
Simulation time 92795708 ps
CPU time 0.75 seconds
Started Jul 01 11:49:18 AM PDT 24
Finished Jul 01 11:49:19 AM PDT 24
Peak memory 216912 kb
Host smart-fd37fa2b-9619-449c-9952-4ff9a3e6147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137478688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1137478688
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1858386850
Short name T372
Test name
Test status
Simulation time 6066625647 ps
CPU time 85.09 seconds
Started Jul 01 11:49:19 AM PDT 24
Finished Jul 01 11:50:45 AM PDT 24
Peak memory 258636 kb
Host smart-fc94d6cc-7278-4d85-b13e-fd718c616d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858386850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1858386850
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2679990015
Short name T592
Test name
Test status
Simulation time 2705031435 ps
CPU time 43.34 seconds
Started Jul 01 11:49:16 AM PDT 24
Finished Jul 01 11:50:00 AM PDT 24
Peak memory 241664 kb
Host smart-9026e6f4-3f97-4483-8ae8-f723fc18e149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679990015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2679990015
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3194475888
Short name T573
Test name
Test status
Simulation time 208061004 ps
CPU time 5.14 seconds
Started Jul 01 11:49:12 AM PDT 24
Finished Jul 01 11:49:19 AM PDT 24
Peak memory 233788 kb
Host smart-5341fc17-9438-4344-9e3e-28ab749b645b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194475888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3194475888
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2895490691
Short name T943
Test name
Test status
Simulation time 6499322274 ps
CPU time 17.79 seconds
Started Jul 01 11:49:18 AM PDT 24
Finished Jul 01 11:49:37 AM PDT 24
Peak memory 252200 kb
Host smart-106c3805-9d33-465a-a86a-394dcaedef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895490691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2895490691
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1202910882
Short name T564
Test name
Test status
Simulation time 2835176018 ps
CPU time 27.17 seconds
Started Jul 01 11:49:08 AM PDT 24
Finished Jul 01 11:49:36 AM PDT 24
Peak memory 233876 kb
Host smart-ce68401f-f8f8-4655-b2cf-0b8498e1073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202910882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1202910882
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.544570359
Short name T237
Test name
Test status
Simulation time 3832790196 ps
CPU time 14.87 seconds
Started Jul 01 11:49:08 AM PDT 24
Finished Jul 01 11:49:24 AM PDT 24
Peak memory 238648 kb
Host smart-f13976ae-342e-4c07-9d25-3ecb20f0cc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544570359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.544570359
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3951565050
Short name T626
Test name
Test status
Simulation time 117808025 ps
CPU time 1.07 seconds
Started Jul 01 11:49:07 AM PDT 24
Finished Jul 01 11:49:09 AM PDT 24
Peak memory 217636 kb
Host smart-ce0624a9-d056-4bfa-b799-4a4b8169f827
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951565050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3951565050
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2994654829
Short name T394
Test name
Test status
Simulation time 1133111594 ps
CPU time 2.24 seconds
Started Jul 01 11:49:09 AM PDT 24
Finished Jul 01 11:49:12 AM PDT 24
Peak memory 225420 kb
Host smart-d11589b1-6c29-4639-952d-9595afd0ab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994654829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2994654829
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1599163855
Short name T127
Test name
Test status
Simulation time 826718732 ps
CPU time 9.74 seconds
Started Jul 01 11:49:08 AM PDT 24
Finished Jul 01 11:49:19 AM PDT 24
Peak memory 233812 kb
Host smart-b8a3fec8-8963-4178-8b41-63c6d18f21c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599163855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1599163855
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1660737035
Short name T934
Test name
Test status
Simulation time 2730003942 ps
CPU time 6.02 seconds
Started Jul 01 11:49:18 AM PDT 24
Finished Jul 01 11:49:25 AM PDT 24
Peak memory 222640 kb
Host smart-5f5735b7-0543-42ec-94c8-372ef425709e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1660737035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1660737035
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.588734988
Short name T485
Test name
Test status
Simulation time 54104539 ps
CPU time 1.04 seconds
Started Jul 01 11:49:18 AM PDT 24
Finished Jul 01 11:49:20 AM PDT 24
Peak memory 207716 kb
Host smart-744014f3-88fa-4093-9714-6d74ade88abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588734988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.588734988
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.4080078863
Short name T320
Test name
Test status
Simulation time 13537739 ps
CPU time 0.73 seconds
Started Jul 01 11:49:07 AM PDT 24
Finished Jul 01 11:49:09 AM PDT 24
Peak memory 206688 kb
Host smart-0d183bd1-2b4a-49d8-87cd-98ddd2d81cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080078863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4080078863
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1484027
Short name T846
Test name
Test status
Simulation time 1226563681 ps
CPU time 5.74 seconds
Started Jul 01 11:49:07 AM PDT 24
Finished Jul 01 11:49:13 AM PDT 24
Peak memory 217204 kb
Host smart-c7b06c4f-3131-4a65-87b7-3247ea434004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1484027
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.650775401
Short name T880
Test name
Test status
Simulation time 192515233 ps
CPU time 1.38 seconds
Started Jul 01 11:49:06 AM PDT 24
Finished Jul 01 11:49:08 AM PDT 24
Peak memory 209208 kb
Host smart-3f8c5a58-5bca-4d21-9449-9c1e54a59f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650775401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.650775401
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2290516883
Short name T867
Test name
Test status
Simulation time 35381807 ps
CPU time 0.77 seconds
Started Jul 01 11:49:07 AM PDT 24
Finished Jul 01 11:49:08 AM PDT 24
Peak memory 207032 kb
Host smart-a91e9fdd-b732-44fd-b12d-d5224a5d3203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290516883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2290516883
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1930441095
Short name T790
Test name
Test status
Simulation time 2947170319 ps
CPU time 15.25 seconds
Started Jul 01 11:49:12 AM PDT 24
Finished Jul 01 11:49:29 AM PDT 24
Peak memory 233828 kb
Host smart-e9e7f5f1-04a7-47e5-ac5b-6251f1ceff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930441095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1930441095
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3082271321
Short name T303
Test name
Test status
Simulation time 56811320 ps
CPU time 0.73 seconds
Started Jul 01 11:49:29 AM PDT 24
Finished Jul 01 11:49:32 AM PDT 24
Peak memory 205808 kb
Host smart-c6b254bd-40e3-44e4-aeb0-a83496d81baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082271321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
082271321
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1437747287
Short name T789
Test name
Test status
Simulation time 320184693 ps
CPU time 3.38 seconds
Started Jul 01 11:49:29 AM PDT 24
Finished Jul 01 11:49:34 AM PDT 24
Peak memory 233776 kb
Host smart-5e08cd18-9ef5-4a39-a408-f6065fbfd5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437747287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1437747287
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1318533430
Short name T311
Test name
Test status
Simulation time 42235472 ps
CPU time 0.8 seconds
Started Jul 01 11:49:25 AM PDT 24
Finished Jul 01 11:49:27 AM PDT 24
Peak memory 207516 kb
Host smart-e4e57886-eeb3-4e09-a44f-59eaa0336d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318533430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1318533430
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.969183453
Short name T261
Test name
Test status
Simulation time 67185021836 ps
CPU time 155.36 seconds
Started Jul 01 11:49:31 AM PDT 24
Finished Jul 01 11:52:08 AM PDT 24
Peak memory 264028 kb
Host smart-b8210ab6-b774-45ed-9e2e-80be5453bd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969183453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.969183453
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4086183946
Short name T265
Test name
Test status
Simulation time 42053872229 ps
CPU time 109.74 seconds
Started Jul 01 11:49:29 AM PDT 24
Finished Jul 01 11:51:20 AM PDT 24
Peak memory 274748 kb
Host smart-8bc75062-0976-4910-a36a-fe09bcd64d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086183946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4086183946
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.70925165
Short name T560
Test name
Test status
Simulation time 1412867594 ps
CPU time 14.65 seconds
Started Jul 01 11:49:29 AM PDT 24
Finished Jul 01 11:49:45 AM PDT 24
Peak memory 223060 kb
Host smart-6bd4ff05-5a4e-4aae-890b-de2c2e0ad0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70925165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.70925165
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2209736181
Short name T277
Test name
Test status
Simulation time 12979874692 ps
CPU time 35.15 seconds
Started Jul 01 11:49:28 AM PDT 24
Finished Jul 01 11:50:05 AM PDT 24
Peak memory 242072 kb
Host smart-00ff9942-a85c-474f-afff-dc84681bb0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209736181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2209736181
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.104719300
Short name T884
Test name
Test status
Simulation time 96130159 ps
CPU time 2.13 seconds
Started Jul 01 11:49:24 AM PDT 24
Finished Jul 01 11:49:27 AM PDT 24
Peak memory 224764 kb
Host smart-abb46771-8460-4eca-a2dc-5f95fc509a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104719300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.104719300
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1436842417
Short name T434
Test name
Test status
Simulation time 1823920720 ps
CPU time 8.32 seconds
Started Jul 01 11:49:26 AM PDT 24
Finished Jul 01 11:49:35 AM PDT 24
Peak memory 233712 kb
Host smart-14e38f6a-0fbe-4ccb-abcc-b1c6ffa1e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436842417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1436842417
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2085565856
Short name T854
Test name
Test status
Simulation time 117074084 ps
CPU time 1.1 seconds
Started Jul 01 11:49:25 AM PDT 24
Finished Jul 01 11:49:28 AM PDT 24
Peak memory 217604 kb
Host smart-77ba9f29-c4bc-48a2-82dd-4b3e3fff956b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085565856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2085565856
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2968011332
Short name T812
Test name
Test status
Simulation time 1217363167 ps
CPU time 6.02 seconds
Started Jul 01 11:49:27 AM PDT 24
Finished Jul 01 11:49:34 AM PDT 24
Peak memory 225548 kb
Host smart-055f09c5-b8c8-4633-a34f-40dee104f6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968011332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2968011332
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1483131350
Short name T197
Test name
Test status
Simulation time 10406918786 ps
CPU time 16.93 seconds
Started Jul 01 11:49:24 AM PDT 24
Finished Jul 01 11:49:42 AM PDT 24
Peak memory 233896 kb
Host smart-bb25f7ef-3ab9-4e35-970e-bd469de63649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483131350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1483131350
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2242794201
Short name T799
Test name
Test status
Simulation time 679446267 ps
CPU time 9.57 seconds
Started Jul 01 11:49:30 AM PDT 24
Finished Jul 01 11:49:41 AM PDT 24
Peak memory 224820 kb
Host smart-b55ccebe-f56d-433a-ba27-77d93b93cd47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2242794201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2242794201
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1525702761
Short name T432
Test name
Test status
Simulation time 13092411592 ps
CPU time 52.02 seconds
Started Jul 01 11:49:29 AM PDT 24
Finished Jul 01 11:50:23 AM PDT 24
Peak memory 250464 kb
Host smart-94981475-3d83-43ba-82f7-67b7c0abd54a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525702761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1525702761
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.835531651
Short name T288
Test name
Test status
Simulation time 2805069267 ps
CPU time 14.48 seconds
Started Jul 01 11:49:26 AM PDT 24
Finished Jul 01 11:49:42 AM PDT 24
Peak memory 217440 kb
Host smart-4000bea2-fbcd-43f3-a175-4b036690015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835531651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.835531651
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4236863051
Short name T393
Test name
Test status
Simulation time 10202852175 ps
CPU time 18.44 seconds
Started Jul 01 11:49:25 AM PDT 24
Finished Jul 01 11:49:45 AM PDT 24
Peak memory 217444 kb
Host smart-520e68ea-0751-4ce9-8122-f7c16d6302b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236863051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4236863051
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3319741335
Short name T553
Test name
Test status
Simulation time 54276407 ps
CPU time 1.14 seconds
Started Jul 01 11:49:25 AM PDT 24
Finished Jul 01 11:49:28 AM PDT 24
Peak memory 208952 kb
Host smart-2ea476ea-764d-422d-a0b7-78600087f7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319741335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3319741335
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3261027985
Short name T862
Test name
Test status
Simulation time 74415143 ps
CPU time 0.93 seconds
Started Jul 01 11:49:27 AM PDT 24
Finished Jul 01 11:49:29 AM PDT 24
Peak memory 206904 kb
Host smart-39867559-ad1c-4791-966f-cd9422d4ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261027985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3261027985
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1119726434
Short name T696
Test name
Test status
Simulation time 65468522 ps
CPU time 2.53 seconds
Started Jul 01 11:49:25 AM PDT 24
Finished Jul 01 11:49:29 AM PDT 24
Peak memory 234008 kb
Host smart-7f137e13-ed83-4af7-b79a-7b32fb9fac07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119726434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1119726434
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1092042387
Short name T371
Test name
Test status
Simulation time 14686263 ps
CPU time 0.79 seconds
Started Jul 01 11:49:40 AM PDT 24
Finished Jul 01 11:49:42 AM PDT 24
Peak memory 206320 kb
Host smart-0ab6b32c-353c-420b-bec8-28bfa6a62239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092042387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
092042387
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3702195073
Short name T893
Test name
Test status
Simulation time 1870064716 ps
CPU time 18.7 seconds
Started Jul 01 11:49:38 AM PDT 24
Finished Jul 01 11:49:57 AM PDT 24
Peak memory 225604 kb
Host smart-a3d4595b-2d7f-437e-9e73-9cdd226040b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702195073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3702195073
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3999622944
Short name T618
Test name
Test status
Simulation time 26838352 ps
CPU time 0.82 seconds
Started Jul 01 11:49:29 AM PDT 24
Finished Jul 01 11:49:30 AM PDT 24
Peak memory 207504 kb
Host smart-71ff54f7-79b7-4b5e-a93c-fc29a8139f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999622944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3999622944
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.340435314
Short name T507
Test name
Test status
Simulation time 146795631 ps
CPU time 0.85 seconds
Started Jul 01 11:49:36 AM PDT 24
Finished Jul 01 11:49:38 AM PDT 24
Peak memory 217008 kb
Host smart-f9ef3a46-b80e-4c7f-9029-b862714f0f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340435314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.340435314
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3481666841
Short name T517
Test name
Test status
Simulation time 7287890118 ps
CPU time 126.35 seconds
Started Jul 01 11:49:35 AM PDT 24
Finished Jul 01 11:51:43 AM PDT 24
Peak memory 274292 kb
Host smart-dfa46de3-0b92-4d90-a682-349e40383d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481666841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3481666841
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1701458311
Short name T608
Test name
Test status
Simulation time 43429290825 ps
CPU time 131.07 seconds
Started Jul 01 11:49:39 AM PDT 24
Finished Jul 01 11:51:51 AM PDT 24
Peak memory 250392 kb
Host smart-41206739-31af-4fe1-80f3-5553429be489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701458311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1701458311
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2685714465
Short name T829
Test name
Test status
Simulation time 69197524745 ps
CPU time 145.96 seconds
Started Jul 01 11:49:35 AM PDT 24
Finished Jul 01 11:52:03 AM PDT 24
Peak memory 250236 kb
Host smart-d15ef212-6eb1-4299-b1da-45b4a3f991d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685714465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2685714465
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2318790978
Short name T425
Test name
Test status
Simulation time 2094081113 ps
CPU time 19.89 seconds
Started Jul 01 11:49:35 AM PDT 24
Finished Jul 01 11:49:57 AM PDT 24
Peak memory 229572 kb
Host smart-52353483-5de3-4163-ab48-aaefa9e954c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318790978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2318790978
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.4092366567
Short name T250
Test name
Test status
Simulation time 1352667479 ps
CPU time 7.31 seconds
Started Jul 01 11:49:34 AM PDT 24
Finished Jul 01 11:49:43 AM PDT 24
Peak memory 225568 kb
Host smart-b9d960c0-4f75-471c-8284-78237c59e7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092366567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.4092366567
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2383193755
Short name T357
Test name
Test status
Simulation time 29863010 ps
CPU time 1.03 seconds
Started Jul 01 11:49:30 AM PDT 24
Finished Jul 01 11:49:33 AM PDT 24
Peak memory 217692 kb
Host smart-3875d6b0-7fec-47fe-b6f2-3fab8bd3053e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383193755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2383193755
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1977157061
Short name T691
Test name
Test status
Simulation time 3467024885 ps
CPU time 10.97 seconds
Started Jul 01 11:49:37 AM PDT 24
Finished Jul 01 11:49:49 AM PDT 24
Peak memory 225660 kb
Host smart-482b9cbf-8f08-4e99-9d71-7cca65dd0c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977157061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1977157061
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3012155624
Short name T252
Test name
Test status
Simulation time 9733181546 ps
CPU time 13.99 seconds
Started Jul 01 11:49:36 AM PDT 24
Finished Jul 01 11:49:51 AM PDT 24
Peak memory 234084 kb
Host smart-7e31787e-38a9-4b7a-aa43-9288372d9344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012155624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3012155624
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3982536218
Short name T845
Test name
Test status
Simulation time 619654316 ps
CPU time 9.1 seconds
Started Jul 01 11:49:34 AM PDT 24
Finished Jul 01 11:49:45 AM PDT 24
Peak memory 223512 kb
Host smart-a62baa35-139f-4094-b60d-8bb547cb9c4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3982536218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3982536218
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2469350269
Short name T16
Test name
Test status
Simulation time 93607497 ps
CPU time 0.87 seconds
Started Jul 01 11:49:39 AM PDT 24
Finished Jul 01 11:49:41 AM PDT 24
Peak memory 207740 kb
Host smart-a95353d5-bf3a-4b38-8ff2-b2d4475436a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469350269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2469350269
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2771833732
Short name T861
Test name
Test status
Simulation time 1184553924 ps
CPU time 12.02 seconds
Started Jul 01 11:49:34 AM PDT 24
Finished Jul 01 11:49:48 AM PDT 24
Peak memory 217764 kb
Host smart-283b35f8-7a78-43e6-a890-48892396e8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771833732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2771833732
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1954794839
Short name T581
Test name
Test status
Simulation time 2318646744 ps
CPU time 4.03 seconds
Started Jul 01 11:49:33 AM PDT 24
Finished Jul 01 11:49:38 AM PDT 24
Peak memory 217400 kb
Host smart-5ecfb78f-f5df-4bb0-8689-f96ca4cf1333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954794839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1954794839
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1673047323
Short name T336
Test name
Test status
Simulation time 89886894 ps
CPU time 1.45 seconds
Started Jul 01 11:49:33 AM PDT 24
Finished Jul 01 11:49:36 AM PDT 24
Peak memory 217352 kb
Host smart-8772c93c-1ca0-45fa-b5b2-9e7a5ace10c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673047323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1673047323
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2088194127
Short name T506
Test name
Test status
Simulation time 15810631 ps
CPU time 0.77 seconds
Started Jul 01 11:49:34 AM PDT 24
Finished Jul 01 11:49:37 AM PDT 24
Peak memory 206972 kb
Host smart-5644a77b-4421-4aad-a2b4-3965df4c7d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088194127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2088194127
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2213486023
Short name T754
Test name
Test status
Simulation time 35869254619 ps
CPU time 8.72 seconds
Started Jul 01 11:49:38 AM PDT 24
Finished Jul 01 11:49:47 AM PDT 24
Peak memory 225696 kb
Host smart-5d53ffb1-d116-4dfb-8bda-41616ed759c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213486023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2213486023
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3851850296
Short name T451
Test name
Test status
Simulation time 51316787 ps
CPU time 0.74 seconds
Started Jul 01 11:49:50 AM PDT 24
Finished Jul 01 11:49:52 AM PDT 24
Peak memory 205740 kb
Host smart-c1a3298f-c321-4f95-96d0-97bf92f2e16a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851850296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
851850296
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3458786551
Short name T173
Test name
Test status
Simulation time 137789646 ps
CPU time 3.52 seconds
Started Jul 01 11:49:45 AM PDT 24
Finished Jul 01 11:49:49 AM PDT 24
Peak memory 225548 kb
Host smart-206ab5e5-daee-404d-afc8-29b6d8ae7515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458786551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3458786551
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2088878676
Short name T721
Test name
Test status
Simulation time 38489039 ps
CPU time 0.84 seconds
Started Jul 01 11:49:40 AM PDT 24
Finished Jul 01 11:49:42 AM PDT 24
Peak memory 207476 kb
Host smart-286ab26d-3cfd-4c9d-8f7e-ba8345b4a37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088878676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2088878676
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2661348735
Short name T231
Test name
Test status
Simulation time 12140626134 ps
CPU time 67.62 seconds
Started Jul 01 11:49:46 AM PDT 24
Finished Jul 01 11:50:54 AM PDT 24
Peak memory 252256 kb
Host smart-96646e81-029b-4bb0-931a-e4114dd3a4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661348735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2661348735
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2087903528
Short name T775
Test name
Test status
Simulation time 24406541765 ps
CPU time 51.11 seconds
Started Jul 01 11:49:45 AM PDT 24
Finished Jul 01 11:50:37 AM PDT 24
Peak memory 256600 kb
Host smart-c069c84c-945d-4141-bf9c-83546e4c7596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087903528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2087903528
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3551558184
Short name T633
Test name
Test status
Simulation time 298068282 ps
CPU time 7.84 seconds
Started Jul 01 11:49:44 AM PDT 24
Finished Jul 01 11:49:53 AM PDT 24
Peak memory 225532 kb
Host smart-e0f22c94-afe8-4de3-b0e9-e00f52c2e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551558184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3551558184
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.25921441
Short name T562
Test name
Test status
Simulation time 31156948 ps
CPU time 0.76 seconds
Started Jul 01 11:49:46 AM PDT 24
Finished Jul 01 11:49:47 AM PDT 24
Peak memory 216924 kb
Host smart-dfec3485-4990-4825-991a-75c7e443ffe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25921441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.25921441
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2535515900
Short name T511
Test name
Test status
Simulation time 102298646 ps
CPU time 3.23 seconds
Started Jul 01 11:49:44 AM PDT 24
Finished Jul 01 11:49:48 AM PDT 24
Peak memory 233788 kb
Host smart-1d44bf67-c3f3-4f8c-86f0-f72eab68200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535515900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2535515900
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.4157368702
Short name T747
Test name
Test status
Simulation time 2528938322 ps
CPU time 10.66 seconds
Started Jul 01 11:49:46 AM PDT 24
Finished Jul 01 11:49:57 AM PDT 24
Peak memory 233884 kb
Host smart-6da84fc2-e04e-4629-854e-217009b3a946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157368702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.4157368702
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2406653215
Short name T871
Test name
Test status
Simulation time 32509107 ps
CPU time 1.06 seconds
Started Jul 01 11:49:38 AM PDT 24
Finished Jul 01 11:49:40 AM PDT 24
Peak memory 218960 kb
Host smart-c458f9e9-1b66-4d12-b86f-63afb27a731d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406653215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2406653215
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3506385821
Short name T990
Test name
Test status
Simulation time 678932196 ps
CPU time 2.56 seconds
Started Jul 01 11:49:39 AM PDT 24
Finished Jul 01 11:49:42 AM PDT 24
Peak memory 225564 kb
Host smart-55219b51-fe58-4d31-a3ff-7bc57099daf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506385821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3506385821
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1157196615
Short name T710
Test name
Test status
Simulation time 6328585985 ps
CPU time 8.97 seconds
Started Jul 01 11:49:40 AM PDT 24
Finished Jul 01 11:49:50 AM PDT 24
Peak memory 233864 kb
Host smart-656c527c-de14-49a9-a4a3-151f9946bc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157196615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1157196615
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1876446550
Short name T466
Test name
Test status
Simulation time 2989959952 ps
CPU time 9.68 seconds
Started Jul 01 11:49:47 AM PDT 24
Finished Jul 01 11:49:57 AM PDT 24
Peak memory 221820 kb
Host smart-d24550d5-e9cf-4631-b3c4-efa23140303c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1876446550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1876446550
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1592499730
Short name T15
Test name
Test status
Simulation time 36381954478 ps
CPU time 364.58 seconds
Started Jul 01 11:49:45 AM PDT 24
Finished Jul 01 11:55:51 AM PDT 24
Peak memory 266620 kb
Host smart-b0c9926f-dcc2-4a1d-837a-497098c0326e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592499730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1592499730
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3442976272
Short name T576
Test name
Test status
Simulation time 616565775 ps
CPU time 6.78 seconds
Started Jul 01 11:49:39 AM PDT 24
Finished Jul 01 11:49:47 AM PDT 24
Peak memory 218980 kb
Host smart-c0aa3cbf-3616-4b3c-838b-0ef5e1e553a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442976272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3442976272
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1530898391
Short name T455
Test name
Test status
Simulation time 1072800418 ps
CPU time 4.86 seconds
Started Jul 01 11:49:38 AM PDT 24
Finished Jul 01 11:49:44 AM PDT 24
Peak memory 217392 kb
Host smart-139fa386-64cb-48b2-b526-c9135851d29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530898391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1530898391
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4098669932
Short name T756
Test name
Test status
Simulation time 74606715 ps
CPU time 1.58 seconds
Started Jul 01 11:49:40 AM PDT 24
Finished Jul 01 11:49:42 AM PDT 24
Peak memory 217312 kb
Host smart-b64f6c9b-46fc-4303-8edb-649d25ae867c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098669932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4098669932
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1716048048
Short name T339
Test name
Test status
Simulation time 74956110 ps
CPU time 0.78 seconds
Started Jul 01 11:49:42 AM PDT 24
Finished Jul 01 11:49:43 AM PDT 24
Peak memory 207032 kb
Host smart-18b52237-fe69-4e8d-a808-9267f4605e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716048048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1716048048
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.892459119
Short name T437
Test name
Test status
Simulation time 5779062453 ps
CPU time 7.05 seconds
Started Jul 01 11:49:45 AM PDT 24
Finished Jul 01 11:49:53 AM PDT 24
Peak memory 225692 kb
Host smart-970e407b-0301-450b-be7d-cfea4a6931d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892459119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.892459119
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1308571282
Short name T739
Test name
Test status
Simulation time 24099748 ps
CPU time 0.76 seconds
Started Jul 01 11:49:56 AM PDT 24
Finished Jul 01 11:49:57 AM PDT 24
Peak memory 206408 kb
Host smart-e3b42ddb-20fa-45e1-ad32-b5217ba7de4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308571282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
308571282
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4069349411
Short name T714
Test name
Test status
Simulation time 185083943 ps
CPU time 3.32 seconds
Started Jul 01 11:49:57 AM PDT 24
Finished Jul 01 11:50:01 AM PDT 24
Peak memory 225544 kb
Host smart-fe860014-2ccf-49dd-995b-54875e9a6755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069349411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4069349411
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.231070357
Short name T929
Test name
Test status
Simulation time 16021237 ps
CPU time 0.78 seconds
Started Jul 01 11:49:50 AM PDT 24
Finished Jul 01 11:49:51 AM PDT 24
Peak memory 207500 kb
Host smart-53a9ff38-b043-4bad-b425-5a74ece23f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231070357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.231070357
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3529844282
Short name T601
Test name
Test status
Simulation time 188717125903 ps
CPU time 539.48 seconds
Started Jul 01 11:49:56 AM PDT 24
Finished Jul 01 11:58:56 AM PDT 24
Peak memory 266328 kb
Host smart-4657fb09-f55e-4cd0-9957-4b167fe71507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529844282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3529844282
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.587721479
Short name T734
Test name
Test status
Simulation time 5022790512 ps
CPU time 31.85 seconds
Started Jul 01 11:49:56 AM PDT 24
Finished Jul 01 11:50:29 AM PDT 24
Peak memory 239264 kb
Host smart-5ab1820b-a020-464c-8e88-19ce7752bd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587721479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.587721479
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2845682526
Short name T550
Test name
Test status
Simulation time 7622655782 ps
CPU time 28.52 seconds
Started Jul 01 11:49:58 AM PDT 24
Finished Jul 01 11:50:27 AM PDT 24
Peak memory 249980 kb
Host smart-113fa0b7-ce5c-4428-9d62-98e8dfcab8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845682526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2845682526
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1843937326
Short name T711
Test name
Test status
Simulation time 314174604 ps
CPU time 8.15 seconds
Started Jul 01 11:49:55 AM PDT 24
Finished Jul 01 11:50:04 AM PDT 24
Peak memory 234808 kb
Host smart-7137326e-300a-45d5-a940-25d17fea8d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843937326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1843937326
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1599844321
Short name T260
Test name
Test status
Simulation time 41017866576 ps
CPU time 53.31 seconds
Started Jul 01 11:49:56 AM PDT 24
Finished Jul 01 11:50:51 AM PDT 24
Peak memory 225716 kb
Host smart-78e33cff-88ae-483e-b14f-414ff72eaae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599844321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1599844321
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1362694963
Short name T397
Test name
Test status
Simulation time 109073508 ps
CPU time 2.55 seconds
Started Jul 01 11:49:49 AM PDT 24
Finished Jul 01 11:49:53 AM PDT 24
Peak memory 233796 kb
Host smart-35e1dc5b-c0f7-4590-b1e9-e62163aaea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362694963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1362694963
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3999134162
Short name T886
Test name
Test status
Simulation time 1001115676 ps
CPU time 14.37 seconds
Started Jul 01 11:49:49 AM PDT 24
Finished Jul 01 11:50:05 AM PDT 24
Peak memory 233668 kb
Host smart-69e3e76e-4f1c-4104-9b0b-a88633e108d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999134162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3999134162
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.4093290617
Short name T37
Test name
Test status
Simulation time 28240714 ps
CPU time 1.1 seconds
Started Jul 01 11:49:49 AM PDT 24
Finished Jul 01 11:49:51 AM PDT 24
Peak memory 217604 kb
Host smart-d0fa5103-dc73-4bb9-99d8-2666a3c7ce03
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093290617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4093290617
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1389937121
Short name T784
Test name
Test status
Simulation time 3286425850 ps
CPU time 5.37 seconds
Started Jul 01 11:49:51 AM PDT 24
Finished Jul 01 11:49:57 AM PDT 24
Peak memory 233884 kb
Host smart-dfaaf528-2dcb-448d-a6f0-452400a1127d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389937121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1389937121
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1816665212
Short name T743
Test name
Test status
Simulation time 1959892930 ps
CPU time 7.96 seconds
Started Jul 01 11:49:49 AM PDT 24
Finished Jul 01 11:49:58 AM PDT 24
Peak memory 241888 kb
Host smart-3f4192d6-9c7c-4e47-a1d7-1ac5e29c3d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816665212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1816665212
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1383636452
Short name T686
Test name
Test status
Simulation time 1750328895 ps
CPU time 8.63 seconds
Started Jul 01 11:49:56 AM PDT 24
Finished Jul 01 11:50:06 AM PDT 24
Peak memory 223320 kb
Host smart-92e07cfc-7b6d-4275-8ed8-95b70299e7c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1383636452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1383636452
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3232112657
Short name T299
Test name
Test status
Simulation time 78631789607 ps
CPU time 277.44 seconds
Started Jul 01 11:49:56 AM PDT 24
Finished Jul 01 11:54:34 AM PDT 24
Peak memory 250380 kb
Host smart-7eecadc3-5381-4b40-868f-bd1dda7bbf14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232112657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3232112657
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2785307422
Short name T612
Test name
Test status
Simulation time 2910226955 ps
CPU time 9.83 seconds
Started Jul 01 11:49:49 AM PDT 24
Finished Jul 01 11:50:00 AM PDT 24
Peak memory 217480 kb
Host smart-7856086a-4ef4-45f8-b137-8256a6f25e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785307422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2785307422
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2584646598
Short name T989
Test name
Test status
Simulation time 193714368 ps
CPU time 1.64 seconds
Started Jul 01 11:49:51 AM PDT 24
Finished Jul 01 11:49:53 AM PDT 24
Peak memory 208936 kb
Host smart-146d39a6-6e93-4deb-b7d6-5e6b579594b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584646598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2584646598
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2136736995
Short name T477
Test name
Test status
Simulation time 36678249 ps
CPU time 0.9 seconds
Started Jul 01 11:49:49 AM PDT 24
Finished Jul 01 11:49:51 AM PDT 24
Peak memory 208172 kb
Host smart-29849b04-8b95-4ec7-be96-954c418e7fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136736995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2136736995
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.76824181
Short name T527
Test name
Test status
Simulation time 127943805 ps
CPU time 0.88 seconds
Started Jul 01 11:49:49 AM PDT 24
Finished Jul 01 11:49:51 AM PDT 24
Peak memory 206928 kb
Host smart-cec834d4-cecb-46be-927d-1d70796a8ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76824181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.76824181
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1787728474
Short name T730
Test name
Test status
Simulation time 1662187169 ps
CPU time 8.12 seconds
Started Jul 01 11:49:51 AM PDT 24
Finished Jul 01 11:50:00 AM PDT 24
Peak memory 237476 kb
Host smart-51a86155-694e-49db-9b19-ba337bda8d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787728474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1787728474
Directory /workspace/9.spi_device_upload/latest
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