Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2560533	1			T2	1		T3	1		T4	6
all_values[1]	2560533	1			T2	1		T3	1		T4	6
all_values[2]	2560533	1			T2	1		T3	1		T4	6
all_values[3]	2560533	1			T2	1		T3	1		T4	6
all_values[4]	2560533	1			T2	1		T3	1		T4	6
all_values[5]	2560533	1			T2	1		T3	1		T4	6
all_values[6]	2560533	1			T2	1		T3	1		T4	6
all_values[7]	2560533	1			T2	1		T3	1		T4	6

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20234162

1

T2

8

T3

8

T4

48

auto[1]

250102

1

T18

28

T19

78

T21

88

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20460746

1

T2

8

T3

8

T4

48

auto[1]

23518

1

T31

236

T36

180

T18

165

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2498812	1			T2	1		T3	1		T4	6
all_values[0]	auto[0]	auto[1]	10839	1			T31	125		T36	91		T18	99
all_values[0]	auto[1]	auto[0]	50434	1			T18	3		T19	8		T21	4
all_values[0]	auto[1]	auto[1]	448	1			T18	3		T19	5		T21	5
all_values[1]	auto[0]	auto[0]	2531128	1			T2	1		T3	1		T4	6
all_values[1]	auto[0]	auto[1]	7179	1			T31	111		T36	89		T18	49
all_values[1]	auto[1]	auto[0]	21736	1			T18	4		T19	2		T21	4
all_values[1]	auto[1]	auto[1]	490	1			T18	1		T19	9		T21	9
all_values[2]	auto[0]	auto[0]	2500164	1			T2	1		T3	1		T4	6
all_values[2]	auto[0]	auto[1]	2342	1			T81	45		T58	46		T19	2
all_values[2]	auto[1]	auto[0]	57610	1			T18	4		T19	2		T21	6
all_values[2]	auto[1]	auto[1]	417	1			T18	1		T19	5		T21	6
all_values[3]	auto[0]	auto[0]	2538124	1			T2	1		T3	1		T4	6
all_values[3]	auto[0]	auto[1]	214	1			T18	4		T166	3		T150	1
all_values[3]	auto[1]	auto[0]	22039	1			T19	14		T21	6		T37	5
all_values[3]	auto[1]	auto[1]	156	1			T19	2		T21	6		T37	4
all_values[4]	auto[0]	auto[0]	2548241	1			T2	1		T3	1		T4	6
all_values[4]	auto[0]	auto[1]	196	1			T18	3		T19	2		T21	7
all_values[4]	auto[1]	auto[0]	11902	1			T19	10		T21	5		T24	1
all_values[4]	auto[1]	auto[1]	194	1			T19	2		T21	6		T38	1
all_values[5]	auto[0]	auto[0]	2549567	1			T2	1		T3	1		T4	6
all_values[5]	auto[0]	auto[1]	166	1			T18	1		T19	6		T21	6
all_values[5]	auto[1]	auto[0]	10650	1			T18	4		T21	7		T24	1
all_values[5]	auto[1]	auto[1]	150	1			T18	1		T19	2		T21	1
all_values[6]	auto[0]	auto[0]	2499285	1			T2	1		T3	1		T4	6
all_values[6]	auto[0]	auto[1]	168	1			T19	5		T21	6		T37	2
all_values[6]	auto[1]	auto[0]	60885	1			T18	3		T19	4		T21	3
all_values[6]	auto[1]	auto[1]	195	1			T18	3		T19	3		T21	10
all_values[7]	auto[0]	auto[0]	2547545	1			T2	1		T3	1		T4	6
all_values[7]	auto[0]	auto[1]	192	1			T19	4		T21	8		T24	2
all_values[7]	auto[1]	auto[0]	12624	1			T18	1		T19	4		T21	5
all_values[7]	auto[1]	auto[1]	172	1			T19	6		T21	5		T24	1