Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35331	1			T3	6		T4	2		T13	8
auto[SpiFlashAddrCfg]	7480	1			T3	8		T13	5		T14	8
auto[SpiFlashAddr3b]	8969	1			T13	5		T14	6		T15	21
auto[SpiFlashAddr4b]	7653	1			T3	4		T11	4		T13	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33581

1

T4

2

T11

4

T13

12

auto[1]

25852

1

T3

18

T13

8

T14

26

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31137

1

T3

6

T4

2

T11

2

auto[1]

28296

1

T3

12

T11

2

T13

7

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39872	1			T3	8		T4	2		T13	12
values[1]	1021	1			T15	1		T50	4		T136	1
values[2]	1560	1			T3	2		T15	2		T16	2
values[3]	1419	1			T15	4		T16	2		T28	3
values[4]	1295	1			T14	2		T15	1		T16	2
values[5]	1449	1			T3	6		T14	4		T15	2
values[6]	1525	1			T11	2		T13	2		T14	4
values[7]	1501	1			T55	6		T52	1		T56	4
values[8]	9791	1			T3	2		T11	2		T13	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28740

1

T3

18

T4

2

T11

4

auto[1]

30693

1

T13

20

T28

6

T40

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56145

1

T3

18

T4

2

T11

4

write

3288

1

T13

3

T14

6

T15

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18852

1

T3

6

T4

2

T13

8

valids[0x1]

40581

1

T3

12

T11

4

T13

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1491	1			T3	4		T13	1		T15	3
internal_process_ops[0x5a]	1510	1			T13	2		T15	1		T41	2
internal_process_ops[0x05]	21832	1			T13	1		T14	2		T15	19
internal_process_ops[0x35]	1524	1			T13	1		T14	4		T27	2
internal_process_ops[0x15]	1537	1			T15	2		T55	4		T51	8
internal_process_ops[0x03]	1073	1			T11	2		T14	2		T15	2
internal_process_ops[0x0b]	1052	1			T3	6		T11	2		T15	3
internal_process_ops[0x3b]	1028	1			T15	2		T16	2		T43	3
internal_process_ops[0x6b]	1059	1			T3	2		T14	4		T15	3
internal_process_ops[0xbb]	1027	1			T14	4		T15	1		T28	3
internal_process_ops[0xeb]	1025	1			T15	3		T16	2		T41	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57762

1

T3

18

T4

2

T11

4

auto[1]

1671

1

T13

3

T14

6

T55

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57136

1

T3

18

T4

2

T11

4

auto[1]

2297

1

T13

1

T15

3

T55

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9008

1

T4

2

T15

27

T27

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6401

1

T3

6

T14

6

T15

11

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1901

1

T15

4

T16

2

T41

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1689

1

T3

8

T14

8

T15

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2464

1

T15

13

T16

16

T41

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2038

1

T14

4

T15

6

T56

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1992

1

T11

4

T15

4

T41

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1729

1

T3

4

T14

2

T15

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

122

1

T50

2

T57

3

T184

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

89

1

T53

1

T57

1

T59

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

77

1

T57

2

T58

2

T62

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

113

1

T57

2

T58

2

T65

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

104

1

T57

3

T184

1

T23

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

104

1

T57

1

T62

2

T23

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

75

1

T15

2

T57

2

T184

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

112

1

T56

2

T53

1

T57

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

75

1

T62

1

T21

1

T23

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

85

1

T62

1

T59

1

T23

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

77

1

T15

2

T53

2

T23

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

95

1

T14

2

T57

2

T58

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

114

1

T53

2

T62

1

T185

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

74

1

T57

2

T58

3

T59

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

86

1

T53

3

T58

3

T59

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

116

1

T14

4

T53

1

T57

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11490

1

T13

7

T55

41

T52

58

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7614

1

T13

1

T55

77

T52

46

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1573

1

T13

2

T40

1

T43

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1497

1

T13

3

T55

12

T52

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1897

1

T43

3

T55

11

T120

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1805

1

T13

3

T55

7

T52

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1588

1

T13

1

T28

6

T40

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1459

1

T55

5

T52

2

T51

20

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

129

1

T80

1

T18

2

T81

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

91

1

T66

1

T155

1

T186

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

90

1

T51

6

T80

1

T18

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

107

1

T31

3

T18

2

T81

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

120

1

T55

1

T52

2

T81

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

98

1

T36

2

T80

1

T81

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

107

1

T36

1

T80

4

T81

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

100

1

T55

1

T52

1

T51

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

103

1

T51

2

T31

3

T81

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

111

1

T13

2

T31

2

T18

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

98

1

T55

2

T31

3

T81

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

121

1

T52

2

T20

1

T155

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

117

1

T80

1

T66

3

T81

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

132

1

T36

1

T66

1

T81

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

123

1

T52

1

T80

2

T81

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

123

1

T13

1

T55

1

T51

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3516	1			T3	2		T4	2		T15	12
auto[0]	values[0]	valids[0x1]	14570	1			T3	6		T14	12		T15	32
auto[0]	values[1]	valids[0x1]	513	1			T15	1		T50	4		T53	4
auto[0]	values[2]	valids[0x0]	547	1			T3	2		T15	2		T16	2
auto[0]	values[2]	valids[0x1]	299	1			T53	4		T184	2		T58	3
auto[0]	values[3]	valids[0x0]	529	1			T15	3		T16	2		T53	2
auto[0]	values[3]	valids[0x1]	266	1			T15	1		T53	3		T57	1
auto[0]	values[4]	valids[0x0]	490	1			T15	1		T16	2		T60	2
auto[0]	values[4]	valids[0x1]	230	1			T14	2		T53	2		T57	2
auto[0]	values[5]	valids[0x0]	529	1			T14	4		T15	2		T53	1
auto[0]	values[5]	valids[0x1]	299	1			T3	6		T16	4		T50	2
auto[0]	values[6]	valids[0x0]	547	1			T14	4		T15	2		T16	2
auto[0]	values[6]	valids[0x1]	312	1			T11	2		T53	2		T187	2
auto[0]	values[7]	valids[0x0]	560	1			T56	4		T53	1		T57	8
auto[0]	values[7]	valids[0x1]	242	1			T53	1		T57	7		T58	1
auto[0]	values[8]	valids[0x0]	3256	1			T3	2		T14	2		T15	9
auto[0]	values[8]	valids[0x1]	2035	1			T11	2		T14	2		T15	12
auto[1]	values[0]	valids[0x0]	3864	1			T13	5		T55	31		T52	11
auto[1]	values[0]	valids[0x1]	17922	1			T13	7		T55	101		T52	100
auto[1]	values[1]	valids[0x1]	508	1			T136	1		T51	11		T31	10
auto[1]	values[2]	valids[0x0]	416	1			T55	4		T52	1		T51	12
auto[1]	values[2]	valids[0x1]	298	1			T55	2		T51	1		T31	3
auto[1]	values[3]	valids[0x0]	392	1			T28	3		T40	3		T55	3
auto[1]	values[3]	valids[0x1]	232	1			T43	2		T51	1		T31	5
auto[1]	values[4]	valids[0x0]	324	1			T52	4		T51	5		T31	1
auto[1]	values[4]	valids[0x1]	251	1			T52	3		T51	4		T36	1
auto[1]	values[5]	valids[0x0]	366	1			T40	1		T55	1		T136	1
auto[1]	values[5]	valids[0x1]	255	1			T55	1		T120	1		T51	7
auto[1]	values[6]	valids[0x0]	401	1			T13	2		T55	1		T51	3
auto[1]	values[6]	valids[0x1]	265	1			T55	2		T51	5		T36	1
auto[1]	values[7]	valids[0x0]	421	1			T55	3		T52	1		T51	3
auto[1]	values[7]	valids[0x1]	278	1			T55	3		T51	3		T31	2
auto[1]	values[8]	valids[0x0]	2694	1			T13	1		T43	3		T55	10
auto[1]	values[8]	valids[0x1]	1806	1			T13	5		T28	3		T55	8