Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3219023

1

T2

1632

T3

1

T4

1

auto[1]

31542

1

T13

3

T15

17

T55

70

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

859324

1

T2

1632

T3

1

T4

1

auto[1]

2391241

1

T13

193

T15

1737

T55

3505

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	631471	1			T2	181		T3	1		T4	1
auto[524288:1048575]	355114	1			T2	203		T15	7		T27	5
auto[1048576:1572863]	358340	1			T2	83		T11	4546		T15	7
auto[1572864:2097151]	393108	1			T2	219		T13	149		T15	4
auto[2097152:2621439]	338203	1			T2	834		T5	122		T11	2
auto[2621440:3145727]	351823	1			T2	28		T5	121		T11	249
auto[3145728:3670015]	413584	1			T2	41		T15	1		T27	568
auto[3670016:4194303]	408922	1			T2	43		T5	2		T27	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2424216

1

T2

469

T3

1

T4

1

auto[1]

826349

1

T2

1163

T5

679

T11

9912

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2810575

1

T2

1632

T3

1

T4

1

auto[1]

439990

1

T13

5

T15

1483

T55

2939

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	210608	1			T2	181		T3	1		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	360213	1			T13	65		T50	2		T111	2927
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	68659	1			T2	203		T15	2		T27	5
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	237169	1			T15	1		T55	260		T111	2532
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	110931	1			T2	83		T11	4546		T27	770
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	181768	1			T51	128		T31	4		T53	640
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	91895	1			T2	219		T13	17		T15	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	237728	1			T13	128		T111	2494		T51	1403
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	86496	1			T2	834		T5	122		T11	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	190008	1			T111	2093		T51	4		T31	388
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	76163	1			T2	28		T5	121		T11	249
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	232326	1			T15	261		T55	1		T111	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	98089	1			T2	41		T15	1		T27	568
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	260192	1			T31	514		T53	1		T36	513
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	102620	1			T2	43		T5	2		T27	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	239664	1			T55	256		T51	896		T31	513
auto[0]	auto[1]	auto[0:524287]	auto[0]	1680	1			T13	1		T15	6		T55	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	54971	1			T15	1460		T55	1055		T80	471
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2032	1			T55	5		T51	16		T31	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	42424	1			T55	384		T31	1904		T20	531
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	525	1			T15	3		T55	3		T80	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	61182	1			T15	1		T55	1224		T66	1238
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	675	1			T13	4		T52	1		T51	16
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	58516	1			T52	1		T36	771		T57	2840
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	848	1			T51	4		T66	2		T57	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	57348	1			T31	237		T66	768		T57	513
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1011	1			T55	1		T36	1		T57	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	38577	1			T55	5		T53	5		T36	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2671	1			T51	15		T80	2		T81	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	49745	1			T55	256		T80	671		T18	512
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	614	1			T55	2		T52	3		T51	26
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	61675	1			T52	1		T51	640		T66	512
auto[1]	auto[0]	auto[0:524287]	auto[0]	441	1			T13	3		T50	2		T52	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3091	1			T50	25		T52	24		T31	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	383	1			T15	1		T55	4		T52	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3836	1			T15	3		T55	45		T52	21
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	450	1			T31	1		T18	1		T66	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2982	1			T31	9		T66	1		T57	14
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	406	1			T51	8		T53	2		T36	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3164	1			T53	27		T36	7		T58	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	389	1			T51	3		T31	4		T18	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2221	1			T31	16		T18	3		T57	36
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	380	1			T55	1		T52	1		T51	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2868	1			T55	18		T52	5		T31	10
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	333	1			T31	2		T53	1		T36	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1980	1			T31	3		T53	3		T36	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	375	1			T51	21		T31	1		T53	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2747	1			T51	128		T31	2		T53	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	64	1			T15	1		T18	1		T57	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	403	1			T15	9		T18	7		T57	27
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	70	1			T62	3		T110	3		T250	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	541	1			T250	24		T251	5		T252	44
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	77	1			T15	1		T55	1		T62	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	425	1			T15	2		T55	1		T95	12
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	82	1			T52	1		T57	1		T81	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	642	1			T52	17		T57	46		T81	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	97	1			T51	3		T57	1		T155	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	796	1			T57	19		T155	120		T23	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	53	1			T51	2		T36	1		T57	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	445	1			T36	5		T57	5		T253	13
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	94	1			T80	2		T110	6		T206	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	480	1			T80	32		T54	17		T38	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	113	1			T52	1		T57	1		T81	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1114	1			T52	17		T57	30		T184	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1964312	1			T2	469		T3	1		T4	1
auto[0]	auto[0]	auto[1]	820217	1			T2	1163		T5	679		T11	9912
auto[0]	auto[1]	auto[0]	429012	1			T13	5		T15	1468		T55	2936
auto[0]	auto[1]	auto[1]	5482	1			T15	2		T55	1		T80	1
auto[1]	auto[0]	auto[0]	25495	1			T13	2		T15	4		T55	68
auto[1]	auto[0]	auto[1]	551	1			T13	1		T50	1		T52	2
auto[1]	auto[1]	auto[0]	5397	1			T15	13		T55	2		T52	34
auto[1]	auto[1]	auto[1]	99	1			T52	2		T51	1		T57	1