Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2560533	1			T2	1		T3	1		T4	6
all_pins[1]	2560533	1			T2	1		T3	1		T4	6
all_pins[2]	2560533	1			T2	1		T3	1		T4	6
all_pins[3]	2560533	1			T2	1		T3	1		T4	6
all_pins[4]	2560533	1			T2	1		T3	1		T4	6
all_pins[5]	2560533	1			T2	1		T3	1		T4	6
all_pins[6]	2560533	1			T2	1		T3	1		T4	6
all_pins[7]	2560533	1			T2	1		T3	1		T4	6

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20422020	1			T2	8		T3	8		T4	48
values[0x1]	62244	1			T18	9		T19	34		T21	48
transitions[0x0=>0x1]	61313	1			T18	8		T19	21		T21	32
transitions[0x1=>0x0]	61329	1			T18	8		T19	21		T21	32

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2560040	1			T2	1		T3	1		T4	6
all_pins[0]	values[0x1]	493	1			T18	3		T19	5		T21	5
all_pins[0]	transitions[0x0=>0x1]	450	1			T18	3		T19	1		T21	3
all_pins[0]	transitions[0x1=>0x0]	480	1			T18	1		T19	5		T21	7
all_pins[1]	values[0x0]	2560010	1			T2	1		T3	1		T4	6
all_pins[1]	values[0x1]	523	1			T18	1		T19	9		T21	9
all_pins[1]	transitions[0x0=>0x1]	334	1			T18	1		T19	4		T21	6
all_pins[1]	transitions[0x1=>0x0]	246	1			T18	1		T21	3		T24	93
all_pins[2]	values[0x0]	2560098	1			T2	1		T3	1		T4	6
all_pins[2]	values[0x1]	435	1			T18	1		T19	5		T21	6
all_pins[2]	transitions[0x0=>0x1]	390	1			T18	1		T19	5		T21	3
all_pins[2]	transitions[0x1=>0x0]	111	1			T19	2		T21	3		T37	3
all_pins[3]	values[0x0]	2560377	1			T2	1		T3	1		T4	6
all_pins[3]	values[0x1]	156	1			T19	2		T21	6		T37	4
all_pins[3]	transitions[0x0=>0x1]	106	1			T19	2		T21	4		T37	4
all_pins[3]	transitions[0x1=>0x0]	144	1			T19	2		T21	4		T38	1
all_pins[4]	values[0x0]	2560339	1			T2	1		T3	1		T4	6
all_pins[4]	values[0x1]	194	1			T19	2		T21	6		T38	1
all_pins[4]	transitions[0x0=>0x1]	155	1			T19	2		T21	6		T174	3
all_pins[4]	transitions[0x1=>0x0]	934	1			T18	1		T19	2		T21	1
all_pins[5]	values[0x0]	2559560	1			T2	1		T3	1		T4	6
all_pins[5]	values[0x1]	973	1			T18	1		T19	2		T21	1
all_pins[5]	transitions[0x0=>0x1]	509	1			T19	2		T174	1		T175	3
all_pins[5]	transitions[0x1=>0x0]	58834	1			T18	2		T19	3		T21	9
all_pins[6]	values[0x0]	2501235	1			T2	1		T3	1		T4	6
all_pins[6]	values[0x1]	59298	1			T18	3		T19	3		T21	10
all_pins[6]	transitions[0x0=>0x1]	59253	1			T18	3		T21	7		T24	43182
all_pins[6]	transitions[0x1=>0x0]	127	1			T19	3		T21	2		T24	1
all_pins[7]	values[0x0]	2560361	1			T2	1		T3	1		T4	6
all_pins[7]	values[0x1]	172	1			T19	6		T21	5		T24	1
all_pins[7]	transitions[0x0=>0x1]	116	1			T19	5		T21	3		T24	1
all_pins[7]	transitions[0x1=>0x0]	453	1			T18	3		T19	4		T21	3