Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16132

1

T4

2

T11

4

T15

48

auto[1]

12608

1

T3

18

T14

26

T15

29

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3372	1			T3	18		T15	30		T254	10
values[1]	4133	1			T11	4		T16	18		T57	94
values[2]	3935	1			T15	47		T41	8		T111	6
values[3]	3309	1			T27	4		T56	12		T53	24
values[4]	3568	1			T60	18		T181	8		T59	20
values[5]	3557	1			T14	26		T255	4		T256	12
values[6]	3387	1			T50	39		T53	20		T112	26
values[7]	3479	1			T4	2		T53	137		T57	109

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3649	1			T112	26		T256	12		T57	43
values[1]	3821	1			T53	20		T187	16		T57	60
values[2]	3606	1			T4	2		T15	20		T53	40
values[3]	3252	1			T3	18		T111	6		T56	12
values[4]	4298	1			T15	30		T27	4		T60	18
values[5]	2732	1			T15	27		T41	8		T53	24
values[6]	3440	1			T11	4		T16	18		T50	39
values[7]	3942	1			T14	26		T57	201		T58	23

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	211	1			T57	13		T58	10		T94	11
auto[0]	values[0]	values[1]	282	1			T58	8		T23	9		T92	4
auto[0]	values[0]	values[2]	174	1			T59	8		T24	35		T257	16
auto[0]	values[0]	values[3]	218	1			T59	13		T89	6		T94	13
auto[0]	values[0]	values[4]	228	1			T15	25		T254	10		T258	20
auto[0]	values[0]	values[5]	245	1			T259	33		T203	20		T220	14
auto[0]	values[0]	values[6]	123	1			T23	11		T94	7		T203	11
auto[0]	values[0]	values[7]	248	1			T21	11		T54	18		T218	12
auto[0]	values[1]	values[0]	374	1			T105	12		T260	20		T198	10
auto[0]	values[1]	values[1]	188	1			T57	12		T59	12		T23	18
auto[0]	values[1]	values[2]	188	1			T54	10		T204	9		T198	13
auto[0]	values[1]	values[3]	320	1			T57	28		T24	10		T38	9
auto[0]	values[1]	values[4]	291	1			T185	22		T107	10		T23	19
auto[0]	values[1]	values[5]	134	1			T62	13		T24	13		T204	11
auto[0]	values[1]	values[6]	407	1			T11	4		T16	18		T23	11
auto[0]	values[1]	values[7]	212	1			T57	39		T261	6		T54	18
auto[0]	values[2]	values[0]	313	1			T207	23		T262	39		T215	48
auto[0]	values[2]	values[1]	222	1			T187	16		T263	4		T54	12
auto[0]	values[2]	values[2]	283	1			T15	15		T62	10		T202	20
auto[0]	values[2]	values[3]	357	1			T111	6		T94	12		T203	12
auto[0]	values[2]	values[4]	520	1			T57	122		T58	10		T23	19
auto[0]	values[2]	values[5]	232	1			T15	8		T41	8		T204	11
auto[0]	values[2]	values[6]	170	1			T264	4		T58	20		T265	10
auto[0]	values[2]	values[7]	306	1			T59	8		T266	4		T246	19
auto[0]	values[3]	values[0]	113	1			T204	13		T157	12		T201	10
auto[0]	values[3]	values[1]	461	1			T184	8		T267	4		T218	14
auto[0]	values[3]	values[2]	271	1			T58	7		T23	11		T198	7
auto[0]	values[3]	values[3]	268	1			T21	13		T233	18		T268	14
auto[0]	values[3]	values[4]	191	1			T27	4		T62	28		T204	9
auto[0]	values[3]	values[5]	190	1			T53	11		T58	13		T62	11
auto[0]	values[3]	values[6]	168	1			T218	56		T246	13		T269	10
auto[0]	values[3]	values[7]	125	1			T58	15		T198	8		T270	7
auto[0]	values[4]	values[0]	413	1			T204	113		T220	16		T271	11
auto[0]	values[4]	values[1]	100	1			T211	10		T272	10		T273	2
auto[0]	values[4]	values[2]	263	1			T181	8		T94	13		T274	2
auto[0]	values[4]	values[3]	202	1			T59	7		T207	13		T270	67
auto[0]	values[4]	values[4]	241	1			T60	18		T220	9		T275	8
auto[0]	values[4]	values[5]	139	1			T218	17		T276	26		T234	14
auto[0]	values[4]	values[6]	243	1			T38	9		T225	9		T215	14
auto[0]	values[4]	values[7]	470	1			T23	16		T24	8		T38	6
auto[0]	values[5]	values[0]	205	1			T256	12		T214	12		T277	12
auto[0]	values[5]	values[1]	249	1			T23	11		T54	22		T24	11
auto[0]	values[5]	values[2]	196	1			T59	10		T23	13		T239	12
auto[0]	values[5]	values[3]	214	1			T58	10		T59	13		T23	10
auto[0]	values[5]	values[4]	329	1			T58	6		T219	2		T23	17
auto[0]	values[5]	values[5]	217	1			T57	14		T59	28		T198	11
auto[0]	values[5]	values[6]	216	1			T255	4		T24	8		T207	8
auto[0]	values[5]	values[7]	371	1			T54	14		T157	12		T198	26
auto[0]	values[6]	values[0]	168	1			T112	26		T59	17		T246	9
auto[0]	values[6]	values[1]	225	1			T21	13		T222	4		T59	11
auto[0]	values[6]	values[2]	215	1			T53	14		T94	12		T54	30
auto[0]	values[6]	values[3]	239	1			T58	11		T238	6		T59	18
auto[0]	values[6]	values[4]	238	1			T38	13		T212	9		T198	12
auto[0]	values[6]	values[5]	253	1			T230	24		T23	23		T207	9
auto[0]	values[6]	values[6]	309	1			T50	39		T57	12		T94	7
auto[0]	values[6]	values[7]	227	1			T57	80		T23	6		T54	8
auto[0]	values[7]	values[0]	365	1			T62	12		T218	13		T215	14
auto[0]	values[7]	values[1]	396	1			T53	5		T57	11		T23	23
auto[0]	values[7]	values[2]	275	1			T4	2		T53	10		T184	13
auto[0]	values[7]	values[3]	149	1			T57	36		T278	6		T54	11
auto[0]	values[7]	values[4]	241	1			T53	13		T62	10		T21	10
auto[0]	values[7]	values[5]	219	1			T57	15		T279	16		T280	10
auto[0]	values[7]	values[6]	312	1			T53	54		T94	16		T201	38
auto[0]	values[7]	values[7]	200	1			T23	13		T281	4		T209	19
auto[1]	values[0]	values[0]	113	1			T57	30		T58	10		T94	9
auto[1]	values[0]	values[1]	144	1			T58	14		T23	23		T24	10
auto[1]	values[0]	values[2]	177	1			T59	12		T24	7		T216	78
auto[1]	values[0]	values[3]	148	1			T3	18		T59	7		T94	7
auto[1]	values[0]	values[4]	170	1			T15	5		T225	9		T271	18
auto[1]	values[0]	values[5]	171	1			T203	8		T220	6		T216	13
auto[1]	values[0]	values[6]	344	1			T64	14		T23	9		T94	13
auto[1]	values[0]	values[7]	376	1			T21	23		T54	67		T218	8
auto[1]	values[1]	values[0]	305	1			T198	10		T240	4		T271	8
auto[1]	values[1]	values[1]	350	1			T57	8		T59	8		T23	3
auto[1]	values[1]	values[2]	178	1			T54	36		T204	11		T198	7
auto[1]	values[1]	values[3]	282	1			T57	5		T24	11		T244	26
auto[1]	values[1]	values[4]	349	1			T23	5		T54	82		T218	27
auto[1]	values[1]	values[5]	101	1			T62	7		T24	8		T204	9
auto[1]	values[1]	values[6]	260	1			T23	9		T94	9		T203	4
auto[1]	values[1]	values[7]	194	1			T57	2		T224	18		T54	12
auto[1]	values[2]	values[0]	120	1			T63	8		T207	17		T262	10
auto[1]	values[2]	values[1]	194	1			T54	59		T24	14		T157	11
auto[1]	values[2]	values[2]	140	1			T15	5		T62	10		T203	9
auto[1]	values[2]	values[3]	174	1			T94	8		T203	9		T207	10
auto[1]	values[2]	values[4]	285	1			T57	21		T58	83		T23	34
auto[1]	values[2]	values[5]	169	1			T15	19		T204	9		T227	5
auto[1]	values[2]	values[6]	212	1			T58	9		T265	10		T282	11
auto[1]	values[2]	values[7]	238	1			T59	12		T246	10		T177	8
auto[1]	values[3]	values[0]	188	1			T283	12		T65	24		T204	92
auto[1]	values[3]	values[1]	181	1			T184	27		T218	6		T204	5
auto[1]	values[3]	values[2]	326	1			T58	14		T23	9		T198	13
auto[1]	values[3]	values[3]	77	1			T56	12		T21	7		T179	9
auto[1]	values[3]	values[4]	204	1			T61	16		T62	12		T217	8
auto[1]	values[3]	values[5]	224	1			T53	13		T58	12		T62	9
auto[1]	values[3]	values[6]	164	1			T218	4		T246	7		T269	10
auto[1]	values[3]	values[7]	158	1			T58	8		T198	12		T270	45
auto[1]	values[4]	values[0]	255	1			T204	3		T220	11		T271	9
auto[1]	values[4]	values[1]	138	1			T211	72		T242	10		T284	6
auto[1]	values[4]	values[2]	223	1			T94	7		T54	7		T218	9
auto[1]	values[4]	values[3]	114	1			T59	13		T207	7		T270	19
auto[1]	values[4]	values[4]	255	1			T226	12		T220	12		T285	6
auto[1]	values[4]	values[5]	56	1			T218	6		T234	13		T286	3
auto[1]	values[4]	values[6]	115	1			T38	11		T225	15		T215	6
auto[1]	values[4]	values[7]	341	1			T23	8		T24	16		T38	14
auto[1]	values[5]	values[0]	99	1			T204	4		T234	10		T179	7
auto[1]	values[5]	values[1]	205	1			T23	15		T54	23		T24	15
auto[1]	values[5]	values[2]	240	1			T59	10		T23	7		T239	8
auto[1]	values[5]	values[3]	187	1			T58	29		T59	7		T23	10
auto[1]	values[5]	values[4]	325	1			T58	14		T23	11		T220	6
auto[1]	values[5]	values[5]	160	1			T57	6		T59	12		T198	9
auto[1]	values[5]	values[6]	173	1			T90	6		T24	12		T207	12
auto[1]	values[5]	values[7]	171	1			T14	26		T54	6		T157	10
auto[1]	values[6]	values[0]	78	1			T59	3		T246	11		T242	9
auto[1]	values[6]	values[1]	275	1			T21	7		T59	9		T23	8
auto[1]	values[6]	values[2]	227	1			T53	6		T94	8		T54	7
auto[1]	values[6]	values[3]	214	1			T58	11		T59	2		T207	8
auto[1]	values[6]	values[4]	218	1			T38	12		T212	11		T198	8
auto[1]	values[6]	values[5]	116	1			T23	31		T207	11		T287	4
auto[1]	values[6]	values[6]	152	1			T57	41		T94	13		T270	17
auto[1]	values[6]	values[7]	233	1			T57	80		T23	28		T54	12
auto[1]	values[7]	values[0]	329	1			T62	8		T218	12		T215	6
auto[1]	values[7]	values[1]	211	1			T53	15		T57	29		T23	17
auto[1]	values[7]	values[2]	230	1			T53	10		T184	11		T23	16
auto[1]	values[7]	values[3]	89	1			T57	7		T54	9		T210	6
auto[1]	values[7]	values[4]	213	1			T53	7		T62	10		T21	10
auto[1]	values[7]	values[5]	106	1			T57	11		T240	9		T286	5
auto[1]	values[7]	values[6]	72	1			T53	23		T94	4		T201	9
auto[1]	values[7]	values[7]	72	1			T23	7		T209	9		T159	12