Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	409	1			T15	3		T41	6		T60	4
auto[ReadAddrCrossIntoMailbox]	264	1			T15	3		T60	6		T53	1
auto[ReadAddrCrossOutOfMailbox]	279	1			T11	2		T60	4		T57	4
auto[ReadAddrCrossAllMailbox]	196	1			T57	2		T58	2		T62	1
auto[ReadAddrOutsideMailbox]	3439	1			T3	8		T11	2		T14	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2342

1

T3

4

T11

2

T14

5

auto[1]

2245

1

T3

4

T11

2

T14

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	786	1			T11	2		T14	2		T15	2
read_ops[0x0b]	755	1			T3	6		T11	2		T15	3
read_ops[0x3b]	773	1			T15	2		T16	2		T50	2
read_ops[0x6b]	806	1			T3	2		T14	4		T15	3
read_ops[0xbb]	741	1			T14	4		T15	1		T50	2
read_ops[0xeb]	726	1			T15	3		T16	2		T41	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T15	1		T57	1		T59	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T57	1		T21	1		T59	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T15	1		T60	2		T53	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T60	2		T24	1		T198	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T59	1		T23	1		T262	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T57	1		T59	1		T23	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T230	1		T94	1		T38	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T57	1		T230	1		T23	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T11	1		T14	1		T50	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T11	1		T14	1		T50	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T53	1		T62	1		T214	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T214	1		T38	1		T218	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T230	1		T54	1		T203	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T15	1		T230	1		T59	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T11	1		T57	1		T62	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T11	1		T58	1		T24	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T57	1		T230	1		T54	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T230	1		T23	2		T207	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T3	3		T15	2		T16	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T3	3		T16	2		T50	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T60	2		T57	1		T230	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T60	2		T62	1		T230	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T58	1		T157	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	11	1			T15	1		T177	1		T289	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T60	1		T94	1		T24	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T60	1		T59	2		T23	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T58	1		T230	1		T59	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T230	1		T54	1		T38	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T15	1		T16	1		T50	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	289	1			T16	1		T50	1		T60	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T15	2		T41	2		T57	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T41	2		T230	1		T59	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T60	1		T230	1		T23	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T60	1		T230	1		T24	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T58	1		T54	1		T198	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T57	1		T59	2		T218	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T59	1		T24	2		T207	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T23	1		T54	1		T24	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T3	1		T14	2		T15	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T3	1		T14	2		T16	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T238	2		T24	2		T218	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T58	1		T238	2		T59	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T58	1		T230	1		T204	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T57	1		T230	1		T24	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T60	1		T230	2		T59	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T60	1		T57	1		T230	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T58	1		T89	1		T198	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T89	1		T23	2		T24	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T14	2		T50	1		T57	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	264	1			T14	2		T15	1		T50	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T41	1		T21	1		T24	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T41	1		T58	2		T21	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T23	1		T24	1		T203	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T58	1		T59	2		T215	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T184	1		T198	1		T239	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T58	1		T59	1		T23	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T262	1		T227	1		T243	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T62	1		T23	1		T24	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T15	2		T16	1		T60	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T15	1		T16	1		T60	1