Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	761	1			T18	4		T19	14		T21	20
all_values[1]	761	1			T18	4		T19	14		T21	20
all_values[2]	761	1			T18	4		T19	14		T21	20
all_values[3]	761	1			T18	4		T19	14		T21	20
all_values[4]	761	1			T18	4		T19	14		T21	20
all_values[5]	761	1			T18	4		T19	14		T21	20
all_values[6]	761	1			T18	4		T19	14		T21	20
all_values[7]	761	1			T18	4		T19	14		T21	20

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3219

1

T18

19

T19

64

T21

90

auto[1]

2869

1

T18

13

T19

48

T21

70

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2407

1

T18

13

T19

42

T21

53

auto[1]

3681

1

T18

19

T19

70

T21

107

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3479

1

T18

19

T19

60

T21

84

auto[1]

2609

1

T18

13

T19

52

T21

76

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	174	1			T19	2		T21	5		T38	1
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T19	1		T21	3		T37	3
all_values[0]	auto[0]	auto[1]	auto[0]	130	1			T19	2		T21	2		T37	1
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T18	2		T19	3		T21	2
all_values[0]	auto[1]	auto[0]	auto[1]	167	1			T18	1		T19	3		T21	5
all_values[0]	auto[1]	auto[1]	auto[1]	139	1			T18	1		T19	3		T21	3
all_values[1]	auto[0]	auto[0]	auto[0]	144	1			T18	2		T21	4		T24	2
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T19	1		T21	2		T37	1
all_values[1]	auto[0]	auto[1]	auto[0]	129	1			T18	1		T19	1		T21	1
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T19	2		T21	5		T175	4
all_values[1]	auto[1]	auto[0]	auto[1]	192	1			T18	1		T19	5		T21	6
all_values[1]	auto[1]	auto[1]	auto[1]	147	1			T19	5		T21	2		T37	2
all_values[2]	auto[0]	auto[0]	auto[0]	141	1			T19	4		T21	4		T37	1
all_values[2]	auto[0]	auto[0]	auto[1]	62	1			T19	3		T21	1		T175	2
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T18	2		T19	1		T21	3
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T21	2		T37	1		T175	4
all_values[2]	auto[1]	auto[0]	auto[1]	165	1			T18	1		T19	2		T21	6
all_values[2]	auto[1]	auto[1]	auto[1]	164	1			T18	1		T19	4		T21	4
all_values[3]	auto[0]	auto[0]	auto[0]	144	1			T19	1		T21	3		T24	2
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T18	1		T21	2		T38	1
all_values[3]	auto[0]	auto[1]	auto[0]	127	1			T19	9		T21	3		T37	1
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T21	2		T37	2		T183	2
all_values[3]	auto[1]	auto[0]	auto[1]	200	1			T18	3		T19	1		T21	4
all_values[3]	auto[1]	auto[1]	auto[1]	140	1			T19	3		T21	6		T37	2
all_values[4]	auto[0]	auto[0]	auto[0]	130	1			T18	1		T19	5		T21	4
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T18	1		T19	1		T21	1
all_values[4]	auto[0]	auto[1]	auto[0]	133	1			T19	4		T21	2		T37	1
all_values[4]	auto[0]	auto[1]	auto[1]	83	1			T21	3		T174	1		T175	4
all_values[4]	auto[1]	auto[0]	auto[1]	177	1			T18	2		T19	2		T21	6
all_values[4]	auto[1]	auto[1]	auto[1]	156	1			T19	2		T21	4		T24	1
all_values[5]	auto[0]	auto[0]	auto[0]	250	1			T19	6		T21	9		T24	3
all_values[5]	auto[0]	auto[1]	auto[0]	195	1			T18	2		T21	4		T24	1
all_values[5]	auto[1]	auto[0]	auto[1]	171	1			T18	1		T19	8		T21	6
all_values[5]	auto[1]	auto[1]	auto[1]	145	1			T18	1		T21	1		T37	1
all_values[6]	auto[0]	auto[0]	auto[0]	162	1			T18	1		T19	4		T21	2
all_values[6]	auto[0]	auto[0]	auto[1]	72	1			T19	3		T21	2		T37	1
all_values[6]	auto[0]	auto[1]	auto[0]	127	1			T19	1		T21	1		T37	1
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T18	2		T19	1		T21	3
all_values[6]	auto[1]	auto[0]	auto[1]	168	1			T19	4		T21	3		T24	1
all_values[6]	auto[1]	auto[1]	auto[1]	150	1			T18	1		T19	1		T21	9
all_values[7]	auto[0]	auto[0]	auto[0]	134	1			T18	4		T19	2		T21	3
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T19	1		T21	2		T24	1
all_values[7]	auto[0]	auto[1]	auto[0]	143	1			T21	3		T37	2		T174	1
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T19	2		T21	1		T38	1
all_values[7]	auto[1]	auto[0]	auto[1]	173	1			T19	5		T21	7		T24	2
all_values[7]	auto[1]	auto[1]	auto[1]	155	1			T19	4		T21	4		T24	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal