Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1639

1

T7

1

T25

5

T29

2

auto[1]

1601

1

T7

5

T25

7

T29

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1715

1

T25

10

T31

9

T32

1

auto[1]

1525

1

T7

6

T25

2

T29

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2585

1

T7

6

T25

7

T29

4

auto[1]

655

1

T25

5

T31

3

T36

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	643	1			T25	2		T29	2		T31	4
valid[1]	682	1			T7	3		T25	3		T29	1
valid[2]	642	1			T7	2		T25	1		T31	1
valid[3]	633	1			T25	3		T31	3		T36	2
valid[4]	640	1			T7	1		T25	3		T29	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T35	1		T36	1		T66	1
auto[0]	auto[0]	valid[0]	auto[1]	147	1			T29	2		T31	1		T101	6
auto[0]	auto[0]	valid[1]	auto[0]	119	1			T66	1		T67	1		T81	1
auto[0]	auto[0]	valid[1]	auto[1]	158	1			T31	1		T101	6		T103	1
auto[0]	auto[0]	valid[2]	auto[0]	124	1			T25	1		T35	1		T36	1
auto[0]	auto[0]	valid[2]	auto[1]	157	1			T101	3		T103	2		T104	4
auto[0]	auto[0]	valid[3]	auto[0]	100	1			T25	1		T36	1		T18	1
auto[0]	auto[0]	valid[3]	auto[1]	147	1			T31	2		T18	1		T101	3
auto[0]	auto[0]	valid[4]	auto[0]	100	1			T25	1		T31	2		T36	1
auto[0]	auto[0]	valid[4]	auto[1]	139	1			T7	1		T31	1		T104	1
auto[0]	auto[1]	valid[0]	auto[0]	107	1			T31	2		T32	1		T18	1
auto[0]	auto[1]	valid[0]	auto[1]	147	1			T101	2		T104	3		T352	2
auto[0]	auto[1]	valid[1]	auto[0]	96	1			T25	2		T66	1		T67	1
auto[0]	auto[1]	valid[1]	auto[1]	171	1			T7	3		T29	1		T31	1
auto[0]	auto[1]	valid[2]	auto[0]	91	1			T31	1		T66	3		T67	1
auto[0]	auto[1]	valid[2]	auto[1]	154	1			T7	2		T101	4		T103	1
auto[0]	auto[1]	valid[3]	auto[0]	100	1			T36	1		T66	3		T67	1
auto[0]	auto[1]	valid[3]	auto[1]	149	1			T25	1		T101	2		T102	1
auto[0]	auto[1]	valid[4]	auto[0]	100	1			T31	1		T18	1		T66	1
auto[0]	auto[1]	valid[4]	auto[1]	156	1			T25	1		T29	1		T36	1
auto[1]	auto[0]	valid[0]	auto[0]	52	1			T31	1		T20	1		T23	2
auto[1]	auto[0]	valid[1]	auto[0]	68	1			T67	1		T58	1		T20	1
auto[1]	auto[0]	valid[2]	auto[0]	57	1			T18	1		T81	1		T20	1
auto[1]	auto[0]	valid[3]	auto[0]	75	1			T25	1		T31	1		T20	2
auto[1]	auto[0]	valid[4]	auto[0]	73	1			T25	1		T81	1		T339	2
auto[1]	auto[1]	valid[0]	auto[0]	67	1			T25	2		T339	1		T345	1
auto[1]	auto[1]	valid[1]	auto[0]	70	1			T25	1		T36	1		T66	1
auto[1]	auto[1]	valid[2]	auto[0]	59	1			T339	1		T20	1		T23	2
auto[1]	auto[1]	valid[3]	auto[0]	62	1			T66	2		T330	1		T38	2
auto[1]	auto[1]	valid[4]	auto[0]	72	1			T31	1		T66	1		T81	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal