Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43975

1

T6

7

T25

252

T26

6

auto[1]

15989

1

T7

6

T25

53

T29

70

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43559

1

T6

2

T7

6

T25

206

auto[1]

16405

1

T6

5

T25

99

T26

3

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30644	1			T6	6		T7	6		T25	172
others[1]	5090	1			T25	18		T29	6		T31	34
others[2]	5122	1			T25	24		T29	6		T31	28
others[3]	5783	1			T6	1		T25	23		T29	5
interest[1]	3368	1			T25	19		T29	12		T31	16
interest[4]	20009	1			T6	2		T7	6		T25	116
interest[64]	9957	1			T25	49		T29	10		T34	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14010	1			T6	1		T25	89		T26	3
auto[0]	auto[0]	others[1]	2342	1			T25	11		T31	22		T32	2
auto[0]	auto[0]	others[2]	2344	1			T25	10		T31	13		T32	3
auto[0]	auto[0]	others[3]	2672	1			T6	1		T25	14		T31	14
auto[0]	auto[0]	interest[1]	1554	1			T25	8		T31	9		T32	4
auto[0]	auto[0]	interest[4]	9063	1			T25	61		T31	69		T32	5
auto[0]	auto[0]	interest[64]	4648	1			T25	21		T31	28		T32	3
auto[0]	auto[1]	others[0]	8243	1			T7	6		T25	32		T29	31
auto[0]	auto[1]	others[1]	1321	1			T25	3		T29	6		T31	5
auto[0]	auto[1]	others[2]	1388	1			T25	4		T29	6		T31	4
auto[0]	auto[1]	others[3]	1504	1			T25	3		T29	5		T31	4
auto[0]	auto[1]	interest[1]	875	1			T25	3		T29	12		T31	1
auto[0]	auto[1]	interest[4]	5533	1			T7	6		T25	26		T29	21
auto[0]	auto[1]	interest[64]	2658	1			T25	8		T29	10		T31	9
auto[1]	auto[0]	others[0]	8391	1			T6	5		T25	51		T26	3
auto[1]	auto[0]	others[1]	1427	1			T25	4		T31	7		T36	2
auto[1]	auto[0]	others[2]	1390	1			T25	10		T31	11		T32	2
auto[1]	auto[0]	others[3]	1607	1			T25	6		T31	8		T32	1
auto[1]	auto[0]	interest[1]	939	1			T25	8		T31	6		T35	1
auto[1]	auto[0]	interest[4]	5413	1			T6	2		T25	29		T26	2
auto[1]	auto[0]	interest[64]	2651	1			T25	20		T34	1		T31	20

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal