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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T1043 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1377922413 Jul 01 04:36:13 PM PDT 24 Jul 01 04:36:29 PM PDT 24 67452652 ps
T118 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.546141400 Jul 01 04:35:47 PM PDT 24 Jul 01 04:35:57 PM PDT 24 1587542705 ps
T131 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4004586495 Jul 01 04:36:00 PM PDT 24 Jul 01 04:36:14 PM PDT 24 55102592 ps
T1044 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2734118358 Jul 01 04:36:04 PM PDT 24 Jul 01 04:36:15 PM PDT 24 32282931 ps
T1045 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1435573409 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:09 PM PDT 24 53418639 ps
T1046 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2994839335 Jul 01 04:36:09 PM PDT 24 Jul 01 04:36:24 PM PDT 24 33416681 ps
T172 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2837008430 Jul 01 04:36:01 PM PDT 24 Jul 01 04:36:13 PM PDT 24 246477022 ps
T121 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1216710867 Jul 01 04:35:47 PM PDT 24 Jul 01 04:35:56 PM PDT 24 323823259 ps
T124 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2043838846 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:10 PM PDT 24 138769551 ps
T135 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4174216099 Jul 01 04:36:03 PM PDT 24 Jul 01 04:36:19 PM PDT 24 326725965 ps
T1047 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.366129866 Jul 01 04:36:09 PM PDT 24 Jul 01 04:36:24 PM PDT 24 41407153 ps
T132 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2745698815 Jul 01 04:35:50 PM PDT 24 Jul 01 04:35:58 PM PDT 24 211746320 ps
T127 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3487190362 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:18 PM PDT 24 377206071 ps
T125 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2868981334 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:09 PM PDT 24 119018526 ps
T173 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3227831997 Jul 01 04:35:55 PM PDT 24 Jul 01 04:36:08 PM PDT 24 335534022 ps
T168 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1485869757 Jul 01 04:35:51 PM PDT 24 Jul 01 04:35:58 PM PDT 24 533319020 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1721726804 Jul 01 04:35:51 PM PDT 24 Jul 01 04:35:56 PM PDT 24 36649099 ps
T142 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2183940976 Jul 01 04:35:55 PM PDT 24 Jul 01 04:36:05 PM PDT 24 100295370 ps
T1049 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.601823350 Jul 01 04:35:51 PM PDT 24 Jul 01 04:35:59 PM PDT 24 257529586 ps
T1050 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4247348029 Jul 01 04:36:01 PM PDT 24 Jul 01 04:36:12 PM PDT 24 13130914 ps
T1051 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.551694896 Jul 01 04:36:07 PM PDT 24 Jul 01 04:36:21 PM PDT 24 33327687 ps
T1052 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3062105549 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:29 PM PDT 24 2458444333 ps
T188 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.584361110 Jul 01 04:35:54 PM PDT 24 Jul 01 04:36:15 PM PDT 24 1392315039 ps
T1053 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2226713106 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:10 PM PDT 24 56884084 ps
T97 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3859276044 Jul 01 04:35:53 PM PDT 24 Jul 01 04:36:01 PM PDT 24 23634675 ps
T195 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1580404503 Jul 01 04:35:53 PM PDT 24 Jul 01 04:36:07 PM PDT 24 1886902500 ps
T134 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1095244093 Jul 01 04:36:00 PM PDT 24 Jul 01 04:36:14 PM PDT 24 149834660 ps
T1054 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3168038810 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:15 PM PDT 24 110083935 ps
T122 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3761349225 Jul 01 04:35:49 PM PDT 24 Jul 01 04:35:55 PM PDT 24 63358022 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1681892923 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:05 PM PDT 24 38880816 ps
T1056 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1052255229 Jul 01 04:35:59 PM PDT 24 Jul 01 04:36:11 PM PDT 24 110152143 ps
T133 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.895208856 Jul 01 04:36:04 PM PDT 24 Jul 01 04:36:18 PM PDT 24 120997409 ps
T1057 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2019187716 Jul 01 04:35:44 PM PDT 24 Jul 01 04:36:13 PM PDT 24 361488169 ps
T191 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.362324865 Jul 01 04:35:53 PM PDT 24 Jul 01 04:36:18 PM PDT 24 295413513 ps
T1058 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.615857158 Jul 01 04:36:19 PM PDT 24 Jul 01 04:36:33 PM PDT 24 32579015 ps
T169 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2011026518 Jul 01 04:35:59 PM PDT 24 Jul 01 04:36:10 PM PDT 24 73152662 ps
T170 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3591619660 Jul 01 04:36:04 PM PDT 24 Jul 01 04:36:17 PM PDT 24 143616476 ps
T171 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1139788042 Jul 01 04:35:54 PM PDT 24 Jul 01 04:36:04 PM PDT 24 59870047 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.138827735 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:06 PM PDT 24 64045362 ps
T1060 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1035144795 Jul 01 04:35:44 PM PDT 24 Jul 01 04:35:49 PM PDT 24 19258098 ps
T189 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3478294981 Jul 01 04:35:51 PM PDT 24 Jul 01 04:36:17 PM PDT 24 3864291526 ps
T143 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1593754462 Jul 01 04:35:57 PM PDT 24 Jul 01 04:36:27 PM PDT 24 626008110 ps
T1061 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1068597088 Jul 01 04:35:50 PM PDT 24 Jul 01 04:36:12 PM PDT 24 1704750998 ps
T144 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.229557227 Jul 01 04:35:45 PM PDT 24 Jul 01 04:35:52 PM PDT 24 49347235 ps
T1062 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1097674613 Jul 01 04:36:09 PM PDT 24 Jul 01 04:36:24 PM PDT 24 14640754 ps
T1063 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.7506815 Jul 01 04:35:52 PM PDT 24 Jul 01 04:35:59 PM PDT 24 607039286 ps
T145 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3807749522 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:06 PM PDT 24 22715994 ps
T1064 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2976896496 Jul 01 04:36:17 PM PDT 24 Jul 01 04:36:31 PM PDT 24 120687540 ps
T192 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.413512115 Jul 01 04:35:51 PM PDT 24 Jul 01 04:36:13 PM PDT 24 3627928684 ps
T194 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3096894152 Jul 01 04:36:07 PM PDT 24 Jul 01 04:36:35 PM PDT 24 519943739 ps
T130 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3384990363 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:11 PM PDT 24 667707941 ps
T1065 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2229604726 Jul 01 04:35:52 PM PDT 24 Jul 01 04:35:58 PM PDT 24 19264875 ps
T146 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.100370244 Jul 01 04:35:44 PM PDT 24 Jul 01 04:35:52 PM PDT 24 93600175 ps
T1066 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1619632105 Jul 01 04:36:01 PM PDT 24 Jul 01 04:36:12 PM PDT 24 14171595 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4234070289 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:20 PM PDT 24 639632157 ps
T1068 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3717712407 Jul 01 04:36:01 PM PDT 24 Jul 01 04:36:18 PM PDT 24 427592361 ps
T1069 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2860434523 Jul 01 04:36:17 PM PDT 24 Jul 01 04:36:31 PM PDT 24 18629413 ps
T1070 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3041980319 Jul 01 04:36:01 PM PDT 24 Jul 01 04:36:17 PM PDT 24 669548952 ps
T1071 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.263628838 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:12 PM PDT 24 761641461 ps
T98 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1317804250 Jul 01 04:35:44 PM PDT 24 Jul 01 04:35:51 PM PDT 24 47268821 ps
T123 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3752766359 Jul 01 04:36:00 PM PDT 24 Jul 01 04:36:15 PM PDT 24 75812810 ps
T1072 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.973684823 Jul 01 04:35:52 PM PDT 24 Jul 01 04:35:58 PM PDT 24 20995669 ps
T1073 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3394175888 Jul 01 04:35:55 PM PDT 24 Jul 01 04:36:04 PM PDT 24 38136246 ps
T128 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1953581150 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:11 PM PDT 24 309485769 ps
T1074 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2712748291 Jul 01 04:36:02 PM PDT 24 Jul 01 04:36:15 PM PDT 24 271664510 ps
T1075 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4144506133 Jul 01 04:35:55 PM PDT 24 Jul 01 04:36:07 PM PDT 24 157477304 ps
T1076 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1638327288 Jul 01 04:36:00 PM PDT 24 Jul 01 04:36:11 PM PDT 24 68136755 ps
T1077 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2890516030 Jul 01 04:36:14 PM PDT 24 Jul 01 04:36:33 PM PDT 24 47421894 ps
T1078 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3236185952 Jul 01 04:35:45 PM PDT 24 Jul 01 04:35:53 PM PDT 24 443477352 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1251959132 Jul 01 04:35:51 PM PDT 24 Jul 01 04:35:59 PM PDT 24 127151236 ps
T1080 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2810131740 Jul 01 04:36:06 PM PDT 24 Jul 01 04:36:22 PM PDT 24 57247827 ps
T1081 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3533688731 Jul 01 04:36:02 PM PDT 24 Jul 01 04:36:13 PM PDT 24 20130285 ps
T1082 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3140088482 Jul 01 04:36:08 PM PDT 24 Jul 01 04:36:23 PM PDT 24 83568521 ps
T1083 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1965802978 Jul 01 04:36:06 PM PDT 24 Jul 01 04:36:20 PM PDT 24 17884443 ps
T193 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1197793192 Jul 01 04:35:54 PM PDT 24 Jul 01 04:36:20 PM PDT 24 1470981692 ps
T1084 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.267598888 Jul 01 04:36:06 PM PDT 24 Jul 01 04:36:20 PM PDT 24 16160925 ps
T1085 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3376057781 Jul 01 04:35:51 PM PDT 24 Jul 01 04:35:57 PM PDT 24 24944583 ps
T1086 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3782021902 Jul 01 04:35:50 PM PDT 24 Jul 01 04:35:56 PM PDT 24 66232151 ps
T147 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1098359048 Jul 01 04:35:55 PM PDT 24 Jul 01 04:36:05 PM PDT 24 66238234 ps
T1087 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.298790636 Jul 01 04:35:59 PM PDT 24 Jul 01 04:36:10 PM PDT 24 17217947 ps
T126 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2997939263 Jul 01 04:36:06 PM PDT 24 Jul 01 04:36:22 PM PDT 24 180276508 ps
T129 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.404980747 Jul 01 04:36:17 PM PDT 24 Jul 01 04:36:33 PM PDT 24 336181065 ps
T149 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4119035021 Jul 01 04:35:57 PM PDT 24 Jul 01 04:36:07 PM PDT 24 37282467 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1410505025 Jul 01 04:35:57 PM PDT 24 Jul 01 04:36:29 PM PDT 24 1635623675 ps
T148 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2515617907 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:41 PM PDT 24 2362287457 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1973953722 Jul 01 04:35:57 PM PDT 24 Jul 01 04:36:20 PM PDT 24 3958265005 ps
T1090 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1674552719 Jul 01 04:35:52 PM PDT 24 Jul 01 04:36:00 PM PDT 24 311242454 ps
T99 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2943488678 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:05 PM PDT 24 314986875 ps
T1091 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2566026371 Jul 01 04:36:13 PM PDT 24 Jul 01 04:36:29 PM PDT 24 18490446 ps
T1092 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1498775967 Jul 01 04:36:09 PM PDT 24 Jul 01 04:36:23 PM PDT 24 11502328 ps
T1093 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2645388670 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:08 PM PDT 24 11311456 ps
T1094 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1539513357 Jul 01 04:36:08 PM PDT 24 Jul 01 04:36:23 PM PDT 24 15995020 ps
T1095 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.754307510 Jul 01 04:35:59 PM PDT 24 Jul 01 04:36:11 PM PDT 24 383618230 ps
T1096 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4203291201 Jul 01 04:36:08 PM PDT 24 Jul 01 04:36:22 PM PDT 24 43316980 ps
T1097 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2244622450 Jul 01 04:35:43 PM PDT 24 Jul 01 04:35:48 PM PDT 24 13839360 ps
T1098 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2690298513 Jul 01 04:36:00 PM PDT 24 Jul 01 04:36:17 PM PDT 24 540154678 ps
T1099 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1196544150 Jul 01 04:35:50 PM PDT 24 Jul 01 04:35:57 PM PDT 24 131274137 ps
T1100 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1642602478 Jul 01 04:35:53 PM PDT 24 Jul 01 04:36:02 PM PDT 24 460674237 ps
T1101 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4275166099 Jul 01 04:35:54 PM PDT 24 Jul 01 04:36:04 PM PDT 24 94792678 ps
T1102 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1148907312 Jul 01 04:35:54 PM PDT 24 Jul 01 04:36:04 PM PDT 24 180708145 ps
T1103 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.402548147 Jul 01 04:35:51 PM PDT 24 Jul 01 04:35:58 PM PDT 24 379852091 ps
T1104 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2855529519 Jul 01 04:35:55 PM PDT 24 Jul 01 04:36:05 PM PDT 24 41759281 ps
T1105 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2073487866 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:11 PM PDT 24 57013494 ps
T1106 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2139291027 Jul 01 04:35:53 PM PDT 24 Jul 01 04:36:01 PM PDT 24 118811299 ps
T1107 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1234529458 Jul 01 04:35:52 PM PDT 24 Jul 01 04:36:10 PM PDT 24 4137087981 ps
T1108 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4013618914 Jul 01 04:36:03 PM PDT 24 Jul 01 04:36:15 PM PDT 24 17691632 ps
T1109 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.883997452 Jul 01 04:36:09 PM PDT 24 Jul 01 04:36:24 PM PDT 24 222771968 ps
T1110 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.646677720 Jul 01 04:35:55 PM PDT 24 Jul 01 04:36:03 PM PDT 24 16612453 ps
T1111 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2089251741 Jul 01 04:35:51 PM PDT 24 Jul 01 04:35:57 PM PDT 24 249687941 ps
T1112 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3536868890 Jul 01 04:36:13 PM PDT 24 Jul 01 04:36:29 PM PDT 24 18181031 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3003081622 Jul 01 04:35:52 PM PDT 24 Jul 01 04:36:01 PM PDT 24 699746662 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2192340094 Jul 01 04:35:57 PM PDT 24 Jul 01 04:36:06 PM PDT 24 10309902 ps
T1115 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1678512227 Jul 01 04:35:54 PM PDT 24 Jul 01 04:36:04 PM PDT 24 54380871 ps
T1116 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3272403370 Jul 01 04:35:51 PM PDT 24 Jul 01 04:35:59 PM PDT 24 105262944 ps
T1117 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.221408200 Jul 01 04:36:06 PM PDT 24 Jul 01 04:36:20 PM PDT 24 13290696 ps
T190 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1240708186 Jul 01 04:36:02 PM PDT 24 Jul 01 04:36:26 PM PDT 24 3138350774 ps
T1118 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1011411353 Jul 01 04:36:00 PM PDT 24 Jul 01 04:36:13 PM PDT 24 220096539 ps
T1119 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2748510487 Jul 01 04:36:06 PM PDT 24 Jul 01 04:36:20 PM PDT 24 13746074 ps
T1120 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2214044209 Jul 01 04:35:55 PM PDT 24 Jul 01 04:36:16 PM PDT 24 215173409 ps
T1121 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2924213399 Jul 01 04:35:51 PM PDT 24 Jul 01 04:35:58 PM PDT 24 85579756 ps
T1122 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3597159922 Jul 01 04:35:59 PM PDT 24 Jul 01 04:36:10 PM PDT 24 13740028 ps
T1123 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2569007569 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:06 PM PDT 24 28121066 ps
T1124 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3433527411 Jul 01 04:36:07 PM PDT 24 Jul 01 04:36:21 PM PDT 24 14501345 ps
T1125 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2655744085 Jul 01 04:36:07 PM PDT 24 Jul 01 04:36:21 PM PDT 24 61719848 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1517533517 Jul 01 04:35:53 PM PDT 24 Jul 01 04:36:02 PM PDT 24 48187480 ps
T1127 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3561880560 Jul 01 04:36:10 PM PDT 24 Jul 01 04:36:25 PM PDT 24 64763171 ps
T1128 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3741780382 Jul 01 04:36:00 PM PDT 24 Jul 01 04:36:12 PM PDT 24 54596870 ps
T1129 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2735074102 Jul 01 04:35:59 PM PDT 24 Jul 01 04:36:10 PM PDT 24 808250221 ps
T1130 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3793224403 Jul 01 04:35:56 PM PDT 24 Jul 01 04:36:07 PM PDT 24 25096891 ps
T1131 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1174168323 Jul 01 04:36:17 PM PDT 24 Jul 01 04:36:32 PM PDT 24 110570026 ps
T1132 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1321187748 Jul 01 04:35:54 PM PDT 24 Jul 01 04:36:02 PM PDT 24 28012692 ps
T1133 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3838309810 Jul 01 04:35:49 PM PDT 24 Jul 01 04:36:05 PM PDT 24 635984594 ps
T100 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2405855286 Jul 01 04:35:49 PM PDT 24 Jul 01 04:35:55 PM PDT 24 44893514 ps
T1134 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2503018653 Jul 01 04:35:54 PM PDT 24 Jul 01 04:36:03 PM PDT 24 12692585 ps
T1135 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1827208662 Jul 01 04:36:07 PM PDT 24 Jul 01 04:36:21 PM PDT 24 49266663 ps
T1136 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3705432031 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:10 PM PDT 24 341055389 ps
T1137 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1768455852 Jul 01 04:35:53 PM PDT 24 Jul 01 04:36:01 PM PDT 24 130584992 ps
T1138 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2066349163 Jul 01 04:36:05 PM PDT 24 Jul 01 04:36:18 PM PDT 24 25949163 ps
T1139 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2868469549 Jul 01 04:36:02 PM PDT 24 Jul 01 04:36:18 PM PDT 24 374147168 ps
T1140 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.672412064 Jul 01 04:35:50 PM PDT 24 Jul 01 04:35:55 PM PDT 24 38792960 ps
T1141 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.855184346 Jul 01 04:35:59 PM PDT 24 Jul 01 04:36:09 PM PDT 24 63252201 ps
T1142 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3055849503 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:10 PM PDT 24 115737039 ps
T1143 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3267280769 Jul 01 04:35:59 PM PDT 24 Jul 01 04:36:10 PM PDT 24 296352135 ps
T1144 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2352781569 Jul 01 04:35:53 PM PDT 24 Jul 01 04:36:01 PM PDT 24 164151030 ps
T1145 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2679863536 Jul 01 04:35:45 PM PDT 24 Jul 01 04:35:51 PM PDT 24 13990418 ps
T1146 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3394104935 Jul 01 04:35:58 PM PDT 24 Jul 01 04:36:10 PM PDT 24 192125141 ps
T1147 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2707508223 Jul 01 04:36:00 PM PDT 24 Jul 01 04:36:13 PM PDT 24 272906887 ps
T1148 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4185995 Jul 01 04:35:45 PM PDT 24 Jul 01 04:36:12 PM PDT 24 1932195180 ps
T1149 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.716803433 Jul 01 04:35:59 PM PDT 24 Jul 01 04:36:11 PM PDT 24 66432246 ps
T1150 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1774700326 Jul 01 04:35:53 PM PDT 24 Jul 01 04:36:01 PM PDT 24 34807640 ps
T1151 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3166782073 Jul 01 04:36:03 PM PDT 24 Jul 01 04:36:14 PM PDT 24 74894095 ps

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3759833435
Short name T3
Test name
Test status
Simulation time 6742375083 ps
CPU time 6.33 seconds
Started Jul 01 06:32:08 PM PDT 24
Finished Jul 01 06:32:15 PM PDT 24
Peak memory 225696 kb
Host smart-8fa51ccd-2141-4094-b821-c7b4b4a2a7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759833435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3759833435
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.572973103
Short name T31
Test name
Test status
Simulation time 3191960710 ps
CPU time 76.56 seconds
Started Jul 01 06:33:51 PM PDT 24
Finished Jul 01 06:35:09 PM PDT 24
Peak memory 256196 kb
Host smart-c6c4e685-41a5-4f8a-a01c-a9c2a57da634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572973103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.572973103
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3973801064
Short name T23
Test name
Test status
Simulation time 60729436853 ps
CPU time 651.18 seconds
Started Jul 01 06:31:34 PM PDT 24
Finished Jul 01 06:42:26 PM PDT 24
Peak memory 299568 kb
Host smart-e36ddb8c-cdea-423f-9dcd-9a097eddf72a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973801064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3973801064
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3971979545
Short name T15
Test name
Test status
Simulation time 4310309442 ps
CPU time 18.33 seconds
Started Jul 01 06:33:16 PM PDT 24
Finished Jul 01 06:33:35 PM PDT 24
Peak memory 236752 kb
Host smart-feaa2b31-cd4e-4756-b208-6bb8ad0d03a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971979545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3971979545
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1362221009
Short name T24
Test name
Test status
Simulation time 50843232653 ps
CPU time 479.66 seconds
Started Jul 01 06:34:17 PM PDT 24
Finished Jul 01 06:42:21 PM PDT 24
Peak memory 282912 kb
Host smart-60391096-470a-4647-942e-4d2c68397b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362221009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1362221009
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1110719528
Short name T115
Test name
Test status
Simulation time 159526778 ps
CPU time 3.4 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:21 PM PDT 24
Peak memory 217232 kb
Host smart-902826ec-fa40-4a2d-bc52-c519f859d89a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110719528 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1110719528
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2558218321
Short name T28
Test name
Test status
Simulation time 449293310 ps
CPU time 8.31 seconds
Started Jul 01 06:31:13 PM PDT 24
Finished Jul 01 06:31:23 PM PDT 24
Peak memory 241992 kb
Host smart-6bdcb7c8-66e8-4f77-9ba3-7c4d4a19d7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558218321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2558218321
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4166709447
Short name T42
Test name
Test status
Simulation time 17995749 ps
CPU time 0.76 seconds
Started Jul 01 06:26:34 PM PDT 24
Finished Jul 01 06:26:36 PM PDT 24
Peak memory 217088 kb
Host smart-b27c649d-ecbd-43f2-a3e1-845e2963b882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166709447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4166709447
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1795958101
Short name T58
Test name
Test status
Simulation time 321905307583 ps
CPU time 551.14 seconds
Started Jul 01 06:28:19 PM PDT 24
Finished Jul 01 06:37:31 PM PDT 24
Peak memory 273012 kb
Host smart-9ee97934-dd54-4241-adac-6bfcc070dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795958101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1795958101
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3090362752
Short name T21
Test name
Test status
Simulation time 182007568375 ps
CPU time 200.65 seconds
Started Jul 01 06:30:25 PM PDT 24
Finished Jul 01 06:33:48 PM PDT 24
Peak memory 250452 kb
Host smart-e096f208-9dbf-4104-969c-04801b57a990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090362752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3090362752
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1817432196
Short name T66
Test name
Test status
Simulation time 13984582216 ps
CPU time 127.42 seconds
Started Jul 01 06:29:37 PM PDT 24
Finished Jul 01 06:31:45 PM PDT 24
Peak memory 241796 kb
Host smart-3d9d1aba-3ec2-49e8-9074-2f24698a7a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817432196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1817432196
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2273710715
Short name T220
Test name
Test status
Simulation time 152923518979 ps
CPU time 666.5 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:44:13 PM PDT 24
Peak memory 272356 kb
Host smart-daaa4524-1fa2-4ca4-90c0-3def9e32a294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273710715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2273710715
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.560773342
Short name T22
Test name
Test status
Simulation time 84298102 ps
CPU time 1.23 seconds
Started Jul 01 06:27:46 PM PDT 24
Finished Jul 01 06:27:48 PM PDT 24
Peak memory 236428 kb
Host smart-16793117-85db-4e63-8bdf-ff4e085e0a49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560773342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.560773342
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1402716233
Short name T179
Test name
Test status
Simulation time 116303545374 ps
CPU time 545.51 seconds
Started Jul 01 06:29:22 PM PDT 24
Finished Jul 01 06:38:28 PM PDT 24
Peak memory 275036 kb
Host smart-0629a1e6-d339-4119-ae7b-1558a8f14f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402716233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1402716233
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3922509358
Short name T54
Test name
Test status
Simulation time 56759942601 ps
CPU time 426.49 seconds
Started Jul 01 06:29:37 PM PDT 24
Finished Jul 01 06:36:44 PM PDT 24
Peak memory 274416 kb
Host smart-fc98b521-95d9-4a59-87c2-c3a9654f9a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922509358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3922509358
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.177848589
Short name T302
Test name
Test status
Simulation time 84030233797 ps
CPU time 856.1 seconds
Started Jul 01 06:32:01 PM PDT 24
Finished Jul 01 06:46:19 PM PDT 24
Peak memory 291172 kb
Host smart-74b3e67c-4bde-4c1a-8826-af58d064e9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177848589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.177848589
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3476552115
Short name T36
Test name
Test status
Simulation time 2621222752 ps
CPU time 39.6 seconds
Started Jul 01 06:33:37 PM PDT 24
Finished Jul 01 06:34:18 PM PDT 24
Peak memory 251484 kb
Host smart-d0180a3e-d042-47da-a321-bf079b1da1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476552115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3476552115
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3487190362
Short name T127
Test name
Test status
Simulation time 377206071 ps
CPU time 13.06 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:18 PM PDT 24
Peak memory 215628 kb
Host smart-177662da-7d7b-461a-be6d-d69e1fb62f64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487190362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3487190362
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.866124435
Short name T138
Test name
Test status
Simulation time 28508808 ps
CPU time 1.91 seconds
Started Jul 01 04:36:05 PM PDT 24
Finished Jul 01 04:36:19 PM PDT 24
Peak memory 215452 kb
Host smart-1f1040e3-1da4-49a4-b8da-13a07c53f66d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866124435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.866124435
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3731386873
Short name T25
Test name
Test status
Simulation time 28768757228 ps
CPU time 19.53 seconds
Started Jul 01 06:31:03 PM PDT 24
Finished Jul 01 06:31:24 PM PDT 24
Peak memory 217552 kb
Host smart-99aff97c-318a-4f22-a526-dc5e87eb1817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731386873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3731386873
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.655066928
Short name T198
Test name
Test status
Simulation time 83006560308 ps
CPU time 560.9 seconds
Started Jul 01 06:33:25 PM PDT 24
Finished Jul 01 06:42:47 PM PDT 24
Peak memory 266236 kb
Host smart-46e7dd10-fb70-498e-a398-ce2043973c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655066928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.655066928
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1216710867
Short name T121
Test name
Test status
Simulation time 323823259 ps
CPU time 4.48 seconds
Started Jul 01 04:35:47 PM PDT 24
Finished Jul 01 04:35:56 PM PDT 24
Peak memory 215812 kb
Host smart-722f73a7-f6ba-4a50-9b94-b4c836646d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216710867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
216710867
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4098734632
Short name T203
Test name
Test status
Simulation time 43519316398 ps
CPU time 421.67 seconds
Started Jul 01 06:27:28 PM PDT 24
Finished Jul 01 06:34:31 PM PDT 24
Peak memory 266608 kb
Host smart-31e561b5-026d-4335-90c2-f4c55c9aa277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098734632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4098734632
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1186845334
Short name T47
Test name
Test status
Simulation time 27299360 ps
CPU time 1.05 seconds
Started Jul 01 06:26:35 PM PDT 24
Finished Jul 01 06:26:37 PM PDT 24
Peak memory 217664 kb
Host smart-537461b4-4394-40f5-88d6-f41ae3bdac54
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186845334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1186845334
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2859747583
Short name T10
Test name
Test status
Simulation time 14159315 ps
CPU time 0.75 seconds
Started Jul 01 06:27:13 PM PDT 24
Finished Jul 01 06:27:14 PM PDT 24
Peak memory 206556 kb
Host smart-0266373c-054d-4077-a3f2-978f70371aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859747583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
859747583
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2358307093
Short name T842
Test name
Test status
Simulation time 11633503032 ps
CPU time 65.77 seconds
Started Jul 01 06:33:07 PM PDT 24
Finished Jul 01 06:34:15 PM PDT 24
Peak memory 258420 kb
Host smart-7f56b5c7-ca41-40c3-b830-d30292e4469b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358307093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2358307093
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.364167982
Short name T59
Test name
Test status
Simulation time 121053732261 ps
CPU time 263.99 seconds
Started Jul 01 06:27:56 PM PDT 24
Finished Jul 01 06:32:21 PM PDT 24
Peak memory 258460 kb
Host smart-cc727d82-90d8-4024-90a5-bc61d8e1b95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364167982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
364167982
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1460688314
Short name T240
Test name
Test status
Simulation time 42680440996 ps
CPU time 209.67 seconds
Started Jul 01 06:33:26 PM PDT 24
Finished Jul 01 06:36:57 PM PDT 24
Peak memory 266792 kb
Host smart-7d4dc857-e51f-4f73-aa0c-f6a9e88e0a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460688314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1460688314
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.289162487
Short name T300
Test name
Test status
Simulation time 162307453297 ps
CPU time 886.93 seconds
Started Jul 01 06:27:13 PM PDT 24
Finished Jul 01 06:42:01 PM PDT 24
Peak memory 271108 kb
Host smart-fbf48ebd-3056-4b76-875c-5d19ebff8fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289162487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.289162487
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2600362665
Short name T51
Test name
Test status
Simulation time 7782670290 ps
CPU time 37.95 seconds
Started Jul 01 06:26:50 PM PDT 24
Finished Jul 01 06:27:31 PM PDT 24
Peak memory 250376 kb
Host smart-96796cea-4c4e-480e-b45b-72d85ccdfa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600362665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2600362665
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1034455562
Short name T46
Test name
Test status
Simulation time 70119186407 ps
CPU time 215.4 seconds
Started Jul 01 06:26:57 PM PDT 24
Finished Jul 01 06:30:33 PM PDT 24
Peak memory 258912 kb
Host smart-98c84d24-ebf1-49d0-9e20-338d27bc7695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034455562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1034455562
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.292623201
Short name T234
Test name
Test status
Simulation time 52941052923 ps
CPU time 433.35 seconds
Started Jul 01 06:29:13 PM PDT 24
Finished Jul 01 06:36:27 PM PDT 24
Peak memory 266856 kb
Host smart-5ce758a3-a010-4d46-99c6-b231115bce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292623201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.292623201
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2576050983
Short name T177
Test name
Test status
Simulation time 91025239644 ps
CPU time 830.86 seconds
Started Jul 01 06:28:38 PM PDT 24
Finished Jul 01 06:42:30 PM PDT 24
Peak memory 266844 kb
Host smart-480170b1-4180-4c25-8e31-8f05893d3846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576050983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2576050983
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3417627203
Short name T43
Test name
Test status
Simulation time 16444065401 ps
CPU time 48.07 seconds
Started Jul 01 06:33:27 PM PDT 24
Finished Jul 01 06:34:16 PM PDT 24
Peak memory 241380 kb
Host smart-b265661c-9b97-4f9f-8b1f-3c4a62472c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417627203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3417627203
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2466737651
Short name T246
Test name
Test status
Simulation time 39861883292 ps
CPU time 172.57 seconds
Started Jul 01 06:27:16 PM PDT 24
Finished Jul 01 06:30:10 PM PDT 24
Peak memory 270568 kb
Host smart-41124698-ba9d-4d9a-92a4-5be38b553c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466737651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2466737651
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1463920198
Short name T204
Test name
Test status
Simulation time 3833062435 ps
CPU time 101.07 seconds
Started Jul 01 06:27:57 PM PDT 24
Finished Jul 01 06:29:39 PM PDT 24
Peak memory 274848 kb
Host smart-24746483-951b-4599-8f56-75c9b17050a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463920198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1463920198
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1678512227
Short name T1115
Test name
Test status
Simulation time 54380871 ps
CPU time 3.07 seconds
Started Jul 01 04:35:54 PM PDT 24
Finished Jul 01 04:36:04 PM PDT 24
Peak memory 215688 kb
Host smart-26572ff6-44d1-4015-a4e3-cab3b4dec191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678512227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
678512227
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1240708186
Short name T190
Test name
Test status
Simulation time 3138350774 ps
CPU time 13.03 seconds
Started Jul 01 04:36:02 PM PDT 24
Finished Jul 01 04:36:26 PM PDT 24
Peak memory 215500 kb
Host smart-0bb26c64-5a29-48de-bed9-68e8e9eafb90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240708186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1240708186
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3068337993
Short name T53
Test name
Test status
Simulation time 70748258423 ps
CPU time 245.48 seconds
Started Jul 01 06:29:58 PM PDT 24
Finished Jul 01 06:34:05 PM PDT 24
Peak memory 253280 kb
Host smart-1837160e-5c3d-47bf-9c64-67816bec1ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068337993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3068337993
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1016858131
Short name T207
Test name
Test status
Simulation time 59214747184 ps
CPU time 410.81 seconds
Started Jul 01 06:29:59 PM PDT 24
Finished Jul 01 06:36:50 PM PDT 24
Peak memory 257316 kb
Host smart-33984438-5bf0-4fbb-8847-259877eaa3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016858131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1016858131
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1767886404
Short name T250
Test name
Test status
Simulation time 6148782301 ps
CPU time 87.83 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:34:27 PM PDT 24
Peak memory 266368 kb
Host smart-4dfce970-4477-495a-8215-7fb6e9b2b218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767886404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1767886404
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1197793192
Short name T193
Test name
Test status
Simulation time 1470981692 ps
CPU time 19.21 seconds
Started Jul 01 04:35:54 PM PDT 24
Finished Jul 01 04:36:20 PM PDT 24
Peak memory 215476 kb
Host smart-800b8138-7d59-41e8-abe6-fb7ac8a7f5fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197793192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1197793192
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1092516946
Short name T330
Test name
Test status
Simulation time 2780169019 ps
CPU time 7.9 seconds
Started Jul 01 06:27:03 PM PDT 24
Finished Jul 01 06:27:12 PM PDT 24
Peak memory 217824 kb
Host smart-1aa4ee4a-1fe9-40b9-9e61-42b33139a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092516946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1092516946
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1301385570
Short name T328
Test name
Test status
Simulation time 278452342 ps
CPU time 13.62 seconds
Started Jul 01 06:30:33 PM PDT 24
Finished Jul 01 06:30:48 PM PDT 24
Peak memory 225504 kb
Host smart-80a4337d-bf0d-4ac2-bd6b-26341d17b7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301385570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1301385570
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1367990164
Short name T1002
Test name
Test status
Simulation time 26422475823 ps
CPU time 315.25 seconds
Started Jul 01 06:31:49 PM PDT 24
Finished Jul 01 06:37:05 PM PDT 24
Peak memory 263556 kb
Host smart-bf6d5bdc-b890-4f29-b2d5-b1145bd94845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367990164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1367990164
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3694376780
Short name T108
Test name
Test status
Simulation time 84610148 ps
CPU time 3.72 seconds
Started Jul 01 06:30:28 PM PDT 24
Finished Jul 01 06:30:33 PM PDT 24
Peak memory 225464 kb
Host smart-f47e4ab8-4b5c-4dbb-bf56-341ff42c0cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694376780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3694376780
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1953581150
Short name T128
Test name
Test status
Simulation time 309485769 ps
CPU time 2.96 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:11 PM PDT 24
Peak memory 215740 kb
Host smart-49dd978d-e94d-47b8-8a1b-d75716be499a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953581150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1953581150
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3474796259
Short name T200
Test name
Test status
Simulation time 390538803 ps
CPU time 2.3 seconds
Started Jul 01 06:26:45 PM PDT 24
Finished Jul 01 06:26:51 PM PDT 24
Peak memory 225564 kb
Host smart-2aa33618-1177-4335-b12a-4fb5142ee6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474796259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3474796259
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.4088305504
Short name T313
Test name
Test status
Simulation time 107180993587 ps
CPU time 137.91 seconds
Started Jul 01 06:29:21 PM PDT 24
Finished Jul 01 06:31:40 PM PDT 24
Peak memory 255756 kb
Host smart-0445bae9-5b4c-43eb-b1ec-9b9dcae3b299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088305504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.4088305504
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2489768611
Short name T166
Test name
Test status
Simulation time 893260419 ps
CPU time 7.97 seconds
Started Jul 01 06:29:16 PM PDT 24
Finished Jul 01 06:29:25 PM PDT 24
Peak memory 225588 kb
Host smart-8fabc1c5-f13a-4bef-a35c-9693947a0d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489768611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2489768611
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1442407148
Short name T301
Test name
Test status
Simulation time 33520613100 ps
CPU time 280.33 seconds
Started Jul 01 06:29:33 PM PDT 24
Finished Jul 01 06:34:15 PM PDT 24
Peak memory 268960 kb
Host smart-2535060d-323b-4d64-b35d-0ce44ab631ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442407148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1442407148
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3891386643
Short name T377
Test name
Test status
Simulation time 1292041704 ps
CPU time 8.17 seconds
Started Jul 01 06:29:25 PM PDT 24
Finished Jul 01 06:29:34 PM PDT 24
Peak memory 217388 kb
Host smart-a0762e6e-4784-4f0d-9551-e3f91529ff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891386643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3891386643
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3414654743
Short name T218
Test name
Test status
Simulation time 45663579010 ps
CPU time 322.29 seconds
Started Jul 01 06:31:10 PM PDT 24
Finished Jul 01 06:36:33 PM PDT 24
Peak memory 258300 kb
Host smart-3e045145-139a-4a34-a0b8-3b4daab4b35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414654743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3414654743
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3275392397
Short name T283
Test name
Test status
Simulation time 4517682220 ps
CPU time 15.72 seconds
Started Jul 01 06:27:02 PM PDT 24
Finished Jul 01 06:27:19 PM PDT 24
Peak memory 233924 kb
Host smart-033a7033-5ef5-4fc4-b273-d5fede279803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275392397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3275392397
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1317804250
Short name T98
Test name
Test status
Simulation time 47268821 ps
CPU time 1.43 seconds
Started Jul 01 04:35:44 PM PDT 24
Finished Jul 01 04:35:51 PM PDT 24
Peak memory 207268 kb
Host smart-e242b2a9-3093-49d7-a161-3f821f6c45f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317804250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1317804250
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2924213399
Short name T1121
Test name
Test status
Simulation time 85579756 ps
CPU time 3.02 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:35:58 PM PDT 24
Peak memory 215644 kb
Host smart-d9f43b92-b867-4f85-a85d-187bfec0a5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924213399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
924213399
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.986779435
Short name T165
Test name
Test status
Simulation time 510020361 ps
CPU time 9.63 seconds
Started Jul 01 06:29:31 PM PDT 24
Finished Jul 01 06:29:42 PM PDT 24
Peak memory 221036 kb
Host smart-41aeca67-c626-44e1-828d-e9e0dcb21729
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=986779435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.986779435
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4185995
Short name T1148
Test name
Test status
Simulation time 1932195180 ps
CPU time 22.93 seconds
Started Jul 01 04:35:45 PM PDT 24
Finished Jul 01 04:36:12 PM PDT 24
Peak memory 207324 kb
Host smart-14dd23f7-99e6-4aaa-8158-75fd822137cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_a
liasing.4185995
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2019187716
Short name T1057
Test name
Test status
Simulation time 361488169 ps
CPU time 23.86 seconds
Started Jul 01 04:35:44 PM PDT 24
Finished Jul 01 04:36:13 PM PDT 24
Peak memory 215432 kb
Host smart-b5fb305f-9a57-406d-8990-f196ec5d3b45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019187716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2019187716
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3236185952
Short name T1078
Test name
Test status
Simulation time 443477352 ps
CPU time 2.77 seconds
Started Jul 01 04:35:45 PM PDT 24
Finished Jul 01 04:35:53 PM PDT 24
Peak memory 216460 kb
Host smart-70842521-55fc-4ea6-8de1-2f5f411cf7fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236185952 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3236185952
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.100370244
Short name T146
Test name
Test status
Simulation time 93600175 ps
CPU time 2.29 seconds
Started Jul 01 04:35:44 PM PDT 24
Finished Jul 01 04:35:52 PM PDT 24
Peak memory 207292 kb
Host smart-8ecda811-ad9c-45c7-9121-c3edb8b903d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100370244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.100370244
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2244622450
Short name T1097
Test name
Test status
Simulation time 13839360 ps
CPU time 0.73 seconds
Started Jul 01 04:35:43 PM PDT 24
Finished Jul 01 04:35:48 PM PDT 24
Peak memory 204308 kb
Host smart-002e91f5-fc32-4367-8fae-235edcd02305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244622450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
244622450
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.229557227
Short name T144
Test name
Test status
Simulation time 49347235 ps
CPU time 1.92 seconds
Started Jul 01 04:35:45 PM PDT 24
Finished Jul 01 04:35:52 PM PDT 24
Peak memory 215528 kb
Host smart-56122647-c8f8-497d-a17a-2de28e7bee76
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229557227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.229557227
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2679863536
Short name T1145
Test name
Test status
Simulation time 13990418 ps
CPU time 0.71 seconds
Started Jul 01 04:35:45 PM PDT 24
Finished Jul 01 04:35:51 PM PDT 24
Peak memory 204156 kb
Host smart-3fb6da86-7ce5-42a0-b8f6-3673f34d6191
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679863536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2679863536
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3003081622
Short name T1113
Test name
Test status
Simulation time 699746662 ps
CPU time 3.81 seconds
Started Jul 01 04:35:52 PM PDT 24
Finished Jul 01 04:36:01 PM PDT 24
Peak memory 215412 kb
Host smart-ff88b820-0302-4df0-9963-54613c0c658a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003081622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3003081622
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2089251741
Short name T1111
Test name
Test status
Simulation time 249687941 ps
CPU time 1.93 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:35:57 PM PDT 24
Peak memory 215668 kb
Host smart-ba99a0c8-4e16-4194-945e-5231fa47cb19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089251741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
089251741
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.413512115
Short name T192
Test name
Test status
Simulation time 3627928684 ps
CPU time 18.14 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:36:13 PM PDT 24
Peak memory 215828 kb
Host smart-6f66c1ea-f960-4034-a830-f067b5eb4d89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413512115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.413512115
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4234070289
Short name T1067
Test name
Test status
Simulation time 639632157 ps
CPU time 15.58 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:20 PM PDT 24
Peak memory 215504 kb
Host smart-56f1db84-db2e-4b30-a243-a17d5447e020
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234070289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4234070289
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3062105549
Short name T1052
Test name
Test status
Simulation time 2458444333 ps
CPU time 24.73 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:29 PM PDT 24
Peak memory 207384 kb
Host smart-d2f9ced7-d6d7-4fd7-9cea-4b3edb3e30cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062105549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3062105549
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2943488678
Short name T99
Test name
Test status
Simulation time 314986875 ps
CPU time 1.46 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:05 PM PDT 24
Peak memory 207240 kb
Host smart-ee668600-0593-407f-8099-29bb98ebb538
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943488678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2943488678
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2139291027
Short name T1106
Test name
Test status
Simulation time 118811299 ps
CPU time 2.58 seconds
Started Jul 01 04:35:53 PM PDT 24
Finished Jul 01 04:36:01 PM PDT 24
Peak memory 216812 kb
Host smart-83309f60-9629-492b-b5f6-56585fa50b0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139291027 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2139291027
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3705432031
Short name T1136
Test name
Test status
Simulation time 341055389 ps
CPU time 2.4 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 215340 kb
Host smart-9b43b952-f6df-4e90-ba4e-050f0eec8618
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705432031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
705432031
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1035144795
Short name T1060
Test name
Test status
Simulation time 19258098 ps
CPU time 0.72 seconds
Started Jul 01 04:35:44 PM PDT 24
Finished Jul 01 04:35:49 PM PDT 24
Peak memory 203920 kb
Host smart-b4062afc-0319-48f1-87cb-9d64555259a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035144795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
035144795
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3807749522
Short name T145
Test name
Test status
Simulation time 22715994 ps
CPU time 1.55 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:06 PM PDT 24
Peak memory 215500 kb
Host smart-c0bd8b7c-dfc5-4f71-9fed-72f065ec29ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807749522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3807749522
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.262140705
Short name T1034
Test name
Test status
Simulation time 10321361 ps
CPU time 0.68 seconds
Started Jul 01 04:35:50 PM PDT 24
Finished Jul 01 04:35:55 PM PDT 24
Peak memory 204164 kb
Host smart-b821a45c-fee4-41a9-9cea-56e4e747eb5f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262140705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.262140705
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1517533517
Short name T1126
Test name
Test status
Simulation time 48187480 ps
CPU time 2.75 seconds
Started Jul 01 04:35:53 PM PDT 24
Finished Jul 01 04:36:02 PM PDT 24
Peak memory 215532 kb
Host smart-a082f8b0-94a9-445f-8208-c162f8aadfcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517533517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1517533517
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.546141400
Short name T118
Test name
Test status
Simulation time 1587542705 ps
CPU time 6.27 seconds
Started Jul 01 04:35:47 PM PDT 24
Finished Jul 01 04:35:57 PM PDT 24
Peak memory 216056 kb
Host smart-95d1369a-739f-45b8-af8b-98d78683981e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546141400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.546141400
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.601823350
Short name T1049
Test name
Test status
Simulation time 257529586 ps
CPU time 3.58 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:35:59 PM PDT 24
Peak memory 217220 kb
Host smart-8e81405b-708a-486d-991f-e41022781cd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601823350 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.601823350
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1148907312
Short name T1102
Test name
Test status
Simulation time 180708145 ps
CPU time 2.56 seconds
Started Jul 01 04:35:54 PM PDT 24
Finished Jul 01 04:36:04 PM PDT 24
Peak memory 215396 kb
Host smart-82e44bc2-edc3-4110-84d1-16b59f8c7a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148907312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1148907312
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.855184346
Short name T1141
Test name
Test status
Simulation time 63252201 ps
CPU time 0.76 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:09 PM PDT 24
Peak memory 203884 kb
Host smart-7d99deb2-63a6-443f-b2f6-45f7526b0b67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855184346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.855184346
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2011026518
Short name T169
Test name
Test status
Simulation time 73152662 ps
CPU time 1.88 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 215416 kb
Host smart-2d9739d3-55eb-4c2a-9139-2d7810c2f7be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011026518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2011026518
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3394104935
Short name T1146
Test name
Test status
Simulation time 192125141 ps
CPU time 2.5 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 215684 kb
Host smart-04edc20e-f70a-4c9f-8b44-f74d7e5c6131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394104935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3394104935
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2868469549
Short name T1139
Test name
Test status
Simulation time 374147168 ps
CPU time 5.64 seconds
Started Jul 01 04:36:02 PM PDT 24
Finished Jul 01 04:36:18 PM PDT 24
Peak memory 215592 kb
Host smart-c1e49614-a5fa-4d12-ac61-822499cd2198
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868469549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2868469549
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3272403370
Short name T1116
Test name
Test status
Simulation time 105262944 ps
CPU time 3.74 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:35:59 PM PDT 24
Peak memory 217228 kb
Host smart-655b1bc7-a441-4015-a263-f99166cea5dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272403370 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3272403370
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.716803433
Short name T1149
Test name
Test status
Simulation time 66432246 ps
CPU time 2.01 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:11 PM PDT 24
Peak memory 215688 kb
Host smart-a0ca3619-9baf-4395-bd32-226bbff54353
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716803433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.716803433
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2503018653
Short name T1134
Test name
Test status
Simulation time 12692585 ps
CPU time 0.77 seconds
Started Jul 01 04:35:54 PM PDT 24
Finished Jul 01 04:36:03 PM PDT 24
Peak memory 203904 kb
Host smart-f8f181e0-685c-4a6f-900b-d44c10d23594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503018653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2503018653
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2837008430
Short name T172
Test name
Test status
Simulation time 246477022 ps
CPU time 1.82 seconds
Started Jul 01 04:36:01 PM PDT 24
Finished Jul 01 04:36:13 PM PDT 24
Peak memory 207220 kb
Host smart-f74fe0be-6800-46d5-9db0-0c343ce69355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837008430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2837008430
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3227831997
Short name T173
Test name
Test status
Simulation time 335534022 ps
CPU time 4 seconds
Started Jul 01 04:35:55 PM PDT 24
Finished Jul 01 04:36:08 PM PDT 24
Peak memory 215740 kb
Host smart-cc975d44-9188-49b3-b57f-f96197e2c5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227831997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3227831997
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1580404503
Short name T195
Test name
Test status
Simulation time 1886902500 ps
CPU time 7.16 seconds
Started Jul 01 04:35:53 PM PDT 24
Finished Jul 01 04:36:07 PM PDT 24
Peak memory 215808 kb
Host smart-d2c246d8-22c3-4896-abdf-2e5178d5f942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580404503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1580404503
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1674552719
Short name T1090
Test name
Test status
Simulation time 311242454 ps
CPU time 2.64 seconds
Started Jul 01 04:35:52 PM PDT 24
Finished Jul 01 04:36:00 PM PDT 24
Peak memory 216672 kb
Host smart-08ff8d23-b60a-4497-8d88-add3cfdc1c9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674552719 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1674552719
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.284695021
Short name T1038
Test name
Test status
Simulation time 93834175 ps
CPU time 1.41 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:08 PM PDT 24
Peak memory 207416 kb
Host smart-bcaa12dd-4898-489e-931f-da4701d75dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284695021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.284695021
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2569007569
Short name T1123
Test name
Test status
Simulation time 28121066 ps
CPU time 0.78 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:06 PM PDT 24
Peak memory 204080 kb
Host smart-9a825f9f-acfc-4e70-8a1c-655509bb8fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569007569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2569007569
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.402548147
Short name T1103
Test name
Test status
Simulation time 379852091 ps
CPU time 2.87 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:35:58 PM PDT 24
Peak memory 215492 kb
Host smart-4d631287-1175-4358-b01e-06c035a53a4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402548147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.402548147
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2073487866
Short name T1105
Test name
Test status
Simulation time 57013494 ps
CPU time 3.44 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:11 PM PDT 24
Peak memory 215660 kb
Host smart-7c0dcca6-3f1c-4d99-8a00-e1ccfad61006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073487866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2073487866
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2214044209
Short name T1120
Test name
Test status
Simulation time 215173409 ps
CPU time 12.97 seconds
Started Jul 01 04:35:55 PM PDT 24
Finished Jul 01 04:36:16 PM PDT 24
Peak memory 215504 kb
Host smart-c983450f-6187-46a9-b539-c43592c3d362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214044209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2214044209
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2712748291
Short name T1074
Test name
Test status
Simulation time 271664510 ps
CPU time 1.99 seconds
Started Jul 01 04:36:02 PM PDT 24
Finished Jul 01 04:36:15 PM PDT 24
Peak memory 215708 kb
Host smart-454a25eb-e4f3-4e39-a2bb-fb6db64dc194
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712748291 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2712748291
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3741780382
Short name T1128
Test name
Test status
Simulation time 54596870 ps
CPU time 1.95 seconds
Started Jul 01 04:36:00 PM PDT 24
Finished Jul 01 04:36:12 PM PDT 24
Peak memory 215628 kb
Host smart-5acc1c11-65d9-4dc7-89fb-e5ab82cb9fe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741780382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3741780382
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.298790636
Short name T1087
Test name
Test status
Simulation time 17217947 ps
CPU time 0.74 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 203904 kb
Host smart-47ddbbc3-53f0-4441-b337-312d12519802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298790636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.298790636
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.263628838
Short name T1071
Test name
Test status
Simulation time 761641461 ps
CPU time 4.15 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:12 PM PDT 24
Peak memory 215520 kb
Host smart-7734ac6f-095c-4f3a-b619-5ce0c90a427e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263628838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.263628838
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3752766359
Short name T123
Test name
Test status
Simulation time 75812810 ps
CPU time 4.76 seconds
Started Jul 01 04:36:00 PM PDT 24
Finished Jul 01 04:36:15 PM PDT 24
Peak memory 216744 kb
Host smart-8f82c53a-7a0d-456e-a14f-41e4aa693d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752766359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3752766359
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3717712407
Short name T1068
Test name
Test status
Simulation time 427592361 ps
CPU time 6.95 seconds
Started Jul 01 04:36:01 PM PDT 24
Finished Jul 01 04:36:18 PM PDT 24
Peak memory 215752 kb
Host smart-a4219da9-8120-4ecb-bc11-277dd6089c15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717712407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3717712407
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4004586495
Short name T131
Test name
Test status
Simulation time 55102592 ps
CPU time 3.82 seconds
Started Jul 01 04:36:00 PM PDT 24
Finished Jul 01 04:36:14 PM PDT 24
Peak memory 217172 kb
Host smart-d8aff5c2-82a9-4bc8-bf1c-cfea366c7466
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004586495 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4004586495
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2735074102
Short name T1129
Test name
Test status
Simulation time 808250221 ps
CPU time 1.91 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 215416 kb
Host smart-f528e6fd-a317-4983-ac0c-394a3bccf19e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735074102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2735074102
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3597159922
Short name T1122
Test name
Test status
Simulation time 13740028 ps
CPU time 0.75 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 204032 kb
Host smart-99b704d6-8436-454f-b40c-88d64f3b51c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597159922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3597159922
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1638327288
Short name T1076
Test name
Test status
Simulation time 68136755 ps
CPU time 1.79 seconds
Started Jul 01 04:36:00 PM PDT 24
Finished Jul 01 04:36:11 PM PDT 24
Peak memory 215340 kb
Host smart-dd825d97-7210-4db2-95ca-3734dfac4e22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638327288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1638327288
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3096894152
Short name T194
Test name
Test status
Simulation time 519943739 ps
CPU time 7.23 seconds
Started Jul 01 04:36:07 PM PDT 24
Finished Jul 01 04:36:35 PM PDT 24
Peak memory 215388 kb
Host smart-906ce5de-8f99-4c04-8ca9-28a4bc8e5f79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096894152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3096894152
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1095244093
Short name T134
Test name
Test status
Simulation time 149834660 ps
CPU time 3.81 seconds
Started Jul 01 04:36:00 PM PDT 24
Finished Jul 01 04:36:14 PM PDT 24
Peak memory 218368 kb
Host smart-5786d7d3-9786-4bca-8d95-6b0c5e06ca6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095244093 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1095244093
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1240374691
Short name T139
Test name
Test status
Simulation time 32190315 ps
CPU time 1.21 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:09 PM PDT 24
Peak memory 215472 kb
Host smart-194fa25c-3263-48cb-8f01-925f5b3a29cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240374691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1240374691
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4013618914
Short name T1108
Test name
Test status
Simulation time 17691632 ps
CPU time 0.76 seconds
Started Jul 01 04:36:03 PM PDT 24
Finished Jul 01 04:36:15 PM PDT 24
Peak memory 203956 kb
Host smart-097ee40c-731d-4350-9ad1-be4dacd2cbed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013618914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4013618914
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2810131740
Short name T1080
Test name
Test status
Simulation time 57247827 ps
CPU time 1.75 seconds
Started Jul 01 04:36:06 PM PDT 24
Finished Jul 01 04:36:22 PM PDT 24
Peak memory 215384 kb
Host smart-3fb29fc6-353f-4fda-96c2-e0638c558aa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810131740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2810131740
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1011411353
Short name T1118
Test name
Test status
Simulation time 220096539 ps
CPU time 2.4 seconds
Started Jul 01 04:36:00 PM PDT 24
Finished Jul 01 04:36:13 PM PDT 24
Peak memory 215804 kb
Host smart-4e95d0e8-7581-4199-ab8d-79d54c95ea8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011411353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1011411353
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4174216099
Short name T135
Test name
Test status
Simulation time 326725965 ps
CPU time 4.06 seconds
Started Jul 01 04:36:03 PM PDT 24
Finished Jul 01 04:36:19 PM PDT 24
Peak memory 217432 kb
Host smart-99916a0f-b77c-45a5-b5af-8e52b6804be9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174216099 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4174216099
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.731726630
Short name T161
Test name
Test status
Simulation time 42761424 ps
CPU time 1.31 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:09 PM PDT 24
Peak memory 207160 kb
Host smart-e152d309-a7df-496d-9564-d0efb3767861
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731726630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.731726630
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4247348029
Short name T1050
Test name
Test status
Simulation time 13130914 ps
CPU time 0.78 seconds
Started Jul 01 04:36:01 PM PDT 24
Finished Jul 01 04:36:12 PM PDT 24
Peak memory 204208 kb
Host smart-bb0d7dec-f531-44a7-ad48-967d3f4be123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247348029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4247348029
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3812223691
Short name T162
Test name
Test status
Simulation time 104194615 ps
CPU time 2.89 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:11 PM PDT 24
Peak memory 215404 kb
Host smart-c5ccf12c-3abd-4278-b852-79d69cba01bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812223691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3812223691
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2707508223
Short name T1147
Test name
Test status
Simulation time 272906887 ps
CPU time 3.72 seconds
Started Jul 01 04:36:00 PM PDT 24
Finished Jul 01 04:36:13 PM PDT 24
Peak memory 215844 kb
Host smart-8897dadf-ead9-40ba-ae3a-f06bcc3843e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707508223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2707508223
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2690298513
Short name T1098
Test name
Test status
Simulation time 540154678 ps
CPU time 7.01 seconds
Started Jul 01 04:36:00 PM PDT 24
Finished Jul 01 04:36:17 PM PDT 24
Peak memory 215368 kb
Host smart-505d16fc-ddb5-415c-b096-283cd992cf75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690298513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2690298513
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1052255229
Short name T1056
Test name
Test status
Simulation time 110152143 ps
CPU time 1.73 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:11 PM PDT 24
Peak memory 215464 kb
Host smart-47c33e2a-70a4-4ea3-a1b5-369d8971df82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052255229 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1052255229
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.754307510
Short name T1095
Test name
Test status
Simulation time 383618230 ps
CPU time 1.43 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:11 PM PDT 24
Peak memory 207288 kb
Host smart-b3e0103a-39bd-495d-8c39-5cc7964d7243
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754307510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.754307510
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2645388670
Short name T1093
Test name
Test status
Simulation time 11311456 ps
CPU time 0.71 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:08 PM PDT 24
Peak memory 204208 kb
Host smart-8742cf46-0f88-44c6-bcd2-5faea8e97f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645388670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2645388670
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2226713106
Short name T1053
Test name
Test status
Simulation time 56884084 ps
CPU time 1.72 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 215544 kb
Host smart-3f7c7a8f-08f0-4943-b821-23d5af7107f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226713106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2226713106
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3797730021
Short name T113
Test name
Test status
Simulation time 31748976 ps
CPU time 1.84 seconds
Started Jul 01 04:36:03 PM PDT 24
Finished Jul 01 04:36:16 PM PDT 24
Peak memory 215844 kb
Host smart-f088caed-0d17-4d0b-a86d-d277e889f064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797730021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3797730021
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3168038810
Short name T1054
Test name
Test status
Simulation time 110083935 ps
CPU time 6.72 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:15 PM PDT 24
Peak memory 215404 kb
Host smart-2b985cef-7885-43c6-8fa1-486aae96ace0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168038810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3168038810
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.895208856
Short name T133
Test name
Test status
Simulation time 120997409 ps
CPU time 2.4 seconds
Started Jul 01 04:36:04 PM PDT 24
Finished Jul 01 04:36:18 PM PDT 24
Peak memory 215624 kb
Host smart-13e4d0ed-7d8c-452f-82e6-dc9a294238e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895208856 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.895208856
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3533688731
Short name T1081
Test name
Test status
Simulation time 20130285 ps
CPU time 1.09 seconds
Started Jul 01 04:36:02 PM PDT 24
Finished Jul 01 04:36:13 PM PDT 24
Peak memory 215296 kb
Host smart-0bf48613-bdf2-4d9c-a632-eb1d73c54ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533688731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3533688731
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2734118358
Short name T1044
Test name
Test status
Simulation time 32282931 ps
CPU time 0.73 seconds
Started Jul 01 04:36:04 PM PDT 24
Finished Jul 01 04:36:15 PM PDT 24
Peak memory 204036 kb
Host smart-77d498ff-b2fd-4433-9cbd-e480f9980bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734118358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2734118358
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.775422663
Short name T164
Test name
Test status
Simulation time 245884798 ps
CPU time 3.19 seconds
Started Jul 01 04:36:03 PM PDT 24
Finished Jul 01 04:36:17 PM PDT 24
Peak memory 215492 kb
Host smart-e44f3a56-0378-4b06-bb92-ae7896df0cb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775422663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.775422663
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2043838846
Short name T124
Test name
Test status
Simulation time 138769551 ps
CPU time 2.47 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 216784 kb
Host smart-ced10afa-f8ef-4efe-b4b5-9b4bcffc167d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043838846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2043838846
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.338029255
Short name T114
Test name
Test status
Simulation time 363296077 ps
CPU time 6.36 seconds
Started Jul 01 04:36:04 PM PDT 24
Finished Jul 01 04:36:22 PM PDT 24
Peak memory 215612 kb
Host smart-53230a98-ba9c-47ce-b7d9-c19633a2254b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338029255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.338029255
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.883997452
Short name T1109
Test name
Test status
Simulation time 222771968 ps
CPU time 1.58 seconds
Started Jul 01 04:36:09 PM PDT 24
Finished Jul 01 04:36:24 PM PDT 24
Peak memory 215532 kb
Host smart-2e645bc7-00db-4c5d-a219-6765df951283
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883997452 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.883997452
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3798276935
Short name T1039
Test name
Test status
Simulation time 141990930 ps
CPU time 2.49 seconds
Started Jul 01 04:36:04 PM PDT 24
Finished Jul 01 04:36:20 PM PDT 24
Peak memory 215524 kb
Host smart-24d25bcb-fee4-4386-b458-ce8c21164de7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798276935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3798276935
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2235088624
Short name T1033
Test name
Test status
Simulation time 14738809 ps
CPU time 0.75 seconds
Started Jul 01 04:36:01 PM PDT 24
Finished Jul 01 04:36:12 PM PDT 24
Peak memory 203924 kb
Host smart-63e30c10-b940-4761-9877-c83418a10947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235088624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2235088624
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3591619660
Short name T170
Test name
Test status
Simulation time 143616476 ps
CPU time 1.86 seconds
Started Jul 01 04:36:04 PM PDT 24
Finished Jul 01 04:36:17 PM PDT 24
Peak memory 215520 kb
Host smart-6e88b9f4-f6ed-42fd-929b-eaef7b1db637
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591619660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3591619660
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.404980747
Short name T129
Test name
Test status
Simulation time 336181065 ps
CPU time 2.74 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:36:33 PM PDT 24
Peak memory 215640 kb
Host smart-28629330-6818-4c33-821c-736b1c88cf48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404980747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.404980747
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1588182507
Short name T117
Test name
Test status
Simulation time 284986008 ps
CPU time 16.87 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:36:47 PM PDT 24
Peak memory 215464 kb
Host smart-e66babe2-3001-45ce-9eaf-958578a4d222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588182507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1588182507
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1068597088
Short name T1061
Test name
Test status
Simulation time 1704750998 ps
CPU time 17.59 seconds
Started Jul 01 04:35:50 PM PDT 24
Finished Jul 01 04:36:12 PM PDT 24
Peak memory 207212 kb
Host smart-43078d0e-89aa-44eb-81a7-3782748f9224
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068597088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1068597088
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2515617907
Short name T148
Test name
Test status
Simulation time 2362287457 ps
CPU time 36.15 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:41 PM PDT 24
Peak memory 207380 kb
Host smart-917b49d4-6f6e-42ca-bf58-b6cb0367d33e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515617907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2515617907
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3859276044
Short name T97
Test name
Test status
Simulation time 23634675 ps
CPU time 1.33 seconds
Started Jul 01 04:35:53 PM PDT 24
Finished Jul 01 04:36:01 PM PDT 24
Peak memory 216540 kb
Host smart-1b486be2-6e30-40b6-8f0e-3870ed7aad12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859276044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3859276044
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2745698815
Short name T132
Test name
Test status
Simulation time 211746320 ps
CPU time 2.78 seconds
Started Jul 01 04:35:50 PM PDT 24
Finished Jul 01 04:35:58 PM PDT 24
Peak memory 216524 kb
Host smart-8fd29b8c-0052-4d26-8766-cfdb64ca4a8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745698815 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2745698815
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1196544150
Short name T1099
Test name
Test status
Simulation time 131274137 ps
CPU time 2.48 seconds
Started Jul 01 04:35:50 PM PDT 24
Finished Jul 01 04:35:57 PM PDT 24
Peak memory 207392 kb
Host smart-b487b5f2-6726-4fb3-8efb-890a90715b4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196544150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
196544150
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2855529519
Short name T1104
Test name
Test status
Simulation time 41759281 ps
CPU time 0.77 seconds
Started Jul 01 04:35:55 PM PDT 24
Finished Jul 01 04:36:05 PM PDT 24
Peak memory 204176 kb
Host smart-99cfcd40-df02-4ce3-8ed5-dd02f3133119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855529519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
855529519
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4119035021
Short name T149
Test name
Test status
Simulation time 37282467 ps
CPU time 1.32 seconds
Started Jul 01 04:35:57 PM PDT 24
Finished Jul 01 04:36:07 PM PDT 24
Peak memory 215420 kb
Host smart-037ec1ba-ccaa-4a25-9252-7928d5cd5721
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119035021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4119035021
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.672412064
Short name T1140
Test name
Test status
Simulation time 38792960 ps
CPU time 0.71 seconds
Started Jul 01 04:35:50 PM PDT 24
Finished Jul 01 04:35:55 PM PDT 24
Peak memory 204264 kb
Host smart-5dab6f63-006d-48b4-b95e-78836820f338
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672412064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.672412064
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1485869757
Short name T168
Test name
Test status
Simulation time 533319020 ps
CPU time 3.12 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:35:58 PM PDT 24
Peak memory 215412 kb
Host smart-1b9b90fe-ee5a-4b73-9bf0-666f9859e63e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485869757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1485869757
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3761349225
Short name T122
Test name
Test status
Simulation time 63358022 ps
CPU time 2.28 seconds
Started Jul 01 04:35:49 PM PDT 24
Finished Jul 01 04:35:55 PM PDT 24
Peak memory 215848 kb
Host smart-c842b571-f660-4d4f-8987-74aabf86f552
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761349225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
761349225
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3838309810
Short name T1133
Test name
Test status
Simulation time 635984594 ps
CPU time 12.52 seconds
Started Jul 01 04:35:49 PM PDT 24
Finished Jul 01 04:36:05 PM PDT 24
Peak memory 215524 kb
Host smart-c55cc5c1-353a-4306-b976-f8d20b035c55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838309810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3838309810
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4203291201
Short name T1096
Test name
Test status
Simulation time 43316980 ps
CPU time 0.71 seconds
Started Jul 01 04:36:08 PM PDT 24
Finished Jul 01 04:36:22 PM PDT 24
Peak memory 203936 kb
Host smart-002fa731-3426-4d99-94eb-bafbd193ad30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203291201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4203291201
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.221408200
Short name T1117
Test name
Test status
Simulation time 13290696 ps
CPU time 0.74 seconds
Started Jul 01 04:36:06 PM PDT 24
Finished Jul 01 04:36:20 PM PDT 24
Peak memory 204036 kb
Host smart-6bcd8d20-7e18-4b20-acb8-e55cb85e69f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221408200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.221408200
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.366129866
Short name T1047
Test name
Test status
Simulation time 41407153 ps
CPU time 0.74 seconds
Started Jul 01 04:36:09 PM PDT 24
Finished Jul 01 04:36:24 PM PDT 24
Peak memory 203956 kb
Host smart-70c06aa6-6994-4973-a585-092a5327e1e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366129866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.366129866
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.551694896
Short name T1051
Test name
Test status
Simulation time 33327687 ps
CPU time 0.73 seconds
Started Jul 01 04:36:07 PM PDT 24
Finished Jul 01 04:36:21 PM PDT 24
Peak memory 204020 kb
Host smart-9b7e2983-c6b9-4084-adec-4dc8e9a7848d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551694896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.551694896
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3561880560
Short name T1127
Test name
Test status
Simulation time 64763171 ps
CPU time 0.8 seconds
Started Jul 01 04:36:10 PM PDT 24
Finished Jul 01 04:36:25 PM PDT 24
Peak memory 204236 kb
Host smart-b2426f11-29e0-481d-8c3d-70e760dce57f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561880560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3561880560
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2994839335
Short name T1046
Test name
Test status
Simulation time 33416681 ps
CPU time 0.74 seconds
Started Jul 01 04:36:09 PM PDT 24
Finished Jul 01 04:36:24 PM PDT 24
Peak memory 204200 kb
Host smart-85c98a9a-6bd5-4ed2-9d02-417817102efe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994839335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2994839335
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2655744085
Short name T1125
Test name
Test status
Simulation time 61719848 ps
CPU time 0.74 seconds
Started Jul 01 04:36:07 PM PDT 24
Finished Jul 01 04:36:21 PM PDT 24
Peak memory 204312 kb
Host smart-15f0cf11-da6b-4722-b754-193e3094a6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655744085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2655744085
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2748510487
Short name T1119
Test name
Test status
Simulation time 13746074 ps
CPU time 0.71 seconds
Started Jul 01 04:36:06 PM PDT 24
Finished Jul 01 04:36:20 PM PDT 24
Peak memory 203880 kb
Host smart-07354708-3715-4439-9720-f411fcd82a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748510487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2748510487
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3140088482
Short name T1082
Test name
Test status
Simulation time 83568521 ps
CPU time 0.77 seconds
Started Jul 01 04:36:08 PM PDT 24
Finished Jul 01 04:36:23 PM PDT 24
Peak memory 204272 kb
Host smart-b7aa40f1-9081-4996-82e7-b7898d243ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140088482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3140088482
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1827208662
Short name T1135
Test name
Test status
Simulation time 49266663 ps
CPU time 0.83 seconds
Started Jul 01 04:36:07 PM PDT 24
Finished Jul 01 04:36:21 PM PDT 24
Peak memory 204016 kb
Host smart-5d5e3c0d-d0da-4628-b31e-d19444511c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827208662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1827208662
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.591786958
Short name T141
Test name
Test status
Simulation time 4259244954 ps
CPU time 22.85 seconds
Started Jul 01 04:35:54 PM PDT 24
Finished Jul 01 04:36:23 PM PDT 24
Peak memory 215532 kb
Host smart-9ba24ebc-d708-4448-8d5f-a9c70ed5b09d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591786958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.591786958
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1973953722
Short name T1089
Test name
Test status
Simulation time 3958265005 ps
CPU time 13.55 seconds
Started Jul 01 04:35:57 PM PDT 24
Finished Jul 01 04:36:20 PM PDT 24
Peak memory 207260 kb
Host smart-30063038-ef6a-45ba-be9b-00c8014c3b23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973953722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1973953722
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2405855286
Short name T100
Test name
Test status
Simulation time 44893514 ps
CPU time 1.44 seconds
Started Jul 01 04:35:49 PM PDT 24
Finished Jul 01 04:35:55 PM PDT 24
Peak memory 207304 kb
Host smart-3853bfdf-0ec3-4426-a770-fdfa68fce9f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405855286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2405855286
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.138827735
Short name T1059
Test name
Test status
Simulation time 64045362 ps
CPU time 1.89 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:06 PM PDT 24
Peak memory 216504 kb
Host smart-49f4bbed-d510-4f96-8385-3bceb267b0d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138827735 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.138827735
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1655403458
Short name T1037
Test name
Test status
Simulation time 673865162 ps
CPU time 1.97 seconds
Started Jul 01 04:35:57 PM PDT 24
Finished Jul 01 04:36:08 PM PDT 24
Peak memory 215420 kb
Host smart-75cc1d84-8e57-4a61-bca6-7f886b459b33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655403458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
655403458
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1681892923
Short name T1055
Test name
Test status
Simulation time 38880816 ps
CPU time 0.73 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:05 PM PDT 24
Peak memory 204020 kb
Host smart-1ec9b78f-9c83-49ff-a622-0f47f6cf3538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681892923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
681892923
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1774700326
Short name T1150
Test name
Test status
Simulation time 34807640 ps
CPU time 1.25 seconds
Started Jul 01 04:35:53 PM PDT 24
Finished Jul 01 04:36:01 PM PDT 24
Peak memory 215456 kb
Host smart-f4144b89-36eb-4fa6-a623-a4f67e2c7f5f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774700326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1774700326
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1721726804
Short name T1048
Test name
Test status
Simulation time 36649099 ps
CPU time 0.72 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:35:56 PM PDT 24
Peak memory 203784 kb
Host smart-e12cef16-3f59-4720-8a71-00f5d7e35b10
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721726804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1721726804
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3782021902
Short name T1086
Test name
Test status
Simulation time 66232151 ps
CPU time 1.95 seconds
Started Jul 01 04:35:50 PM PDT 24
Finished Jul 01 04:35:56 PM PDT 24
Peak memory 215444 kb
Host smart-dbc959fe-77ee-46a3-bbed-8e14a23b1f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782021902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3782021902
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2352781569
Short name T1144
Test name
Test status
Simulation time 164151030 ps
CPU time 1.56 seconds
Started Jul 01 04:35:53 PM PDT 24
Finished Jul 01 04:36:01 PM PDT 24
Peak memory 215684 kb
Host smart-10720463-d9c7-4d26-ba40-d1e4979866cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352781569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
352781569
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1234529458
Short name T1107
Test name
Test status
Simulation time 4137087981 ps
CPU time 13.7 seconds
Started Jul 01 04:35:52 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 215588 kb
Host smart-e84e39c9-8f0f-4404-840b-29bb350826b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234529458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1234529458
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2042386436
Short name T1035
Test name
Test status
Simulation time 74654147 ps
CPU time 0.75 seconds
Started Jul 01 04:36:09 PM PDT 24
Finished Jul 01 04:36:25 PM PDT 24
Peak memory 204004 kb
Host smart-5a514be6-f80b-4cf8-8d8f-5ff42f2cc37e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042386436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2042386436
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1965802978
Short name T1083
Test name
Test status
Simulation time 17884443 ps
CPU time 0.69 seconds
Started Jul 01 04:36:06 PM PDT 24
Finished Jul 01 04:36:20 PM PDT 24
Peak memory 203936 kb
Host smart-b4c92327-17b4-4644-b93b-874e9efbca3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965802978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1965802978
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2155148615
Short name T1042
Test name
Test status
Simulation time 13073292 ps
CPU time 0.69 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:36:31 PM PDT 24
Peak memory 203884 kb
Host smart-2dbacdb0-8285-4f31-8ca5-38f42f12821d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155148615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2155148615
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2860434523
Short name T1069
Test name
Test status
Simulation time 18629413 ps
CPU time 0.71 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:36:31 PM PDT 24
Peak memory 203900 kb
Host smart-5e450af0-5e60-4f7b-8e4b-6b7310c37a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860434523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2860434523
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3536868890
Short name T1112
Test name
Test status
Simulation time 18181031 ps
CPU time 0.81 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:36:29 PM PDT 24
Peak memory 203904 kb
Host smart-67ba3bae-2080-4229-9d5f-c96a43d5b957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536868890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3536868890
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1377922413
Short name T1043
Test name
Test status
Simulation time 67452652 ps
CPU time 0.72 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:36:29 PM PDT 24
Peak memory 203832 kb
Host smart-0af13f57-5794-47f0-89b0-76916ab2e99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377922413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1377922413
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2566026371
Short name T1091
Test name
Test status
Simulation time 18490446 ps
CPU time 0.78 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:36:29 PM PDT 24
Peak memory 203904 kb
Host smart-67a9d1b4-6610-4baf-985f-c448cfe7847e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566026371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2566026371
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.267598888
Short name T1084
Test name
Test status
Simulation time 16160925 ps
CPU time 0.76 seconds
Started Jul 01 04:36:06 PM PDT 24
Finished Jul 01 04:36:20 PM PDT 24
Peak memory 204044 kb
Host smart-f22d7b04-093a-46a9-8908-966de964b2ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267598888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.267598888
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3166782073
Short name T1151
Test name
Test status
Simulation time 74894095 ps
CPU time 0.78 seconds
Started Jul 01 04:36:03 PM PDT 24
Finished Jul 01 04:36:14 PM PDT 24
Peak memory 203964 kb
Host smart-cc39c3ef-02c1-4dd8-96a1-140832c96783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166782073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3166782073
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1498775967
Short name T1092
Test name
Test status
Simulation time 11502328 ps
CPU time 0.71 seconds
Started Jul 01 04:36:09 PM PDT 24
Finished Jul 01 04:36:23 PM PDT 24
Peak memory 203996 kb
Host smart-74b9af23-e32f-4594-a47c-eda57d583ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498775967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1498775967
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1593754462
Short name T143
Test name
Test status
Simulation time 626008110 ps
CPU time 20.3 seconds
Started Jul 01 04:35:57 PM PDT 24
Finished Jul 01 04:36:27 PM PDT 24
Peak memory 215336 kb
Host smart-cbe2278e-8d38-4e85-beea-761fd09f90a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593754462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1593754462
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1410505025
Short name T1088
Test name
Test status
Simulation time 1635623675 ps
CPU time 22.8 seconds
Started Jul 01 04:35:57 PM PDT 24
Finished Jul 01 04:36:29 PM PDT 24
Peak memory 215436 kb
Host smart-d9242d4c-1f2b-4edd-be65-c4f9640a3a13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410505025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1410505025
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1435573409
Short name T1045
Test name
Test status
Simulation time 53418639 ps
CPU time 0.96 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:09 PM PDT 24
Peak memory 206956 kb
Host smart-810e9c0d-b7bc-4312-8fe7-92a223463e7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435573409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1435573409
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1642602478
Short name T1100
Test name
Test status
Simulation time 460674237 ps
CPU time 3.17 seconds
Started Jul 01 04:35:53 PM PDT 24
Finished Jul 01 04:36:02 PM PDT 24
Peak memory 216932 kb
Host smart-2ff7b28c-7243-455d-94ef-15d3ac58baef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642602478 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1642602478
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1095808489
Short name T140
Test name
Test status
Simulation time 330640871 ps
CPU time 2.69 seconds
Started Jul 01 04:35:57 PM PDT 24
Finished Jul 01 04:36:09 PM PDT 24
Peak memory 207160 kb
Host smart-a54b8d0f-78e2-4a50-8fac-607b7d54726f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095808489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
095808489
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.646677720
Short name T1110
Test name
Test status
Simulation time 16612453 ps
CPU time 0.81 seconds
Started Jul 01 04:35:55 PM PDT 24
Finished Jul 01 04:36:03 PM PDT 24
Peak memory 204236 kb
Host smart-150bc503-0231-415e-93b2-ca4b0a5d21be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646677720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.646677720
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2183940976
Short name T142
Test name
Test status
Simulation time 100295370 ps
CPU time 2.04 seconds
Started Jul 01 04:35:55 PM PDT 24
Finished Jul 01 04:36:05 PM PDT 24
Peak memory 215536 kb
Host smart-f730bd85-1a52-4a5c-a0b1-8bdd9966cbdf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183940976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2183940976
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2192340094
Short name T1114
Test name
Test status
Simulation time 10309902 ps
CPU time 0.71 seconds
Started Jul 01 04:35:57 PM PDT 24
Finished Jul 01 04:36:06 PM PDT 24
Peak memory 203912 kb
Host smart-262e6879-bceb-48bc-a03e-969fd0b33135
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192340094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2192340094
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4275166099
Short name T1101
Test name
Test status
Simulation time 94792678 ps
CPU time 1.72 seconds
Started Jul 01 04:35:54 PM PDT 24
Finished Jul 01 04:36:04 PM PDT 24
Peak memory 215392 kb
Host smart-ac781852-fda1-4e53-a128-699082baccba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275166099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4275166099
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1251959132
Short name T1079
Test name
Test status
Simulation time 127151236 ps
CPU time 3.08 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:35:59 PM PDT 24
Peak memory 215748 kb
Host smart-27e34c77-e6c0-496e-ab19-15f7076ad23c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251959132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
251959132
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.584361110
Short name T188
Test name
Test status
Simulation time 1392315039 ps
CPU time 13.17 seconds
Started Jul 01 04:35:54 PM PDT 24
Finished Jul 01 04:36:15 PM PDT 24
Peak memory 215928 kb
Host smart-d4cc2a4c-3c6e-4207-baef-83a9e3f0efd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584361110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.584361110
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1174168323
Short name T1131
Test name
Test status
Simulation time 110570026 ps
CPU time 0.72 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:36:32 PM PDT 24
Peak memory 203900 kb
Host smart-62275d0d-9e18-4d08-bcd4-564d6294e278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174168323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1174168323
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2066349163
Short name T1138
Test name
Test status
Simulation time 25949163 ps
CPU time 0.74 seconds
Started Jul 01 04:36:05 PM PDT 24
Finished Jul 01 04:36:18 PM PDT 24
Peak memory 204308 kb
Host smart-d207ae7e-34a9-472e-86c7-57de22f7ca4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066349163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2066349163
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1539513357
Short name T1094
Test name
Test status
Simulation time 15995020 ps
CPU time 0.7 seconds
Started Jul 01 04:36:08 PM PDT 24
Finished Jul 01 04:36:23 PM PDT 24
Peak memory 204264 kb
Host smart-fdce3e18-6d25-49a2-bec6-bd418c51ebaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539513357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1539513357
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3433527411
Short name T1124
Test name
Test status
Simulation time 14501345 ps
CPU time 0.84 seconds
Started Jul 01 04:36:07 PM PDT 24
Finished Jul 01 04:36:21 PM PDT 24
Peak memory 204016 kb
Host smart-56c07247-e9ad-446b-966e-d73e94e2231b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433527411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3433527411
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2859340746
Short name T1040
Test name
Test status
Simulation time 23404786 ps
CPU time 0.69 seconds
Started Jul 01 04:36:09 PM PDT 24
Finished Jul 01 04:36:24 PM PDT 24
Peak memory 203832 kb
Host smart-f41ef7b9-7e41-4a3f-97a0-3e01a1f7303d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859340746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2859340746
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2890516030
Short name T1077
Test name
Test status
Simulation time 47421894 ps
CPU time 0.67 seconds
Started Jul 01 04:36:14 PM PDT 24
Finished Jul 01 04:36:33 PM PDT 24
Peak memory 203832 kb
Host smart-e72289df-5f18-4f92-95f5-1b8e41a593a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890516030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2890516030
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.615857158
Short name T1058
Test name
Test status
Simulation time 32579015 ps
CPU time 0.75 seconds
Started Jul 01 04:36:19 PM PDT 24
Finished Jul 01 04:36:33 PM PDT 24
Peak memory 204216 kb
Host smart-ce8b158b-3511-4589-8ccc-d902d430da11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615857158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.615857158
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1202867390
Short name T1036
Test name
Test status
Simulation time 35256555 ps
CPU time 0.75 seconds
Started Jul 01 04:36:20 PM PDT 24
Finished Jul 01 04:36:34 PM PDT 24
Peak memory 203940 kb
Host smart-cc55c33b-3a2e-485d-b259-f63d5c3cad4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202867390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1202867390
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1097674613
Short name T1062
Test name
Test status
Simulation time 14640754 ps
CPU time 0.75 seconds
Started Jul 01 04:36:09 PM PDT 24
Finished Jul 01 04:36:24 PM PDT 24
Peak memory 204012 kb
Host smart-f3936773-f83c-40fb-beb8-084eeed8dfb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097674613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1097674613
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2976896496
Short name T1064
Test name
Test status
Simulation time 120687540 ps
CPU time 0.76 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:36:31 PM PDT 24
Peak memory 203932 kb
Host smart-68b669c7-0712-4247-9ef9-4a2fde1d8d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976896496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2976896496
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3793224403
Short name T1130
Test name
Test status
Simulation time 25096891 ps
CPU time 1.63 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:07 PM PDT 24
Peak memory 215760 kb
Host smart-47dd7997-5142-4087-ae0a-6539ddcbe227
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793224403 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3793224403
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.973684823
Short name T1072
Test name
Test status
Simulation time 20995669 ps
CPU time 1.28 seconds
Started Jul 01 04:35:52 PM PDT 24
Finished Jul 01 04:35:58 PM PDT 24
Peak memory 207328 kb
Host smart-67c25811-6358-48fb-aa13-a84547ce69ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973684823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.973684823
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3376057781
Short name T1085
Test name
Test status
Simulation time 24944583 ps
CPU time 0.76 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:35:57 PM PDT 24
Peak memory 203952 kb
Host smart-7aa04da2-eab4-41c0-8e4c-f8fe281b6f34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376057781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
376057781
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1321187748
Short name T1132
Test name
Test status
Simulation time 28012692 ps
CPU time 1.9 seconds
Started Jul 01 04:35:54 PM PDT 24
Finished Jul 01 04:36:02 PM PDT 24
Peak memory 215500 kb
Host smart-313e2123-80d6-4162-9e1d-07e40531af73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321187748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1321187748
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2868981334
Short name T125
Test name
Test status
Simulation time 119018526 ps
CPU time 4.14 seconds
Started Jul 01 04:35:56 PM PDT 24
Finished Jul 01 04:36:09 PM PDT 24
Peak memory 219600 kb
Host smart-68226c9b-9d46-4ce8-93b8-226a42c7d544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868981334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
868981334
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3494925824
Short name T119
Test name
Test status
Simulation time 195101606 ps
CPU time 3.06 seconds
Started Jul 01 04:35:54 PM PDT 24
Finished Jul 01 04:36:04 PM PDT 24
Peak memory 218196 kb
Host smart-b95f77ca-536e-4b7a-9a64-142a85928a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494925824 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3494925824
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3267280769
Short name T1143
Test name
Test status
Simulation time 296352135 ps
CPU time 1.92 seconds
Started Jul 01 04:35:59 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 207176 kb
Host smart-940c5596-2ac2-46ac-af96-ae5f9337efd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267280769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
267280769
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2229604726
Short name T1065
Test name
Test status
Simulation time 19264875 ps
CPU time 0.77 seconds
Started Jul 01 04:35:52 PM PDT 24
Finished Jul 01 04:35:58 PM PDT 24
Peak memory 204236 kb
Host smart-965fbd3f-bfd0-4ad1-82b8-4d8d5ec45fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229604726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
229604726
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3055849503
Short name T1142
Test name
Test status
Simulation time 115737039 ps
CPU time 1.82 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 215604 kb
Host smart-11982040-efce-4b20-aa18-38b7e2a5324d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055849503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3055849503
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1619632105
Short name T1066
Test name
Test status
Simulation time 14171595 ps
CPU time 0.74 seconds
Started Jul 01 04:36:01 PM PDT 24
Finished Jul 01 04:36:12 PM PDT 24
Peak memory 203896 kb
Host smart-5826fc56-90c4-4697-8ad8-4f527c4eeb9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619632105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
619632105
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2972189988
Short name T163
Test name
Test status
Simulation time 62015301 ps
CPU time 3.97 seconds
Started Jul 01 04:36:06 PM PDT 24
Finished Jul 01 04:36:23 PM PDT 24
Peak memory 215400 kb
Host smart-3aff7d5a-e3e7-404c-a18c-b99982ae98a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972189988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2972189988
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2997939263
Short name T126
Test name
Test status
Simulation time 180276508 ps
CPU time 2.56 seconds
Started Jul 01 04:36:06 PM PDT 24
Finished Jul 01 04:36:22 PM PDT 24
Peak memory 215660 kb
Host smart-10a31cb1-c055-4d7e-a4c1-3d612b690af2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997939263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
997939263
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.362324865
Short name T191
Test name
Test status
Simulation time 295413513 ps
CPU time 19.55 seconds
Started Jul 01 04:35:53 PM PDT 24
Finished Jul 01 04:36:18 PM PDT 24
Peak memory 215416 kb
Host smart-5f16b8c8-5a52-44fa-b748-a46d1680d660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362324865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.362324865
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1139788042
Short name T171
Test name
Test status
Simulation time 59870047 ps
CPU time 1.8 seconds
Started Jul 01 04:35:54 PM PDT 24
Finished Jul 01 04:36:04 PM PDT 24
Peak memory 216524 kb
Host smart-331ad7c4-44c0-4dc5-b881-9b117fa1a42b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139788042 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1139788042
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1768455852
Short name T1137
Test name
Test status
Simulation time 130584992 ps
CPU time 2.01 seconds
Started Jul 01 04:35:53 PM PDT 24
Finished Jul 01 04:36:01 PM PDT 24
Peak memory 207260 kb
Host smart-9a5b60cb-7c1d-4793-b413-802837a14f8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768455852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
768455852
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1195060578
Short name T1041
Test name
Test status
Simulation time 20945884 ps
CPU time 0.71 seconds
Started Jul 01 04:35:55 PM PDT 24
Finished Jul 01 04:36:04 PM PDT 24
Peak memory 204304 kb
Host smart-885d2fc8-566d-41fa-9f89-be10ebabd742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195060578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
195060578
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.7506815
Short name T1063
Test name
Test status
Simulation time 607039286 ps
CPU time 2.02 seconds
Started Jul 01 04:35:52 PM PDT 24
Finished Jul 01 04:35:59 PM PDT 24
Peak memory 215580 kb
Host smart-75e5563a-8d88-43af-8189-01b40f9e1357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7506815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_
device_same_csr_outstanding.7506815
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3384990363
Short name T130
Test name
Test status
Simulation time 667707941 ps
CPU time 3.82 seconds
Started Jul 01 04:35:58 PM PDT 24
Finished Jul 01 04:36:11 PM PDT 24
Peak memory 216652 kb
Host smart-01815188-272b-4f07-8559-f6dedec69cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384990363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
384990363
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3041980319
Short name T1070
Test name
Test status
Simulation time 669548952 ps
CPU time 6.1 seconds
Started Jul 01 04:36:01 PM PDT 24
Finished Jul 01 04:36:17 PM PDT 24
Peak memory 215524 kb
Host smart-f561c6f9-5361-4626-9011-1a384e84ecd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041980319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3041980319
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1222503726
Short name T116
Test name
Test status
Simulation time 91173372 ps
CPU time 2.52 seconds
Started Jul 01 04:35:55 PM PDT 24
Finished Jul 01 04:36:06 PM PDT 24
Peak memory 216580 kb
Host smart-37421892-4328-49a0-abb1-8049528a4a5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222503726 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1222503726
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1098359048
Short name T147
Test name
Test status
Simulation time 66238234 ps
CPU time 1.8 seconds
Started Jul 01 04:35:55 PM PDT 24
Finished Jul 01 04:36:05 PM PDT 24
Peak memory 207332 kb
Host smart-8f0c4e8a-a37a-472b-84c6-53b8e4fc47bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098359048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
098359048
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3394175888
Short name T1073
Test name
Test status
Simulation time 38136246 ps
CPU time 0.72 seconds
Started Jul 01 04:35:55 PM PDT 24
Finished Jul 01 04:36:04 PM PDT 24
Peak memory 203984 kb
Host smart-e7e4bb42-646c-40af-92f2-06eb1aeb9860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394175888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
394175888
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4144506133
Short name T1075
Test name
Test status
Simulation time 157477304 ps
CPU time 4.1 seconds
Started Jul 01 04:35:55 PM PDT 24
Finished Jul 01 04:36:07 PM PDT 24
Peak memory 215492 kb
Host smart-0d8d8d20-e993-49d1-811f-4aa8274403f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144506133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4144506133
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3478294981
Short name T189
Test name
Test status
Simulation time 3864291526 ps
CPU time 21.32 seconds
Started Jul 01 04:35:51 PM PDT 24
Finished Jul 01 04:36:17 PM PDT 24
Peak memory 215656 kb
Host smart-5f4be558-3413-4639-820a-2f4028376ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478294981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3478294981
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2944306245
Short name T529
Test name
Test status
Simulation time 16748814 ps
CPU time 0.77 seconds
Started Jul 01 06:26:56 PM PDT 24
Finished Jul 01 06:26:58 PM PDT 24
Peak memory 205824 kb
Host smart-22066e0d-29d6-4a1f-a910-219e34158dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944306245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
944306245
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2451613238
Short name T539
Test name
Test status
Simulation time 47340893 ps
CPU time 0.76 seconds
Started Jul 01 06:26:35 PM PDT 24
Finished Jul 01 06:26:37 PM PDT 24
Peak memory 207516 kb
Host smart-6df25cd1-77c8-48fb-8fd1-fc8fbb901b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451613238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2451613238
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3250982685
Short name T216
Test name
Test status
Simulation time 6302308483 ps
CPU time 42.41 seconds
Started Jul 01 06:26:51 PM PDT 24
Finished Jul 01 06:27:36 PM PDT 24
Peak memory 249452 kb
Host smart-117312e0-26ea-4916-a248-f877697b6c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250982685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3250982685
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2082551268
Short name T557
Test name
Test status
Simulation time 103705886043 ps
CPU time 82.82 seconds
Started Jul 01 06:26:51 PM PDT 24
Finished Jul 01 06:28:16 PM PDT 24
Peak memory 268388 kb
Host smart-dc15b425-c9a5-4078-9a33-7ed0c4e6abcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082551268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2082551268
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3684544520
Short name T973
Test name
Test status
Simulation time 2233517447 ps
CPU time 31.15 seconds
Started Jul 01 06:26:45 PM PDT 24
Finished Jul 01 06:27:20 PM PDT 24
Peak memory 225784 kb
Host smart-ae2b3ceb-fe9b-4c5d-b3cf-580d4803ceb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684544520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3684544520
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4107027889
Short name T726
Test name
Test status
Simulation time 2190487077 ps
CPU time 11.61 seconds
Started Jul 01 06:26:44 PM PDT 24
Finished Jul 01 06:27:00 PM PDT 24
Peak memory 233884 kb
Host smart-ec577b58-ba5f-43c8-96b1-dbdf251392a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107027889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4107027889
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3441148314
Short name T622
Test name
Test status
Simulation time 2445935167 ps
CPU time 7.09 seconds
Started Jul 01 06:26:47 PM PDT 24
Finished Jul 01 06:26:58 PM PDT 24
Peak memory 233880 kb
Host smart-88304cbf-bbf8-40d3-860b-0fd511ece7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441148314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3441148314
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4123058513
Short name T221
Test name
Test status
Simulation time 8827971203 ps
CPU time 8.89 seconds
Started Jul 01 06:26:38 PM PDT 24
Finished Jul 01 06:26:49 PM PDT 24
Peak memory 233888 kb
Host smart-7acabc99-3cbc-4c99-8d7a-0552eea63b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123058513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4123058513
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2299752623
Short name T768
Test name
Test status
Simulation time 1383222489 ps
CPU time 5.74 seconds
Started Jul 01 06:26:39 PM PDT 24
Finished Jul 01 06:26:48 PM PDT 24
Peak memory 225520 kb
Host smart-d108d9f2-3537-4700-8f50-4f541ce56620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299752623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2299752623
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3497149720
Short name T562
Test name
Test status
Simulation time 1018655809 ps
CPU time 11.99 seconds
Started Jul 01 06:26:49 PM PDT 24
Finished Jul 01 06:27:04 PM PDT 24
Peak memory 222260 kb
Host smart-d7322316-8f2f-4eb3-96e6-ba7ed5a5a88a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3497149720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3497149720
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2870160572
Short name T86
Test name
Test status
Simulation time 818743439 ps
CPU time 0.98 seconds
Started Jul 01 06:26:58 PM PDT 24
Finished Jul 01 06:27:01 PM PDT 24
Peak memory 236364 kb
Host smart-a4bca1a9-2b0e-40e7-840c-8363d7112877
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870160572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2870160572
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4256935168
Short name T883
Test name
Test status
Simulation time 139748621 ps
CPU time 1.29 seconds
Started Jul 01 06:26:57 PM PDT 24
Finished Jul 01 06:26:59 PM PDT 24
Peak memory 208804 kb
Host smart-d22e7fca-c628-48d1-9934-262ef80b5840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256935168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4256935168
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.106790731
Short name T349
Test name
Test status
Simulation time 6357281665 ps
CPU time 20.26 seconds
Started Jul 01 06:26:34 PM PDT 24
Finished Jul 01 06:26:55 PM PDT 24
Peak memory 217552 kb
Host smart-bf87ea17-48a8-4b86-bd10-01de30c73b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106790731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.106790731
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.58119041
Short name T489
Test name
Test status
Simulation time 6366192184 ps
CPU time 16.46 seconds
Started Jul 01 06:26:34 PM PDT 24
Finished Jul 01 06:26:51 PM PDT 24
Peak memory 217572 kb
Host smart-8029c7a6-a3f7-4bc7-83cd-02deafd9256b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58119041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.58119041
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3946593046
Short name T764
Test name
Test status
Simulation time 26494017 ps
CPU time 0.71 seconds
Started Jul 01 06:26:41 PM PDT 24
Finished Jul 01 06:26:45 PM PDT 24
Peak memory 206588 kb
Host smart-ee0de60e-8564-433a-9b2e-99845ea51675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946593046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3946593046
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.313738786
Short name T698
Test name
Test status
Simulation time 65872676 ps
CPU time 0.91 seconds
Started Jul 01 06:26:35 PM PDT 24
Finished Jul 01 06:26:37 PM PDT 24
Peak memory 207136 kb
Host smart-80eb00fc-9dac-44b0-a0ea-065f3d5185d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313738786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.313738786
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1609381598
Short name T564
Test name
Test status
Simulation time 5242878369 ps
CPU time 23.25 seconds
Started Jul 01 06:26:44 PM PDT 24
Finished Jul 01 06:27:12 PM PDT 24
Peak memory 234788 kb
Host smart-69fab425-3b1d-452f-9885-dde117175065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609381598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1609381598
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.827256269
Short name T863
Test name
Test status
Simulation time 689425099 ps
CPU time 3.78 seconds
Started Jul 01 06:27:09 PM PDT 24
Finished Jul 01 06:27:14 PM PDT 24
Peak memory 225548 kb
Host smart-5f8657df-baa0-4b0c-b82d-966a222e3807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827256269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.827256269
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2806615911
Short name T488
Test name
Test status
Simulation time 19209851 ps
CPU time 0.78 seconds
Started Jul 01 06:26:57 PM PDT 24
Finished Jul 01 06:26:59 PM PDT 24
Peak memory 207880 kb
Host smart-3f5dac77-530d-46f3-b073-9d5a1f5ce029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806615911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2806615911
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.254953014
Short name T625
Test name
Test status
Simulation time 10514481389 ps
CPU time 73.49 seconds
Started Jul 01 06:27:08 PM PDT 24
Finished Jul 01 06:28:23 PM PDT 24
Peak memory 242112 kb
Host smart-5bd2e036-3ab8-4114-aa9c-f65823a48c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254953014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.254953014
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1191657283
Short name T516
Test name
Test status
Simulation time 874949120 ps
CPU time 3.56 seconds
Started Jul 01 06:27:05 PM PDT 24
Finished Jul 01 06:27:10 PM PDT 24
Peak memory 225588 kb
Host smart-b97b1343-3a19-471e-a292-96916831431d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191657283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1191657283
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3046767124
Short name T871
Test name
Test status
Simulation time 5266930780 ps
CPU time 17.49 seconds
Started Jul 01 06:27:09 PM PDT 24
Finished Jul 01 06:27:27 PM PDT 24
Peak memory 238104 kb
Host smart-05ea477f-ca95-4ed1-9ab9-cfc0363213fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046767124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3046767124
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1851094323
Short name T788
Test name
Test status
Simulation time 291808457 ps
CPU time 5.68 seconds
Started Jul 01 06:27:03 PM PDT 24
Finished Jul 01 06:27:10 PM PDT 24
Peak memory 225580 kb
Host smart-5fdd3d4c-d063-499b-aeaf-25f5d47a806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851094323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1851094323
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2905979640
Short name T657
Test name
Test status
Simulation time 6180994519 ps
CPU time 18.78 seconds
Started Jul 01 06:27:04 PM PDT 24
Finished Jul 01 06:27:24 PM PDT 24
Peak memory 237864 kb
Host smart-31ef2325-a268-4f65-8cf2-0828f715a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905979640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2905979640
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.917264853
Short name T807
Test name
Test status
Simulation time 17340566 ps
CPU time 1.08 seconds
Started Jul 01 06:26:56 PM PDT 24
Finished Jul 01 06:26:58 PM PDT 24
Peak memory 217768 kb
Host smart-ec69fd7c-fcf8-40a9-a025-03febb3e9673
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917264853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.917264853
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.271193977
Short name T929
Test name
Test status
Simulation time 27435836967 ps
CPU time 17.42 seconds
Started Jul 01 06:27:02 PM PDT 24
Finished Jul 01 06:27:21 PM PDT 24
Peak memory 225736 kb
Host smart-f95c8981-cfa1-499d-98ec-b61ce29a6623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271193977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.271193977
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1957004031
Short name T365
Test name
Test status
Simulation time 729558211 ps
CPU time 4.35 seconds
Started Jul 01 06:27:08 PM PDT 24
Finished Jul 01 06:27:14 PM PDT 24
Peak memory 224156 kb
Host smart-e0f099bd-5354-42a8-9e6b-f6da40c9e756
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957004031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1957004031
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3603486464
Short name T87
Test name
Test status
Simulation time 176020666 ps
CPU time 0.94 seconds
Started Jul 01 06:27:12 PM PDT 24
Finished Jul 01 06:27:14 PM PDT 24
Peak memory 236372 kb
Host smart-706da2e7-0714-4d54-9e6c-4d1a91e22eca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603486464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3603486464
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.955690664
Short name T175
Test name
Test status
Simulation time 87323627 ps
CPU time 0.95 seconds
Started Jul 01 06:27:15 PM PDT 24
Finished Jul 01 06:27:16 PM PDT 24
Peak memory 207736 kb
Host smart-4b658922-6a15-4d4a-8349-09e0adb00008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955690664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.955690664
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.92052012
Short name T839
Test name
Test status
Simulation time 10924926611 ps
CPU time 8.59 seconds
Started Jul 01 06:27:02 PM PDT 24
Finished Jul 01 06:27:12 PM PDT 24
Peak memory 218700 kb
Host smart-0a58862b-0d3d-4637-a45e-a793b370b648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92052012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.92052012
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2311443186
Short name T892
Test name
Test status
Simulation time 106642038 ps
CPU time 2.12 seconds
Started Jul 01 06:27:04 PM PDT 24
Finished Jul 01 06:27:07 PM PDT 24
Peak memory 217336 kb
Host smart-00707fa1-4e22-4233-b8ae-b9f32d1b51c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311443186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2311443186
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1162950426
Short name T671
Test name
Test status
Simulation time 41092165 ps
CPU time 0.79 seconds
Started Jul 01 06:27:01 PM PDT 24
Finished Jul 01 06:27:02 PM PDT 24
Peak memory 207080 kb
Host smart-7001195e-8c35-4aa5-a06e-ea6c4106cc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162950426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1162950426
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.76894148
Short name T691
Test name
Test status
Simulation time 570591284 ps
CPU time 4.32 seconds
Started Jul 01 06:27:02 PM PDT 24
Finished Jul 01 06:27:07 PM PDT 24
Peak memory 230988 kb
Host smart-8a688f1e-395c-4ec2-a8f3-e3d13e334f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76894148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.76894148
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2280133210
Short name T512
Test name
Test status
Simulation time 40311577 ps
CPU time 0.73 seconds
Started Jul 01 06:29:11 PM PDT 24
Finished Jul 01 06:29:12 PM PDT 24
Peak memory 206752 kb
Host smart-588ef6b2-9f3d-458b-92a1-2a47e6e30a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280133210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2280133210
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3463494235
Short name T866
Test name
Test status
Simulation time 850906268 ps
CPU time 2.38 seconds
Started Jul 01 06:29:08 PM PDT 24
Finished Jul 01 06:29:12 PM PDT 24
Peak memory 225560 kb
Host smart-41f739cc-7356-470f-8b96-e5fecdf799cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463494235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3463494235
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1331636258
Short name T473
Test name
Test status
Simulation time 15576706 ps
CPU time 0.83 seconds
Started Jul 01 06:29:02 PM PDT 24
Finished Jul 01 06:29:07 PM PDT 24
Peak memory 207548 kb
Host smart-ec9260c5-2124-4a74-8dfa-b520a20e5f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331636258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1331636258
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4060157645
Short name T206
Test name
Test status
Simulation time 21161143566 ps
CPU time 145.09 seconds
Started Jul 01 06:29:10 PM PDT 24
Finished Jul 01 06:31:36 PM PDT 24
Peak memory 250272 kb
Host smart-f798ffda-3a02-474c-a913-c4124168f599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060157645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4060157645
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.977875570
Short name T859
Test name
Test status
Simulation time 2174868860 ps
CPU time 48.19 seconds
Started Jul 01 06:29:10 PM PDT 24
Finished Jul 01 06:29:59 PM PDT 24
Peak memory 255332 kb
Host smart-114e70dd-9aac-4f3b-9e36-fc6bdbef4f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977875570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.977875570
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2189870567
Short name T670
Test name
Test status
Simulation time 9467490073 ps
CPU time 33.7 seconds
Started Jul 01 06:29:07 PM PDT 24
Finished Jul 01 06:29:43 PM PDT 24
Peak memory 250220 kb
Host smart-da00685d-e815-41b1-8e74-ca86d12dd838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189870567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2189870567
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3065513719
Short name T954
Test name
Test status
Simulation time 40150156777 ps
CPU time 69.22 seconds
Started Jul 01 06:29:06 PM PDT 24
Finished Jul 01 06:30:18 PM PDT 24
Peak memory 249828 kb
Host smart-ed710b30-8bdc-4a23-89cb-dee9c6df7359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065513719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3065513719
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1031478673
Short name T280
Test name
Test status
Simulation time 8244802335 ps
CPU time 23.01 seconds
Started Jul 01 06:29:07 PM PDT 24
Finished Jul 01 06:29:32 PM PDT 24
Peak memory 233832 kb
Host smart-2a2a2b00-c8c6-45f7-b306-244aceed5fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031478673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1031478673
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1353276243
Short name T514
Test name
Test status
Simulation time 41327968 ps
CPU time 2.81 seconds
Started Jul 01 06:29:07 PM PDT 24
Finished Jul 01 06:29:12 PM PDT 24
Peak memory 233508 kb
Host smart-1d13f3c2-142c-458c-b317-a80a3cfb8bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353276243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1353276243
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3618374958
Short name T574
Test name
Test status
Simulation time 189276634 ps
CPU time 1.07 seconds
Started Jul 01 06:29:05 PM PDT 24
Finished Jul 01 06:29:09 PM PDT 24
Peak memory 217640 kb
Host smart-2ed35fb8-07bf-4757-9724-f44c643212b4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618374958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3618374958
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2876830193
Short name T217
Test name
Test status
Simulation time 871823320 ps
CPU time 5.38 seconds
Started Jul 01 06:29:07 PM PDT 24
Finished Jul 01 06:29:14 PM PDT 24
Peak memory 225604 kb
Host smart-b2c732a1-c26d-490d-a664-921a81a5acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876830193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2876830193
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2947875273
Short name T983
Test name
Test status
Simulation time 15499510917 ps
CPU time 10.02 seconds
Started Jul 01 06:29:07 PM PDT 24
Finished Jul 01 06:29:19 PM PDT 24
Peak memory 225704 kb
Host smart-14ac8f13-c25b-4793-bf8f-21e010ead8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947875273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2947875273
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4124219529
Short name T860
Test name
Test status
Simulation time 1614422643 ps
CPU time 11.21 seconds
Started Jul 01 06:29:07 PM PDT 24
Finished Jul 01 06:29:20 PM PDT 24
Peak memory 222724 kb
Host smart-8f7b7cf8-da3d-4eb9-882c-1ac6e4e8c1d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4124219529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4124219529
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4232338293
Short name T319
Test name
Test status
Simulation time 13967037355 ps
CPU time 200.81 seconds
Started Jul 01 06:29:11 PM PDT 24
Finished Jul 01 06:32:33 PM PDT 24
Peak memory 266364 kb
Host smart-b36684f8-096e-483b-a8ac-90172905b2a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232338293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4232338293
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.94830989
Short name T897
Test name
Test status
Simulation time 5754541657 ps
CPU time 25.53 seconds
Started Jul 01 06:29:03 PM PDT 24
Finished Jul 01 06:29:32 PM PDT 24
Peak memory 217796 kb
Host smart-82aada04-cfe1-4e6f-8b71-3d0093332578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94830989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.94830989
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2143615365
Short name T844
Test name
Test status
Simulation time 50869659225 ps
CPU time 10.69 seconds
Started Jul 01 06:29:01 PM PDT 24
Finished Jul 01 06:29:15 PM PDT 24
Peak memory 217556 kb
Host smart-1802b621-612c-4293-a2cc-fe4ae5b83426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143615365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2143615365
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3178554571
Short name T609
Test name
Test status
Simulation time 223100888 ps
CPU time 1.07 seconds
Started Jul 01 06:29:06 PM PDT 24
Finished Jul 01 06:29:10 PM PDT 24
Peak memory 208284 kb
Host smart-b8ed73fc-3504-4c45-89e6-d25d63535fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178554571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3178554571
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2397310469
Short name T645
Test name
Test status
Simulation time 33994843 ps
CPU time 0.81 seconds
Started Jul 01 06:29:06 PM PDT 24
Finished Jul 01 06:29:09 PM PDT 24
Peak memory 206944 kb
Host smart-57635cb0-1918-4f9b-a51e-025b2c8b76b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397310469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2397310469
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.26674720
Short name T79
Test name
Test status
Simulation time 465213627 ps
CPU time 6.49 seconds
Started Jul 01 06:29:06 PM PDT 24
Finished Jul 01 06:29:15 PM PDT 24
Peak memory 225576 kb
Host smart-abe3b99b-d837-407b-8725-3d2d2229b7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26674720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.26674720
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1925225292
Short name T935
Test name
Test status
Simulation time 12775294 ps
CPU time 0.74 seconds
Started Jul 01 06:29:22 PM PDT 24
Finished Jul 01 06:29:24 PM PDT 24
Peak memory 206448 kb
Host smart-4103e511-f730-4079-a4ac-5ed273092a00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925225292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1925225292
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.695011782
Short name T951
Test name
Test status
Simulation time 3256262492 ps
CPU time 5.7 seconds
Started Jul 01 06:29:17 PM PDT 24
Finished Jul 01 06:29:24 PM PDT 24
Peak memory 233976 kb
Host smart-62d6490b-a328-4da8-9de6-b6a09c14891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695011782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.695011782
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2354719509
Short name T594
Test name
Test status
Simulation time 46154726 ps
CPU time 0.76 seconds
Started Jul 01 06:29:19 PM PDT 24
Finished Jul 01 06:29:21 PM PDT 24
Peak memory 207024 kb
Host smart-7916637c-4c9e-45bd-b14e-2fbdefba073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354719509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2354719509
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3420388585
Short name T546
Test name
Test status
Simulation time 35355251653 ps
CPU time 111.12 seconds
Started Jul 01 06:29:27 PM PDT 24
Finished Jul 01 06:31:19 PM PDT 24
Peak memory 258664 kb
Host smart-96f54586-a417-4eb6-9a80-aab9fb5512df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420388585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3420388585
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2536846416
Short name T805
Test name
Test status
Simulation time 4637276791 ps
CPU time 79.46 seconds
Started Jul 01 06:29:23 PM PDT 24
Finished Jul 01 06:30:43 PM PDT 24
Peak memory 252208 kb
Host smart-6545db40-dab9-460e-b553-fe7d0971dacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536846416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2536846416
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.513447010
Short name T543
Test name
Test status
Simulation time 20162882778 ps
CPU time 70.37 seconds
Started Jul 01 06:29:15 PM PDT 24
Finished Jul 01 06:30:26 PM PDT 24
Peak memory 252960 kb
Host smart-49b9d918-2d7a-4229-9b01-0e9be70b07da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513447010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.513447010
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3246425339
Short name T817
Test name
Test status
Simulation time 441329512 ps
CPU time 5.6 seconds
Started Jul 01 06:29:16 PM PDT 24
Finished Jul 01 06:29:23 PM PDT 24
Peak memory 225568 kb
Host smart-9954deb9-fc96-4640-9330-63a4df85b4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246425339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3246425339
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1417129121
Short name T789
Test name
Test status
Simulation time 8041327558 ps
CPU time 70.97 seconds
Started Jul 01 06:29:16 PM PDT 24
Finished Jul 01 06:30:27 PM PDT 24
Peak memory 241840 kb
Host smart-377abf2c-239f-4b0d-b77c-c7029c0c93b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417129121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1417129121
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.361554779
Short name T914
Test name
Test status
Simulation time 125438669 ps
CPU time 1.07 seconds
Started Jul 01 06:29:17 PM PDT 24
Finished Jul 01 06:29:19 PM PDT 24
Peak memory 217656 kb
Host smart-7bd3c5d6-55e2-40e8-8b70-27dc031a840d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361554779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.361554779
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1841938561
Short name T14
Test name
Test status
Simulation time 143320130105 ps
CPU time 30.57 seconds
Started Jul 01 06:29:16 PM PDT 24
Finished Jul 01 06:29:48 PM PDT 24
Peak memory 240348 kb
Host smart-9f415362-b99e-442e-82cc-3d9d1fb1247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841938561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1841938561
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3319814798
Short name T291
Test name
Test status
Simulation time 1460962266 ps
CPU time 5.98 seconds
Started Jul 01 06:29:16 PM PDT 24
Finished Jul 01 06:29:23 PM PDT 24
Peak memory 225584 kb
Host smart-2cd0e342-6025-4a72-b346-6587fb52bd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319814798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3319814798
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4149124171
Short name T974
Test name
Test status
Simulation time 339615075 ps
CPU time 5.38 seconds
Started Jul 01 06:29:24 PM PDT 24
Finished Jul 01 06:29:30 PM PDT 24
Peak memory 220276 kb
Host smart-85df4e0f-4516-4e89-b03c-c725a4470c7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4149124171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4149124171
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1674648068
Short name T479
Test name
Test status
Simulation time 16795536780 ps
CPU time 18.34 seconds
Started Jul 01 06:29:20 PM PDT 24
Finished Jul 01 06:29:39 PM PDT 24
Peak memory 217348 kb
Host smart-efa5a820-81d6-4235-8ef9-b043d0bd9ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674648068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1674648068
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1937626069
Short name T452
Test name
Test status
Simulation time 62937943561 ps
CPU time 13.33 seconds
Started Jul 01 06:29:17 PM PDT 24
Finished Jul 01 06:29:31 PM PDT 24
Peak memory 217484 kb
Host smart-3e0f946c-1f14-4a18-a9f6-ceebec86d1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937626069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1937626069
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2885820387
Short name T578
Test name
Test status
Simulation time 118449354 ps
CPU time 1.64 seconds
Started Jul 01 06:29:15 PM PDT 24
Finished Jul 01 06:29:18 PM PDT 24
Peak memory 217368 kb
Host smart-28dc0100-a833-43b8-8aa3-3c635ed820e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885820387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2885820387
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.4233189796
Short name T453
Test name
Test status
Simulation time 35816346 ps
CPU time 0.94 seconds
Started Jul 01 06:29:20 PM PDT 24
Finished Jul 01 06:29:21 PM PDT 24
Peak memory 207900 kb
Host smart-83908e39-3755-471f-991d-eaa7e389bd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233189796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4233189796
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1757307501
Short name T700
Test name
Test status
Simulation time 1756618552 ps
CPU time 6.21 seconds
Started Jul 01 06:29:21 PM PDT 24
Finished Jul 01 06:29:28 PM PDT 24
Peak memory 233768 kb
Host smart-32b6f4f5-5794-42e0-8cf5-69a101648638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757307501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1757307501
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2640271455
Short name T947
Test name
Test status
Simulation time 33596746 ps
CPU time 0.72 seconds
Started Jul 01 06:29:32 PM PDT 24
Finished Jul 01 06:29:34 PM PDT 24
Peak memory 206476 kb
Host smart-56ca183e-415a-42f8-95a1-16e845a5c1e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640271455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2640271455
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2162476100
Short name T107
Test name
Test status
Simulation time 179302979 ps
CPU time 4.4 seconds
Started Jul 01 06:29:26 PM PDT 24
Finished Jul 01 06:29:31 PM PDT 24
Peak memory 225676 kb
Host smart-78a19848-55cb-4267-851b-241a3cd02c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162476100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2162476100
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1133977837
Short name T353
Test name
Test status
Simulation time 15573376 ps
CPU time 0.79 seconds
Started Jul 01 06:29:22 PM PDT 24
Finished Jul 01 06:29:24 PM PDT 24
Peak memory 207616 kb
Host smart-06721e39-aa31-4701-807c-0bfb1ed9f95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133977837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1133977837
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.705745193
Short name T155
Test name
Test status
Simulation time 10105815808 ps
CPU time 47.59 seconds
Started Jul 01 06:29:37 PM PDT 24
Finished Jul 01 06:30:25 PM PDT 24
Peak memory 250728 kb
Host smart-fc1948c2-fd5c-4741-9093-bbca1abbfc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705745193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.705745193
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1341797151
Short name T70
Test name
Test status
Simulation time 18348958009 ps
CPU time 158.99 seconds
Started Jul 01 06:29:31 PM PDT 24
Finished Jul 01 06:32:12 PM PDT 24
Peak memory 258620 kb
Host smart-5385bc74-bf92-48d9-a06a-2a2265ddd289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341797151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1341797151
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2283526058
Short name T249
Test name
Test status
Simulation time 1444401259 ps
CPU time 13.05 seconds
Started Jul 01 06:29:33 PM PDT 24
Finished Jul 01 06:29:47 PM PDT 24
Peak memory 233840 kb
Host smart-480a3c29-a928-4f6e-9239-fa7394fcd399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283526058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2283526058
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2917470537
Short name T308
Test name
Test status
Simulation time 1104024180 ps
CPU time 24.99 seconds
Started Jul 01 06:29:31 PM PDT 24
Finished Jul 01 06:29:57 PM PDT 24
Peak memory 241992 kb
Host smart-64771679-5a54-4051-8bf7-6de700fcd100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917470537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2917470537
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.879690674
Short name T944
Test name
Test status
Simulation time 496918416 ps
CPU time 6.52 seconds
Started Jul 01 06:29:29 PM PDT 24
Finished Jul 01 06:29:36 PM PDT 24
Peak memory 225560 kb
Host smart-b5cc4216-9a82-4a4e-98e2-02d001bb2aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879690674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.879690674
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3512603173
Short name T60
Test name
Test status
Simulation time 757035183 ps
CPU time 11.86 seconds
Started Jul 01 06:29:33 PM PDT 24
Finished Jul 01 06:29:46 PM PDT 24
Peak memory 234256 kb
Host smart-45f43bec-fbee-4170-b0ed-cf5e9b342b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512603173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3512603173
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3279532088
Short name T49
Test name
Test status
Simulation time 45676266 ps
CPU time 1.11 seconds
Started Jul 01 06:29:22 PM PDT 24
Finished Jul 01 06:29:24 PM PDT 24
Peak memory 217732 kb
Host smart-621ef516-7bbd-4c0d-b1ed-20b20f91eb5d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279532088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3279532088
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1245939511
Short name T831
Test name
Test status
Simulation time 883512987 ps
CPU time 6.75 seconds
Started Jul 01 06:29:33 PM PDT 24
Finished Jul 01 06:29:41 PM PDT 24
Peak memory 233640 kb
Host smart-4c08f837-b82a-4072-99e4-ff055e0359f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245939511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1245939511
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3100089720
Short name T266
Test name
Test status
Simulation time 145741926 ps
CPU time 2.88 seconds
Started Jul 01 06:29:26 PM PDT 24
Finished Jul 01 06:29:30 PM PDT 24
Peak memory 233756 kb
Host smart-cfcc8913-906c-4b14-924c-9e1f4ac597f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100089720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3100089720
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3346342826
Short name T683
Test name
Test status
Simulation time 50440365 ps
CPU time 1.04 seconds
Started Jul 01 06:29:32 PM PDT 24
Finished Jul 01 06:29:35 PM PDT 24
Peak memory 207756 kb
Host smart-7a762629-053a-447d-b577-6a74ff1a0e86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346342826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3346342826
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2332697733
Short name T959
Test name
Test status
Simulation time 6288041222 ps
CPU time 11.62 seconds
Started Jul 01 06:29:24 PM PDT 24
Finished Jul 01 06:29:36 PM PDT 24
Peak memory 217504 kb
Host smart-63ce47d9-1733-4cce-af5e-73d2c19b936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332697733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2332697733
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2504730811
Short name T93
Test name
Test status
Simulation time 116792980 ps
CPU time 1.23 seconds
Started Jul 01 06:29:32 PM PDT 24
Finished Jul 01 06:29:35 PM PDT 24
Peak memory 209020 kb
Host smart-877337d7-07bb-4d48-a239-1fef820fcb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504730811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2504730811
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1913760398
Short name T7
Test name
Test status
Simulation time 113410550 ps
CPU time 0.93 seconds
Started Jul 01 06:29:29 PM PDT 24
Finished Jul 01 06:29:30 PM PDT 24
Peak memory 206980 kb
Host smart-7c745cbe-fe78-41dd-bfa5-fac39c9710a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913760398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1913760398
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.127475405
Short name T279
Test name
Test status
Simulation time 6995310544 ps
CPU time 22.22 seconds
Started Jul 01 06:29:33 PM PDT 24
Finished Jul 01 06:29:56 PM PDT 24
Peak memory 233960 kb
Host smart-6ab35f25-d3ca-4884-974a-c3c893d88e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127475405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.127475405
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2687432044
Short name T495
Test name
Test status
Simulation time 13394120 ps
CPU time 0.72 seconds
Started Jul 01 06:29:44 PM PDT 24
Finished Jul 01 06:29:45 PM PDT 24
Peak memory 205820 kb
Host smart-f977ede5-bfe4-44ae-b6fa-a9ed9b4d1ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687432044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2687432044
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3992931577
Short name T751
Test name
Test status
Simulation time 354866967 ps
CPU time 2.45 seconds
Started Jul 01 06:29:39 PM PDT 24
Finished Jul 01 06:29:42 PM PDT 24
Peak memory 225556 kb
Host smart-451162f4-656c-4c39-afe9-a796de17ae17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992931577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3992931577
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.418375042
Short name T382
Test name
Test status
Simulation time 20209813 ps
CPU time 0.74 seconds
Started Jul 01 06:29:30 PM PDT 24
Finished Jul 01 06:29:32 PM PDT 24
Peak memory 206532 kb
Host smart-da154b42-6c2b-422e-b7e0-5521618c8a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418375042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.418375042
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.441260408
Short name T538
Test name
Test status
Simulation time 20422846867 ps
CPU time 153.78 seconds
Started Jul 01 06:29:38 PM PDT 24
Finished Jul 01 06:32:13 PM PDT 24
Peak memory 254228 kb
Host smart-f121e309-304a-4d4c-9a8c-0314a7ca8629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441260408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.441260408
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3044040773
Short name T549
Test name
Test status
Simulation time 5971465818 ps
CPU time 44.08 seconds
Started Jul 01 06:29:38 PM PDT 24
Finished Jul 01 06:30:23 PM PDT 24
Peak memory 233952 kb
Host smart-ba508499-90f5-4ce2-a343-509ac07b49dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044040773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3044040773
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2614469969
Short name T826
Test name
Test status
Simulation time 17064463 ps
CPU time 0.75 seconds
Started Jul 01 06:29:38 PM PDT 24
Finished Jul 01 06:29:40 PM PDT 24
Peak memory 217032 kb
Host smart-6754faee-a0e2-4dfc-abc0-20db945bea0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614469969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2614469969
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4187383795
Short name T1016
Test name
Test status
Simulation time 79077001 ps
CPU time 3.72 seconds
Started Jul 01 06:29:41 PM PDT 24
Finished Jul 01 06:29:45 PM PDT 24
Peak memory 233868 kb
Host smart-d7872b57-0505-4426-b2ed-ccfa13ad1a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187383795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4187383795
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1710771942
Short name T778
Test name
Test status
Simulation time 604251724 ps
CPU time 13.08 seconds
Started Jul 01 06:29:42 PM PDT 24
Finished Jul 01 06:29:56 PM PDT 24
Peak memory 233708 kb
Host smart-3d318354-9379-4dcf-a355-7dc0b1acb32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710771942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1710771942
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3759726152
Short name T1011
Test name
Test status
Simulation time 24949603 ps
CPU time 1.06 seconds
Started Jul 01 06:29:34 PM PDT 24
Finished Jul 01 06:29:36 PM PDT 24
Peak memory 217668 kb
Host smart-b14f296a-c20f-4340-8bae-d827b6913d6f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759726152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3759726152
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2121018525
Short name T618
Test name
Test status
Simulation time 935476387 ps
CPU time 8.75 seconds
Started Jul 01 06:29:39 PM PDT 24
Finished Jul 01 06:29:49 PM PDT 24
Peak memory 233792 kb
Host smart-0ec4eec7-a629-4629-89a7-a03328064b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121018525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2121018525
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.288280970
Short name T288
Test name
Test status
Simulation time 320451574 ps
CPU time 2.56 seconds
Started Jul 01 06:29:39 PM PDT 24
Finished Jul 01 06:29:42 PM PDT 24
Peak memory 225552 kb
Host smart-c56efdcd-4296-47a3-a8a7-df0ba24398cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288280970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.288280970
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1169232238
Short name T882
Test name
Test status
Simulation time 780244525 ps
CPU time 4.91 seconds
Started Jul 01 06:29:40 PM PDT 24
Finished Jul 01 06:29:45 PM PDT 24
Peak memory 222892 kb
Host smart-ce0abbc7-9e6c-44be-ba2f-ed3d9922ae70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1169232238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1169232238
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3501120404
Short name T779
Test name
Test status
Simulation time 2792642399 ps
CPU time 68.43 seconds
Started Jul 01 06:29:44 PM PDT 24
Finished Jul 01 06:30:53 PM PDT 24
Peak memory 254032 kb
Host smart-1ba7af34-af09-4743-bfed-ccdd1e658cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501120404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3501120404
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.994961283
Short name T804
Test name
Test status
Simulation time 11918596661 ps
CPU time 44.59 seconds
Started Jul 01 06:29:38 PM PDT 24
Finished Jul 01 06:30:24 PM PDT 24
Peak memory 217552 kb
Host smart-3234ce93-b602-4afc-bf63-8754c08de5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994961283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.994961283
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3825465210
Short name T480
Test name
Test status
Simulation time 23854782 ps
CPU time 0.7 seconds
Started Jul 01 06:29:51 PM PDT 24
Finished Jul 01 06:29:53 PM PDT 24
Peak memory 206656 kb
Host smart-deeaf9ab-e9a6-44ca-ad22-d7d50e644235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825465210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3825465210
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1268256815
Short name T666
Test name
Test status
Simulation time 126840185 ps
CPU time 5.02 seconds
Started Jul 01 06:29:45 PM PDT 24
Finished Jul 01 06:29:51 PM PDT 24
Peak memory 217408 kb
Host smart-54947384-2b0c-465b-b7ab-30cd4e2756a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268256815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1268256815
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.774705215
Short name T493
Test name
Test status
Simulation time 102758948 ps
CPU time 0.8 seconds
Started Jul 01 06:29:36 PM PDT 24
Finished Jul 01 06:29:38 PM PDT 24
Peak memory 206956 kb
Host smart-6a7f1d43-bb46-4b97-9aab-803b933ff527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774705215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.774705215
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3484060469
Short name T646
Test name
Test status
Simulation time 1965276640 ps
CPU time 4.12 seconds
Started Jul 01 06:29:40 PM PDT 24
Finished Jul 01 06:29:45 PM PDT 24
Peak memory 233816 kb
Host smart-1ec4f8ca-9564-4c57-95a9-7c056ae6c6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484060469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3484060469
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.971036840
Short name T460
Test name
Test status
Simulation time 21661703 ps
CPU time 0.72 seconds
Started Jul 01 06:29:48 PM PDT 24
Finished Jul 01 06:29:50 PM PDT 24
Peak memory 206440 kb
Host smart-99d51640-de6b-4d81-b9dd-92848d587cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971036840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.971036840
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1748776450
Short name T256
Test name
Test status
Simulation time 102588986 ps
CPU time 3.83 seconds
Started Jul 01 06:29:54 PM PDT 24
Finished Jul 01 06:29:59 PM PDT 24
Peak memory 233704 kb
Host smart-812552a1-5895-4bb6-a443-2c273b472145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748776450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1748776450
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.891189069
Short name T458
Test name
Test status
Simulation time 27446953 ps
CPU time 0.8 seconds
Started Jul 01 06:29:45 PM PDT 24
Finished Jul 01 06:29:47 PM PDT 24
Peak memory 207552 kb
Host smart-a690e680-aa28-4985-a739-0076bdee9a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891189069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.891189069
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.214186487
Short name T753
Test name
Test status
Simulation time 11170143 ps
CPU time 0.76 seconds
Started Jul 01 06:29:46 PM PDT 24
Finished Jul 01 06:29:48 PM PDT 24
Peak memory 217128 kb
Host smart-5ada73ac-dde2-446e-ac12-455ae1a05f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214186487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.214186487
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4079260954
Short name T496
Test name
Test status
Simulation time 5610722494 ps
CPU time 80.77 seconds
Started Jul 01 06:29:48 PM PDT 24
Finished Jul 01 06:31:10 PM PDT 24
Peak memory 251400 kb
Host smart-5f3a7c62-826d-4620-a753-83c87a314256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079260954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4079260954
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3230352564
Short name T986
Test name
Test status
Simulation time 5031898312 ps
CPU time 98.57 seconds
Started Jul 01 06:29:54 PM PDT 24
Finished Jul 01 06:31:34 PM PDT 24
Peak memory 269812 kb
Host smart-d1902945-9d52-4a37-8e6b-b895d2ca4112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230352564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3230352564
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2602283489
Short name T765
Test name
Test status
Simulation time 6114825828 ps
CPU time 15.86 seconds
Started Jul 01 06:29:47 PM PDT 24
Finished Jul 01 06:30:04 PM PDT 24
Peak memory 225740 kb
Host smart-d6a77227-4b24-411a-9403-ee9ca615b5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602283489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2602283489
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.472339525
Short name T979
Test name
Test status
Simulation time 24408815625 ps
CPU time 36.83 seconds
Started Jul 01 06:29:47 PM PDT 24
Finished Jul 01 06:30:24 PM PDT 24
Peak memory 242068 kb
Host smart-4e130624-18a3-4dbb-a969-8874a2a7027b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472339525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.472339525
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3428323138
Short name T960
Test name
Test status
Simulation time 334537296 ps
CPU time 2.96 seconds
Started Jul 01 06:29:44 PM PDT 24
Finished Jul 01 06:29:48 PM PDT 24
Peak memory 225580 kb
Host smart-1e9c505a-01f8-4c30-9136-91d3b1ea3d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428323138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3428323138
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1999723103
Short name T485
Test name
Test status
Simulation time 18289218950 ps
CPU time 49.38 seconds
Started Jul 01 06:29:44 PM PDT 24
Finished Jul 01 06:30:34 PM PDT 24
Peak memory 233936 kb
Host smart-dd4b27aa-bd05-41f8-8f24-9433eb4813d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999723103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1999723103
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1706774522
Short name T414
Test name
Test status
Simulation time 222020348 ps
CPU time 1.06 seconds
Started Jul 01 06:29:45 PM PDT 24
Finished Jul 01 06:29:47 PM PDT 24
Peak memory 218884 kb
Host smart-3c3fd367-4fde-4737-b0f7-c890b8614ad9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706774522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1706774522
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2290872710
Short name T63
Test name
Test status
Simulation time 10088965962 ps
CPU time 12.52 seconds
Started Jul 01 06:29:44 PM PDT 24
Finished Jul 01 06:29:57 PM PDT 24
Peak memory 252592 kb
Host smart-ba1363ee-6c58-4005-92f1-6a1bd7e161c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290872710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2290872710
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3417138838
Short name T455
Test name
Test status
Simulation time 2579049496 ps
CPU time 9.94 seconds
Started Jul 01 06:29:45 PM PDT 24
Finished Jul 01 06:29:56 PM PDT 24
Peak memory 241968 kb
Host smart-de51413d-ed23-4cee-acea-d607bbd76797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417138838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3417138838
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2252489989
Short name T619
Test name
Test status
Simulation time 23165055896 ps
CPU time 11.1 seconds
Started Jul 01 06:29:48 PM PDT 24
Finished Jul 01 06:30:00 PM PDT 24
Peak memory 224292 kb
Host smart-e1fbdea2-1d60-4bc3-8fd0-8f683d526d4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2252489989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2252489989
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3354551986
Short name T1009
Test name
Test status
Simulation time 134779930599 ps
CPU time 100.85 seconds
Started Jul 01 06:29:47 PM PDT 24
Finished Jul 01 06:31:29 PM PDT 24
Peak memory 256224 kb
Host smart-04f5f05a-2ac2-4e39-adf2-7242bd0a78f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354551986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3354551986
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2993769768
Short name T568
Test name
Test status
Simulation time 12039848004 ps
CPU time 22.6 seconds
Started Jul 01 06:29:45 PM PDT 24
Finished Jul 01 06:30:09 PM PDT 24
Peak memory 217724 kb
Host smart-48a5352c-5123-44e2-88bb-01534c5233c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993769768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2993769768
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3934733594
Short name T449
Test name
Test status
Simulation time 516225365 ps
CPU time 1.35 seconds
Started Jul 01 06:29:43 PM PDT 24
Finished Jul 01 06:29:44 PM PDT 24
Peak memory 208816 kb
Host smart-f1140a06-268f-4e28-993d-c07b3659b4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934733594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3934733594
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3396823562
Short name T1021
Test name
Test status
Simulation time 44702551 ps
CPU time 0.87 seconds
Started Jul 01 06:29:44 PM PDT 24
Finished Jul 01 06:29:45 PM PDT 24
Peak memory 207752 kb
Host smart-e8b8aef0-4993-4b8b-8b0d-840abbbed91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396823562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3396823562
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2524490987
Short name T402
Test name
Test status
Simulation time 55043995 ps
CPU time 0.85 seconds
Started Jul 01 06:29:46 PM PDT 24
Finished Jul 01 06:29:48 PM PDT 24
Peak memory 206964 kb
Host smart-2cd9fc07-08cd-4ea9-9f6d-434ee635d42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524490987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2524490987
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4048098845
Short name T701
Test name
Test status
Simulation time 118617755 ps
CPU time 2.44 seconds
Started Jul 01 06:29:43 PM PDT 24
Finished Jul 01 06:29:46 PM PDT 24
Peak memory 225292 kb
Host smart-c46e27e8-515f-4c1b-b116-997eac1780c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048098845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4048098845
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1222653921
Short name T554
Test name
Test status
Simulation time 20279334 ps
CPU time 0.75 seconds
Started Jul 01 06:29:59 PM PDT 24
Finished Jul 01 06:30:01 PM PDT 24
Peak memory 205844 kb
Host smart-833f92ed-2880-47ff-922a-49c7a67ec7e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222653921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1222653921
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.297933304
Short name T545
Test name
Test status
Simulation time 421340671 ps
CPU time 5.77 seconds
Started Jul 01 06:29:53 PM PDT 24
Finished Jul 01 06:30:00 PM PDT 24
Peak memory 225428 kb
Host smart-1d4ddf42-4e14-4c21-8c8b-ae23b667d1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297933304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.297933304
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1518048971
Short name T747
Test name
Test status
Simulation time 51449195 ps
CPU time 0.77 seconds
Started Jul 01 06:30:00 PM PDT 24
Finished Jul 01 06:30:02 PM PDT 24
Peak memory 206396 kb
Host smart-82bc7c48-37f1-4f32-aafc-c55c0ede2dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518048971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1518048971
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3547262307
Short name T899
Test name
Test status
Simulation time 2405151070 ps
CPU time 26.11 seconds
Started Jul 01 06:29:57 PM PDT 24
Finished Jul 01 06:30:24 PM PDT 24
Peak memory 253428 kb
Host smart-51c7536f-6e22-4167-b9e4-9ca99e4e09bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547262307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3547262307
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2194153538
Short name T772
Test name
Test status
Simulation time 15549914856 ps
CPU time 64.72 seconds
Started Jul 01 06:29:59 PM PDT 24
Finished Jul 01 06:31:05 PM PDT 24
Peak memory 250420 kb
Host smart-9f636309-cb80-47e8-948c-83fa12151c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194153538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2194153538
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3155361338
Short name T71
Test name
Test status
Simulation time 524120587 ps
CPU time 10.24 seconds
Started Jul 01 06:29:55 PM PDT 24
Finished Jul 01 06:30:06 PM PDT 24
Peak memory 233868 kb
Host smart-aa031d13-ba9d-4cf1-914c-3e7f66c521db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155361338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3155361338
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3949237623
Short name T397
Test name
Test status
Simulation time 31204451 ps
CPU time 2.12 seconds
Started Jul 01 06:29:55 PM PDT 24
Finished Jul 01 06:29:57 PM PDT 24
Peak memory 233548 kb
Host smart-95279928-48c7-4c8c-a1f7-5ef42603cf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949237623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3949237623
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3721199608
Short name T656
Test name
Test status
Simulation time 12941971070 ps
CPU time 36.13 seconds
Started Jul 01 06:29:53 PM PDT 24
Finished Jul 01 06:30:30 PM PDT 24
Peak memory 238448 kb
Host smart-ac9ac647-c25f-4975-8154-5448f4331f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721199608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3721199608
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3928710374
Short name T938
Test name
Test status
Simulation time 90029747 ps
CPU time 1.07 seconds
Started Jul 01 06:30:00 PM PDT 24
Finished Jul 01 06:30:02 PM PDT 24
Peak memory 218816 kb
Host smart-ec1f0fee-05c1-4e5b-a629-58ba322f77e6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928710374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3928710374
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4029326431
Short name T56
Test name
Test status
Simulation time 1428185014 ps
CPU time 6.85 seconds
Started Jul 01 06:30:00 PM PDT 24
Finished Jul 01 06:30:08 PM PDT 24
Peak memory 239856 kb
Host smart-ab400199-37d6-4ec7-a3f1-08b57c3d8702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029326431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4029326431
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.964001040
Short name T908
Test name
Test status
Simulation time 3937548488 ps
CPU time 16.48 seconds
Started Jul 01 06:29:54 PM PDT 24
Finished Jul 01 06:30:12 PM PDT 24
Peak memory 242048 kb
Host smart-bfe2f79c-9bd9-4b58-88d0-c50221c80452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964001040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.964001040
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3036481534
Short name T580
Test name
Test status
Simulation time 2119941219 ps
CPU time 8.4 seconds
Started Jul 01 06:30:00 PM PDT 24
Finished Jul 01 06:30:09 PM PDT 24
Peak memory 224360 kb
Host smart-5395410b-6873-4983-aea5-aa8c5e2a48c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3036481534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3036481534
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1240383957
Short name T604
Test name
Test status
Simulation time 5236121057 ps
CPU time 59.51 seconds
Started Jul 01 06:29:57 PM PDT 24
Finished Jul 01 06:30:58 PM PDT 24
Peak memory 256096 kb
Host smart-48442c1a-f2cd-49f2-869a-738014ae01e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240383957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1240383957
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2768501904
Short name T600
Test name
Test status
Simulation time 4887922829 ps
CPU time 22.07 seconds
Started Jul 01 06:29:53 PM PDT 24
Finished Jul 01 06:30:16 PM PDT 24
Peak memory 217528 kb
Host smart-e6aff08b-ecbe-4f77-acca-872209c36cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768501904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2768501904
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2104163938
Short name T814
Test name
Test status
Simulation time 1281417727 ps
CPU time 6.24 seconds
Started Jul 01 06:29:53 PM PDT 24
Finished Jul 01 06:30:00 PM PDT 24
Peak memory 217376 kb
Host smart-daf035a0-728b-4ce9-a413-bfcc8362d9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104163938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2104163938
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.920250425
Short name T441
Test name
Test status
Simulation time 47921818 ps
CPU time 0.94 seconds
Started Jul 01 06:30:02 PM PDT 24
Finished Jul 01 06:30:04 PM PDT 24
Peak memory 208000 kb
Host smart-b314af4d-3abb-42f7-b36c-17b84761b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920250425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.920250425
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.755001867
Short name T486
Test name
Test status
Simulation time 121284472 ps
CPU time 0.81 seconds
Started Jul 01 06:29:52 PM PDT 24
Finished Jul 01 06:29:54 PM PDT 24
Peak memory 206996 kb
Host smart-a741a149-0007-4255-9cf6-83a9110b0fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755001867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.755001867
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1757821505
Short name T750
Test name
Test status
Simulation time 2723307575 ps
CPU time 12.67 seconds
Started Jul 01 06:29:54 PM PDT 24
Finished Jul 01 06:30:07 PM PDT 24
Peak memory 241984 kb
Host smart-5307030c-085c-4622-9519-37ad41a100a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757821505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1757821505
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3770072919
Short name T378
Test name
Test status
Simulation time 43559019 ps
CPU time 0.73 seconds
Started Jul 01 06:30:11 PM PDT 24
Finished Jul 01 06:30:12 PM PDT 24
Peak memory 205828 kb
Host smart-73135acf-6641-4edc-8b49-979cc9d7bcae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770072919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3770072919
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.621351861
Short name T281
Test name
Test status
Simulation time 117727826 ps
CPU time 2.37 seconds
Started Jul 01 06:30:08 PM PDT 24
Finished Jul 01 06:30:12 PM PDT 24
Peak memory 225684 kb
Host smart-36a826d8-1d5e-4d57-9c0a-bd58984d7a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621351861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.621351861
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.240906704
Short name T425
Test name
Test status
Simulation time 180009037 ps
CPU time 0.75 seconds
Started Jul 01 06:29:57 PM PDT 24
Finished Jul 01 06:29:59 PM PDT 24
Peak memory 207540 kb
Host smart-198968b2-d37e-471a-8c12-232a11e02642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240906704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.240906704
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2318261306
Short name T95
Test name
Test status
Simulation time 80830857203 ps
CPU time 166.8 seconds
Started Jul 01 06:30:10 PM PDT 24
Finished Jul 01 06:32:58 PM PDT 24
Peak memory 252828 kb
Host smart-8c95fa6a-c3c6-43e1-a3a7-a7e936278513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318261306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2318261306
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.509031817
Short name T582
Test name
Test status
Simulation time 16414012501 ps
CPU time 76.45 seconds
Started Jul 01 06:30:12 PM PDT 24
Finished Jul 01 06:31:29 PM PDT 24
Peak memory 250412 kb
Host smart-e2b5cba8-75e9-4b5f-af79-a509abed8064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509031817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.509031817
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1916964420
Short name T68
Test name
Test status
Simulation time 50017648086 ps
CPU time 460.72 seconds
Started Jul 01 06:30:11 PM PDT 24
Finished Jul 01 06:37:53 PM PDT 24
Peak memory 266800 kb
Host smart-72b824a8-bae0-45c6-8973-5bc9dd0c948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916964420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1916964420
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.804843569
Short name T387
Test name
Test status
Simulation time 4408650297 ps
CPU time 18.21 seconds
Started Jul 01 06:30:09 PM PDT 24
Finished Jul 01 06:30:28 PM PDT 24
Peak memory 225744 kb
Host smart-70fe663b-be49-4b58-a6f9-aad23b1baef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804843569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.804843569
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2919879392
Short name T584
Test name
Test status
Simulation time 3301716226 ps
CPU time 41.22 seconds
Started Jul 01 06:30:08 PM PDT 24
Finished Jul 01 06:30:50 PM PDT 24
Peak memory 250328 kb
Host smart-05e1a7aa-24ba-4ddc-8713-2e050e01f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919879392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2919879392
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.962716108
Short name T795
Test name
Test status
Simulation time 4988046448 ps
CPU time 8.97 seconds
Started Jul 01 06:30:04 PM PDT 24
Finished Jul 01 06:30:14 PM PDT 24
Peak memory 233928 kb
Host smart-10f69ccc-9a90-44b4-bff9-07b1ff4655bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962716108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.962716108
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2838872551
Short name T448
Test name
Test status
Simulation time 2855825348 ps
CPU time 18.1 seconds
Started Jul 01 06:30:03 PM PDT 24
Finished Jul 01 06:30:22 PM PDT 24
Peak memory 242032 kb
Host smart-b0f15b1a-1f24-4a36-9376-0f7542a57caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838872551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2838872551
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1876675352
Short name T924
Test name
Test status
Simulation time 17296118 ps
CPU time 1.11 seconds
Started Jul 01 06:29:57 PM PDT 24
Finished Jul 01 06:29:59 PM PDT 24
Peak memory 217684 kb
Host smart-7d81fc8d-9e5d-4fde-95fd-3deda9b29c16
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876675352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1876675352
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2580117245
Short name T776
Test name
Test status
Simulation time 230476601 ps
CPU time 5.15 seconds
Started Jul 01 06:30:05 PM PDT 24
Finished Jul 01 06:30:11 PM PDT 24
Peak memory 233752 kb
Host smart-5dbaee8d-0f56-4546-a6ac-69243136c023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580117245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2580117245
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.680815176
Short name T297
Test name
Test status
Simulation time 89291584 ps
CPU time 2.72 seconds
Started Jul 01 06:30:05 PM PDT 24
Finished Jul 01 06:30:09 PM PDT 24
Peak memory 233756 kb
Host smart-0477dd6f-6878-4601-810a-c856401a59ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680815176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.680815176
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1183251122
Short name T890
Test name
Test status
Simulation time 1532756858 ps
CPU time 4.63 seconds
Started Jul 01 06:30:10 PM PDT 24
Finished Jul 01 06:30:16 PM PDT 24
Peak memory 221344 kb
Host smart-e000827d-7575-4bf2-9b23-9c8bc9993b1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1183251122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1183251122
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1137177934
Short name T326
Test name
Test status
Simulation time 107761983359 ps
CPU time 348.96 seconds
Started Jul 01 06:30:11 PM PDT 24
Finished Jul 01 06:36:00 PM PDT 24
Peak memory 283288 kb
Host smart-2583b55e-d61e-47e3-8bba-1b9a714cf903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137177934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1137177934
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1683431208
Short name T991
Test name
Test status
Simulation time 1689860094 ps
CPU time 23.86 seconds
Started Jul 01 06:30:03 PM PDT 24
Finished Jul 01 06:30:28 PM PDT 24
Peak memory 217596 kb
Host smart-0939243c-1755-4462-9ecb-14b1a2e07336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683431208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1683431208
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2199210745
Short name T706
Test name
Test status
Simulation time 11425531 ps
CPU time 0.7 seconds
Started Jul 01 06:30:05 PM PDT 24
Finished Jul 01 06:30:06 PM PDT 24
Peak memory 206632 kb
Host smart-7adc2e06-5fc7-4a51-8edf-baa2e6fb4cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199210745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2199210745
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2802474011
Short name T379
Test name
Test status
Simulation time 416805691 ps
CPU time 1.87 seconds
Started Jul 01 06:30:04 PM PDT 24
Finished Jul 01 06:30:06 PM PDT 24
Peak memory 209180 kb
Host smart-c4843278-b3cd-4893-b8dc-d339cd5f3185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802474011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2802474011
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1687190992
Short name T435
Test name
Test status
Simulation time 216128290 ps
CPU time 0.88 seconds
Started Jul 01 06:30:02 PM PDT 24
Finished Jul 01 06:30:04 PM PDT 24
Peak memory 207004 kb
Host smart-7715daa8-a135-46ed-bbfe-2e32ad5b1d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687190992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1687190992
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2802217862
Short name T716
Test name
Test status
Simulation time 9485907653 ps
CPU time 30.68 seconds
Started Jul 01 06:30:05 PM PDT 24
Finished Jul 01 06:30:36 PM PDT 24
Peak memory 234192 kb
Host smart-f5ed8188-c195-48e6-af31-1c0af5c4a4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802217862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2802217862
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2805265676
Short name T560
Test name
Test status
Simulation time 55755979 ps
CPU time 0.74 seconds
Started Jul 01 06:30:23 PM PDT 24
Finished Jul 01 06:30:25 PM PDT 24
Peak memory 206392 kb
Host smart-d78cfd5b-5fd9-403d-a858-ef2988066136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805265676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2805265676
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2815808072
Short name T704
Test name
Test status
Simulation time 233979777 ps
CPU time 3.93 seconds
Started Jul 01 06:30:23 PM PDT 24
Finished Jul 01 06:30:28 PM PDT 24
Peak memory 225616 kb
Host smart-876d654c-00c6-41c3-b4fe-dcfcb8c8d0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815808072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2815808072
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4131904639
Short name T985
Test name
Test status
Simulation time 44485674 ps
CPU time 0.81 seconds
Started Jul 01 06:30:08 PM PDT 24
Finished Jul 01 06:30:09 PM PDT 24
Peak memory 207488 kb
Host smart-a29387c3-a2df-4f45-bf80-04687b6a0cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131904639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4131904639
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.494038131
Short name T824
Test name
Test status
Simulation time 4831746909 ps
CPU time 39.06 seconds
Started Jul 01 06:30:18 PM PDT 24
Finished Jul 01 06:30:59 PM PDT 24
Peak memory 225724 kb
Host smart-4c3aa17d-905a-4b48-acf7-f33e1ee3e8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494038131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.494038131
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1540457061
Short name T237
Test name
Test status
Simulation time 3776779533 ps
CPU time 54.62 seconds
Started Jul 01 06:30:20 PM PDT 24
Finished Jul 01 06:31:16 PM PDT 24
Peak memory 250412 kb
Host smart-9de63483-1b1a-488d-a9b8-eb18be3b2539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540457061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1540457061
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.21886126
Short name T505
Test name
Test status
Simulation time 17562760868 ps
CPU time 187.52 seconds
Started Jul 01 06:30:23 PM PDT 24
Finished Jul 01 06:33:31 PM PDT 24
Peak memory 274052 kb
Host smart-53917af4-6879-4c06-9218-8dc49e5e8b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21886126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.21886126
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1029525642
Short name T681
Test name
Test status
Simulation time 775545479 ps
CPU time 12.27 seconds
Started Jul 01 06:30:19 PM PDT 24
Finished Jul 01 06:30:32 PM PDT 24
Peak memory 233920 kb
Host smart-d494b2cd-bae1-4a82-b006-c72cff0eca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029525642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1029525642
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2111576693
Short name T867
Test name
Test status
Simulation time 94984887647 ps
CPU time 120.9 seconds
Started Jul 01 06:30:19 PM PDT 24
Finished Jul 01 06:32:21 PM PDT 24
Peak memory 252860 kb
Host smart-64ac06f4-8c6c-4a11-b1eb-85c5ad5293c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111576693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2111576693
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3486204332
Short name T428
Test name
Test status
Simulation time 158600550 ps
CPU time 3.72 seconds
Started Jul 01 06:30:13 PM PDT 24
Finished Jul 01 06:30:17 PM PDT 24
Peak memory 233824 kb
Host smart-905c1a33-6195-40ea-b729-d18c78c4ebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486204332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3486204332
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.421440411
Short name T854
Test name
Test status
Simulation time 1816341029 ps
CPU time 8.39 seconds
Started Jul 01 06:30:13 PM PDT 24
Finished Jul 01 06:30:22 PM PDT 24
Peak memory 233848 kb
Host smart-5a111282-ec83-4691-b56f-0ea5220869db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421440411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.421440411
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.71567312
Short name T932
Test name
Test status
Simulation time 50713702 ps
CPU time 0.99 seconds
Started Jul 01 06:30:08 PM PDT 24
Finished Jul 01 06:30:10 PM PDT 24
Peak memory 218984 kb
Host smart-b122255e-1b9d-4d35-8806-778e8f2237fa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71567312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.71567312
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2411341014
Short name T296
Test name
Test status
Simulation time 13873342376 ps
CPU time 19.39 seconds
Started Jul 01 06:30:13 PM PDT 24
Finished Jul 01 06:30:33 PM PDT 24
Peak memory 250696 kb
Host smart-7a83c3b0-d6ed-4e60-86ff-28988370f688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411341014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2411341014
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3055805781
Short name T703
Test name
Test status
Simulation time 2633504209 ps
CPU time 7.47 seconds
Started Jul 01 06:30:14 PM PDT 24
Finished Jul 01 06:30:22 PM PDT 24
Peak memory 233948 kb
Host smart-a6c442a6-de47-4f5c-8cb9-f186a679f1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055805781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3055805781
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1905363345
Short name T548
Test name
Test status
Simulation time 1526583549 ps
CPU time 6.91 seconds
Started Jul 01 06:30:23 PM PDT 24
Finished Jul 01 06:30:31 PM PDT 24
Peak memory 223520 kb
Host smart-54919313-868e-4a68-9a6c-b976d9f3c77e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1905363345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1905363345
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.974296673
Short name T926
Test name
Test status
Simulation time 58385564836 ps
CPU time 296.93 seconds
Started Jul 01 06:30:20 PM PDT 24
Finished Jul 01 06:35:18 PM PDT 24
Peak memory 275000 kb
Host smart-6ba2c01a-26ea-44c3-ba73-4150911c11ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974296673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.974296673
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.864675264
Short name T348
Test name
Test status
Simulation time 1802318130 ps
CPU time 17.42 seconds
Started Jul 01 06:30:11 PM PDT 24
Finished Jul 01 06:30:29 PM PDT 24
Peak memory 217368 kb
Host smart-254f1338-01fa-47be-b3b7-747523c5a14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864675264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.864675264
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2191098394
Short name T694
Test name
Test status
Simulation time 9368628599 ps
CPU time 21.01 seconds
Started Jul 01 06:30:10 PM PDT 24
Finished Jul 01 06:30:31 PM PDT 24
Peak memory 217484 kb
Host smart-1b0c7672-9cfe-4e95-870a-3e66476804d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191098394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2191098394
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2424547996
Short name T872
Test name
Test status
Simulation time 374761052 ps
CPU time 2.69 seconds
Started Jul 01 06:30:15 PM PDT 24
Finished Jul 01 06:30:19 PM PDT 24
Peak memory 217352 kb
Host smart-f5561ea9-82e3-4d71-9b7a-d212c70c695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424547996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2424547996
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3186938346
Short name T688
Test name
Test status
Simulation time 32493780 ps
CPU time 0.79 seconds
Started Jul 01 06:30:13 PM PDT 24
Finished Jul 01 06:30:15 PM PDT 24
Peak memory 207104 kb
Host smart-81c4b828-9393-4923-81b6-67b15a15ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186938346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3186938346
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2283905385
Short name T1022
Test name
Test status
Simulation time 26495865338 ps
CPU time 32.29 seconds
Started Jul 01 06:30:20 PM PDT 24
Finished Jul 01 06:30:53 PM PDT 24
Peak memory 234916 kb
Host smart-c3481cf7-1eb8-4068-a2ec-dc09aa139609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283905385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2283905385
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.325603779
Short name T474
Test name
Test status
Simulation time 13044743 ps
CPU time 0.7 seconds
Started Jul 01 06:30:25 PM PDT 24
Finished Jul 01 06:30:26 PM PDT 24
Peak memory 206748 kb
Host smart-1e3b4845-7d08-4e38-85c6-cbc801d16a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325603779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.325603779
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2806187497
Short name T403
Test name
Test status
Simulation time 13259293 ps
CPU time 0.79 seconds
Started Jul 01 06:30:19 PM PDT 24
Finished Jul 01 06:30:20 PM PDT 24
Peak memory 207508 kb
Host smart-3e25f187-28b7-4047-a83a-1ee768485037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806187497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2806187497
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1741765022
Short name T669
Test name
Test status
Simulation time 10460291625 ps
CPU time 24.23 seconds
Started Jul 01 06:30:27 PM PDT 24
Finished Jul 01 06:30:53 PM PDT 24
Peak memory 256544 kb
Host smart-782e630c-99ec-45a0-9512-dc69ee0fd65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741765022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1741765022
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4023288991
Short name T340
Test name
Test status
Simulation time 42280179869 ps
CPU time 49.63 seconds
Started Jul 01 06:30:27 PM PDT 24
Finished Jul 01 06:31:19 PM PDT 24
Peak memory 218660 kb
Host smart-2c75eb52-850b-42aa-89d9-63fe706592d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023288991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4023288991
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3692423939
Short name T321
Test name
Test status
Simulation time 32362040196 ps
CPU time 139.89 seconds
Started Jul 01 06:30:27 PM PDT 24
Finished Jul 01 06:32:48 PM PDT 24
Peak memory 253304 kb
Host smart-55c6954a-125d-4979-8eec-eb8e5c5b7a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692423939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3692423939
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3793710474
Short name T639
Test name
Test status
Simulation time 5249370804 ps
CPU time 10.36 seconds
Started Jul 01 06:30:28 PM PDT 24
Finished Jul 01 06:30:40 PM PDT 24
Peak memory 236556 kb
Host smart-26fee1d6-6332-4f04-a249-c2d5fd470cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793710474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3793710474
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2100671009
Short name T205
Test name
Test status
Simulation time 3046820453 ps
CPU time 27.42 seconds
Started Jul 01 06:30:25 PM PDT 24
Finished Jul 01 06:30:54 PM PDT 24
Peak memory 235488 kb
Host smart-8efe950d-c3aa-4811-9cdd-d4129a907328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100671009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2100671009
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1756930854
Short name T264
Test name
Test status
Simulation time 1017391714 ps
CPU time 4.96 seconds
Started Jul 01 06:30:28 PM PDT 24
Finished Jul 01 06:30:35 PM PDT 24
Peak memory 233672 kb
Host smart-08c8f11a-0e69-4d35-88ad-9ab2e1c78d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756930854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1756930854
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2427692294
Short name T796
Test name
Test status
Simulation time 2109129452 ps
CPU time 24.82 seconds
Started Jul 01 06:30:25 PM PDT 24
Finished Jul 01 06:30:52 PM PDT 24
Peak memory 233824 kb
Host smart-52a420c5-96bf-41cd-838a-4d947455e439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427692294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2427692294
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1164681858
Short name T75
Test name
Test status
Simulation time 58137059 ps
CPU time 0.98 seconds
Started Jul 01 06:30:21 PM PDT 24
Finished Jul 01 06:30:23 PM PDT 24
Peak memory 218904 kb
Host smart-661045ce-dffc-4974-8e1e-b8c17efd2512
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164681858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1164681858
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1589295942
Short name T939
Test name
Test status
Simulation time 158067792 ps
CPU time 2.83 seconds
Started Jul 01 06:30:27 PM PDT 24
Finished Jul 01 06:30:31 PM PDT 24
Peak memory 233824 kb
Host smart-d2bc261a-f154-4971-82ed-d862b605717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589295942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1589295942
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1653370801
Short name T830
Test name
Test status
Simulation time 11248866107 ps
CPU time 7.92 seconds
Started Jul 01 06:30:23 PM PDT 24
Finished Jul 01 06:30:32 PM PDT 24
Peak memory 233872 kb
Host smart-9dc0270b-471c-430e-9a01-5652f51b531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653370801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1653370801
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.513571756
Short name T417
Test name
Test status
Simulation time 363144491 ps
CPU time 5.33 seconds
Started Jul 01 06:30:24 PM PDT 24
Finished Jul 01 06:30:30 PM PDT 24
Peak memory 219972 kb
Host smart-c7c5cd1d-3aee-45fc-9861-30ae1721b81b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=513571756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.513571756
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1153651281
Short name T727
Test name
Test status
Simulation time 16664470951 ps
CPU time 14.86 seconds
Started Jul 01 06:30:21 PM PDT 24
Finished Jul 01 06:30:37 PM PDT 24
Peak memory 217744 kb
Host smart-c66e26d5-5859-4b28-b8c1-779b04f5dba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153651281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1153651281
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2471032915
Short name T451
Test name
Test status
Simulation time 577317714 ps
CPU time 3.48 seconds
Started Jul 01 06:30:19 PM PDT 24
Finished Jul 01 06:30:24 PM PDT 24
Peak memory 217408 kb
Host smart-eba9633b-7ab4-4635-a835-2407f1b725ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471032915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2471032915
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.136670957
Short name T400
Test name
Test status
Simulation time 13093733 ps
CPU time 0.71 seconds
Started Jul 01 06:30:21 PM PDT 24
Finished Jul 01 06:30:22 PM PDT 24
Peak memory 206560 kb
Host smart-ef1d934c-774d-4787-88c1-b81c65d98ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136670957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.136670957
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.935761744
Short name T592
Test name
Test status
Simulation time 49227506 ps
CPU time 0.71 seconds
Started Jul 01 06:30:21 PM PDT 24
Finished Jul 01 06:30:23 PM PDT 24
Peak memory 206892 kb
Host smart-8eacf35a-15ca-43c0-a99b-093e7ee1292a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935761744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.935761744
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3463803610
Short name T1028
Test name
Test status
Simulation time 11595271610 ps
CPU time 36.94 seconds
Started Jul 01 06:30:25 PM PDT 24
Finished Jul 01 06:31:04 PM PDT 24
Peak memory 242108 kb
Host smart-8ee161e8-032e-429a-925a-0e865e339fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463803610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3463803610
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3633661985
Short name T972
Test name
Test status
Simulation time 12242466 ps
CPU time 0.74 seconds
Started Jul 01 06:30:39 PM PDT 24
Finished Jul 01 06:30:40 PM PDT 24
Peak memory 205736 kb
Host smart-2e29dce0-b6e7-4e8a-ab43-277feedc106b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633661985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3633661985
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.621480080
Short name T494
Test name
Test status
Simulation time 166040330 ps
CPU time 2.44 seconds
Started Jul 01 06:30:29 PM PDT 24
Finished Jul 01 06:30:33 PM PDT 24
Peak memory 233640 kb
Host smart-5cbac21c-e305-4abe-a0c6-c2a6e4a60056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621480080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.621480080
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1939371353
Short name T689
Test name
Test status
Simulation time 36866285 ps
CPU time 0.77 seconds
Started Jul 01 06:30:25 PM PDT 24
Finished Jul 01 06:30:28 PM PDT 24
Peak memory 207516 kb
Host smart-e87d3445-2304-4105-a619-414851b78896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939371353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1939371353
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2538881115
Short name T323
Test name
Test status
Simulation time 10686286118 ps
CPU time 138.47 seconds
Started Jul 01 06:30:37 PM PDT 24
Finished Jul 01 06:32:56 PM PDT 24
Peak memory 258192 kb
Host smart-97e020d9-4916-4b55-99b6-1af381b1a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538881115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2538881115
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3943431966
Short name T303
Test name
Test status
Simulation time 35700671018 ps
CPU time 211.33 seconds
Started Jul 01 06:30:37 PM PDT 24
Finished Jul 01 06:34:09 PM PDT 24
Peak memory 265340 kb
Host smart-071f8289-a43e-466f-916b-6cb4daddb488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943431966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3943431966
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3614272699
Short name T999
Test name
Test status
Simulation time 14365254086 ps
CPU time 77.8 seconds
Started Jul 01 06:30:34 PM PDT 24
Finished Jul 01 06:31:53 PM PDT 24
Peak memory 257028 kb
Host smart-c3541100-3c4b-4bba-9505-9624b0d0dd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614272699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3614272699
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2840860546
Short name T239
Test name
Test status
Simulation time 22153706675 ps
CPU time 79.61 seconds
Started Jul 01 06:30:31 PM PDT 24
Finished Jul 01 06:31:52 PM PDT 24
Peak memory 269916 kb
Host smart-6297ddc0-564b-44c9-8899-3336d0a95a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840860546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2840860546
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3724902679
Short name T596
Test name
Test status
Simulation time 6707524446 ps
CPU time 15.8 seconds
Started Jul 01 06:30:30 PM PDT 24
Finished Jul 01 06:30:47 PM PDT 24
Peak memory 233952 kb
Host smart-6c2454ea-1a04-457a-803c-81743bde7317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724902679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3724902679
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2795990086
Short name T89
Test name
Test status
Simulation time 412510165 ps
CPU time 10.03 seconds
Started Jul 01 06:30:31 PM PDT 24
Finished Jul 01 06:30:42 PM PDT 24
Peak memory 225636 kb
Host smart-d0f7bb9b-67fe-4bff-9899-0585844fdb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795990086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2795990086
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.216507598
Short name T780
Test name
Test status
Simulation time 25274372 ps
CPU time 1.07 seconds
Started Jul 01 06:30:25 PM PDT 24
Finished Jul 01 06:30:27 PM PDT 24
Peak memory 218936 kb
Host smart-3d432a0a-4b1d-4bf3-bd3d-c310dd16a1c1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216507598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.216507598
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.607113172
Short name T690
Test name
Test status
Simulation time 98395473 ps
CPU time 2.19 seconds
Started Jul 01 06:30:29 PM PDT 24
Finished Jul 01 06:30:33 PM PDT 24
Peak memory 224828 kb
Host smart-50a18644-4a24-454e-86f6-1875c24407d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607113172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.607113172
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3382280533
Short name T277
Test name
Test status
Simulation time 7114022582 ps
CPU time 19.96 seconds
Started Jul 01 06:30:31 PM PDT 24
Finished Jul 01 06:30:53 PM PDT 24
Peak memory 225744 kb
Host smart-f616f28c-7641-4080-b251-904b12fbe221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382280533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3382280533
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.379682134
Short name T761
Test name
Test status
Simulation time 300885583 ps
CPU time 3.82 seconds
Started Jul 01 06:30:30 PM PDT 24
Finished Jul 01 06:30:35 PM PDT 24
Peak memory 219716 kb
Host smart-365cf5fe-836f-4ac8-8fd1-54ef9db876f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=379682134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.379682134
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3700446429
Short name T792
Test name
Test status
Simulation time 577635133 ps
CPU time 1.09 seconds
Started Jul 01 06:30:43 PM PDT 24
Finished Jul 01 06:30:46 PM PDT 24
Peak memory 207920 kb
Host smart-67b50b36-bd28-415b-b259-a84cd1d074a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700446429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3700446429
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2212119577
Short name T887
Test name
Test status
Simulation time 6131567913 ps
CPU time 27.88 seconds
Started Jul 01 06:30:32 PM PDT 24
Finished Jul 01 06:31:02 PM PDT 24
Peak memory 217456 kb
Host smart-6c381050-eee8-40d0-a999-1c555498a963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212119577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2212119577
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.585107283
Short name T361
Test name
Test status
Simulation time 2904010339 ps
CPU time 6.92 seconds
Started Jul 01 06:30:25 PM PDT 24
Finished Jul 01 06:30:32 PM PDT 24
Peak memory 217520 kb
Host smart-2d48f46b-ebb5-4e18-b888-a284dccd5fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585107283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.585107283
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3669037924
Short name T696
Test name
Test status
Simulation time 144941744 ps
CPU time 1.22 seconds
Started Jul 01 06:30:35 PM PDT 24
Finished Jul 01 06:30:38 PM PDT 24
Peak memory 209164 kb
Host smart-9823c9ae-c09b-4f22-ae5f-4fe1c4243da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669037924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3669037924
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.311059937
Short name T371
Test name
Test status
Simulation time 37465743 ps
CPU time 0.73 seconds
Started Jul 01 06:30:29 PM PDT 24
Finished Jul 01 06:30:31 PM PDT 24
Peak memory 206992 kb
Host smart-932a7dc3-cc6a-4522-bfc4-14a8df3b692c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311059937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.311059937
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.832613315
Short name T247
Test name
Test status
Simulation time 35414340762 ps
CPU time 29.83 seconds
Started Jul 01 06:30:35 PM PDT 24
Finished Jul 01 06:31:05 PM PDT 24
Peak memory 250040 kb
Host smart-19614835-b972-4298-a657-b9d01a65f91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832613315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.832613315
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.548806944
Short name T363
Test name
Test status
Simulation time 29655645 ps
CPU time 0.71 seconds
Started Jul 01 06:27:35 PM PDT 24
Finished Jul 01 06:27:36 PM PDT 24
Peak memory 205852 kb
Host smart-823c9177-5dbe-4715-9e35-7287211cbf0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548806944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.548806944
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3560199064
Short name T756
Test name
Test status
Simulation time 5551351510 ps
CPU time 11.67 seconds
Started Jul 01 06:27:30 PM PDT 24
Finished Jul 01 06:27:42 PM PDT 24
Peak memory 233928 kb
Host smart-35bbd46f-ab6e-4cab-85fa-d1c201f71a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560199064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3560199064
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.48806432
Short name T687
Test name
Test status
Simulation time 15932430 ps
CPU time 0.76 seconds
Started Jul 01 06:27:15 PM PDT 24
Finished Jul 01 06:27:16 PM PDT 24
Peak memory 206484 kb
Host smart-f6524109-6c3e-4d12-8484-adec659cb973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48806432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.48806432
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2242928151
Short name T925
Test name
Test status
Simulation time 30256508 ps
CPU time 0.77 seconds
Started Jul 01 06:27:30 PM PDT 24
Finished Jul 01 06:27:32 PM PDT 24
Peak memory 216992 kb
Host smart-b9600b5c-e46e-44f8-a123-33db96f0a7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242928151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2242928151
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3915835756
Short name T243
Test name
Test status
Simulation time 6981590943 ps
CPU time 51.9 seconds
Started Jul 01 06:27:29 PM PDT 24
Finished Jul 01 06:28:21 PM PDT 24
Peak memory 250720 kb
Host smart-ff863d97-0f26-4f5e-a112-6ba542fde4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915835756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3915835756
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.362731327
Short name T518
Test name
Test status
Simulation time 847122656 ps
CPU time 15.09 seconds
Started Jul 01 06:27:28 PM PDT 24
Finished Jul 01 06:27:44 PM PDT 24
Peak memory 233776 kb
Host smart-b8d3299a-ba14-4948-aeab-6e1ae9bfd221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362731327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.362731327
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.705446152
Short name T110
Test name
Test status
Simulation time 3297951292 ps
CPU time 44.7 seconds
Started Jul 01 06:27:27 PM PDT 24
Finished Jul 01 06:28:13 PM PDT 24
Peak memory 250276 kb
Host smart-0677abe0-131b-4731-8b56-53877f075a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705446152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
705446152
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.431226294
Short name T523
Test name
Test status
Simulation time 340423572 ps
CPU time 5.57 seconds
Started Jul 01 06:27:22 PM PDT 24
Finished Jul 01 06:27:29 PM PDT 24
Peak memory 233848 kb
Host smart-a176a1ce-b6e8-4496-9b6b-75c91d037e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431226294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.431226294
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2620455631
Short name T76
Test name
Test status
Simulation time 99514410932 ps
CPU time 78.83 seconds
Started Jul 01 06:27:26 PM PDT 24
Finished Jul 01 06:28:46 PM PDT 24
Peak memory 242160 kb
Host smart-a8f0e7a9-c6c5-4682-8f5a-449df0c55f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620455631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2620455631
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2209682607
Short name T837
Test name
Test status
Simulation time 27154777 ps
CPU time 1.09 seconds
Started Jul 01 06:27:13 PM PDT 24
Finished Jul 01 06:27:14 PM PDT 24
Peak memory 217676 kb
Host smart-ef251789-ed92-4730-8d9d-697b180b1ad6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209682607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2209682607
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3834948012
Short name T65
Test name
Test status
Simulation time 28361798525 ps
CPU time 24.92 seconds
Started Jul 01 06:27:24 PM PDT 24
Finished Jul 01 06:27:49 PM PDT 24
Peak memory 239204 kb
Host smart-3bc2b57d-f9fa-4652-b36f-31bf1afc30c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834948012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3834948012
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1186997691
Short name T544
Test name
Test status
Simulation time 39334596503 ps
CPU time 13.85 seconds
Started Jul 01 06:27:22 PM PDT 24
Finished Jul 01 06:27:37 PM PDT 24
Peak memory 225712 kb
Host smart-4fa8cc35-9544-4072-accd-74610a155069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186997691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1186997691
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1419811784
Short name T151
Test name
Test status
Simulation time 871660375 ps
CPU time 4.85 seconds
Started Jul 01 06:27:28 PM PDT 24
Finished Jul 01 06:27:33 PM PDT 24
Peak memory 223556 kb
Host smart-46f974bc-3394-4578-8e06-da578bb4bac1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1419811784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1419811784
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.585274283
Short name T85
Test name
Test status
Simulation time 134223963 ps
CPU time 0.97 seconds
Started Jul 01 06:27:33 PM PDT 24
Finished Jul 01 06:27:34 PM PDT 24
Peak memory 236376 kb
Host smart-3ec6c63f-4b58-4290-9fa8-6584ba871a62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585274283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.585274283
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2076544295
Short name T583
Test name
Test status
Simulation time 512964568588 ps
CPU time 322.74 seconds
Started Jul 01 06:27:36 PM PDT 24
Finished Jul 01 06:32:59 PM PDT 24
Peak memory 258284 kb
Host smart-da26ffa3-e1fd-42ff-ad8c-d77c3d3e075d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076544295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2076544295
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3777400194
Short name T32
Test name
Test status
Simulation time 147819975 ps
CPU time 2.42 seconds
Started Jul 01 06:27:18 PM PDT 24
Finished Jul 01 06:27:21 PM PDT 24
Peak memory 217392 kb
Host smart-9fbe8380-37db-4207-81b5-952c9cb1b0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777400194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3777400194
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1323163842
Short name T390
Test name
Test status
Simulation time 473084970 ps
CPU time 3.79 seconds
Started Jul 01 06:27:18 PM PDT 24
Finished Jul 01 06:27:23 PM PDT 24
Peak memory 217396 kb
Host smart-f7596b62-11fd-479b-940a-424007996210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323163842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1323163842
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2554772197
Short name T376
Test name
Test status
Simulation time 721000793 ps
CPU time 8.97 seconds
Started Jul 01 06:27:18 PM PDT 24
Finished Jul 01 06:27:29 PM PDT 24
Peak memory 217404 kb
Host smart-e6ddaedf-f766-4fad-9cc1-335bb9887b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554772197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2554772197
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4078315409
Short name T723
Test name
Test status
Simulation time 92469558 ps
CPU time 0.75 seconds
Started Jul 01 06:27:18 PM PDT 24
Finished Jul 01 06:27:20 PM PDT 24
Peak memory 207044 kb
Host smart-08d9d30f-c687-43cc-b948-c251facbc907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078315409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4078315409
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2402003767
Short name T278
Test name
Test status
Simulation time 2828645141 ps
CPU time 3.94 seconds
Started Jul 01 06:27:21 PM PDT 24
Finished Jul 01 06:27:26 PM PDT 24
Peak memory 225688 kb
Host smart-4805ccff-166c-458a-b879-0c30af7ab18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402003767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2402003767
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2210284744
Short name T1000
Test name
Test status
Simulation time 12273855 ps
CPU time 0.73 seconds
Started Jul 01 06:30:44 PM PDT 24
Finished Jul 01 06:30:45 PM PDT 24
Peak memory 206376 kb
Host smart-f535d195-a85d-482f-8799-4096dee9a858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210284744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2210284744
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.791197293
Short name T275
Test name
Test status
Simulation time 3758316509 ps
CPU time 8.47 seconds
Started Jul 01 06:30:48 PM PDT 24
Finished Jul 01 06:30:57 PM PDT 24
Peak memory 224852 kb
Host smart-26786ed0-2521-491e-9b76-5ace09c6ded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791197293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.791197293
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1220142359
Short name T526
Test name
Test status
Simulation time 48617532 ps
CPU time 0.81 seconds
Started Jul 01 06:30:35 PM PDT 24
Finished Jul 01 06:30:37 PM PDT 24
Peak memory 206560 kb
Host smart-3208fb9d-69cb-4da4-8499-30253e17c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220142359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1220142359
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2367033625
Short name T57
Test name
Test status
Simulation time 180100258525 ps
CPU time 311.82 seconds
Started Jul 01 06:30:42 PM PDT 24
Finished Jul 01 06:35:55 PM PDT 24
Peak memory 268712 kb
Host smart-5adb4b5e-7723-44d7-9eaf-4f2d9aa4a970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367033625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2367033625
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1438691029
Short name T69
Test name
Test status
Simulation time 44265073356 ps
CPU time 67.45 seconds
Started Jul 01 06:30:43 PM PDT 24
Finished Jul 01 06:31:52 PM PDT 24
Peak memory 250400 kb
Host smart-2c7d39fd-1160-433e-a9ab-1c51c0006af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438691029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1438691029
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.797561590
Short name T713
Test name
Test status
Simulation time 11075695722 ps
CPU time 94.27 seconds
Started Jul 01 06:30:44 PM PDT 24
Finished Jul 01 06:32:20 PM PDT 24
Peak memory 250256 kb
Host smart-6ef67b1a-a9b7-45ab-8438-1585d59bd458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797561590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.797561590
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.346119444
Short name T903
Test name
Test status
Simulation time 10992835491 ps
CPU time 40.83 seconds
Started Jul 01 06:30:43 PM PDT 24
Finished Jul 01 06:31:25 PM PDT 24
Peak memory 242124 kb
Host smart-41f903c1-59f1-48b4-a754-41bd3410e7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346119444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.346119444
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1682759838
Short name T88
Test name
Test status
Simulation time 1415844982 ps
CPU time 4.6 seconds
Started Jul 01 06:30:44 PM PDT 24
Finished Jul 01 06:30:50 PM PDT 24
Peak memory 234824 kb
Host smart-aacf894d-082e-430e-8ffa-8437d68f1d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682759838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1682759838
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4096899052
Short name T528
Test name
Test status
Simulation time 3112741209 ps
CPU time 11.53 seconds
Started Jul 01 06:30:45 PM PDT 24
Finished Jul 01 06:30:57 PM PDT 24
Peak memory 233864 kb
Host smart-7ba56bcb-c5c7-4964-a21a-76a32ca71009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096899052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4096899052
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3970591242
Short name T709
Test name
Test status
Simulation time 4544044460 ps
CPU time 15.1 seconds
Started Jul 01 06:30:42 PM PDT 24
Finished Jul 01 06:30:58 PM PDT 24
Peak memory 232472 kb
Host smart-e35c64b1-0c12-4c6e-8893-0226244f3df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970591242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3970591242
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3571466356
Short name T64
Test name
Test status
Simulation time 12085104247 ps
CPU time 9.78 seconds
Started Jul 01 06:30:36 PM PDT 24
Finished Jul 01 06:30:47 PM PDT 24
Peak memory 225640 kb
Host smart-2081b2e1-8a78-4d6e-a3ed-053d01f4f27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571466356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3571466356
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2494196283
Short name T672
Test name
Test status
Simulation time 15927235337 ps
CPU time 8.29 seconds
Started Jul 01 06:30:42 PM PDT 24
Finished Jul 01 06:30:51 PM PDT 24
Peak memory 225716 kb
Host smart-a77bde63-b5f5-4c25-a23d-507d4d6c197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494196283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2494196283
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3831674822
Short name T368
Test name
Test status
Simulation time 762800277 ps
CPU time 8.02 seconds
Started Jul 01 06:30:44 PM PDT 24
Finished Jul 01 06:30:53 PM PDT 24
Peak memory 223600 kb
Host smart-26e561da-8307-4ffc-a717-230ecc330f10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3831674822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3831674822
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1473112434
Short name T662
Test name
Test status
Simulation time 681950901 ps
CPU time 1 seconds
Started Jul 01 06:30:48 PM PDT 24
Finished Jul 01 06:30:49 PM PDT 24
Peak memory 206852 kb
Host smart-ff0c00c0-99b6-4b0d-ad6c-e150c40983e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473112434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1473112434
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.846449056
Short name T813
Test name
Test status
Simulation time 2169736802 ps
CPU time 19.22 seconds
Started Jul 01 06:30:43 PM PDT 24
Finished Jul 01 06:31:03 PM PDT 24
Peak memory 217484 kb
Host smart-38a2f6bf-e017-4e77-bef0-b21d4e22d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846449056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.846449056
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4050568776
Short name T521
Test name
Test status
Simulation time 7704755849 ps
CPU time 8.7 seconds
Started Jul 01 06:30:42 PM PDT 24
Finished Jul 01 06:30:52 PM PDT 24
Peak memory 217484 kb
Host smart-57fd40f6-4feb-4ca5-b748-61f6e7c75fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050568776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4050568776
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4281950346
Short name T152
Test name
Test status
Simulation time 19519152 ps
CPU time 0.84 seconds
Started Jul 01 06:30:38 PM PDT 24
Finished Jul 01 06:30:40 PM PDT 24
Peak memory 207592 kb
Host smart-518718cd-3fe1-41b7-8140-0841215e4583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281950346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4281950346
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2592198117
Short name T901
Test name
Test status
Simulation time 34191154 ps
CPU time 0.82 seconds
Started Jul 01 06:30:40 PM PDT 24
Finished Jul 01 06:30:41 PM PDT 24
Peak memory 206876 kb
Host smart-1017ddf2-a354-4872-b19a-93723a034694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592198117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2592198117
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.745309252
Short name T869
Test name
Test status
Simulation time 2543108684 ps
CPU time 8.51 seconds
Started Jul 01 06:30:44 PM PDT 24
Finished Jul 01 06:30:54 PM PDT 24
Peak memory 225800 kb
Host smart-c3210c51-81d7-4aaa-a349-4e4a6ed22974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745309252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.745309252
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3664151408
Short name T370
Test name
Test status
Simulation time 30746119 ps
CPU time 0.72 seconds
Started Jul 01 06:30:56 PM PDT 24
Finished Jul 01 06:30:59 PM PDT 24
Peak memory 206392 kb
Host smart-0056eff7-c66a-4af7-a09a-6362ff9d77e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664151408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3664151408
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1150423942
Short name T506
Test name
Test status
Simulation time 2024206422 ps
CPU time 2.43 seconds
Started Jul 01 06:30:53 PM PDT 24
Finished Jul 01 06:30:57 PM PDT 24
Peak memory 225480 kb
Host smart-8b1be620-9fda-46f8-a9e9-3685aeed33c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150423942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1150423942
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4156032503
Short name T695
Test name
Test status
Simulation time 21558129 ps
CPU time 0.78 seconds
Started Jul 01 06:30:53 PM PDT 24
Finished Jul 01 06:30:56 PM PDT 24
Peak memory 207848 kb
Host smart-77b69f0b-44d7-4248-885f-3655fd519325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156032503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4156032503
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.82306202
Short name T55
Test name
Test status
Simulation time 7291362621 ps
CPU time 23.23 seconds
Started Jul 01 06:30:56 PM PDT 24
Finished Jul 01 06:31:21 PM PDT 24
Peak memory 250372 kb
Host smart-45eaf296-f385-4b04-bdd7-3cfd5af44519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82306202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.82306202
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.4260471456
Short name T157
Test name
Test status
Simulation time 551986342658 ps
CPU time 425.44 seconds
Started Jul 01 06:30:56 PM PDT 24
Finished Jul 01 06:38:03 PM PDT 24
Peak memory 257200 kb
Host smart-1f0f579b-e4c2-4bd1-a2bd-5dab9c9daae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260471456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.4260471456
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1802818959
Short name T886
Test name
Test status
Simulation time 484492028 ps
CPU time 6.98 seconds
Started Jul 01 06:30:56 PM PDT 24
Finished Jul 01 06:31:04 PM PDT 24
Peak memory 236044 kb
Host smart-72286132-e1c4-4e56-a5db-c98420cde710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802818959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1802818959
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1078257389
Short name T120
Test name
Test status
Simulation time 1780651028 ps
CPU time 9.99 seconds
Started Jul 01 06:30:53 PM PDT 24
Finished Jul 01 06:31:04 PM PDT 24
Peak memory 233732 kb
Host smart-fa977198-970f-4a3b-a5e1-a8377ab4d04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078257389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1078257389
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1180920055
Short name T196
Test name
Test status
Simulation time 6696196647 ps
CPU time 20.73 seconds
Started Jul 01 06:30:48 PM PDT 24
Finished Jul 01 06:31:10 PM PDT 24
Peak memory 242152 kb
Host smart-47f26e2d-a837-4bfb-bbf9-c2338eb57918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180920055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1180920055
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.231756401
Short name T407
Test name
Test status
Simulation time 55968896 ps
CPU time 2.34 seconds
Started Jul 01 06:30:50 PM PDT 24
Finished Jul 01 06:30:54 PM PDT 24
Peak memory 225636 kb
Host smart-5ce4b8c5-38da-4fe3-8a16-42921b3749af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231756401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.231756401
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2069959667
Short name T724
Test name
Test status
Simulation time 410151207 ps
CPU time 6.47 seconds
Started Jul 01 06:30:50 PM PDT 24
Finished Jul 01 06:30:58 PM PDT 24
Peak memory 225520 kb
Host smart-14841fae-9b75-4c4e-b72e-588eda739e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069959667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2069959667
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2642905318
Short name T285
Test name
Test status
Simulation time 1578639153 ps
CPU time 6.59 seconds
Started Jul 01 06:30:50 PM PDT 24
Finished Jul 01 06:30:58 PM PDT 24
Peak memory 233796 kb
Host smart-55e037c2-0475-44dc-8d21-e5ef75957b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642905318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2642905318
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2733049446
Short name T497
Test name
Test status
Simulation time 6347616571 ps
CPU time 17.9 seconds
Started Jul 01 06:30:50 PM PDT 24
Finished Jul 01 06:31:09 PM PDT 24
Peak memory 225740 kb
Host smart-fea66719-bbd2-4d42-88f9-4ccb3781624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733049446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2733049446
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3601568050
Short name T915
Test name
Test status
Simulation time 3696069223 ps
CPU time 8.15 seconds
Started Jul 01 06:30:57 PM PDT 24
Finished Jul 01 06:31:07 PM PDT 24
Peak memory 222720 kb
Host smart-02a10d81-1bf5-4865-abd9-0c7caa85e803
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3601568050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3601568050
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1183498712
Short name T754
Test name
Test status
Simulation time 81555670484 ps
CPU time 208.24 seconds
Started Jul 01 06:30:56 PM PDT 24
Finished Jul 01 06:34:26 PM PDT 24
Peak memory 250480 kb
Host smart-8e70caa2-aa17-47d4-a3c1-d2b5b394779b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183498712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1183498712
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4084711754
Short name T347
Test name
Test status
Simulation time 13264998163 ps
CPU time 27.5 seconds
Started Jul 01 06:30:53 PM PDT 24
Finished Jul 01 06:31:22 PM PDT 24
Peak memory 217516 kb
Host smart-f76e9680-4062-4a35-983f-62efe86720d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084711754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4084711754
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3203111543
Short name T471
Test name
Test status
Simulation time 16968032299 ps
CPU time 9.32 seconds
Started Jul 01 06:30:49 PM PDT 24
Finished Jul 01 06:30:59 PM PDT 24
Peak memory 217528 kb
Host smart-d87177d9-fa97-4f22-983a-badb354752f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203111543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3203111543
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3932218448
Short name T966
Test name
Test status
Simulation time 36456796 ps
CPU time 0.7 seconds
Started Jul 01 06:30:51 PM PDT 24
Finished Jul 01 06:30:54 PM PDT 24
Peak memory 206556 kb
Host smart-43e6c294-7023-4574-a93c-db1587b18294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932218448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3932218448
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.132364084
Short name T467
Test name
Test status
Simulation time 21539236 ps
CPU time 0.73 seconds
Started Jul 01 06:30:49 PM PDT 24
Finished Jul 01 06:30:51 PM PDT 24
Peak memory 206976 kb
Host smart-42370cee-84e5-40dc-a673-613cbe8424f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132364084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.132364084
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.118358022
Short name T385
Test name
Test status
Simulation time 144053872 ps
CPU time 2.31 seconds
Started Jul 01 06:30:50 PM PDT 24
Finished Jul 01 06:30:54 PM PDT 24
Peak memory 233568 kb
Host smart-91cf948b-2075-4b98-8e71-27564b75bc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118358022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.118358022
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2171003793
Short name T853
Test name
Test status
Simulation time 88898116 ps
CPU time 0.69 seconds
Started Jul 01 06:31:05 PM PDT 24
Finished Jul 01 06:31:06 PM PDT 24
Peak memory 206484 kb
Host smart-bc37f266-df4d-473f-a033-a5ca9a7c542a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171003793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2171003793
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.195252726
Short name T267
Test name
Test status
Simulation time 109667925 ps
CPU time 3.75 seconds
Started Jul 01 06:31:01 PM PDT 24
Finished Jul 01 06:31:06 PM PDT 24
Peak memory 233732 kb
Host smart-0625a073-9d1a-46c9-9543-e5c60d3069ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195252726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.195252726
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1282348283
Short name T650
Test name
Test status
Simulation time 173099362 ps
CPU time 0.75 seconds
Started Jul 01 06:30:55 PM PDT 24
Finished Jul 01 06:30:57 PM PDT 24
Peak memory 207524 kb
Host smart-be623477-8697-436f-b93c-72f0bb3c5ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282348283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1282348283
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1603481328
Short name T318
Test name
Test status
Simulation time 101171489659 ps
CPU time 403.95 seconds
Started Jul 01 06:31:02 PM PDT 24
Finished Jul 01 06:37:48 PM PDT 24
Peak memory 255444 kb
Host smart-5c794808-51cb-40c1-9b07-75388629d42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603481328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1603481328
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3698890577
Short name T975
Test name
Test status
Simulation time 17911114716 ps
CPU time 20 seconds
Started Jul 01 06:31:03 PM PDT 24
Finished Jul 01 06:31:24 PM PDT 24
Peak memory 224544 kb
Host smart-cc6bab8c-1416-457e-9385-7cd9d5b6b482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698890577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3698890577
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2369089147
Short name T828
Test name
Test status
Simulation time 4820053708 ps
CPU time 14.25 seconds
Started Jul 01 06:31:02 PM PDT 24
Finished Jul 01 06:31:17 PM PDT 24
Peak memory 218836 kb
Host smart-6e5d5081-e0b0-4229-8a1f-4edd3438b308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369089147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2369089147
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2915083848
Short name T617
Test name
Test status
Simulation time 1957666355 ps
CPU time 9.48 seconds
Started Jul 01 06:31:00 PM PDT 24
Finished Jul 01 06:31:10 PM PDT 24
Peak memory 235148 kb
Host smart-ae9360c7-bbf6-4aa3-9b67-2b620df03bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915083848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2915083848
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1912673185
Short name T94
Test name
Test status
Simulation time 33760802227 ps
CPU time 107.67 seconds
Started Jul 01 06:31:04 PM PDT 24
Finished Jul 01 06:32:53 PM PDT 24
Peak memory 258356 kb
Host smart-bbd98f2e-a6ef-4350-a483-d33376165ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912673185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1912673185
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1655241183
Short name T510
Test name
Test status
Simulation time 34882039 ps
CPU time 2.4 seconds
Started Jul 01 06:31:02 PM PDT 24
Finished Jul 01 06:31:06 PM PDT 24
Peak memory 233448 kb
Host smart-183f5efd-8a9e-46f7-bb96-70cfdc7a58b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655241183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1655241183
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.261617687
Short name T223
Test name
Test status
Simulation time 9221540881 ps
CPU time 81.47 seconds
Started Jul 01 06:31:06 PM PDT 24
Finished Jul 01 06:32:29 PM PDT 24
Peak memory 233780 kb
Host smart-7a866048-0e4c-4e5c-afc7-3768ed77c64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261617687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.261617687
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.703355824
Short name T224
Test name
Test status
Simulation time 242528064 ps
CPU time 4.05 seconds
Started Jul 01 06:31:01 PM PDT 24
Finished Jul 01 06:31:07 PM PDT 24
Peak memory 225596 kb
Host smart-42fe0b0e-2655-457b-a566-67f18a021ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703355824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.703355824
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2528690652
Short name T832
Test name
Test status
Simulation time 6031858628 ps
CPU time 9.67 seconds
Started Jul 01 06:31:02 PM PDT 24
Finished Jul 01 06:31:14 PM PDT 24
Peak memory 225720 kb
Host smart-7d70680f-782b-4783-a4a1-fb9df5ae193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528690652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2528690652
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2230696419
Short name T833
Test name
Test status
Simulation time 2035572417 ps
CPU time 3.84 seconds
Started Jul 01 06:31:01 PM PDT 24
Finished Jul 01 06:31:06 PM PDT 24
Peak memory 219676 kb
Host smart-ce56fb9d-feda-41b4-ae96-b54d57a95904
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2230696419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2230696419
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1958528834
Short name T160
Test name
Test status
Simulation time 44656221477 ps
CPU time 225.13 seconds
Started Jul 01 06:31:06 PM PDT 24
Finished Jul 01 06:34:52 PM PDT 24
Peak memory 283120 kb
Host smart-f420854f-35f0-41ff-9ed0-350ce857b3d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958528834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1958528834
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.84118097
Short name T570
Test name
Test status
Simulation time 3456635967 ps
CPU time 15.35 seconds
Started Jul 01 06:30:57 PM PDT 24
Finished Jul 01 06:31:14 PM PDT 24
Peak memory 217556 kb
Host smart-06f6e093-baaf-4ec8-bd33-307c41439b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84118097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.84118097
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3361454965
Short name T810
Test name
Test status
Simulation time 4737330327 ps
CPU time 13.97 seconds
Started Jul 01 06:30:56 PM PDT 24
Finished Jul 01 06:31:11 PM PDT 24
Peak memory 217500 kb
Host smart-9f24ad8e-979f-4dd3-91bc-97bc6fbecf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361454965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3361454965
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2855819360
Short name T898
Test name
Test status
Simulation time 29127715 ps
CPU time 0.82 seconds
Started Jul 01 06:31:02 PM PDT 24
Finished Jul 01 06:31:05 PM PDT 24
Peak memory 206972 kb
Host smart-71f5563a-66c8-4bf7-8bd3-efb99f2a1c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855819360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2855819360
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3306214917
Short name T73
Test name
Test status
Simulation time 145095197 ps
CPU time 0.82 seconds
Started Jul 01 06:30:58 PM PDT 24
Finished Jul 01 06:31:00 PM PDT 24
Peak memory 207080 kb
Host smart-94e9f6f3-31e8-439a-8f96-5eed80096b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306214917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3306214917
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1085729467
Short name T515
Test name
Test status
Simulation time 2655979521 ps
CPU time 11.17 seconds
Started Jul 01 06:31:00 PM PDT 24
Finished Jul 01 06:31:13 PM PDT 24
Peak memory 233872 kb
Host smart-31f3840c-8377-4e40-9226-fb831902094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085729467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1085729467
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3445123011
Short name T530
Test name
Test status
Simulation time 40549909 ps
CPU time 0.74 seconds
Started Jul 01 06:31:09 PM PDT 24
Finished Jul 01 06:31:11 PM PDT 24
Peak memory 206384 kb
Host smart-bc91b833-6f4a-4d22-8444-cc990b83b5e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445123011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3445123011
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2918401738
Short name T784
Test name
Test status
Simulation time 1146303306 ps
CPU time 2.28 seconds
Started Jul 01 06:31:09 PM PDT 24
Finished Jul 01 06:31:12 PM PDT 24
Peak memory 225556 kb
Host smart-75776980-e2e7-419d-be00-020ab2efdd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918401738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2918401738
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2790266215
Short name T354
Test name
Test status
Simulation time 16312008 ps
CPU time 0.82 seconds
Started Jul 01 06:31:01 PM PDT 24
Finished Jul 01 06:31:04 PM PDT 24
Peak memory 207684 kb
Host smart-274bf870-77cb-4266-a59c-12ec1dae5dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790266215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2790266215
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1722492334
Short name T44
Test name
Test status
Simulation time 5705527382 ps
CPU time 30.77 seconds
Started Jul 01 06:31:09 PM PDT 24
Finished Jul 01 06:31:41 PM PDT 24
Peak memory 238264 kb
Host smart-ef1863fe-1276-49ef-ba95-2307fcc531d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722492334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1722492334
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1299366262
Short name T1019
Test name
Test status
Simulation time 44046717896 ps
CPU time 227.77 seconds
Started Jul 01 06:31:08 PM PDT 24
Finished Jul 01 06:34:56 PM PDT 24
Peak memory 251920 kb
Host smart-e226f04a-131b-46be-816c-1ae1a18f2a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299366262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1299366262
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2211500893
Short name T327
Test name
Test status
Simulation time 2885062894 ps
CPU time 22.86 seconds
Started Jul 01 06:31:08 PM PDT 24
Finished Jul 01 06:31:33 PM PDT 24
Peak memory 242068 kb
Host smart-a6e9bf9b-2a9e-462f-9c41-0d8e50bdf07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211500893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2211500893
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3575324726
Short name T942
Test name
Test status
Simulation time 18747762147 ps
CPU time 71.29 seconds
Started Jul 01 06:31:08 PM PDT 24
Finished Jul 01 06:32:21 PM PDT 24
Peak memory 253484 kb
Host smart-49777306-b00a-424f-a0a5-51c30e39f0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575324726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3575324726
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3955072562
Short name T812
Test name
Test status
Simulation time 17293740955 ps
CPU time 26.84 seconds
Started Jul 01 06:31:09 PM PDT 24
Finished Jul 01 06:31:38 PM PDT 24
Peak memory 225660 kb
Host smart-4c45544e-fe0e-437a-a698-3c86c113c734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955072562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3955072562
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3634811950
Short name T608
Test name
Test status
Simulation time 1527841394 ps
CPU time 20.35 seconds
Started Jul 01 06:31:11 PM PDT 24
Finished Jul 01 06:31:32 PM PDT 24
Peak memory 225524 kb
Host smart-2a0e0c1d-1fc2-4adb-b5ae-2e574589df38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634811950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3634811950
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1306340341
Short name T936
Test name
Test status
Simulation time 684431452 ps
CPU time 4.94 seconds
Started Jul 01 06:31:08 PM PDT 24
Finished Jul 01 06:31:14 PM PDT 24
Peak memory 233724 kb
Host smart-383e5fbf-0b81-4068-99da-ce514f2c1e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306340341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1306340341
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.246587372
Short name T729
Test name
Test status
Simulation time 33602480 ps
CPU time 2.43 seconds
Started Jul 01 06:31:03 PM PDT 24
Finished Jul 01 06:31:07 PM PDT 24
Peak memory 228912 kb
Host smart-9b934b08-eda4-4619-b6f2-b27d33c129f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246587372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.246587372
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2391657765
Short name T411
Test name
Test status
Simulation time 2121145043 ps
CPU time 5.19 seconds
Started Jul 01 06:31:09 PM PDT 24
Finished Jul 01 06:31:15 PM PDT 24
Peak memory 223216 kb
Host smart-367ec62f-ac8d-483f-9eb8-e450bd6e0ea3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2391657765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2391657765
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4053685828
Short name T38
Test name
Test status
Simulation time 45740101921 ps
CPU time 408.38 seconds
Started Jul 01 06:31:08 PM PDT 24
Finished Jul 01 06:37:57 PM PDT 24
Peak memory 266548 kb
Host smart-062a1256-cfa7-4b57-abe4-76445d97f33c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053685828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4053685828
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.893538872
Short name T405
Test name
Test status
Simulation time 3282337211 ps
CPU time 6.92 seconds
Started Jul 01 06:31:02 PM PDT 24
Finished Jul 01 06:31:11 PM PDT 24
Peak memory 217552 kb
Host smart-dad86420-0e30-426d-bffe-9016aea666c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893538872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.893538872
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3705980809
Short name T33
Test name
Test status
Simulation time 10894991 ps
CPU time 0.71 seconds
Started Jul 01 06:31:01 PM PDT 24
Finished Jul 01 06:31:03 PM PDT 24
Peak memory 206928 kb
Host smart-8929c200-ea52-4534-b912-fda651b91772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705980809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3705980809
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1221495721
Short name T1015
Test name
Test status
Simulation time 179330286 ps
CPU time 1.06 seconds
Started Jul 01 06:31:03 PM PDT 24
Finished Jul 01 06:31:06 PM PDT 24
Peak memory 207924 kb
Host smart-80ea3504-fefd-4351-b634-a320703835be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221495721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1221495721
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1343423110
Short name T399
Test name
Test status
Simulation time 427821139 ps
CPU time 7.06 seconds
Started Jul 01 06:31:07 PM PDT 24
Finished Jul 01 06:31:15 PM PDT 24
Peak memory 233784 kb
Host smart-5ae2db89-448b-400e-8406-181475543897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343423110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1343423110
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1805368915
Short name T818
Test name
Test status
Simulation time 46766072 ps
CPU time 0.72 seconds
Started Jul 01 06:31:19 PM PDT 24
Finished Jul 01 06:31:21 PM PDT 24
Peak memory 206448 kb
Host smart-9ec3f9ba-ae79-43c9-9646-0f64f0e51df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805368915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1805368915
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.164734265
Short name T740
Test name
Test status
Simulation time 318055683 ps
CPU time 4.25 seconds
Started Jul 01 06:31:14 PM PDT 24
Finished Jul 01 06:31:19 PM PDT 24
Peak memory 233816 kb
Host smart-de013d27-7087-4607-b83b-7209fc138e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164734265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.164734265
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1315769984
Short name T440
Test name
Test status
Simulation time 24215240 ps
CPU time 0.74 seconds
Started Jul 01 06:31:09 PM PDT 24
Finished Jul 01 06:31:11 PM PDT 24
Peak memory 206816 kb
Host smart-c9e9122c-135b-4909-98d6-2aac2b01117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315769984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1315769984
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1007306737
Short name T547
Test name
Test status
Simulation time 6838571660 ps
CPU time 69.96 seconds
Started Jul 01 06:31:20 PM PDT 24
Finished Jul 01 06:32:31 PM PDT 24
Peak memory 250356 kb
Host smart-caca5a3a-6661-49d2-a5e6-be54489b8699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007306737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1007306737
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.589771033
Short name T410
Test name
Test status
Simulation time 11378864753 ps
CPU time 24.07 seconds
Started Jul 01 06:31:22 PM PDT 24
Finished Jul 01 06:31:47 PM PDT 24
Peak memory 218884 kb
Host smart-c3a346f3-4c6f-48d9-b8a8-b91f56c2b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589771033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.589771033
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3116121771
Short name T661
Test name
Test status
Simulation time 15735794185 ps
CPU time 36.59 seconds
Started Jul 01 06:31:22 PM PDT 24
Finished Jul 01 06:31:59 PM PDT 24
Peak memory 241916 kb
Host smart-ee5b845e-3a89-46f4-a021-fefaf8021624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116121771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3116121771
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.649494388
Short name T62
Test name
Test status
Simulation time 9192340980 ps
CPU time 62.82 seconds
Started Jul 01 06:31:13 PM PDT 24
Finished Jul 01 06:32:17 PM PDT 24
Peak memory 251628 kb
Host smart-24036e5a-69f6-44a6-9ee6-a5118693ce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649494388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.649494388
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3836634763
Short name T72
Test name
Test status
Simulation time 129273761 ps
CPU time 3.03 seconds
Started Jul 01 06:31:13 PM PDT 24
Finished Jul 01 06:31:16 PM PDT 24
Peak memory 233808 kb
Host smart-fe40c3a5-8cbc-4ae8-9e04-21ef71ebc2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836634763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3836634763
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.292034819
Short name T941
Test name
Test status
Simulation time 97582311 ps
CPU time 2.17 seconds
Started Jul 01 06:31:13 PM PDT 24
Finished Jul 01 06:31:16 PM PDT 24
Peak memory 219748 kb
Host smart-5a6286bc-1b1f-4603-bf4c-9e5bf0d9f18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292034819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.292034819
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2539480085
Short name T907
Test name
Test status
Simulation time 17804266913 ps
CPU time 12.43 seconds
Started Jul 01 06:31:15 PM PDT 24
Finished Jul 01 06:31:28 PM PDT 24
Peak memory 233940 kb
Host smart-5a1e1b4d-2482-4524-ad59-262c99bd100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539480085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2539480085
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3727772681
Short name T487
Test name
Test status
Simulation time 29434879277 ps
CPU time 19.9 seconds
Started Jul 01 06:31:07 PM PDT 24
Finished Jul 01 06:31:28 PM PDT 24
Peak memory 225732 kb
Host smart-45ccde46-e877-4aba-aed3-d9146bfc9d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727772681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3727772681
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3445474852
Short name T737
Test name
Test status
Simulation time 2078802068 ps
CPU time 13.4 seconds
Started Jul 01 06:31:12 PM PDT 24
Finished Jul 01 06:31:26 PM PDT 24
Peak memory 221472 kb
Host smart-6ede1ccf-91c7-49da-974a-b66aad82b844
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3445474852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3445474852
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2102586361
Short name T868
Test name
Test status
Simulation time 7656896095 ps
CPU time 129.52 seconds
Started Jul 01 06:31:21 PM PDT 24
Finished Jul 01 06:33:32 PM PDT 24
Peak memory 266260 kb
Host smart-4704e9a2-9a75-40ad-91e0-42252b9ea18c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102586361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2102586361
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.86896007
Short name T346
Test name
Test status
Simulation time 3610614692 ps
CPU time 14.79 seconds
Started Jul 01 06:31:06 PM PDT 24
Finished Jul 01 06:31:22 PM PDT 24
Peak memory 217580 kb
Host smart-d9f82b15-7ae5-4b51-97c9-c68dde2edb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86896007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.86896007
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4012885925
Short name T783
Test name
Test status
Simulation time 4526810659 ps
CPU time 7.48 seconds
Started Jul 01 06:31:11 PM PDT 24
Finished Jul 01 06:31:19 PM PDT 24
Peak memory 217564 kb
Host smart-f2dcdd3a-d48b-46d1-bc17-24d459a5ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012885925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4012885925
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.325926916
Short name T855
Test name
Test status
Simulation time 12878778 ps
CPU time 0.72 seconds
Started Jul 01 06:31:07 PM PDT 24
Finished Jul 01 06:31:09 PM PDT 24
Peak memory 206548 kb
Host smart-a9b43c16-b828-4438-831c-d8c9bc91f046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325926916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.325926916
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.701541585
Short name T517
Test name
Test status
Simulation time 11762384 ps
CPU time 0.7 seconds
Started Jul 01 06:31:11 PM PDT 24
Finished Jul 01 06:31:12 PM PDT 24
Peak memory 206548 kb
Host smart-5eed7e64-2eca-46c1-8f2b-301e8ef3c070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701541585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.701541585
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.38706816
Short name T569
Test name
Test status
Simulation time 121610816 ps
CPU time 2.86 seconds
Started Jul 01 06:31:14 PM PDT 24
Finished Jul 01 06:31:17 PM PDT 24
Peak memory 229424 kb
Host smart-be0c0054-3cd9-4012-895a-2946bf68b8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38706816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.38706816
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2517966365
Short name T720
Test name
Test status
Simulation time 18085262 ps
CPU time 0.69 seconds
Started Jul 01 06:31:33 PM PDT 24
Finished Jul 01 06:31:35 PM PDT 24
Peak memory 206416 kb
Host smart-98203bf4-9355-4570-9fee-cc584286fb3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517966365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2517966365
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3054542127
Short name T1005
Test name
Test status
Simulation time 312434998 ps
CPU time 2.55 seconds
Started Jul 01 06:31:26 PM PDT 24
Finished Jul 01 06:31:29 PM PDT 24
Peak memory 233764 kb
Host smart-0a862d63-72a4-45cb-b3fb-702f7d5772a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054542127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3054542127
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4188811520
Short name T406
Test name
Test status
Simulation time 34121458 ps
CPU time 0.86 seconds
Started Jul 01 06:31:21 PM PDT 24
Finished Jul 01 06:31:23 PM PDT 24
Peak memory 207536 kb
Host smart-f6370026-627e-462d-9d4e-2129609a8627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188811520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4188811520
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1838321478
Short name T325
Test name
Test status
Simulation time 7035714552 ps
CPU time 91.61 seconds
Started Jul 01 06:31:31 PM PDT 24
Finished Jul 01 06:33:03 PM PDT 24
Peak memory 257200 kb
Host smart-ad8a87b0-337b-49e5-b0e4-da4d19eae85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838321478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1838321478
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2180630091
Short name T225
Test name
Test status
Simulation time 43242784953 ps
CPU time 441.2 seconds
Started Jul 01 06:31:35 PM PDT 24
Finished Jul 01 06:38:57 PM PDT 24
Peak memory 273172 kb
Host smart-44e8922c-01e0-41ce-8d7e-c124137c7fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180630091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2180630091
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3450457378
Short name T984
Test name
Test status
Simulation time 26586240408 ps
CPU time 84.66 seconds
Started Jul 01 06:31:34 PM PDT 24
Finished Jul 01 06:33:00 PM PDT 24
Peak memory 240440 kb
Host smart-d39a0ceb-f059-4313-9e56-6afa4f0e8831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450457378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3450457378
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2729401350
Short name T542
Test name
Test status
Simulation time 1020315725 ps
CPU time 6.51 seconds
Started Jul 01 06:31:27 PM PDT 24
Finished Jul 01 06:31:34 PM PDT 24
Peak memory 225592 kb
Host smart-6cf4ba56-57ac-486d-892d-2ccd0567a9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729401350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2729401350
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1775186684
Short name T13
Test name
Test status
Simulation time 3576713362 ps
CPU time 6.21 seconds
Started Jul 01 06:31:33 PM PDT 24
Finished Jul 01 06:31:41 PM PDT 24
Peak memory 225712 kb
Host smart-069efbe0-416d-4d2b-88e4-5333546201e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775186684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1775186684
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4142410511
Short name T248
Test name
Test status
Simulation time 1322946480 ps
CPU time 15.07 seconds
Started Jul 01 06:31:26 PM PDT 24
Finished Jul 01 06:31:43 PM PDT 24
Peak memory 225536 kb
Host smart-ce392e2f-6a9f-4cc5-8bbf-6f35a00731ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142410511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4142410511
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3128514443
Short name T483
Test name
Test status
Simulation time 318575488 ps
CPU time 5.59 seconds
Started Jul 01 06:31:26 PM PDT 24
Finished Jul 01 06:31:32 PM PDT 24
Peak memory 225576 kb
Host smart-0d8730aa-9000-4f7d-8c16-42633c833bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128514443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3128514443
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.162706038
Short name T769
Test name
Test status
Simulation time 863313905 ps
CPU time 4.99 seconds
Started Jul 01 06:31:26 PM PDT 24
Finished Jul 01 06:31:32 PM PDT 24
Peak memory 225560 kb
Host smart-edf83083-b14b-4d2e-b494-628329be0305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162706038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.162706038
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.490408251
Short name T525
Test name
Test status
Simulation time 210598458 ps
CPU time 2.25 seconds
Started Jul 01 06:31:26 PM PDT 24
Finished Jul 01 06:31:30 PM PDT 24
Peak memory 225556 kb
Host smart-d7eb60e7-fe70-440e-b1ac-313a66469bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490408251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.490408251
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1267409777
Short name T1
Test name
Test status
Simulation time 996586854 ps
CPU time 3.92 seconds
Started Jul 01 06:31:31 PM PDT 24
Finished Jul 01 06:31:36 PM PDT 24
Peak memory 221640 kb
Host smart-ba769b58-df76-4d39-b3dd-f08776ad591a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1267409777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1267409777
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2617378308
Short name T576
Test name
Test status
Simulation time 799572645 ps
CPU time 2.98 seconds
Started Jul 01 06:31:27 PM PDT 24
Finished Jul 01 06:31:31 PM PDT 24
Peak memory 217636 kb
Host smart-e601ce99-5073-4a25-9de7-669f118f8593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617378308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2617378308
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1810992677
Short name T490
Test name
Test status
Simulation time 5284408483 ps
CPU time 8.72 seconds
Started Jul 01 06:31:25 PM PDT 24
Finished Jul 01 06:31:34 PM PDT 24
Peak memory 217524 kb
Host smart-3b61336a-bf17-445f-a764-b2624e586236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810992677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1810992677
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3730262722
Short name T26
Test name
Test status
Simulation time 16350940 ps
CPU time 0.82 seconds
Started Jul 01 06:31:23 PM PDT 24
Finished Jul 01 06:31:25 PM PDT 24
Peak memory 207584 kb
Host smart-51cd6fd3-c2e5-474c-b850-9746be89a54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730262722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3730262722
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2959237476
Short name T849
Test name
Test status
Simulation time 28186061 ps
CPU time 0.75 seconds
Started Jul 01 06:31:25 PM PDT 24
Finished Jul 01 06:31:26 PM PDT 24
Peak memory 206972 kb
Host smart-7497bca2-2986-4d36-8b4b-19a0c4e14c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959237476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2959237476
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2674838809
Short name T380
Test name
Test status
Simulation time 1397623497 ps
CPU time 7.72 seconds
Started Jul 01 06:31:25 PM PDT 24
Finished Jul 01 06:31:33 PM PDT 24
Peak memory 225552 kb
Host smart-4455094b-96e5-4551-a47b-fcd5d78a059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674838809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2674838809
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4052988283
Short name T697
Test name
Test status
Simulation time 11929999 ps
CPU time 0.74 seconds
Started Jul 01 06:31:37 PM PDT 24
Finished Jul 01 06:31:38 PM PDT 24
Peak memory 206752 kb
Host smart-d0de6b78-60dc-4dfb-b2a3-6aef5da04af7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052988283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4052988283
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1814511434
Short name T423
Test name
Test status
Simulation time 826303478 ps
CPU time 10.69 seconds
Started Jul 01 06:31:35 PM PDT 24
Finished Jul 01 06:31:46 PM PDT 24
Peak memory 233800 kb
Host smart-f1736f74-b41f-4c63-992f-e4ffabc97ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814511434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1814511434
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3828032497
Short name T718
Test name
Test status
Simulation time 19126506 ps
CPU time 0.77 seconds
Started Jul 01 06:31:33 PM PDT 24
Finished Jul 01 06:31:35 PM PDT 24
Peak memory 207472 kb
Host smart-3d32e240-164d-4d1f-8a2f-8b405b7e8b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828032497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3828032497
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3015151364
Short name T80
Test name
Test status
Simulation time 1341685864 ps
CPU time 23.78 seconds
Started Jul 01 06:31:36 PM PDT 24
Finished Jul 01 06:32:01 PM PDT 24
Peak memory 240856 kb
Host smart-b67a41a9-2e2d-405d-a4bc-127b22b515c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015151364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3015151364
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.138452583
Short name T969
Test name
Test status
Simulation time 9057462282 ps
CPU time 77.56 seconds
Started Jul 01 06:31:36 PM PDT 24
Finished Jul 01 06:32:55 PM PDT 24
Peak memory 241800 kb
Host smart-14898885-0699-4095-a25f-faa96fa1b7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138452583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.138452583
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2850757379
Short name T299
Test name
Test status
Simulation time 1353011611 ps
CPU time 29.22 seconds
Started Jul 01 06:31:38 PM PDT 24
Finished Jul 01 06:32:08 PM PDT 24
Peak memory 241436 kb
Host smart-f4134554-ef6a-40ef-9896-416bb0db12b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850757379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2850757379
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3319625207
Short name T628
Test name
Test status
Simulation time 7184739878 ps
CPU time 13.89 seconds
Started Jul 01 06:31:32 PM PDT 24
Finished Jul 01 06:31:47 PM PDT 24
Peak memory 242132 kb
Host smart-188fcd48-3883-41f1-a722-d00dbfd2bdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319625207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3319625207
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2221400817
Short name T771
Test name
Test status
Simulation time 10122762997 ps
CPU time 89.3 seconds
Started Jul 01 06:31:33 PM PDT 24
Finished Jul 01 06:33:03 PM PDT 24
Peak memory 255656 kb
Host smart-f0e82638-ab62-4202-aae6-04cee76c9ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221400817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2221400817
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3164521822
Short name T41
Test name
Test status
Simulation time 777565743 ps
CPU time 6.06 seconds
Started Jul 01 06:31:33 PM PDT 24
Finished Jul 01 06:31:40 PM PDT 24
Peak memory 225524 kb
Host smart-bfbc5547-4482-4667-a087-a152f3d2376a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164521822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3164521822
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1978604400
Short name T712
Test name
Test status
Simulation time 18302536675 ps
CPU time 43.96 seconds
Started Jul 01 06:31:33 PM PDT 24
Finished Jul 01 06:32:18 PM PDT 24
Peak memory 225720 kb
Host smart-1ac2528b-9ebb-4dfb-ba48-28b1212a682a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978604400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1978604400
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1744193438
Short name T797
Test name
Test status
Simulation time 1872438513 ps
CPU time 3.59 seconds
Started Jul 01 06:31:32 PM PDT 24
Finished Jul 01 06:31:37 PM PDT 24
Peak memory 225576 kb
Host smart-2a4f683c-8237-4fbe-bbf5-515b4f2768f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744193438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1744193438
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4081644357
Short name T801
Test name
Test status
Simulation time 1964011408 ps
CPU time 7.68 seconds
Started Jul 01 06:31:31 PM PDT 24
Finished Jul 01 06:31:40 PM PDT 24
Peak memory 233736 kb
Host smart-8e24ef02-a081-40b7-bec8-67c402c21272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081644357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4081644357
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2697858839
Short name T816
Test name
Test status
Simulation time 800974432 ps
CPU time 7.66 seconds
Started Jul 01 06:31:35 PM PDT 24
Finished Jul 01 06:31:44 PM PDT 24
Peak memory 221584 kb
Host smart-0f5f7c10-1c49-4931-a73e-a03a77d8f115
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2697858839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2697858839
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3320429914
Short name T840
Test name
Test status
Simulation time 289049325002 ps
CPU time 959.78 seconds
Started Jul 01 06:31:37 PM PDT 24
Finished Jul 01 06:47:38 PM PDT 24
Peak memory 270384 kb
Host smart-d812a818-6aab-422b-bee9-6415fd5bfb16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320429914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3320429914
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.418133392
Short name T334
Test name
Test status
Simulation time 17306830263 ps
CPU time 48.13 seconds
Started Jul 01 06:31:31 PM PDT 24
Finished Jul 01 06:32:20 PM PDT 24
Peak memory 217572 kb
Host smart-ffca07f3-da69-471f-8a7b-d8d762bd3b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418133392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.418133392
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3054711729
Short name T74
Test name
Test status
Simulation time 28693523 ps
CPU time 0.75 seconds
Started Jul 01 06:31:32 PM PDT 24
Finished Jul 01 06:31:34 PM PDT 24
Peak memory 206692 kb
Host smart-7fac5fdc-25fb-4a8c-bdcf-5d31c4ee2eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054711729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3054711729
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3848874986
Short name T905
Test name
Test status
Simulation time 26346182 ps
CPU time 0.81 seconds
Started Jul 01 06:31:31 PM PDT 24
Finished Jul 01 06:31:32 PM PDT 24
Peak memory 207580 kb
Host smart-af946b64-e8b2-4c64-ad48-af6125dd1332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848874986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3848874986
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1450568103
Short name T933
Test name
Test status
Simulation time 245680700 ps
CPU time 1.03 seconds
Started Jul 01 06:31:32 PM PDT 24
Finished Jul 01 06:31:34 PM PDT 24
Peak memory 208008 kb
Host smart-734e2252-0190-437f-b0cc-1a8bcc827ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450568103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1450568103
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.793207788
Short name T744
Test name
Test status
Simulation time 2820677659 ps
CPU time 3.44 seconds
Started Jul 01 06:31:35 PM PDT 24
Finished Jul 01 06:31:39 PM PDT 24
Peak memory 233880 kb
Host smart-4da305d4-3870-4070-8c91-b392d92a0217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793207788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.793207788
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3321276825
Short name T524
Test name
Test status
Simulation time 24936485 ps
CPU time 0.71 seconds
Started Jul 01 06:31:43 PM PDT 24
Finished Jul 01 06:31:44 PM PDT 24
Peak memory 205824 kb
Host smart-22820024-d3cf-4666-a68b-469c2963f3e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321276825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3321276825
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.304061708
Short name T109
Test name
Test status
Simulation time 1795544721 ps
CPU time 6.99 seconds
Started Jul 01 06:31:42 PM PDT 24
Finished Jul 01 06:31:50 PM PDT 24
Peak memory 225612 kb
Host smart-0ff615d0-54c2-4d20-8315-262a9007f374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304061708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.304061708
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2661246082
Short name T952
Test name
Test status
Simulation time 14412760 ps
CPU time 0.79 seconds
Started Jul 01 06:31:35 PM PDT 24
Finished Jul 01 06:31:37 PM PDT 24
Peak memory 207552 kb
Host smart-22c6235d-fbb2-4862-9e53-ee648d3d472d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661246082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2661246082
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2304235490
Short name T632
Test name
Test status
Simulation time 84734989308 ps
CPU time 186.59 seconds
Started Jul 01 06:31:42 PM PDT 24
Finished Jul 01 06:34:49 PM PDT 24
Peak memory 256148 kb
Host smart-6dcdb47e-4bad-4832-8e47-fd352daa79ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304235490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2304235490
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2393465937
Short name T587
Test name
Test status
Simulation time 30438062873 ps
CPU time 21.97 seconds
Started Jul 01 06:31:42 PM PDT 24
Finished Jul 01 06:32:05 PM PDT 24
Peak memory 218848 kb
Host smart-24ae341a-2d19-43c2-acb0-99b341ed4971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393465937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2393465937
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2113911801
Short name T446
Test name
Test status
Simulation time 68325903264 ps
CPU time 271.21 seconds
Started Jul 01 06:31:44 PM PDT 24
Finished Jul 01 06:36:16 PM PDT 24
Peak memory 266812 kb
Host smart-b623d2cd-ff28-4375-bc4e-b9ee8432205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113911801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2113911801
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1088332616
Short name T232
Test name
Test status
Simulation time 4732231590 ps
CPU time 11.23 seconds
Started Jul 01 06:31:42 PM PDT 24
Finished Jul 01 06:31:55 PM PDT 24
Peak memory 249636 kb
Host smart-77576a11-328a-4f41-91b6-3c4053946c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088332616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1088332616
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.474344241
Short name T438
Test name
Test status
Simulation time 6711242011 ps
CPU time 49.76 seconds
Started Jul 01 06:31:45 PM PDT 24
Finished Jul 01 06:32:36 PM PDT 24
Peak memory 242516 kb
Host smart-3fde4d2c-efd9-42f3-9f52-2d229af275e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474344241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.474344241
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1020808634
Short name T702
Test name
Test status
Simulation time 222353737 ps
CPU time 5.25 seconds
Started Jul 01 06:31:37 PM PDT 24
Finished Jul 01 06:31:43 PM PDT 24
Peak memory 225600 kb
Host smart-9a598206-f67a-4bc9-ae89-409b5930acdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020808634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1020808634
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1766924122
Short name T111
Test name
Test status
Simulation time 12403483167 ps
CPU time 36.53 seconds
Started Jul 01 06:31:46 PM PDT 24
Finished Jul 01 06:32:23 PM PDT 24
Peak memory 234096 kb
Host smart-8370fa87-581f-4536-a85d-40fc2a608186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766924122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1766924122
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2390035114
Short name T235
Test name
Test status
Simulation time 99894001312 ps
CPU time 20.73 seconds
Started Jul 01 06:31:36 PM PDT 24
Finished Jul 01 06:31:58 PM PDT 24
Peak memory 225712 kb
Host smart-d03af93b-65f4-4a20-8e7a-df92c4d75870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390035114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2390035114
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3734935646
Short name T741
Test name
Test status
Simulation time 1054978126 ps
CPU time 10.94 seconds
Started Jul 01 06:31:35 PM PDT 24
Finished Jul 01 06:31:47 PM PDT 24
Peak memory 233780 kb
Host smart-dad12d36-4dea-443c-a4a6-387ae33ccf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734935646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3734935646
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3314773404
Short name T408
Test name
Test status
Simulation time 1911319517 ps
CPU time 19.93 seconds
Started Jul 01 06:31:45 PM PDT 24
Finished Jul 01 06:32:06 PM PDT 24
Peak memory 223612 kb
Host smart-b9081525-0103-4ca5-bb3e-c4bac5826a4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3314773404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3314773404
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2808897162
Short name T904
Test name
Test status
Simulation time 116055571 ps
CPU time 1.14 seconds
Started Jul 01 06:31:42 PM PDT 24
Finished Jul 01 06:31:44 PM PDT 24
Peak memory 208792 kb
Host smart-b26d355a-0c10-4184-b1dd-191a64b11c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808897162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2808897162
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1230450091
Short name T345
Test name
Test status
Simulation time 1721315978 ps
CPU time 13.64 seconds
Started Jul 01 06:31:39 PM PDT 24
Finished Jul 01 06:31:53 PM PDT 24
Peak memory 217488 kb
Host smart-3ef1c5f5-7af1-4f04-b9da-7a3af2902a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230450091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1230450091
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1412366382
Short name T621
Test name
Test status
Simulation time 5378207720 ps
CPU time 14.06 seconds
Started Jul 01 06:31:36 PM PDT 24
Finished Jul 01 06:31:51 PM PDT 24
Peak memory 217612 kb
Host smart-00a1a076-3292-4c00-91ce-911b16f66b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412366382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1412366382
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.591494631
Short name T341
Test name
Test status
Simulation time 154188617 ps
CPU time 2.07 seconds
Started Jul 01 06:31:36 PM PDT 24
Finished Jul 01 06:31:39 PM PDT 24
Peak memory 217332 kb
Host smart-abc29afa-95e6-449e-8f99-969c23b33351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591494631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.591494631
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3430452433
Short name T841
Test name
Test status
Simulation time 66684306 ps
CPU time 0.92 seconds
Started Jul 01 06:31:36 PM PDT 24
Finished Jul 01 06:31:38 PM PDT 24
Peak memory 207460 kb
Host smart-cc333179-aec9-41a9-8c09-d96ec690dbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430452433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3430452433
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2963695556
Short name T255
Test name
Test status
Simulation time 146558683 ps
CPU time 2.97 seconds
Started Jul 01 06:31:42 PM PDT 24
Finished Jul 01 06:31:46 PM PDT 24
Peak memory 225716 kb
Host smart-334d109d-8fa8-4537-8daa-23844b65960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963695556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2963695556
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4066200747
Short name T922
Test name
Test status
Simulation time 62059810 ps
CPU time 0.7 seconds
Started Jul 01 06:31:46 PM PDT 24
Finished Jul 01 06:31:48 PM PDT 24
Peak memory 206328 kb
Host smart-9531af0f-917b-4457-99c0-6b4d8c26045f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066200747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4066200747
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1441982444
Short name T2
Test name
Test status
Simulation time 338475811 ps
CPU time 7.73 seconds
Started Jul 01 06:31:47 PM PDT 24
Finished Jul 01 06:31:56 PM PDT 24
Peak memory 225552 kb
Host smart-8a2cfbae-f417-46c2-94ee-6d8f8a6e66be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441982444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1441982444
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3698347806
Short name T434
Test name
Test status
Simulation time 18298460 ps
CPU time 0.77 seconds
Started Jul 01 06:31:46 PM PDT 24
Finished Jul 01 06:31:48 PM PDT 24
Peak memory 206692 kb
Host smart-c9a628a1-d34b-4dff-adf6-d3d79ff2a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698347806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3698347806
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1236844889
Short name T586
Test name
Test status
Simulation time 1727469677 ps
CPU time 38.51 seconds
Started Jul 01 06:31:47 PM PDT 24
Finished Jul 01 06:32:27 PM PDT 24
Peak memory 250200 kb
Host smart-682fa673-fd75-4bbd-8a84-a430eb14afb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236844889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1236844889
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1786225837
Short name T976
Test name
Test status
Simulation time 26999933177 ps
CPU time 128.31 seconds
Started Jul 01 06:31:48 PM PDT 24
Finished Jul 01 06:33:58 PM PDT 24
Peak memory 253372 kb
Host smart-09dd4976-a904-4a46-a8b1-03a8c24f240d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786225837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1786225837
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4018532236
Short name T265
Test name
Test status
Simulation time 2960022979 ps
CPU time 17.95 seconds
Started Jul 01 06:31:50 PM PDT 24
Finished Jul 01 06:32:09 PM PDT 24
Peak memory 242156 kb
Host smart-0acad65f-d305-4034-b4d3-fa1206a8ffcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018532236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4018532236
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2316427333
Short name T470
Test name
Test status
Simulation time 205319527 ps
CPU time 4.52 seconds
Started Jul 01 06:32:22 PM PDT 24
Finished Jul 01 06:32:28 PM PDT 24
Peak memory 225492 kb
Host smart-e098b9f4-1fd8-45bb-9d0f-35c425d6fdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316427333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2316427333
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.55800632
Short name T210
Test name
Test status
Simulation time 3597519667 ps
CPU time 36.95 seconds
Started Jul 01 06:31:49 PM PDT 24
Finished Jul 01 06:32:27 PM PDT 24
Peak memory 231284 kb
Host smart-150d8180-f5b5-44b8-bc4b-b0a991208d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55800632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.55800632
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3666828673
Short name T422
Test name
Test status
Simulation time 539645592 ps
CPU time 7.16 seconds
Started Jul 01 06:31:46 PM PDT 24
Finished Jul 01 06:31:55 PM PDT 24
Peak memory 233764 kb
Host smart-121fa0ff-164c-4e3c-bf57-d1f9236b62b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666828673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3666828673
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2187664657
Short name T877
Test name
Test status
Simulation time 1261481923 ps
CPU time 18.19 seconds
Started Jul 01 06:31:48 PM PDT 24
Finished Jul 01 06:32:07 PM PDT 24
Peak memory 233884 kb
Host smart-21c29e4b-c9c2-4b4e-95ac-b2b7d27e6d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187664657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2187664657
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3467464477
Short name T640
Test name
Test status
Simulation time 251398762 ps
CPU time 6.15 seconds
Started Jul 01 06:31:47 PM PDT 24
Finished Jul 01 06:31:55 PM PDT 24
Peak memory 234780 kb
Host smart-3832f257-d4a8-4ba7-add4-cc169a1c1de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467464477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3467464477
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3429658625
Short name T112
Test name
Test status
Simulation time 650369559 ps
CPU time 10.04 seconds
Started Jul 01 06:31:47 PM PDT 24
Finished Jul 01 06:31:58 PM PDT 24
Peak memory 225596 kb
Host smart-1c11bb29-c7bc-48d3-a2e4-3c85374b0d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429658625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3429658625
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2154073465
Short name T731
Test name
Test status
Simulation time 1682090508 ps
CPU time 4.43 seconds
Started Jul 01 06:31:48 PM PDT 24
Finished Jul 01 06:31:54 PM PDT 24
Peak memory 220360 kb
Host smart-8db5e4f2-e748-4d2f-8e4e-6bcf08ddb53c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2154073465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2154073465
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4025532678
Short name T794
Test name
Test status
Simulation time 32155535665 ps
CPU time 44.15 seconds
Started Jul 01 06:31:40 PM PDT 24
Finished Jul 01 06:32:25 PM PDT 24
Peak memory 222112 kb
Host smart-d388f901-2806-47f0-91ba-558f334bedbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025532678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4025532678
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.794981018
Short name T426
Test name
Test status
Simulation time 11395602572 ps
CPU time 8.39 seconds
Started Jul 01 06:31:41 PM PDT 24
Finished Jul 01 06:31:50 PM PDT 24
Peak memory 217456 kb
Host smart-2beb6a92-8c84-472d-9830-53361511d010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794981018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.794981018
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1292711605
Short name T631
Test name
Test status
Simulation time 32952307 ps
CPU time 1.33 seconds
Started Jul 01 06:31:46 PM PDT 24
Finished Jul 01 06:31:48 PM PDT 24
Peak memory 217460 kb
Host smart-ac7e7b69-217c-40c2-b149-7721a72aa78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292711605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1292711605
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.39125652
Short name T563
Test name
Test status
Simulation time 69838113 ps
CPU time 0.88 seconds
Started Jul 01 06:31:41 PM PDT 24
Finished Jul 01 06:31:42 PM PDT 24
Peak memory 206968 kb
Host smart-d6a07af0-2413-48ea-a2dc-891dfb5736aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39125652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.39125652
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4149056253
Short name T738
Test name
Test status
Simulation time 449210401 ps
CPU time 2.55 seconds
Started Jul 01 06:31:47 PM PDT 24
Finished Jul 01 06:31:51 PM PDT 24
Peak memory 233768 kb
Host smart-167db68f-0811-4f1e-9aff-38a43686fb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149056253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4149056253
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2051996178
Short name T775
Test name
Test status
Simulation time 14192073 ps
CPU time 0.69 seconds
Started Jul 01 06:32:01 PM PDT 24
Finished Jul 01 06:32:04 PM PDT 24
Peak memory 205720 kb
Host smart-a46687d7-797e-4f7b-bbbd-ac9cf3f7320d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051996178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2051996178
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3613081351
Short name T1018
Test name
Test status
Simulation time 408580395 ps
CPU time 6.28 seconds
Started Jul 01 06:31:53 PM PDT 24
Finished Jul 01 06:32:00 PM PDT 24
Peak memory 225572 kb
Host smart-ac51420d-7a7e-49bc-8ec7-d5aa30829ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613081351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3613081351
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1745694713
Short name T934
Test name
Test status
Simulation time 73379429 ps
CPU time 0.77 seconds
Started Jul 01 06:31:55 PM PDT 24
Finished Jul 01 06:31:56 PM PDT 24
Peak memory 206508 kb
Host smart-03271146-6f19-40d0-8668-6a9e4f53b916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745694713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1745694713
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3997873425
Short name T889
Test name
Test status
Simulation time 8588649125 ps
CPU time 73.77 seconds
Started Jul 01 06:31:58 PM PDT 24
Finished Jul 01 06:33:14 PM PDT 24
Peak memory 250300 kb
Host smart-7a7fed48-0ebe-4380-8644-8e285bed20cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997873425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3997873425
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3071422634
Short name T766
Test name
Test status
Simulation time 24979628 ps
CPU time 0.83 seconds
Started Jul 01 06:31:57 PM PDT 24
Finished Jul 01 06:31:59 PM PDT 24
Peak memory 218208 kb
Host smart-d09d4306-506c-4703-a57f-37ca12e1bd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071422634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3071422634
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1229735491
Short name T304
Test name
Test status
Simulation time 38977286836 ps
CPU time 181.93 seconds
Started Jul 01 06:31:58 PM PDT 24
Finished Jul 01 06:35:02 PM PDT 24
Peak memory 251460 kb
Host smart-9b1d6f62-0d86-4f56-aa0b-d47c3507f464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229735491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1229735491
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3572169639
Short name T329
Test name
Test status
Simulation time 1347836277 ps
CPU time 10.09 seconds
Started Jul 01 06:32:01 PM PDT 24
Finished Jul 01 06:32:13 PM PDT 24
Peak memory 240784 kb
Host smart-2e0d26d0-2b54-4ff9-bdc3-4ee2e10bbebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572169639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3572169639
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1121795055
Short name T707
Test name
Test status
Simulation time 137486562726 ps
CPU time 251.39 seconds
Started Jul 01 06:31:58 PM PDT 24
Finished Jul 01 06:36:11 PM PDT 24
Peak memory 258592 kb
Host smart-14c9d6fb-8282-4069-9bea-794d25961874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121795055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1121795055
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3948329095
Short name T876
Test name
Test status
Simulation time 304093609 ps
CPU time 5.27 seconds
Started Jul 01 06:31:57 PM PDT 24
Finished Jul 01 06:32:03 PM PDT 24
Peak memory 233780 kb
Host smart-50efee2c-4ecf-44b8-b0a2-bbb9495c3a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948329095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3948329095
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2390729390
Short name T559
Test name
Test status
Simulation time 22051304228 ps
CPU time 54.74 seconds
Started Jul 01 06:31:51 PM PDT 24
Finished Jul 01 06:32:47 PM PDT 24
Peak memory 233900 kb
Host smart-41aedc59-7a66-4c81-b75c-2b8546c96887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390729390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2390729390
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4199466451
Short name T746
Test name
Test status
Simulation time 64890784 ps
CPU time 3.25 seconds
Started Jul 01 06:31:52 PM PDT 24
Finished Jul 01 06:31:55 PM PDT 24
Peak memory 233764 kb
Host smart-c50382a2-7c7f-4208-94f8-07878989756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199466451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4199466451
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1386233653
Short name T185
Test name
Test status
Simulation time 12943609958 ps
CPU time 21.05 seconds
Started Jul 01 06:31:52 PM PDT 24
Finished Jul 01 06:32:14 PM PDT 24
Peak memory 242048 kb
Host smart-5461103a-8e73-4759-85f7-1c9b47724022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386233653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1386233653
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1953610240
Short name T848
Test name
Test status
Simulation time 635725860 ps
CPU time 7.87 seconds
Started Jul 01 06:31:58 PM PDT 24
Finished Jul 01 06:32:07 PM PDT 24
Peak memory 223556 kb
Host smart-e1a7fe18-ca4b-4684-a681-0b23772a6e57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1953610240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1953610240
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.808144672
Short name T581
Test name
Test status
Simulation time 5682027731 ps
CPU time 20.81 seconds
Started Jul 01 06:31:52 PM PDT 24
Finished Jul 01 06:32:14 PM PDT 24
Peak memory 217520 kb
Host smart-097c51d9-c9ff-4db5-85d4-08f9c08ebca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808144672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.808144672
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3226699474
Short name T821
Test name
Test status
Simulation time 1201028474 ps
CPU time 3.16 seconds
Started Jul 01 06:31:54 PM PDT 24
Finished Jul 01 06:31:57 PM PDT 24
Peak memory 217388 kb
Host smart-c4d4c162-f5d5-446a-91fd-48b3b48ae15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226699474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3226699474
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3193594763
Short name T386
Test name
Test status
Simulation time 166812753 ps
CPU time 1.42 seconds
Started Jul 01 06:31:57 PM PDT 24
Finished Jul 01 06:31:59 PM PDT 24
Peak memory 209132 kb
Host smart-48d8f9ba-0126-49d5-b6a7-88bdbfedcaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193594763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3193594763
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2514191822
Short name T362
Test name
Test status
Simulation time 244878449 ps
CPU time 0.91 seconds
Started Jul 01 06:31:53 PM PDT 24
Finished Jul 01 06:31:55 PM PDT 24
Peak memory 207984 kb
Host smart-866f0083-bf7c-474f-988b-4d7054c54bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514191822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2514191822
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.612006082
Short name T447
Test name
Test status
Simulation time 49933782 ps
CPU time 2.32 seconds
Started Jul 01 06:31:52 PM PDT 24
Finished Jul 01 06:31:55 PM PDT 24
Peak memory 225264 kb
Host smart-52e8bc65-bc04-4324-aa73-b9785da6f529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612006082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.612006082
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1768689854
Short name T394
Test name
Test status
Simulation time 34108234 ps
CPU time 0.73 seconds
Started Jul 01 06:27:47 PM PDT 24
Finished Jul 01 06:27:48 PM PDT 24
Peak memory 206356 kb
Host smart-a099a8be-3f17-4713-8cab-b17ecbc512ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768689854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
768689854
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.4118589489
Short name T92
Test name
Test status
Simulation time 2518057230 ps
CPU time 9.33 seconds
Started Jul 01 06:27:48 PM PDT 24
Finished Jul 01 06:27:58 PM PDT 24
Peak memory 234976 kb
Host smart-c703392b-fd90-4751-9fb0-818e1ef2f7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118589489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4118589489
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1419764187
Short name T845
Test name
Test status
Simulation time 59719209 ps
CPU time 0.79 seconds
Started Jul 01 06:27:35 PM PDT 24
Finished Jul 01 06:27:37 PM PDT 24
Peak memory 206504 kb
Host smart-c069272f-f750-420d-9246-367e268fb9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419764187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1419764187
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2420920968
Short name T725
Test name
Test status
Simulation time 19602473 ps
CPU time 0.75 seconds
Started Jul 01 06:27:45 PM PDT 24
Finished Jul 01 06:27:47 PM PDT 24
Peak memory 216916 kb
Host smart-6db4de4c-6451-416e-b623-d5672aefeb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420920968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2420920968
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1112140048
Short name T819
Test name
Test status
Simulation time 8343622901 ps
CPU time 66.19 seconds
Started Jul 01 06:27:45 PM PDT 24
Finished Jul 01 06:28:52 PM PDT 24
Peak memory 242004 kb
Host smart-2592755c-7062-47aa-925a-9bb6f13fd2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112140048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1112140048
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1753498573
Short name T337
Test name
Test status
Simulation time 4663260584 ps
CPU time 47.39 seconds
Started Jul 01 06:27:46 PM PDT 24
Finished Jul 01 06:28:34 PM PDT 24
Peak memory 240956 kb
Host smart-a6406815-e262-42b9-8471-fb36d5f91a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753498573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1753498573
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2123094520
Short name T40
Test name
Test status
Simulation time 515549134 ps
CPU time 10.3 seconds
Started Jul 01 06:27:46 PM PDT 24
Finished Jul 01 06:27:57 PM PDT 24
Peak memory 225616 kb
Host smart-f5655cf3-f7dd-45d8-99c7-492e1b601b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123094520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2123094520
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2764975555
Short name T398
Test name
Test status
Simulation time 19389778 ps
CPU time 0.83 seconds
Started Jul 01 06:27:45 PM PDT 24
Finished Jul 01 06:27:46 PM PDT 24
Peak memory 216928 kb
Host smart-d7a85b62-d08c-4b50-bcc6-fa4bfa1e1135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764975555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2764975555
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1069280189
Short name T1024
Test name
Test status
Simulation time 531020928 ps
CPU time 6.83 seconds
Started Jul 01 06:27:40 PM PDT 24
Finished Jul 01 06:27:48 PM PDT 24
Peak memory 225556 kb
Host smart-70e0f9b9-3718-44fe-b5ed-138bc91731d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069280189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1069280189
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1135671188
Short name T230
Test name
Test status
Simulation time 32787361715 ps
CPU time 77.85 seconds
Started Jul 01 06:27:39 PM PDT 24
Finished Jul 01 06:28:58 PM PDT 24
Peak memory 242060 kb
Host smart-4a8f93a1-1d80-4682-afa0-42f54476d840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135671188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1135671188
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2668613291
Short name T513
Test name
Test status
Simulation time 27402403 ps
CPU time 0.98 seconds
Started Jul 01 06:27:35 PM PDT 24
Finished Jul 01 06:27:37 PM PDT 24
Peak memory 218848 kb
Host smart-bd01f572-84da-4659-8cd1-734ba7169b8d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668613291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2668613291
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2498191399
Short name T913
Test name
Test status
Simulation time 3906870413 ps
CPU time 14.07 seconds
Started Jul 01 06:27:41 PM PDT 24
Finished Jul 01 06:27:56 PM PDT 24
Peak memory 233984 kb
Host smart-01d22d97-9bf6-42f8-9c19-c6c51f0f16af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498191399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2498191399
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3307017489
Short name T187
Test name
Test status
Simulation time 1385851229 ps
CPU time 4.59 seconds
Started Jul 01 06:27:41 PM PDT 24
Finished Jul 01 06:27:46 PM PDT 24
Peak memory 225556 kb
Host smart-a026aee5-b438-4009-b088-826b6d3b07bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307017489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3307017489
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.159810382
Short name T484
Test name
Test status
Simulation time 8210552206 ps
CPU time 11.46 seconds
Started Jul 01 06:27:46 PM PDT 24
Finished Jul 01 06:27:59 PM PDT 24
Peak memory 224336 kb
Host smart-347d6420-4d2a-4cc8-ae76-ce216c144d35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=159810382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.159810382
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.820235685
Short name T183
Test name
Test status
Simulation time 198719539 ps
CPU time 1.05 seconds
Started Jul 01 06:27:45 PM PDT 24
Finished Jul 01 06:27:47 PM PDT 24
Peak memory 208728 kb
Host smart-309bb1ed-a75a-45da-99e0-eea49e31888c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820235685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.820235685
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4080088513
Short name T433
Test name
Test status
Simulation time 13357762815 ps
CPU time 20.63 seconds
Started Jul 01 06:27:34 PM PDT 24
Finished Jul 01 06:27:56 PM PDT 24
Peak memory 217640 kb
Host smart-a0bb08cd-7028-4cba-a202-8cff6e86ebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080088513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4080088513
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3646953761
Short name T104
Test name
Test status
Simulation time 29736609958 ps
CPU time 17.69 seconds
Started Jul 01 06:27:34 PM PDT 24
Finished Jul 01 06:27:53 PM PDT 24
Peak memory 217568 kb
Host smart-9251b31d-802b-4093-809b-84a1f4429a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646953761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3646953761
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.4229285817
Short name T743
Test name
Test status
Simulation time 299447291 ps
CPU time 1.48 seconds
Started Jul 01 06:27:35 PM PDT 24
Finished Jul 01 06:27:37 PM PDT 24
Peak memory 217356 kb
Host smart-14966218-74ae-4285-8108-eb21e0226ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229285817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4229285817
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.48292072
Short name T1020
Test name
Test status
Simulation time 27190141 ps
CPU time 0.81 seconds
Started Jul 01 06:27:38 PM PDT 24
Finished Jul 01 06:27:39 PM PDT 24
Peak memory 206980 kb
Host smart-7f35efe3-63b7-414a-bd67-d99c2cb10bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48292072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.48292072
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3602168924
Short name T273
Test name
Test status
Simulation time 9972067038 ps
CPU time 7 seconds
Started Jul 01 06:27:45 PM PDT 24
Finished Jul 01 06:27:52 PM PDT 24
Peak memory 234000 kb
Host smart-bed15ee8-3bbc-4267-8ce9-51e80d294bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602168924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3602168924
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2936276935
Short name T627
Test name
Test status
Simulation time 40597717 ps
CPU time 0.7 seconds
Started Jul 01 06:32:12 PM PDT 24
Finished Jul 01 06:32:14 PM PDT 24
Peak memory 205816 kb
Host smart-1dab6330-3953-429b-8eee-49160f869153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936276935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2936276935
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2961781972
Short name T677
Test name
Test status
Simulation time 6101348647 ps
CPU time 22.28 seconds
Started Jul 01 06:32:04 PM PDT 24
Finished Jul 01 06:32:28 PM PDT 24
Peak memory 225644 kb
Host smart-e48cb400-23df-4d83-8ab5-9694f41f23ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961781972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2961781972
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1395147058
Short name T12
Test name
Test status
Simulation time 22441107 ps
CPU time 0.92 seconds
Started Jul 01 06:31:58 PM PDT 24
Finished Jul 01 06:32:01 PM PDT 24
Peak memory 207520 kb
Host smart-58747769-5aa8-4ab8-be2d-9403e3a45ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395147058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1395147058
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1137337815
Short name T1012
Test name
Test status
Simulation time 431378496 ps
CPU time 8.98 seconds
Started Jul 01 06:32:04 PM PDT 24
Finished Jul 01 06:32:15 PM PDT 24
Peak memory 225628 kb
Host smart-6b48988e-2415-48f5-91bb-5d44c3744e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137337815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1137337815
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2013247995
Short name T555
Test name
Test status
Simulation time 1852956052 ps
CPU time 53.65 seconds
Started Jul 01 06:32:09 PM PDT 24
Finished Jul 01 06:33:04 PM PDT 24
Peak memory 250348 kb
Host smart-c7c2623d-1c46-43a9-b192-85937c58e7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013247995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2013247995
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2310820488
Short name T786
Test name
Test status
Simulation time 8390536513 ps
CPU time 57.86 seconds
Started Jul 01 06:32:10 PM PDT 24
Finished Jul 01 06:33:09 PM PDT 24
Peak memory 257380 kb
Host smart-1e7e348e-3185-40a3-b95d-04ea95dd9358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310820488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2310820488
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1387950063
Short name T457
Test name
Test status
Simulation time 3564170236 ps
CPU time 16.06 seconds
Started Jul 01 06:32:04 PM PDT 24
Finished Jul 01 06:32:22 PM PDT 24
Peak memory 225832 kb
Host smart-eb0e05cc-c0b4-4668-9567-fafe158d42f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387950063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1387950063
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.4093348921
Short name T241
Test name
Test status
Simulation time 45606900982 ps
CPU time 236.94 seconds
Started Jul 01 06:32:05 PM PDT 24
Finished Jul 01 06:36:04 PM PDT 24
Peak memory 254164 kb
Host smart-d90c85aa-3dac-4f86-8ddc-92fce9f287c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093348921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.4093348921
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2017892956
Short name T834
Test name
Test status
Simulation time 535075559 ps
CPU time 5.36 seconds
Started Jul 01 06:32:04 PM PDT 24
Finished Jul 01 06:32:12 PM PDT 24
Peak memory 233736 kb
Host smart-71d992b8-fb9e-4aa4-98fb-021bc9e854b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017892956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2017892956
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2586769255
Short name T948
Test name
Test status
Simulation time 3938235347 ps
CPU time 4.44 seconds
Started Jul 01 06:32:02 PM PDT 24
Finished Jul 01 06:32:09 PM PDT 24
Peak memory 225688 kb
Host smart-5d253e27-3811-46ba-9131-ff781fcd622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586769255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2586769255
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4179201238
Short name T305
Test name
Test status
Simulation time 429742966 ps
CPU time 4.3 seconds
Started Jul 01 06:32:05 PM PDT 24
Finished Jul 01 06:32:12 PM PDT 24
Peak memory 233796 kb
Host smart-94198189-78e6-4b19-ad10-228a4037e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179201238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4179201238
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.621214565
Short name T732
Test name
Test status
Simulation time 2854649242 ps
CPU time 7.43 seconds
Started Jul 01 06:32:03 PM PDT 24
Finished Jul 01 06:32:12 PM PDT 24
Peak memory 241760 kb
Host smart-d9dac4b3-ce73-49cf-9e57-00d5a0fb51be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621214565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.621214565
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2222472659
Short name T450
Test name
Test status
Simulation time 2438200154 ps
CPU time 15.5 seconds
Started Jul 01 06:32:01 PM PDT 24
Finished Jul 01 06:32:19 PM PDT 24
Peak memory 223220 kb
Host smart-b8c3a0e8-3919-48ff-bcef-b59abcc7c716
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2222472659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2222472659
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2683273431
Short name T311
Test name
Test status
Simulation time 101754524022 ps
CPU time 734.65 seconds
Started Jul 01 06:32:11 PM PDT 24
Finished Jul 01 06:44:27 PM PDT 24
Peak memory 274360 kb
Host smart-7b802c71-b9ca-4fd3-baed-e79ec8e07d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683273431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2683273431
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.577370256
Short name T668
Test name
Test status
Simulation time 2039353882 ps
CPU time 4.16 seconds
Started Jul 01 06:32:00 PM PDT 24
Finished Jul 01 06:32:05 PM PDT 24
Peak memory 217320 kb
Host smart-0762da81-dd7e-4e49-a37c-4a3dd80bc71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577370256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.577370256
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2359407269
Short name T29
Test name
Test status
Simulation time 6474275926 ps
CPU time 3.17 seconds
Started Jul 01 06:31:58 PM PDT 24
Finished Jul 01 06:32:03 PM PDT 24
Peak memory 217484 kb
Host smart-1f19c9f4-02a0-4347-acfb-e41d383661bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359407269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2359407269
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3068684943
Short name T412
Test name
Test status
Simulation time 1730220360 ps
CPU time 1.64 seconds
Started Jul 01 06:32:01 PM PDT 24
Finished Jul 01 06:32:04 PM PDT 24
Peak memory 217236 kb
Host smart-56d17446-d0c9-489e-8412-d1c112d81aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068684943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3068684943
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1802011488
Short name T873
Test name
Test status
Simulation time 247039484 ps
CPU time 0.97 seconds
Started Jul 01 06:32:00 PM PDT 24
Finished Jul 01 06:32:02 PM PDT 24
Peak memory 207896 kb
Host smart-d00c5f0b-183b-4fd3-85ed-4458d92f23c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802011488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1802011488
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3199319308
Short name T601
Test name
Test status
Simulation time 198270682 ps
CPU time 2.32 seconds
Started Jul 01 06:32:04 PM PDT 24
Finished Jul 01 06:32:08 PM PDT 24
Peak memory 225588 kb
Host smart-719e8a4e-be3a-4caf-9a83-fdaf4a4cef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199319308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3199319308
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2042342406
Short name T355
Test name
Test status
Simulation time 40693308 ps
CPU time 0.74 seconds
Started Jul 01 06:32:16 PM PDT 24
Finished Jul 01 06:32:17 PM PDT 24
Peak memory 206368 kb
Host smart-001e988e-09c5-4dad-aea7-96eb54ab851c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042342406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2042342406
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.417463419
Short name T431
Test name
Test status
Simulation time 1036883350 ps
CPU time 11.08 seconds
Started Jul 01 06:32:15 PM PDT 24
Finished Jul 01 06:32:27 PM PDT 24
Peak memory 225576 kb
Host smart-56a1e8ba-eff9-49e1-9e3c-bf2abfcb63ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417463419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.417463419
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3937500384
Short name T793
Test name
Test status
Simulation time 76227694 ps
CPU time 0.78 seconds
Started Jul 01 06:32:10 PM PDT 24
Finished Jul 01 06:32:12 PM PDT 24
Peak memory 207820 kb
Host smart-6caa13c9-2346-47da-8d00-eed9c784f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937500384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3937500384
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2728727530
Short name T228
Test name
Test status
Simulation time 4895458055 ps
CPU time 103.45 seconds
Started Jul 01 06:32:16 PM PDT 24
Finished Jul 01 06:34:00 PM PDT 24
Peak memory 265620 kb
Host smart-7fa9a113-44a9-4740-a447-01c253dffe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728727530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2728727530
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1573701618
Short name T314
Test name
Test status
Simulation time 19688147564 ps
CPU time 88.98 seconds
Started Jul 01 06:32:16 PM PDT 24
Finished Jul 01 06:33:47 PM PDT 24
Peak memory 252736 kb
Host smart-c3a01466-64f7-4a5d-b94b-b40d79ff9501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573701618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1573701618
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3133126874
Short name T994
Test name
Test status
Simulation time 4186160746 ps
CPU time 87.38 seconds
Started Jul 01 06:32:18 PM PDT 24
Finished Jul 01 06:33:47 PM PDT 24
Peak memory 274592 kb
Host smart-3920fd8f-5758-4107-b139-be6da0c82485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133126874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3133126874
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4058331370
Short name T136
Test name
Test status
Simulation time 1268399717 ps
CPU time 6.54 seconds
Started Jul 01 06:32:10 PM PDT 24
Finished Jul 01 06:32:18 PM PDT 24
Peak memory 236788 kb
Host smart-a2de727c-814f-4803-95ef-3ba41228ffaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058331370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4058331370
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1365948383
Short name T921
Test name
Test status
Simulation time 3093315346 ps
CPU time 16.06 seconds
Started Jul 01 06:32:10 PM PDT 24
Finished Jul 01 06:32:28 PM PDT 24
Peak memory 233928 kb
Host smart-f0831f02-8bd8-44f6-9ee5-8684f9c8e4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365948383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1365948383
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2234937680
Short name T219
Test name
Test status
Simulation time 2901347136 ps
CPU time 9.06 seconds
Started Jul 01 06:32:12 PM PDT 24
Finished Jul 01 06:32:22 PM PDT 24
Peak memory 225668 kb
Host smart-16380952-9719-4f49-95c3-c9784f51fac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234937680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2234937680
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.133316291
Short name T491
Test name
Test status
Simulation time 1093844020 ps
CPU time 12.17 seconds
Started Jul 01 06:32:13 PM PDT 24
Finished Jul 01 06:32:26 PM PDT 24
Peak memory 241904 kb
Host smart-5837c614-8111-4068-854e-83a897a5e17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133316291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.133316291
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.188129265
Short name T500
Test name
Test status
Simulation time 308521533 ps
CPU time 4.69 seconds
Started Jul 01 06:32:13 PM PDT 24
Finished Jul 01 06:32:18 PM PDT 24
Peak memory 225496 kb
Host smart-448e1232-eadd-4153-a574-1d11352ca2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188129265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.188129265
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4289337834
Short name T591
Test name
Test status
Simulation time 991340352 ps
CPU time 8 seconds
Started Jul 01 06:32:11 PM PDT 24
Finished Jul 01 06:32:21 PM PDT 24
Peak memory 219856 kb
Host smart-998551e9-15f5-465f-933d-7ceaaa272d4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4289337834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4289337834
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2266755324
Short name T17
Test name
Test status
Simulation time 86751191 ps
CPU time 1.23 seconds
Started Jul 01 06:32:16 PM PDT 24
Finished Jul 01 06:32:19 PM PDT 24
Peak memory 207860 kb
Host smart-95db5843-fa38-439e-b74d-ee0b78692532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266755324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2266755324
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.792097751
Short name T67
Test name
Test status
Simulation time 9229877039 ps
CPU time 42.67 seconds
Started Jul 01 06:32:10 PM PDT 24
Finished Jul 01 06:32:54 PM PDT 24
Peak memory 217512 kb
Host smart-dff9f381-9b5e-44fb-ad64-a1eb2511c5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792097751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.792097751
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3571641471
Short name T895
Test name
Test status
Simulation time 592904044 ps
CPU time 1.48 seconds
Started Jul 01 06:32:09 PM PDT 24
Finished Jul 01 06:32:11 PM PDT 24
Peak memory 208052 kb
Host smart-2ee14378-053e-44df-a138-29b4bb206601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571641471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3571641471
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1914113635
Short name T763
Test name
Test status
Simulation time 321564948 ps
CPU time 2.59 seconds
Started Jul 01 06:32:13 PM PDT 24
Finished Jul 01 06:32:16 PM PDT 24
Peak memory 217392 kb
Host smart-3d01c2b7-fb39-44a9-83d7-105e96bceb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914113635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1914113635
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2982893290
Short name T504
Test name
Test status
Simulation time 24097209 ps
CPU time 0.76 seconds
Started Jul 01 06:32:10 PM PDT 24
Finished Jul 01 06:32:12 PM PDT 24
Peak memory 206964 kb
Host smart-a8882619-4718-4dfe-aa2e-5ab701ca8479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982893290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2982893290
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3939974729
Short name T930
Test name
Test status
Simulation time 2326568209 ps
CPU time 11.15 seconds
Started Jul 01 06:32:10 PM PDT 24
Finished Jul 01 06:32:23 PM PDT 24
Peak memory 241488 kb
Host smart-8994ff25-9487-4cde-875d-bfd14bcf8896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939974729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3939974729
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2575147901
Short name T757
Test name
Test status
Simulation time 50961042 ps
CPU time 0.72 seconds
Started Jul 01 06:32:22 PM PDT 24
Finished Jul 01 06:32:24 PM PDT 24
Peak memory 205804 kb
Host smart-f8e925e8-3fdf-43c0-a27a-beb7fb4ab168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575147901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2575147901
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2793824610
Short name T565
Test name
Test status
Simulation time 130090940 ps
CPU time 3.4 seconds
Started Jul 01 06:32:24 PM PDT 24
Finished Jul 01 06:32:28 PM PDT 24
Peak memory 225584 kb
Host smart-3b0c0675-d7d2-4cb2-8d89-3df0abe6bdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793824610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2793824610
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.700792798
Short name T492
Test name
Test status
Simulation time 19802834 ps
CPU time 0.8 seconds
Started Jul 01 06:32:16 PM PDT 24
Finished Jul 01 06:32:19 PM PDT 24
Peak memory 207492 kb
Host smart-e4f4ea8b-291c-41d0-b8a7-1a9bcee91260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700792798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.700792798
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3656615572
Short name T992
Test name
Test status
Simulation time 669391223 ps
CPU time 14.09 seconds
Started Jul 01 06:32:22 PM PDT 24
Finished Jul 01 06:32:37 PM PDT 24
Peak memory 241592 kb
Host smart-1e606ec0-8539-450d-98bd-72f9d4a0a628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656615572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3656615572
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.12793992
Short name T284
Test name
Test status
Simulation time 63319114554 ps
CPU time 138.27 seconds
Started Jul 01 06:32:21 PM PDT 24
Finished Jul 01 06:34:40 PM PDT 24
Peak memory 250316 kb
Host smart-15dc2cde-b993-48e1-81e5-73c634181653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12793992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.12793992
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1765352657
Short name T213
Test name
Test status
Simulation time 23764182019 ps
CPU time 117.6 seconds
Started Jul 01 06:32:21 PM PDT 24
Finished Jul 01 06:34:19 PM PDT 24
Peak memory 257288 kb
Host smart-720121ed-f0dc-4172-9b8a-cfd92345a17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765352657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1765352657
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2137711287
Short name T636
Test name
Test status
Simulation time 1429196542 ps
CPU time 9.33 seconds
Started Jul 01 06:32:23 PM PDT 24
Finished Jul 01 06:32:33 PM PDT 24
Peak memory 242120 kb
Host smart-8d392211-875a-4b20-b9fc-c6a13e5e30ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137711287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2137711287
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.878328770
Short name T106
Test name
Test status
Simulation time 9824845417 ps
CPU time 70.17 seconds
Started Jul 01 06:32:24 PM PDT 24
Finished Jul 01 06:33:35 PM PDT 24
Peak memory 239348 kb
Host smart-16d54224-7536-4ad3-82ce-9d1e1d149ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878328770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.878328770
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3634276116
Short name T427
Test name
Test status
Simulation time 268500276 ps
CPU time 6.04 seconds
Started Jul 01 06:32:18 PM PDT 24
Finished Jul 01 06:32:25 PM PDT 24
Peak memory 233900 kb
Host smart-1d4707bd-4b33-4322-86ea-4c2b0eb6b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634276116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3634276116
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.801985508
Short name T949
Test name
Test status
Simulation time 4517603408 ps
CPU time 39.77 seconds
Started Jul 01 06:32:15 PM PDT 24
Finished Jul 01 06:32:56 PM PDT 24
Peak memory 241400 kb
Host smart-e2899470-8c86-45d5-a1c9-d9b7fe2737c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801985508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.801985508
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1774905750
Short name T244
Test name
Test status
Simulation time 835326019 ps
CPU time 6.57 seconds
Started Jul 01 06:32:18 PM PDT 24
Finished Jul 01 06:32:25 PM PDT 24
Peak memory 233880 kb
Host smart-c0277d0d-d951-4d79-8196-db7f80bf903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774905750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1774905750
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2544870613
Short name T629
Test name
Test status
Simulation time 778293348 ps
CPU time 5.52 seconds
Started Jul 01 06:32:17 PM PDT 24
Finished Jul 01 06:32:24 PM PDT 24
Peak memory 225656 kb
Host smart-164e3165-465b-453f-8b0c-ac66b2acbecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544870613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2544870613
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2507552858
Short name T359
Test name
Test status
Simulation time 153577484 ps
CPU time 3.6 seconds
Started Jul 01 06:32:23 PM PDT 24
Finished Jul 01 06:32:27 PM PDT 24
Peak memory 220352 kb
Host smart-d86350c1-5de9-4f7c-ae1a-5f9ae8ee0422
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2507552858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2507552858
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3464102106
Short name T174
Test name
Test status
Simulation time 54262011 ps
CPU time 1.07 seconds
Started Jul 01 06:32:24 PM PDT 24
Finished Jul 01 06:32:26 PM PDT 24
Peak memory 208728 kb
Host smart-412ca7a4-39ea-44f3-90af-e42e1541d38b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464102106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3464102106
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1943258474
Short name T338
Test name
Test status
Simulation time 2491058871 ps
CPU time 6.01 seconds
Started Jul 01 06:32:17 PM PDT 24
Finished Jul 01 06:32:25 PM PDT 24
Peak memory 217484 kb
Host smart-69088c71-a91e-4d35-95b3-06f54d14554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943258474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1943258474
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3914016969
Short name T885
Test name
Test status
Simulation time 5047136875 ps
CPU time 9 seconds
Started Jul 01 06:32:18 PM PDT 24
Finished Jul 01 06:32:28 PM PDT 24
Peak memory 217500 kb
Host smart-95364f57-ebfb-4086-a768-baace17ebebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914016969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3914016969
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1330009320
Short name T381
Test name
Test status
Simulation time 515941141 ps
CPU time 1.15 seconds
Started Jul 01 06:32:17 PM PDT 24
Finished Jul 01 06:32:20 PM PDT 24
Peak memory 208908 kb
Host smart-4ad0605b-224b-4276-b1c3-78647d275676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330009320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1330009320
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3875052471
Short name T611
Test name
Test status
Simulation time 91312145 ps
CPU time 0.78 seconds
Started Jul 01 06:32:15 PM PDT 24
Finished Jul 01 06:32:16 PM PDT 24
Peak memory 206996 kb
Host smart-b8bf3e83-cfcf-4a3c-a8e1-66bf355587d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875052471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3875052471
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.559718844
Short name T259
Test name
Test status
Simulation time 9542754184 ps
CPU time 17.03 seconds
Started Jul 01 06:32:17 PM PDT 24
Finished Jul 01 06:32:35 PM PDT 24
Peak memory 249484 kb
Host smart-edd147fd-a3ba-4488-b3ec-d7d8fd29adc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559718844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.559718844
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3715916336
Short name T391
Test name
Test status
Simulation time 25903277 ps
CPU time 0.74 seconds
Started Jul 01 06:32:29 PM PDT 24
Finished Jul 01 06:32:31 PM PDT 24
Peak memory 206404 kb
Host smart-4693cb38-14f5-4e19-a2b9-2ef84feb0bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715916336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3715916336
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2242922547
Short name T295
Test name
Test status
Simulation time 687131867 ps
CPU time 2.57 seconds
Started Jul 01 06:32:29 PM PDT 24
Finished Jul 01 06:32:33 PM PDT 24
Peak memory 225620 kb
Host smart-c4003322-b126-47d5-90ba-991a4e11d0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242922547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2242922547
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1067818640
Short name T501
Test name
Test status
Simulation time 76139807 ps
CPU time 0.77 seconds
Started Jul 01 06:32:22 PM PDT 24
Finished Jul 01 06:32:24 PM PDT 24
Peak memory 207516 kb
Host smart-0471e14c-284c-4da3-bc30-a0070c6a7a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067818640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1067818640
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3738276200
Short name T315
Test name
Test status
Simulation time 19067451225 ps
CPU time 59 seconds
Started Jul 01 06:32:29 PM PDT 24
Finished Jul 01 06:33:29 PM PDT 24
Peak memory 255272 kb
Host smart-f476738a-7fe4-4020-a19b-b62e7a102131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738276200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3738276200
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.652967374
Short name T956
Test name
Test status
Simulation time 24201097899 ps
CPU time 116.09 seconds
Started Jul 01 06:32:29 PM PDT 24
Finished Jul 01 06:34:27 PM PDT 24
Peak memory 226088 kb
Host smart-bf402922-d0d7-4de1-a416-d3c2f9f1cdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652967374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.652967374
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3171892055
Short name T931
Test name
Test status
Simulation time 8223581119 ps
CPU time 118.64 seconds
Started Jul 01 06:32:27 PM PDT 24
Finished Jul 01 06:34:27 PM PDT 24
Peak memory 252396 kb
Host smart-88f71ff5-7d6d-4bdb-af2d-000cf8524d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171892055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3171892055
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4034812835
Short name T958
Test name
Test status
Simulation time 13127853848 ps
CPU time 38.49 seconds
Started Jul 01 06:32:26 PM PDT 24
Finished Jul 01 06:33:06 PM PDT 24
Peak memory 250280 kb
Host smart-bce51bd9-d307-40be-b278-4ca47dd5dbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034812835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4034812835
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1037431736
Short name T468
Test name
Test status
Simulation time 58781610 ps
CPU time 0.83 seconds
Started Jul 01 06:32:31 PM PDT 24
Finished Jul 01 06:32:32 PM PDT 24
Peak memory 217180 kb
Host smart-b0c96b6d-99b3-4294-a216-b963304ff7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037431736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1037431736
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3114079760
Short name T1027
Test name
Test status
Simulation time 213166953 ps
CPU time 5.56 seconds
Started Jul 01 06:32:29 PM PDT 24
Finished Jul 01 06:32:35 PM PDT 24
Peak memory 233964 kb
Host smart-1d317f52-d830-4434-a945-fa47a3e8834d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114079760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3114079760
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3376358538
Short name T835
Test name
Test status
Simulation time 346438245 ps
CPU time 7.45 seconds
Started Jul 01 06:32:29 PM PDT 24
Finished Jul 01 06:32:37 PM PDT 24
Peak memory 233732 kb
Host smart-8aad43fa-2f9c-47cc-8dca-5d74f0a2b3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376358538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3376358538
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3672737618
Short name T820
Test name
Test status
Simulation time 426086183 ps
CPU time 7.38 seconds
Started Jul 01 06:32:20 PM PDT 24
Finished Jul 01 06:32:28 PM PDT 24
Peak memory 233812 kb
Host smart-1485ba0f-305e-4ffc-ab0d-d0b237afd498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672737618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3672737618
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1110755701
Short name T294
Test name
Test status
Simulation time 231571205 ps
CPU time 2.69 seconds
Started Jul 01 06:32:20 PM PDT 24
Finished Jul 01 06:32:24 PM PDT 24
Peak memory 225584 kb
Host smart-0b93d173-17b6-450a-866c-19186e089819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110755701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1110755701
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1234020362
Short name T838
Test name
Test status
Simulation time 309991842 ps
CPU time 4.04 seconds
Started Jul 01 06:32:28 PM PDT 24
Finished Jul 01 06:32:33 PM PDT 24
Peak memory 224208 kb
Host smart-8a561ca9-b7f9-4c9b-88f4-9e66fd99f9e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1234020362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1234020362
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2283120510
Short name T317
Test name
Test status
Simulation time 15767900080 ps
CPU time 167.95 seconds
Started Jul 01 06:32:28 PM PDT 24
Finished Jul 01 06:35:17 PM PDT 24
Peak memory 251472 kb
Host smart-5c525f98-46e4-462f-990a-237cb7c7b0c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283120510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2283120510
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1090105413
Short name T476
Test name
Test status
Simulation time 39770527080 ps
CPU time 40.94 seconds
Started Jul 01 06:32:24 PM PDT 24
Finished Jul 01 06:33:06 PM PDT 24
Peak memory 217552 kb
Host smart-caa0c839-2f65-4107-83d2-03c759de2f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090105413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1090105413
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2762217899
Short name T957
Test name
Test status
Simulation time 9603269895 ps
CPU time 5.98 seconds
Started Jul 01 06:32:24 PM PDT 24
Finished Jul 01 06:32:31 PM PDT 24
Peak memory 217440 kb
Host smart-0d834832-25ed-4123-ac6a-3b2c93907556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762217899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2762217899
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4100506670
Short name T78
Test name
Test status
Simulation time 30999958 ps
CPU time 1.34 seconds
Started Jul 01 06:32:21 PM PDT 24
Finished Jul 01 06:32:23 PM PDT 24
Peak memory 217340 kb
Host smart-8115e55a-aeff-4b6b-ab3e-e64ea977d989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100506670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4100506670
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.47383651
Short name T742
Test name
Test status
Simulation time 37952649 ps
CPU time 0.78 seconds
Started Jul 01 06:32:21 PM PDT 24
Finished Jul 01 06:32:23 PM PDT 24
Peak memory 207136 kb
Host smart-f87e2882-4015-463e-b248-ae649a35c52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47383651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.47383651
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3832765532
Short name T858
Test name
Test status
Simulation time 390688749 ps
CPU time 5.18 seconds
Started Jul 01 06:32:28 PM PDT 24
Finished Jul 01 06:32:35 PM PDT 24
Peak memory 225612 kb
Host smart-09eb5eb3-bcbe-4253-9e5c-396eb19449f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832765532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3832765532
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2157139411
Short name T91
Test name
Test status
Simulation time 15994117 ps
CPU time 0.74 seconds
Started Jul 01 06:32:44 PM PDT 24
Finished Jul 01 06:32:46 PM PDT 24
Peak memory 206644 kb
Host smart-f662112b-c704-4d36-a18d-3f2d4591e005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157139411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2157139411
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3039499291
Short name T664
Test name
Test status
Simulation time 95598313 ps
CPU time 2.3 seconds
Started Jul 01 06:32:33 PM PDT 24
Finished Jul 01 06:32:36 PM PDT 24
Peak memory 225528 kb
Host smart-75308400-6731-4a4a-83f8-1512e82c9fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039499291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3039499291
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2763409033
Short name T777
Test name
Test status
Simulation time 22506148 ps
CPU time 0.82 seconds
Started Jul 01 06:32:36 PM PDT 24
Finished Jul 01 06:32:39 PM PDT 24
Peak memory 207528 kb
Host smart-f36ad7a5-a39d-4ff9-aaf3-ffb4c77302a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763409033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2763409033
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3044585335
Short name T253
Test name
Test status
Simulation time 30994956144 ps
CPU time 90.75 seconds
Started Jul 01 06:32:33 PM PDT 24
Finished Jul 01 06:34:05 PM PDT 24
Peak memory 253540 kb
Host smart-d09405c4-ede6-466b-ba1e-8d69510397e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044585335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3044585335
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2943405624
Short name T955
Test name
Test status
Simulation time 981552629 ps
CPU time 23.34 seconds
Started Jul 01 06:32:35 PM PDT 24
Finished Jul 01 06:33:00 PM PDT 24
Peak memory 225672 kb
Host smart-3bf1f567-6b63-464e-8f60-5d5acd33a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943405624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2943405624
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3287566679
Short name T870
Test name
Test status
Simulation time 7149212166 ps
CPU time 24.63 seconds
Started Jul 01 06:32:35 PM PDT 24
Finished Jul 01 06:33:01 PM PDT 24
Peak memory 218856 kb
Host smart-c46320b8-57c2-4cfa-8511-9a9c5219b5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287566679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3287566679
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2753782833
Short name T154
Test name
Test status
Simulation time 134504306 ps
CPU time 7.2 seconds
Started Jul 01 06:32:35 PM PDT 24
Finished Jul 01 06:32:44 PM PDT 24
Peak memory 241996 kb
Host smart-0c9504fc-f897-4628-844d-10c69bc36808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753782833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2753782833
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3527392302
Short name T981
Test name
Test status
Simulation time 2593623024 ps
CPU time 29.08 seconds
Started Jul 01 06:32:36 PM PDT 24
Finished Jul 01 06:33:07 PM PDT 24
Peak memory 251164 kb
Host smart-6ecfd258-c471-4d82-a4ab-7685be9dc0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527392302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3527392302
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1020926278
Short name T734
Test name
Test status
Simulation time 415548774 ps
CPU time 4.09 seconds
Started Jul 01 06:32:34 PM PDT 24
Finished Jul 01 06:32:39 PM PDT 24
Peak memory 225516 kb
Host smart-171a9337-820e-4057-92ab-3072b2395d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020926278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1020926278
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4111506095
Short name T27
Test name
Test status
Simulation time 4451090903 ps
CPU time 28.87 seconds
Started Jul 01 06:32:37 PM PDT 24
Finished Jul 01 06:33:07 PM PDT 24
Peak memory 233776 kb
Host smart-d9ab2e88-66a0-4105-8530-364508c60a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111506095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4111506095
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1282398767
Short name T292
Test name
Test status
Simulation time 6369039563 ps
CPU time 7.83 seconds
Started Jul 01 06:32:34 PM PDT 24
Finished Jul 01 06:32:44 PM PDT 24
Peak memory 233916 kb
Host smart-fec2aee8-1fee-421a-802d-804cca4a7263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282398767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1282398767
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2071516542
Short name T233
Test name
Test status
Simulation time 21107790423 ps
CPU time 21.97 seconds
Started Jul 01 06:32:36 PM PDT 24
Finished Jul 01 06:33:00 PM PDT 24
Peak memory 250332 kb
Host smart-f2779e79-a0df-41b1-9542-e3daef35120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071516542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2071516542
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3589761168
Short name T988
Test name
Test status
Simulation time 1981401244 ps
CPU time 8 seconds
Started Jul 01 06:32:37 PM PDT 24
Finished Jul 01 06:32:47 PM PDT 24
Peak memory 222908 kb
Host smart-f103ce52-d229-461d-8ad7-afe537557309
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3589761168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3589761168
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2984351745
Short name T18
Test name
Test status
Simulation time 2811754226 ps
CPU time 65.71 seconds
Started Jul 01 06:32:41 PM PDT 24
Finished Jul 01 06:33:48 PM PDT 24
Peak memory 250480 kb
Host smart-2e02229c-860b-4bac-bac2-1f1a86962c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984351745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2984351745
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1140373566
Short name T339
Test name
Test status
Simulation time 2388427261 ps
CPU time 26.33 seconds
Started Jul 01 06:32:36 PM PDT 24
Finished Jul 01 06:33:04 PM PDT 24
Peak memory 220744 kb
Host smart-3dc19f4c-de36-4cf3-9bbb-da5d092f942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140373566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1140373566
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.990885726
Short name T715
Test name
Test status
Simulation time 20553584487 ps
CPU time 10.37 seconds
Started Jul 01 06:32:34 PM PDT 24
Finished Jul 01 06:32:46 PM PDT 24
Peak memory 217560 kb
Host smart-ea112a83-af8b-4289-8e68-e0d6eb52e0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990885726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.990885726
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.645441884
Short name T673
Test name
Test status
Simulation time 1380621970 ps
CPU time 2.21 seconds
Started Jul 01 06:32:37 PM PDT 24
Finished Jul 01 06:32:40 PM PDT 24
Peak memory 217368 kb
Host smart-0601aa43-3703-488e-9c2c-32487fe3adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645441884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.645441884
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2636152046
Short name T752
Test name
Test status
Simulation time 481797347 ps
CPU time 0.83 seconds
Started Jul 01 06:32:34 PM PDT 24
Finished Jul 01 06:32:36 PM PDT 24
Peak memory 206984 kb
Host smart-9d2cc58f-7b2c-4d28-870e-34b4281d94d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636152046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2636152046
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3567770877
Short name T16
Test name
Test status
Simulation time 5650811017 ps
CPU time 10.37 seconds
Started Jul 01 06:32:37 PM PDT 24
Finished Jul 01 06:32:49 PM PDT 24
Peak memory 225676 kb
Host smart-11445525-d9ad-411a-8b35-030ef4baefc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567770877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3567770877
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.209052863
Short name T464
Test name
Test status
Simulation time 47537300 ps
CPU time 0.72 seconds
Started Jul 01 06:32:50 PM PDT 24
Finished Jul 01 06:32:51 PM PDT 24
Peak memory 206736 kb
Host smart-2c0ab8f9-9519-48a9-be8e-c9766ea70802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209052863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.209052863
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.658497324
Short name T436
Test name
Test status
Simulation time 607381256 ps
CPU time 6.6 seconds
Started Jul 01 06:32:44 PM PDT 24
Finished Jul 01 06:32:52 PM PDT 24
Peak memory 225476 kb
Host smart-ae935009-216c-4936-a2f6-941239f9a820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658497324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.658497324
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1603364097
Short name T356
Test name
Test status
Simulation time 63154089 ps
CPU time 0.76 seconds
Started Jul 01 06:32:43 PM PDT 24
Finished Jul 01 06:32:44 PM PDT 24
Peak memory 206492 kb
Host smart-20e7c1e8-0a07-4c34-9af7-7d0a49b8a219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603364097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1603364097
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2993676459
Short name T184
Test name
Test status
Simulation time 12517088432 ps
CPU time 83.17 seconds
Started Jul 01 06:32:41 PM PDT 24
Finished Jul 01 06:34:05 PM PDT 24
Peak memory 242128 kb
Host smart-270e414b-f0d3-4617-8aa0-b667912e6a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993676459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2993676459
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2715741223
Short name T81
Test name
Test status
Simulation time 30566606364 ps
CPU time 315.2 seconds
Started Jul 01 06:32:43 PM PDT 24
Finished Jul 01 06:37:59 PM PDT 24
Peak memory 258388 kb
Host smart-d6bfb44a-a520-42a9-a471-9b0bd1076df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715741223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2715741223
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3283644543
Short name T588
Test name
Test status
Simulation time 3153727555 ps
CPU time 32.22 seconds
Started Jul 01 06:32:44 PM PDT 24
Finished Jul 01 06:33:17 PM PDT 24
Peak memory 218840 kb
Host smart-87841ce6-fa88-44d5-8401-29b00adf2c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283644543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3283644543
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.244048268
Short name T167
Test name
Test status
Simulation time 946695693 ps
CPU time 9.14 seconds
Started Jul 01 06:32:42 PM PDT 24
Finished Jul 01 06:32:52 PM PDT 24
Peak memory 233804 kb
Host smart-14f6ba46-03bb-4b7c-bba2-029c609861fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244048268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.244048268
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1274042010
Short name T445
Test name
Test status
Simulation time 6376219085 ps
CPU time 52.85 seconds
Started Jul 01 06:32:43 PM PDT 24
Finished Jul 01 06:33:37 PM PDT 24
Peak memory 250160 kb
Host smart-1bb10b76-07b3-4683-ba03-299fe31404e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274042010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1274042010
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3545831633
Short name T274
Test name
Test status
Simulation time 260708269 ps
CPU time 5.91 seconds
Started Jul 01 06:32:41 PM PDT 24
Finished Jul 01 06:32:48 PM PDT 24
Peak memory 233928 kb
Host smart-5a971263-9724-49a0-acc9-e8ce4c606134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545831633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3545831633
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3763379976
Short name T535
Test name
Test status
Simulation time 248930086 ps
CPU time 8.11 seconds
Started Jul 01 06:32:44 PM PDT 24
Finished Jul 01 06:32:53 PM PDT 24
Peak memory 241840 kb
Host smart-56235adf-a9b1-4656-9692-ad7d94f96660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763379976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3763379976
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3349528761
Short name T599
Test name
Test status
Simulation time 2995033021 ps
CPU time 9.93 seconds
Started Jul 01 06:32:45 PM PDT 24
Finished Jul 01 06:32:56 PM PDT 24
Peak memory 233832 kb
Host smart-cfb0d267-fdb7-4f65-ad76-6694e99c847b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349528761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3349528761
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.184790408
Short name T977
Test name
Test status
Simulation time 1680658650 ps
CPU time 7.34 seconds
Started Jul 01 06:32:41 PM PDT 24
Finished Jul 01 06:32:49 PM PDT 24
Peak memory 233848 kb
Host smart-9aac00c2-877d-4402-a7c8-be1c60c200b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184790408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.184790408
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3807271780
Short name T39
Test name
Test status
Simulation time 448011471 ps
CPU time 3.58 seconds
Started Jul 01 06:32:42 PM PDT 24
Finished Jul 01 06:32:46 PM PDT 24
Peak memory 221840 kb
Host smart-26c68ff2-e228-46ba-bdcf-c7e63658c29f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3807271780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3807271780
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1104191780
Short name T289
Test name
Test status
Simulation time 18245341894 ps
CPU time 54.8 seconds
Started Jul 01 06:32:42 PM PDT 24
Finished Jul 01 06:33:38 PM PDT 24
Peak memory 257544 kb
Host smart-6f6d2ae9-58f6-4caf-82a7-22e0fc5dfb5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104191780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1104191780
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.397368834
Short name T739
Test name
Test status
Simulation time 20426587685 ps
CPU time 48.65 seconds
Started Jul 01 06:32:42 PM PDT 24
Finished Jul 01 06:33:31 PM PDT 24
Peak memory 217680 kb
Host smart-c836ea75-9c0d-4ccc-8930-e8e73359f22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397368834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.397368834
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.504559999
Short name T352
Test name
Test status
Simulation time 63597983479 ps
CPU time 18.15 seconds
Started Jul 01 06:32:44 PM PDT 24
Finished Jul 01 06:33:03 PM PDT 24
Peak memory 217468 kb
Host smart-2465e50c-764d-4d71-98b1-6d1754c8a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504559999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.504559999
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2667239084
Short name T658
Test name
Test status
Simulation time 304585936 ps
CPU time 1.7 seconds
Started Jul 01 06:32:41 PM PDT 24
Finished Jul 01 06:32:44 PM PDT 24
Peak memory 217328 kb
Host smart-503ada97-ab19-4975-b4ee-c3fd4dabf0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667239084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2667239084
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4108282599
Short name T733
Test name
Test status
Simulation time 306209747 ps
CPU time 0.96 seconds
Started Jul 01 06:32:43 PM PDT 24
Finished Jul 01 06:32:45 PM PDT 24
Peak memory 207840 kb
Host smart-fb6775e0-b0f8-47cc-8888-6b0be096bf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108282599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4108282599
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1790588232
Short name T202
Test name
Test status
Simulation time 811373222 ps
CPU time 7.48 seconds
Started Jul 01 06:32:41 PM PDT 24
Finished Jul 01 06:32:50 PM PDT 24
Peak memory 233724 kb
Host smart-15d93971-8a3e-4fa1-99de-bc91080086e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790588232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1790588232
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3416546714
Short name T675
Test name
Test status
Simulation time 43570418 ps
CPU time 0.71 seconds
Started Jul 01 06:33:07 PM PDT 24
Finished Jul 01 06:33:10 PM PDT 24
Peak memory 205768 kb
Host smart-6476b9fb-3c7b-4078-a6dc-cdd50b0785a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416546714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3416546714
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1631106951
Short name T997
Test name
Test status
Simulation time 79859919 ps
CPU time 2.68 seconds
Started Jul 01 06:32:50 PM PDT 24
Finished Jul 01 06:32:54 PM PDT 24
Peak memory 233748 kb
Host smart-f694c78f-981d-4471-9bbe-09472df1db73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631106951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1631106951
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3127567794
Short name T373
Test name
Test status
Simulation time 58140529 ps
CPU time 0.8 seconds
Started Jul 01 06:32:53 PM PDT 24
Finished Jul 01 06:32:55 PM PDT 24
Peak memory 207536 kb
Host smart-5787b09c-9923-4829-a650-04d22ae1dc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127567794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3127567794
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.970888082
Short name T9
Test name
Test status
Simulation time 156314366 ps
CPU time 0.88 seconds
Started Jul 01 06:32:49 PM PDT 24
Finished Jul 01 06:32:51 PM PDT 24
Peak memory 217140 kb
Host smart-5f0e6c25-cb4a-479b-bd61-b5d5844120b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970888082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.970888082
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.201568994
Short name T822
Test name
Test status
Simulation time 110963406828 ps
CPU time 432.15 seconds
Started Jul 01 06:32:49 PM PDT 24
Finished Jul 01 06:40:01 PM PDT 24
Peak memory 256316 kb
Host smart-bb3bef20-78f0-4f4d-9c36-e5ea5439201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201568994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.201568994
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3622197936
Short name T158
Test name
Test status
Simulation time 14266838790 ps
CPU time 156.53 seconds
Started Jul 01 06:32:49 PM PDT 24
Finished Jul 01 06:35:26 PM PDT 24
Peak memory 266804 kb
Host smart-eb5faa77-5080-4a47-9d29-37540c8eb5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622197936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3622197936
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.4040729060
Short name T519
Test name
Test status
Simulation time 321029092 ps
CPU time 5.91 seconds
Started Jul 01 06:32:50 PM PDT 24
Finished Jul 01 06:32:56 PM PDT 24
Peak memory 225576 kb
Host smart-9011ae3f-e114-4768-bff3-1172a1e7de4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040729060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4040729060
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4140994906
Short name T307
Test name
Test status
Simulation time 193860326767 ps
CPU time 387.05 seconds
Started Jul 01 06:32:51 PM PDT 24
Finished Jul 01 06:39:19 PM PDT 24
Peak memory 274196 kb
Host smart-8e9503ce-7d25-4686-9a4e-67fee13892fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140994906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4140994906
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3089214360
Short name T585
Test name
Test status
Simulation time 1449564349 ps
CPU time 9.93 seconds
Started Jul 01 06:32:51 PM PDT 24
Finished Jul 01 06:33:02 PM PDT 24
Peak memory 225700 kb
Host smart-1d747a06-5d9a-4b93-a21b-373b6a54d905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089214360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3089214360
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2439922056
Short name T857
Test name
Test status
Simulation time 618078929 ps
CPU time 10.88 seconds
Started Jul 01 06:32:53 PM PDT 24
Finished Jul 01 06:33:05 PM PDT 24
Peak memory 239608 kb
Host smart-41927ada-b03d-49ea-88e1-3272823cd786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439922056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2439922056
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3084985804
Short name T316
Test name
Test status
Simulation time 1375005278 ps
CPU time 5.28 seconds
Started Jul 01 06:32:52 PM PDT 24
Finished Jul 01 06:32:58 PM PDT 24
Peak memory 233736 kb
Host smart-1143bef3-fea3-4620-abf4-e37fdb704c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084985804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3084985804
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2922749006
Short name T236
Test name
Test status
Simulation time 1060412688 ps
CPU time 6 seconds
Started Jul 01 06:32:50 PM PDT 24
Finished Jul 01 06:32:57 PM PDT 24
Peak memory 225552 kb
Host smart-0e6b77b1-c51d-4e72-ab51-524fee243f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922749006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2922749006
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3044510330
Short name T416
Test name
Test status
Simulation time 2207447728 ps
CPU time 17.42 seconds
Started Jul 01 06:32:52 PM PDT 24
Finished Jul 01 06:33:10 PM PDT 24
Peak memory 223160 kb
Host smart-00af9a0f-c6c6-4022-9281-982c56734445
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3044510330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3044510330
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2355303791
Short name T322
Test name
Test status
Simulation time 35696167747 ps
CPU time 350.25 seconds
Started Jul 01 06:32:57 PM PDT 24
Finished Jul 01 06:38:49 PM PDT 24
Peak memory 254632 kb
Host smart-6b731bbb-8104-41f2-bfd2-de87da1569d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355303791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2355303791
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3120426804
Short name T652
Test name
Test status
Simulation time 15227556216 ps
CPU time 28.96 seconds
Started Jul 01 06:32:51 PM PDT 24
Finished Jul 01 06:33:21 PM PDT 24
Peak memory 217484 kb
Host smart-ccdd5580-b70a-44c9-8f63-922f4b95fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120426804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3120426804
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.402899278
Short name T404
Test name
Test status
Simulation time 431146126 ps
CPU time 3.81 seconds
Started Jul 01 06:32:52 PM PDT 24
Finished Jul 01 06:32:57 PM PDT 24
Peak memory 217368 kb
Host smart-dc1d28d6-a42d-4c9a-9315-2e4f51e140e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402899278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.402899278
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1484653465
Short name T34
Test name
Test status
Simulation time 293869476 ps
CPU time 1.25 seconds
Started Jul 01 06:32:51 PM PDT 24
Finished Jul 01 06:32:53 PM PDT 24
Peak memory 217220 kb
Host smart-3cefbf50-a7ef-4511-a30d-39423f4c4ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484653465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1484653465
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4188677813
Short name T550
Test name
Test status
Simulation time 27464819 ps
CPU time 0.75 seconds
Started Jul 01 06:32:48 PM PDT 24
Finished Jul 01 06:32:50 PM PDT 24
Peak memory 206964 kb
Host smart-034abcda-76e4-4976-b67a-e68ac2d155e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188677813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4188677813
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1873618577
Short name T736
Test name
Test status
Simulation time 1431246829 ps
CPU time 6.95 seconds
Started Jul 01 06:32:49 PM PDT 24
Finished Jul 01 06:32:57 PM PDT 24
Peak memory 225628 kb
Host smart-ff8d4bbe-9d7e-4937-aa3d-b48b9711c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873618577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1873618577
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3646775245
Short name T552
Test name
Test status
Simulation time 53972418 ps
CPU time 0.69 seconds
Started Jul 01 06:32:57 PM PDT 24
Finished Jul 01 06:32:59 PM PDT 24
Peak memory 205840 kb
Host smart-51dabb18-5041-4550-94f9-45bb0fd0c48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646775245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3646775245
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2930697050
Short name T263
Test name
Test status
Simulation time 65494810 ps
CPU time 2.83 seconds
Started Jul 01 06:32:57 PM PDT 24
Finished Jul 01 06:33:02 PM PDT 24
Peak memory 233760 kb
Host smart-16adedd5-e804-4643-b35c-a5ddc6c811d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930697050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2930697050
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1401141149
Short name T444
Test name
Test status
Simulation time 16945299 ps
CPU time 0.78 seconds
Started Jul 01 06:33:02 PM PDT 24
Finished Jul 01 06:33:04 PM PDT 24
Peak memory 207908 kb
Host smart-67dd377a-dd3e-426f-9aa8-6827dba43864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401141149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1401141149
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3658903477
Short name T209
Test name
Test status
Simulation time 36782332375 ps
CPU time 252.93 seconds
Started Jul 01 06:33:00 PM PDT 24
Finished Jul 01 06:37:14 PM PDT 24
Peak memory 253384 kb
Host smart-9b3c527d-1729-4cee-9e3e-a6d2ef1a27e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658903477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3658903477
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3498593163
Short name T902
Test name
Test status
Simulation time 233409098 ps
CPU time 3.3 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:33:03 PM PDT 24
Peak memory 233932 kb
Host smart-17bc043b-e874-49e8-97a6-1323b6122b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498593163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3498593163
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3411288394
Short name T722
Test name
Test status
Simulation time 5259725186 ps
CPU time 27.57 seconds
Started Jul 01 06:33:07 PM PDT 24
Finished Jul 01 06:33:37 PM PDT 24
Peak memory 252772 kb
Host smart-bee12ee0-f8fe-4288-a5a8-2f7fe47f1e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411288394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3411288394
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3811488977
Short name T238
Test name
Test status
Simulation time 329120301 ps
CPU time 4.55 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:33:04 PM PDT 24
Peak memory 225532 kb
Host smart-e32a8e7f-2821-45d0-ae2c-a5c7b4ab79b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811488977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3811488977
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.203520201
Short name T679
Test name
Test status
Simulation time 832134623 ps
CPU time 10.95 seconds
Started Jul 01 06:33:07 PM PDT 24
Finished Jul 01 06:33:21 PM PDT 24
Peak memory 241532 kb
Host smart-cc164ac3-4bc7-448c-be37-e2383f95851a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203520201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.203520201
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2520119218
Short name T638
Test name
Test status
Simulation time 6134761571 ps
CPU time 7.4 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:33:07 PM PDT 24
Peak memory 225672 kb
Host smart-90d5d501-b415-44fe-b8a9-b0488bf9c70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520119218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2520119218
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.904592894
Short name T730
Test name
Test status
Simulation time 573378833 ps
CPU time 3.61 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:33:04 PM PDT 24
Peak memory 225544 kb
Host smart-33b8a8bb-7f4a-4855-84cf-a9ae83806afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904592894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.904592894
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3816955669
Short name T82
Test name
Test status
Simulation time 1549207241 ps
CPU time 6.47 seconds
Started Jul 01 06:32:57 PM PDT 24
Finished Jul 01 06:33:05 PM PDT 24
Peak memory 221156 kb
Host smart-14cc8129-f44b-4739-82e7-c6a2f8a7679f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3816955669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3816955669
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2727429953
Short name T178
Test name
Test status
Simulation time 81198091388 ps
CPU time 53.39 seconds
Started Jul 01 06:33:07 PM PDT 24
Finished Jul 01 06:34:03 PM PDT 24
Peak memory 242192 kb
Host smart-ab631090-ec16-4ab6-853b-bfc8092bcacf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727429953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2727429953
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1163128283
Short name T475
Test name
Test status
Simulation time 1238377917 ps
CPU time 7.77 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:33:07 PM PDT 24
Peak memory 217476 kb
Host smart-7828c76e-2ad8-4921-b199-8b0f074e9ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163128283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1163128283
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3130720458
Short name T537
Test name
Test status
Simulation time 1425796106 ps
CPU time 3.79 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:33:04 PM PDT 24
Peak memory 217372 kb
Host smart-dab46be6-7c72-47f8-8a9b-1d7362c78fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130720458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3130720458
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.429210791
Short name T351
Test name
Test status
Simulation time 422581405 ps
CPU time 2.64 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:33:02 PM PDT 24
Peak memory 217396 kb
Host smart-3aa9bfb2-bad2-4f39-96d3-e463229c294d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429210791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.429210791
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.277636064
Short name T962
Test name
Test status
Simulation time 164606229 ps
CPU time 0.85 seconds
Started Jul 01 06:33:03 PM PDT 24
Finished Jul 01 06:33:04 PM PDT 24
Peak memory 207048 kb
Host smart-471a6d6a-00f1-4c98-846a-dac542c4e089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277636064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.277636064
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3542979229
Short name T1001
Test name
Test status
Simulation time 7429867427 ps
CPU time 6.75 seconds
Started Jul 01 06:32:56 PM PDT 24
Finished Jul 01 06:33:04 PM PDT 24
Peak memory 229208 kb
Host smart-eddb666b-1cf5-437e-8e43-e89f3e7e2c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542979229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3542979229
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2252839386
Short name T620
Test name
Test status
Simulation time 30317942 ps
CPU time 0.7 seconds
Started Jul 01 06:33:07 PM PDT 24
Finished Jul 01 06:33:10 PM PDT 24
Peak memory 205720 kb
Host smart-545d2be4-e20b-4eec-85b7-7503118ceea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252839386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2252839386
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1988380834
Short name T503
Test name
Test status
Simulation time 199056392 ps
CPU time 2.33 seconds
Started Jul 01 06:33:06 PM PDT 24
Finished Jul 01 06:33:11 PM PDT 24
Peak memory 225564 kb
Host smart-f73fddc5-abfa-4b52-87a6-46c0965e9837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988380834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1988380834
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1338010733
Short name T785
Test name
Test status
Simulation time 21047458 ps
CPU time 0.84 seconds
Started Jul 01 06:32:57 PM PDT 24
Finished Jul 01 06:32:59 PM PDT 24
Peak memory 207520 kb
Host smart-f54ee5f3-627c-468b-a1aa-0bad0bf6795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338010733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1338010733
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.343257849
Short name T1008
Test name
Test status
Simulation time 28081847843 ps
CPU time 203.89 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:36:29 PM PDT 24
Peak memory 250524 kb
Host smart-caebbb66-42af-4e9b-9f76-5c6e20622e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343257849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.343257849
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1511097422
Short name T282
Test name
Test status
Simulation time 22377934035 ps
CPU time 253.91 seconds
Started Jul 01 06:33:06 PM PDT 24
Finished Jul 01 06:37:22 PM PDT 24
Peak memory 250476 kb
Host smart-1c34570e-7f36-4d71-905c-fec1e929d83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511097422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1511097422
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2545943878
Short name T692
Test name
Test status
Simulation time 887522142 ps
CPU time 4.14 seconds
Started Jul 01 06:33:05 PM PDT 24
Finished Jul 01 06:33:12 PM PDT 24
Peak memory 235036 kb
Host smart-43f90efb-1f08-4f4d-9d85-e22b45d31254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545943878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2545943878
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4124834096
Short name T197
Test name
Test status
Simulation time 3253079121 ps
CPU time 35.7 seconds
Started Jul 01 06:33:05 PM PDT 24
Finished Jul 01 06:33:43 PM PDT 24
Peak memory 239752 kb
Host smart-bfb897da-3ded-431a-ae0a-f4be6f034165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124834096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4124834096
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.32122100
Short name T806
Test name
Test status
Simulation time 626120779 ps
CPU time 7.69 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:33:07 PM PDT 24
Peak memory 233824 kb
Host smart-fa3cdc23-6c02-43e9-a7d8-dc13a29d1940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32122100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.32122100
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.134252790
Short name T11
Test name
Test status
Simulation time 5571804562 ps
CPU time 22.23 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:29 PM PDT 24
Peak memory 225692 kb
Host smart-8b751a6f-3849-4fc8-afa6-9b4f286ec3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134252790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.134252790
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1113484769
Short name T90
Test name
Test status
Simulation time 121516569 ps
CPU time 2.92 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:33:02 PM PDT 24
Peak memory 233720 kb
Host smart-cf82d5d8-1501-4e24-acf1-7363b34310d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113484769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1113484769
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2230528030
Short name T918
Test name
Test status
Simulation time 3698431019 ps
CPU time 7.55 seconds
Started Jul 01 06:32:57 PM PDT 24
Finished Jul 01 06:33:05 PM PDT 24
Peak memory 233872 kb
Host smart-224dd715-c841-42d7-905b-50918fc47e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230528030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2230528030
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.783750154
Short name T153
Test name
Test status
Simulation time 18548732195 ps
CPU time 15.08 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:21 PM PDT 24
Peak memory 224152 kb
Host smart-c906febc-c2b1-4067-a690-2f72ec7bb7cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=783750154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.783750154
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1541178735
Short name T946
Test name
Test status
Simulation time 46726763008 ps
CPU time 139.03 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:35:26 PM PDT 24
Peak memory 258604 kb
Host smart-e22e8bb5-a7dc-436f-a8f6-e5af9d8fe873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541178735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1541178735
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1754273382
Short name T760
Test name
Test status
Simulation time 3523685655 ps
CPU time 11 seconds
Started Jul 01 06:32:57 PM PDT 24
Finished Jul 01 06:33:09 PM PDT 24
Peak memory 217528 kb
Host smart-cf47a245-1b5a-4e13-a1ed-3699867fa0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754273382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1754273382
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.962398408
Short name T396
Test name
Test status
Simulation time 39911967 ps
CPU time 0.71 seconds
Started Jul 01 06:33:02 PM PDT 24
Finished Jul 01 06:33:04 PM PDT 24
Peak memory 206696 kb
Host smart-94dbccad-b1d5-40fe-bec9-55db4824b50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962398408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.962398408
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1795401871
Short name T395
Test name
Test status
Simulation time 41328402 ps
CPU time 1.3 seconds
Started Jul 01 06:32:58 PM PDT 24
Finished Jul 01 06:33:01 PM PDT 24
Peak memory 217080 kb
Host smart-60dedcd9-4cd5-4e4f-8067-cd13092751ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795401871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1795401871
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.224590679
Short name T103
Test name
Test status
Simulation time 146904338 ps
CPU time 0.98 seconds
Started Jul 01 06:32:57 PM PDT 24
Finished Jul 01 06:32:59 PM PDT 24
Peak memory 207260 kb
Host smart-7a1d6689-a2cc-47e6-a3c1-0d8b9ec37919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224590679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.224590679
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.4240534373
Short name T199
Test name
Test status
Simulation time 67181895 ps
CPU time 2.37 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:08 PM PDT 24
Peak memory 233756 kb
Host smart-606d9d57-7b4c-45db-9b72-baa1ebd485ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240534373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4240534373
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3690128644
Short name T77
Test name
Test status
Simulation time 155084522 ps
CPU time 0.76 seconds
Started Jul 01 06:33:09 PM PDT 24
Finished Jul 01 06:33:12 PM PDT 24
Peak memory 205856 kb
Host smart-ea0bad72-06a3-44ee-a296-751fb1b0b75d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690128644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3690128644
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2649663309
Short name T641
Test name
Test status
Simulation time 85638723 ps
CPU time 2.82 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:08 PM PDT 24
Peak memory 233804 kb
Host smart-8474b444-9b33-43fe-9a0a-b0484b5b7858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649663309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2649663309
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4189441490
Short name T536
Test name
Test status
Simulation time 93965684 ps
CPU time 0.82 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:07 PM PDT 24
Peak memory 207612 kb
Host smart-84279f06-6a74-41ee-8150-4182fb087933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189441490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4189441490
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1621134416
Short name T442
Test name
Test status
Simulation time 3889753756 ps
CPU time 51.69 seconds
Started Jul 01 06:33:10 PM PDT 24
Finished Jul 01 06:34:03 PM PDT 24
Peak memory 250272 kb
Host smart-65a625cd-aacd-4f19-bfc2-250f5406a45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621134416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1621134416
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.742247584
Short name T312
Test name
Test status
Simulation time 25053202413 ps
CPU time 74.49 seconds
Started Jul 01 06:33:08 PM PDT 24
Finished Jul 01 06:34:25 PM PDT 24
Peak memory 263600 kb
Host smart-723a9251-483d-442a-b24c-7d734515c180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742247584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.742247584
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2271956219
Short name T685
Test name
Test status
Simulation time 5751986363 ps
CPU time 82.71 seconds
Started Jul 01 06:33:15 PM PDT 24
Finished Jul 01 06:34:39 PM PDT 24
Peak memory 258544 kb
Host smart-f3f2b361-4671-4a0d-aeed-cdf9c85aa9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271956219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2271956219
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.7686554
Short name T770
Test name
Test status
Simulation time 37844589 ps
CPU time 2.8 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:08 PM PDT 24
Peak memory 233828 kb
Host smart-84abf70d-07f1-4fdf-8356-0375f01b06eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7686554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.7686554
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.139685200
Short name T634
Test name
Test status
Simulation time 2257404379 ps
CPU time 21.01 seconds
Started Jul 01 06:33:07 PM PDT 24
Finished Jul 01 06:33:30 PM PDT 24
Peak memory 254396 kb
Host smart-7b2e9576-220e-4605-80f5-14ea1019ce2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139685200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.139685200
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3738760654
Short name T637
Test name
Test status
Simulation time 372778435 ps
CPU time 5.09 seconds
Started Jul 01 06:33:06 PM PDT 24
Finished Jul 01 06:33:14 PM PDT 24
Peak memory 225636 kb
Host smart-588a07b2-1316-4804-9a26-f6f791adef5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738760654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3738760654
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1365603739
Short name T827
Test name
Test status
Simulation time 1637682623 ps
CPU time 6.82 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:13 PM PDT 24
Peak memory 233768 kb
Host smart-d84e2475-5e77-4ae2-9338-6bd9c48e3597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365603739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1365603739
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2900430977
Short name T762
Test name
Test status
Simulation time 365089879 ps
CPU time 3.32 seconds
Started Jul 01 06:33:07 PM PDT 24
Finished Jul 01 06:33:13 PM PDT 24
Peak memory 233844 kb
Host smart-38ffd83d-bb78-450a-9f1b-b5005f33f631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900430977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2900430977
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2086899146
Short name T735
Test name
Test status
Simulation time 4692398634 ps
CPU time 8.97 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:15 PM PDT 24
Peak memory 225676 kb
Host smart-019e4a6a-6313-4336-b429-b2136bff9016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086899146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2086899146
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1405145165
Short name T437
Test name
Test status
Simulation time 1379433126 ps
CPU time 9.91 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:16 PM PDT 24
Peak memory 219832 kb
Host smart-3f51fe9d-5d5c-4514-a886-c2a1b8d9ec77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1405145165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1405145165
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2257792174
Short name T176
Test name
Test status
Simulation time 48154748 ps
CPU time 0.98 seconds
Started Jul 01 06:33:14 PM PDT 24
Finished Jul 01 06:33:16 PM PDT 24
Peak memory 208540 kb
Host smart-c078d006-97fd-4b00-93d8-6892a967e6c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257792174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2257792174
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2640873648
Short name T1031
Test name
Test status
Simulation time 5424042741 ps
CPU time 24.67 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:30 PM PDT 24
Peak memory 217484 kb
Host smart-9799d16d-3ddb-48bb-8f52-e1842c040783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640873648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2640873648
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1877524664
Short name T965
Test name
Test status
Simulation time 276795973 ps
CPU time 1.09 seconds
Started Jul 01 06:33:07 PM PDT 24
Finished Jul 01 06:33:10 PM PDT 24
Peak memory 208000 kb
Host smart-f2933e47-6329-4fdc-8f9a-0390a1ac039a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877524664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1877524664
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2181772912
Short name T35
Test name
Test status
Simulation time 72268618 ps
CPU time 1.45 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:06 PM PDT 24
Peak memory 217396 kb
Host smart-4d50a83d-2fb8-48ee-9853-ac2e68fdb3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181772912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2181772912
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2004608514
Short name T367
Test name
Test status
Simulation time 47852488 ps
CPU time 0.93 seconds
Started Jul 01 06:33:04 PM PDT 24
Finished Jul 01 06:33:07 PM PDT 24
Peak memory 206944 kb
Host smart-ec59618f-fcaa-443a-8221-6664a2de6e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004608514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2004608514
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1511925596
Short name T268
Test name
Test status
Simulation time 724110636 ps
CPU time 7.78 seconds
Started Jul 01 06:33:07 PM PDT 24
Finished Jul 01 06:33:17 PM PDT 24
Peak memory 233856 kb
Host smart-4263f66d-1edb-455b-ad5b-cbde84e5b3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511925596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1511925596
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2908178088
Short name T613
Test name
Test status
Simulation time 28578203 ps
CPU time 0.75 seconds
Started Jul 01 06:28:01 PM PDT 24
Finished Jul 01 06:28:03 PM PDT 24
Peak memory 206416 kb
Host smart-18e19789-9773-4e39-a9e0-2a1232530c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908178088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
908178088
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4005263140
Short name T105
Test name
Test status
Simulation time 219647292 ps
CPU time 4.49 seconds
Started Jul 01 06:27:58 PM PDT 24
Finished Jul 01 06:28:03 PM PDT 24
Peak memory 233796 kb
Host smart-b19db9b3-e3ad-44c3-85fb-e1599a750630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005263140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4005263140
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.335577581
Short name T30
Test name
Test status
Simulation time 40387613 ps
CPU time 0.81 seconds
Started Jul 01 06:27:47 PM PDT 24
Finished Jul 01 06:27:49 PM PDT 24
Peak memory 207588 kb
Host smart-52d8930b-516a-456a-b8f2-7e8bbf86c1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335577581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.335577581
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3314055504
Short name T644
Test name
Test status
Simulation time 3955448317 ps
CPU time 52.75 seconds
Started Jul 01 06:27:56 PM PDT 24
Finished Jul 01 06:28:50 PM PDT 24
Peak memory 237540 kb
Host smart-66ae994e-5fee-4070-a82a-fbeb24795282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314055504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3314055504
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3820204993
Short name T251
Test name
Test status
Simulation time 24995788924 ps
CPU time 104.71 seconds
Started Jul 01 06:27:57 PM PDT 24
Finished Jul 01 06:29:43 PM PDT 24
Peak memory 258216 kb
Host smart-8c2b1931-c356-4e93-b244-6f4dbb90a6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820204993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3820204993
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3351791895
Short name T364
Test name
Test status
Simulation time 258790923 ps
CPU time 3 seconds
Started Jul 01 06:27:58 PM PDT 24
Finished Jul 01 06:28:02 PM PDT 24
Peak memory 225588 kb
Host smart-60573c0b-4783-4f4b-9211-722f7f36a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351791895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3351791895
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3392798536
Short name T589
Test name
Test status
Simulation time 353388501 ps
CPU time 3.95 seconds
Started Jul 01 06:27:53 PM PDT 24
Finished Jul 01 06:27:58 PM PDT 24
Peak memory 225580 kb
Host smart-2e240108-9d3f-40a0-bda0-b134cb3e44ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392798536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3392798536
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2905255065
Short name T208
Test name
Test status
Simulation time 10768468333 ps
CPU time 43.25 seconds
Started Jul 01 06:27:56 PM PDT 24
Finished Jul 01 06:28:40 PM PDT 24
Peak memory 234144 kb
Host smart-69cf89e6-7452-4d1d-bd77-ae013c95bd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905255065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2905255065
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2208098508
Short name T48
Test name
Test status
Simulation time 192882057 ps
CPU time 1.05 seconds
Started Jul 01 06:27:49 PM PDT 24
Finished Jul 01 06:27:50 PM PDT 24
Peak memory 217652 kb
Host smart-86f69ded-8ed2-47e9-bda6-54329f7a5889
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208098508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2208098508
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4023968107
Short name T773
Test name
Test status
Simulation time 500061999 ps
CPU time 4.22 seconds
Started Jul 01 06:27:52 PM PDT 24
Finished Jul 01 06:27:57 PM PDT 24
Peak memory 220760 kb
Host smart-ba3adba7-fa7e-4585-9a25-bc1e44d9f886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023968107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4023968107
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3872963837
Short name T916
Test name
Test status
Simulation time 1025086327 ps
CPU time 7.45 seconds
Started Jul 01 06:27:51 PM PDT 24
Finished Jul 01 06:27:59 PM PDT 24
Peak memory 233780 kb
Host smart-690f1fe0-145c-4b83-9568-ec3d4060393c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872963837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3872963837
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1120411804
Short name T156
Test name
Test status
Simulation time 12070951472 ps
CPU time 13.98 seconds
Started Jul 01 06:27:56 PM PDT 24
Finished Jul 01 06:28:11 PM PDT 24
Peak memory 221256 kb
Host smart-4afc656a-f7d7-4efc-ad90-f6baf0701887
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1120411804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1120411804
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2958742511
Short name T84
Test name
Test status
Simulation time 87365583 ps
CPU time 1.25 seconds
Started Jul 01 06:28:02 PM PDT 24
Finished Jul 01 06:28:04 PM PDT 24
Peak memory 237928 kb
Host smart-03592434-5952-4ea2-b4c2-1c7a0aacc98b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958742511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2958742511
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3630630685
Short name T790
Test name
Test status
Simulation time 22111741446 ps
CPU time 404.11 seconds
Started Jul 01 06:28:02 PM PDT 24
Finished Jul 01 06:34:47 PM PDT 24
Peak memory 299600 kb
Host smart-93ab8c45-4cae-4ffa-8c7e-d979dc7fa318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630630685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3630630685
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2925163173
Short name T342
Test name
Test status
Simulation time 43707257394 ps
CPU time 17.78 seconds
Started Jul 01 06:27:50 PM PDT 24
Finished Jul 01 06:28:09 PM PDT 24
Peak memory 217792 kb
Host smart-5c32b526-0e50-42e3-8895-0c947a5ffe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925163173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2925163173
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3168319599
Short name T556
Test name
Test status
Simulation time 2025980733 ps
CPU time 6.26 seconds
Started Jul 01 06:27:53 PM PDT 24
Finished Jul 01 06:28:00 PM PDT 24
Peak memory 217324 kb
Host smart-7cef04ae-b05a-4513-b49e-d1cb0f1077e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168319599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3168319599
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2793551129
Short name T477
Test name
Test status
Simulation time 87951846 ps
CPU time 3.28 seconds
Started Jul 01 06:27:50 PM PDT 24
Finished Jul 01 06:27:55 PM PDT 24
Peak memory 217388 kb
Host smart-bcd11db4-3be6-498b-86d0-e51a10c6470a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793551129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2793551129
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.498370315
Short name T595
Test name
Test status
Simulation time 69276149 ps
CPU time 0.91 seconds
Started Jul 01 06:27:50 PM PDT 24
Finished Jul 01 06:27:52 PM PDT 24
Peak memory 206940 kb
Host smart-f6217646-c913-4a26-9c60-4d86c8d17cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498370315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.498370315
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1330697330
Short name T466
Test name
Test status
Simulation time 822934003 ps
CPU time 4.22 seconds
Started Jul 01 06:27:56 PM PDT 24
Finished Jul 01 06:28:01 PM PDT 24
Peak memory 233808 kb
Host smart-c6376f47-7f22-4f79-a808-6d8bcf0e1d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330697330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1330697330
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3962828202
Short name T502
Test name
Test status
Simulation time 30176276 ps
CPU time 0.74 seconds
Started Jul 01 06:33:20 PM PDT 24
Finished Jul 01 06:33:22 PM PDT 24
Peak memory 206336 kb
Host smart-d2fd1b15-6833-4447-b523-49aa667ad393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962828202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3962828202
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2573086899
Short name T850
Test name
Test status
Simulation time 429615278 ps
CPU time 4.56 seconds
Started Jul 01 06:33:15 PM PDT 24
Finished Jul 01 06:33:20 PM PDT 24
Peak memory 233712 kb
Host smart-54e94bc7-931c-458c-a47d-9d7231f3c376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573086899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2573086899
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1138818162
Short name T624
Test name
Test status
Simulation time 120658049 ps
CPU time 0.78 seconds
Started Jul 01 06:33:12 PM PDT 24
Finished Jul 01 06:33:14 PM PDT 24
Peak memory 207440 kb
Host smart-5f850535-052e-4b22-bed8-fc375603cd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138818162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1138818162
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1321228442
Short name T215
Test name
Test status
Simulation time 30541906056 ps
CPU time 104.12 seconds
Started Jul 01 06:33:16 PM PDT 24
Finished Jul 01 06:35:01 PM PDT 24
Peak memory 250416 kb
Host smart-d00755fb-2192-4c7e-ac5f-bfeb49facab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321228442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1321228442
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3348710262
Short name T293
Test name
Test status
Simulation time 31627089169 ps
CPU time 67.71 seconds
Started Jul 01 06:33:20 PM PDT 24
Finished Jul 01 06:34:29 PM PDT 24
Peak memory 235044 kb
Host smart-92cd1f62-16a7-40e8-895d-0282548a3560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348710262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3348710262
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2651781519
Short name T605
Test name
Test status
Simulation time 16399001243 ps
CPU time 57.69 seconds
Started Jul 01 06:33:17 PM PDT 24
Finished Jul 01 06:34:15 PM PDT 24
Peak memory 233920 kb
Host smart-607f118e-6a0b-44b7-bb8e-38dcecac263b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651781519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2651781519
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2457566756
Short name T798
Test name
Test status
Simulation time 45111296130 ps
CPU time 189.91 seconds
Started Jul 01 06:33:18 PM PDT 24
Finished Jul 01 06:36:28 PM PDT 24
Peak memory 250300 kb
Host smart-00c5b514-371b-4151-b4a6-33f98e074fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457566756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2457566756
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.839539908
Short name T923
Test name
Test status
Simulation time 14452424708 ps
CPU time 31.05 seconds
Started Jul 01 06:33:13 PM PDT 24
Finished Jul 01 06:33:45 PM PDT 24
Peak memory 225676 kb
Host smart-9282fb1b-2800-4360-8ed8-22328310a50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839539908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.839539908
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.113198026
Short name T996
Test name
Test status
Simulation time 4308166017 ps
CPU time 42.51 seconds
Started Jul 01 06:33:10 PM PDT 24
Finished Jul 01 06:33:54 PM PDT 24
Peak memory 233752 kb
Host smart-cce4f99f-1cf0-4a74-813d-9cce6fe4e66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113198026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.113198026
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.58774118
Short name T573
Test name
Test status
Simulation time 11579869168 ps
CPU time 13.46 seconds
Started Jul 01 06:33:15 PM PDT 24
Finished Jul 01 06:33:29 PM PDT 24
Peak memory 233856 kb
Host smart-668b3364-ceb2-40ee-9c82-fb2da0fc3dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58774118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.58774118
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3864680343
Short name T182
Test name
Test status
Simulation time 33597198 ps
CPU time 2.16 seconds
Started Jul 01 06:33:13 PM PDT 24
Finished Jul 01 06:33:16 PM PDT 24
Peak memory 224904 kb
Host smart-6e09f749-bd5d-46ff-90a3-1e4980b2cb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864680343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3864680343
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2658634757
Short name T791
Test name
Test status
Simulation time 64383469 ps
CPU time 3.23 seconds
Started Jul 01 06:33:14 PM PDT 24
Finished Jul 01 06:33:18 PM PDT 24
Peak memory 220464 kb
Host smart-d70363e7-f2f4-4a5c-a2f5-80b4a4edeb21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2658634757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2658634757
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3269133403
Short name T336
Test name
Test status
Simulation time 34789462074 ps
CPU time 408.59 seconds
Started Jul 01 06:33:19 PM PDT 24
Finished Jul 01 06:40:09 PM PDT 24
Peak memory 275040 kb
Host smart-94f08dcd-1590-4084-a71c-40f00793ac03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269133403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3269133403
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4099079340
Short name T802
Test name
Test status
Simulation time 1792065245 ps
CPU time 18.73 seconds
Started Jul 01 06:33:13 PM PDT 24
Finished Jul 01 06:33:33 PM PDT 24
Peak memory 217536 kb
Host smart-bd7a2b77-1042-42ff-a956-bb4da901ee83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099079340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4099079340
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2792660175
Short name T610
Test name
Test status
Simulation time 792172694 ps
CPU time 2.33 seconds
Started Jul 01 06:33:08 PM PDT 24
Finished Jul 01 06:33:12 PM PDT 24
Peak memory 217176 kb
Host smart-776b4f1f-456c-4fe0-a941-9366311416d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792660175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2792660175
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3666081507
Short name T808
Test name
Test status
Simulation time 153102763 ps
CPU time 2.25 seconds
Started Jul 01 06:33:10 PM PDT 24
Finished Jul 01 06:33:14 PM PDT 24
Peak memory 217352 kb
Host smart-47b8d7ab-a952-49c5-a2bf-74b8c056e108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666081507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3666081507
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.657882331
Short name T102
Test name
Test status
Simulation time 66345069 ps
CPU time 0.74 seconds
Started Jul 01 06:33:12 PM PDT 24
Finished Jul 01 06:33:14 PM PDT 24
Peak memory 206956 kb
Host smart-587bbc50-6ae5-4b91-a47a-4dd07197814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657882331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.657882331
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1036086775
Short name T928
Test name
Test status
Simulation time 58382325801 ps
CPU time 35.95 seconds
Started Jul 01 06:33:11 PM PDT 24
Finished Jul 01 06:33:48 PM PDT 24
Peak memory 233992 kb
Host smart-9395ea0f-b330-4760-a297-68c3c4f3f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036086775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1036086775
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2514745332
Short name T910
Test name
Test status
Simulation time 37939269 ps
CPU time 0.73 seconds
Started Jul 01 06:33:26 PM PDT 24
Finished Jul 01 06:33:28 PM PDT 24
Peak memory 206788 kb
Host smart-dbea55e4-e576-438a-bfeb-ee0d64d7a113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514745332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2514745332
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2562339215
Short name T540
Test name
Test status
Simulation time 5102331675 ps
CPU time 6.32 seconds
Started Jul 01 06:33:27 PM PDT 24
Finished Jul 01 06:33:34 PM PDT 24
Peak memory 225648 kb
Host smart-a0eeb41b-25e0-4cbb-9bb2-c4d3c43e62ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562339215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2562339215
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.567680201
Short name T774
Test name
Test status
Simulation time 41650292 ps
CPU time 0.78 seconds
Started Jul 01 06:33:27 PM PDT 24
Finished Jul 01 06:33:29 PM PDT 24
Peak memory 206448 kb
Host smart-5e0f51f5-2f3a-40aa-95af-0d3c5de03ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567680201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.567680201
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1938548860
Short name T607
Test name
Test status
Simulation time 137982584586 ps
CPU time 105.67 seconds
Started Jul 01 06:33:28 PM PDT 24
Finished Jul 01 06:35:15 PM PDT 24
Peak memory 250332 kb
Host smart-5e406728-cfbf-40ac-834c-2671700b1bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938548860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1938548860
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2026133289
Short name T651
Test name
Test status
Simulation time 24691649337 ps
CPU time 103.12 seconds
Started Jul 01 06:33:28 PM PDT 24
Finished Jul 01 06:35:12 PM PDT 24
Peak memory 266416 kb
Host smart-41598f20-092c-4cac-a622-0eba898c864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026133289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2026133289
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1085668842
Short name T214
Test name
Test status
Simulation time 1146854697 ps
CPU time 6.59 seconds
Started Jul 01 06:33:20 PM PDT 24
Finished Jul 01 06:33:28 PM PDT 24
Peak memory 225560 kb
Host smart-3bef2ca8-ca78-4a9b-af8a-3c15f4c75d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085668842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1085668842
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2435531831
Short name T912
Test name
Test status
Simulation time 16686394866 ps
CPU time 71.66 seconds
Started Jul 01 06:33:20 PM PDT 24
Finished Jul 01 06:34:33 PM PDT 24
Peak memory 240744 kb
Host smart-bb8afa57-2b9c-45b8-9172-e40dc4eb07e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435531831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2435531831
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.494163366
Short name T879
Test name
Test status
Simulation time 5366768546 ps
CPU time 7.24 seconds
Started Jul 01 06:33:20 PM PDT 24
Finished Jul 01 06:33:29 PM PDT 24
Peak memory 225736 kb
Host smart-11ed8e11-f5e4-48f7-8829-94186bbb450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494163366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.494163366
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1023592316
Short name T865
Test name
Test status
Simulation time 11487394897 ps
CPU time 18.44 seconds
Started Jul 01 06:33:22 PM PDT 24
Finished Jul 01 06:33:41 PM PDT 24
Peak memory 225576 kb
Host smart-4fc3f807-ae7b-4af0-a44f-e0d6cbb0e61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023592316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1023592316
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4103771156
Short name T678
Test name
Test status
Simulation time 382951415 ps
CPU time 4.57 seconds
Started Jul 01 06:33:26 PM PDT 24
Finished Jul 01 06:33:32 PM PDT 24
Peak memory 221792 kb
Host smart-25e0ee71-392c-4f5c-9fa2-d58814adf068
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4103771156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4103771156
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.868565391
Short name T884
Test name
Test status
Simulation time 21270118397 ps
CPU time 203.64 seconds
Started Jul 01 06:33:27 PM PDT 24
Finished Jul 01 06:36:52 PM PDT 24
Peak memory 265948 kb
Host smart-ac77c763-f13a-443f-8181-1a84cb817500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868565391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.868565391
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.582755348
Short name T684
Test name
Test status
Simulation time 8660835965 ps
CPU time 39.82 seconds
Started Jul 01 06:33:19 PM PDT 24
Finished Jul 01 06:34:00 PM PDT 24
Peak memory 217524 kb
Host smart-04f84437-5375-42ca-ab44-9084c5eb2cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582755348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.582755348
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.484796261
Short name T616
Test name
Test status
Simulation time 5611576809 ps
CPU time 4.9 seconds
Started Jul 01 06:33:19 PM PDT 24
Finished Jul 01 06:33:25 PM PDT 24
Peak memory 217508 kb
Host smart-caf4a4ca-4862-43e2-87b9-61fa9742936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484796261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.484796261
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3003487719
Short name T350
Test name
Test status
Simulation time 45927758 ps
CPU time 1.47 seconds
Started Jul 01 06:33:26 PM PDT 24
Finished Jul 01 06:33:29 PM PDT 24
Peak memory 217364 kb
Host smart-864244db-f8d1-4a86-9b2a-8793487d2b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003487719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3003487719
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3588110820
Short name T982
Test name
Test status
Simulation time 65981034 ps
CPU time 0.85 seconds
Started Jul 01 06:33:27 PM PDT 24
Finished Jul 01 06:33:29 PM PDT 24
Peak memory 206924 kb
Host smart-bbb52424-e556-4bb3-b6ff-02e21e37ff73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588110820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3588110820
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2580616987
Short name T257
Test name
Test status
Simulation time 1649298144 ps
CPU time 9.39 seconds
Started Jul 01 06:33:19 PM PDT 24
Finished Jul 01 06:33:29 PM PDT 24
Peak memory 225556 kb
Host smart-2d5c8130-e5bb-4c98-90ab-d89b3ec82b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580616987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2580616987
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2515036040
Short name T970
Test name
Test status
Simulation time 23168443 ps
CPU time 0.75 seconds
Started Jul 01 06:33:39 PM PDT 24
Finished Jul 01 06:33:40 PM PDT 24
Peak memory 205636 kb
Host smart-1c9ddeca-8d0d-420e-b4b5-9992a2b1e023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515036040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2515036040
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2546452632
Short name T1030
Test name
Test status
Simulation time 5994968564 ps
CPU time 30.85 seconds
Started Jul 01 06:33:31 PM PDT 24
Finished Jul 01 06:34:03 PM PDT 24
Peak memory 233980 kb
Host smart-186207dc-7df5-4c06-abad-c782b6378427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546452632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2546452632
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4084269572
Short name T388
Test name
Test status
Simulation time 68095255 ps
CPU time 0.75 seconds
Started Jul 01 06:33:25 PM PDT 24
Finished Jul 01 06:33:26 PM PDT 24
Peak memory 207872 kb
Host smart-5dc98a27-a448-4c16-b348-da5004208bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084269572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4084269572
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.113745753
Short name T262
Test name
Test status
Simulation time 3292276329 ps
CPU time 56.85 seconds
Started Jul 01 06:33:31 PM PDT 24
Finished Jul 01 06:34:29 PM PDT 24
Peak memory 251320 kb
Host smart-6d6c8dbd-44c8-44d2-80f4-47aefc7feaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113745753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.113745753
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2473380103
Short name T551
Test name
Test status
Simulation time 2552537943 ps
CPU time 8.79 seconds
Started Jul 01 06:33:32 PM PDT 24
Finished Jul 01 06:33:42 PM PDT 24
Peak memory 222324 kb
Host smart-9f91aacb-059f-41d0-ae62-18f052628fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473380103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2473380103
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.832997944
Short name T880
Test name
Test status
Simulation time 71242877800 ps
CPU time 287.85 seconds
Started Jul 01 06:33:31 PM PDT 24
Finished Jul 01 06:38:20 PM PDT 24
Peak memory 257012 kb
Host smart-29214977-8efc-435f-a7a1-06eacad7004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832997944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.832997944
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3450320814
Short name T693
Test name
Test status
Simulation time 86684170 ps
CPU time 2.95 seconds
Started Jul 01 06:33:31 PM PDT 24
Finished Jul 01 06:33:36 PM PDT 24
Peak memory 233760 kb
Host smart-31389369-f7be-408a-b1f3-2f12e3682825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450320814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3450320814
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.143419784
Short name T227
Test name
Test status
Simulation time 46357004639 ps
CPU time 156.3 seconds
Started Jul 01 06:33:31 PM PDT 24
Finished Jul 01 06:36:09 PM PDT 24
Peak memory 239304 kb
Host smart-47907a06-8ce5-4e5e-bedf-272db7219539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143419784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.143419784
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2899220817
Short name T799
Test name
Test status
Simulation time 1408808172 ps
CPU time 18.55 seconds
Started Jul 01 06:33:31 PM PDT 24
Finished Jul 01 06:33:51 PM PDT 24
Peak memory 233800 kb
Host smart-9ffdcce9-5e41-4b45-92d0-96bd78f3f182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899220817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2899220817
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.808826733
Short name T759
Test name
Test status
Simulation time 22903972481 ps
CPU time 40.12 seconds
Started Jul 01 06:33:37 PM PDT 24
Finished Jul 01 06:34:18 PM PDT 24
Peak memory 242032 kb
Host smart-52fcd28f-bf36-4841-9c6c-7b7d8bde3608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808826733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.808826733
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3449233730
Short name T717
Test name
Test status
Simulation time 8254776019 ps
CPU time 25.18 seconds
Started Jul 01 06:33:33 PM PDT 24
Finished Jul 01 06:33:59 PM PDT 24
Peak memory 234080 kb
Host smart-da43790b-f024-494c-918f-682572d37e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449233730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3449233730
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3342333717
Short name T940
Test name
Test status
Simulation time 1852065025 ps
CPU time 2.45 seconds
Started Jul 01 06:33:33 PM PDT 24
Finished Jul 01 06:33:36 PM PDT 24
Peak memory 225552 kb
Host smart-86cb4a0f-117f-4457-b924-49722dccc07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342333717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3342333717
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1087200048
Short name T823
Test name
Test status
Simulation time 5532149236 ps
CPU time 16.84 seconds
Started Jul 01 06:33:31 PM PDT 24
Finished Jul 01 06:33:49 PM PDT 24
Peak memory 220632 kb
Host smart-81eb94c0-6828-433a-b98e-b08d3e4309f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1087200048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1087200048
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3697675445
Short name T893
Test name
Test status
Simulation time 38112382 ps
CPU time 0.97 seconds
Started Jul 01 06:33:36 PM PDT 24
Finished Jul 01 06:33:38 PM PDT 24
Peak memory 208468 kb
Host smart-a479b8ea-e2f4-479c-b28f-b37197b296cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697675445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3697675445
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2448294346
Short name T344
Test name
Test status
Simulation time 3541188312 ps
CPU time 16.1 seconds
Started Jul 01 06:33:32 PM PDT 24
Finished Jul 01 06:33:49 PM PDT 24
Peak memory 217524 kb
Host smart-ec054a23-2eeb-4418-89b0-5e68a25d8d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448294346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2448294346
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4122736109
Short name T667
Test name
Test status
Simulation time 1665350341 ps
CPU time 5.52 seconds
Started Jul 01 06:33:29 PM PDT 24
Finished Jul 01 06:33:35 PM PDT 24
Peak memory 217432 kb
Host smart-fca257fc-6fdb-4d4e-87b2-4abe3545bc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122736109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4122736109
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2977963011
Short name T864
Test name
Test status
Simulation time 271658243 ps
CPU time 1.17 seconds
Started Jul 01 06:33:37 PM PDT 24
Finished Jul 01 06:33:39 PM PDT 24
Peak memory 217020 kb
Host smart-cd02911b-5e5b-4850-97e8-11e67693784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977963011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2977963011
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3540741013
Short name T509
Test name
Test status
Simulation time 80056797 ps
CPU time 0.94 seconds
Started Jul 01 06:33:31 PM PDT 24
Finished Jul 01 06:33:34 PM PDT 24
Peak memory 206972 kb
Host smart-53b87c38-fd75-49fc-b0b3-e4e77c513ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540741013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3540741013
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2557778099
Short name T261
Test name
Test status
Simulation time 914775446 ps
CPU time 8.22 seconds
Started Jul 01 06:33:33 PM PDT 24
Finished Jul 01 06:33:42 PM PDT 24
Peak memory 250200 kb
Host smart-583c8860-578a-42b4-8e54-b435b3ccc29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557778099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2557778099
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3764889676
Short name T953
Test name
Test status
Simulation time 15107771 ps
CPU time 0.73 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:33:44 PM PDT 24
Peak memory 206840 kb
Host smart-ba957f2b-c9f9-4da3-82e1-ebaaa07cef6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764889676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3764889676
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1042411034
Short name T896
Test name
Test status
Simulation time 56672624 ps
CPU time 2.43 seconds
Started Jul 01 06:33:40 PM PDT 24
Finished Jul 01 06:33:43 PM PDT 24
Peak memory 233476 kb
Host smart-a75f29d3-220a-4f08-adb3-fe6f372376c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042411034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1042411034
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3973930452
Short name T507
Test name
Test status
Simulation time 15961062 ps
CPU time 0.79 seconds
Started Jul 01 06:33:39 PM PDT 24
Finished Jul 01 06:33:40 PM PDT 24
Peak memory 206800 kb
Host smart-b311d073-4594-4244-9bab-30b64aa94571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973930452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3973930452
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1587151529
Short name T663
Test name
Test status
Simulation time 6930398578 ps
CPU time 48.51 seconds
Started Jul 01 06:33:39 PM PDT 24
Finished Jul 01 06:34:29 PM PDT 24
Peak memory 250260 kb
Host smart-0a0a590a-2476-4f08-8821-1eb15701b6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587151529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1587151529
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3675622754
Short name T881
Test name
Test status
Simulation time 125517255743 ps
CPU time 614.34 seconds
Started Jul 01 06:33:34 PM PDT 24
Finished Jul 01 06:43:50 PM PDT 24
Peak memory 258588 kb
Host smart-1e9d9b65-fdb7-452d-826a-6744f4743b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675622754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3675622754
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2066747914
Short name T612
Test name
Test status
Simulation time 231501264 ps
CPU time 3.7 seconds
Started Jul 01 06:33:36 PM PDT 24
Finished Jul 01 06:33:40 PM PDT 24
Peak memory 233800 kb
Host smart-2b3e3f94-63ce-4602-9434-4aa8a391c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066747914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2066747914
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1570403803
Short name T389
Test name
Test status
Simulation time 1014093000 ps
CPU time 11.11 seconds
Started Jul 01 06:33:39 PM PDT 24
Finished Jul 01 06:33:52 PM PDT 24
Peak memory 242036 kb
Host smart-20b33cde-9f06-4713-81ef-2c46b8adde56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570403803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1570403803
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3452097175
Short name T781
Test name
Test status
Simulation time 1415797936 ps
CPU time 5.58 seconds
Started Jul 01 06:33:39 PM PDT 24
Finished Jul 01 06:33:46 PM PDT 24
Peak memory 225572 kb
Host smart-1a7d295c-1786-4b53-b8b6-0da3e9685bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452097175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3452097175
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.14944603
Short name T421
Test name
Test status
Simulation time 327518135 ps
CPU time 8.13 seconds
Started Jul 01 06:33:39 PM PDT 24
Finished Jul 01 06:33:48 PM PDT 24
Peak memory 251052 kb
Host smart-96743098-3224-43fe-9ba2-30a65e71da99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14944603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.14944603
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2188095306
Short name T324
Test name
Test status
Simulation time 2541595190 ps
CPU time 10.06 seconds
Started Jul 01 06:33:38 PM PDT 24
Finished Jul 01 06:33:49 PM PDT 24
Peak memory 241652 kb
Host smart-d2912da0-23fc-42fe-8bec-0564c7ad27ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188095306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2188095306
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3249214008
Short name T298
Test name
Test status
Simulation time 20577960593 ps
CPU time 17.07 seconds
Started Jul 01 06:33:35 PM PDT 24
Finished Jul 01 06:33:53 PM PDT 24
Peak memory 250276 kb
Host smart-a19e807e-2d64-4be2-9f0a-46d1033170ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249214008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3249214008
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3113551265
Short name T875
Test name
Test status
Simulation time 102916991 ps
CPU time 4.47 seconds
Started Jul 01 06:33:39 PM PDT 24
Finished Jul 01 06:33:44 PM PDT 24
Peak memory 224112 kb
Host smart-912daf28-4caa-4eb6-a301-14f13d9e5f97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3113551265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3113551265
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2438542475
Short name T271
Test name
Test status
Simulation time 190207610807 ps
CPU time 411.55 seconds
Started Jul 01 06:33:46 PM PDT 24
Finished Jul 01 06:40:38 PM PDT 24
Peak memory 254924 kb
Host smart-1e52f60f-4822-48dd-838a-9dd9bff98466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438542475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2438542475
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3066619954
Short name T598
Test name
Test status
Simulation time 8645568550 ps
CPU time 47.37 seconds
Started Jul 01 06:33:36 PM PDT 24
Finished Jul 01 06:34:24 PM PDT 24
Peak memory 217756 kb
Host smart-4b8be6ea-9f12-4945-95ed-7ae71b3baff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066619954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3066619954
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2230066167
Short name T465
Test name
Test status
Simulation time 13388682 ps
CPU time 0.71 seconds
Started Jul 01 06:33:35 PM PDT 24
Finished Jul 01 06:33:37 PM PDT 24
Peak memory 206700 kb
Host smart-82b9e530-dc5f-4146-a32e-89d6c60c9ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230066167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2230066167
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4274238260
Short name T851
Test name
Test status
Simulation time 46397917 ps
CPU time 0.86 seconds
Started Jul 01 06:33:35 PM PDT 24
Finished Jul 01 06:33:37 PM PDT 24
Peak memory 208024 kb
Host smart-19f574de-9f72-4167-8815-6b8c14ce24d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274238260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4274238260
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.714269057
Short name T1032
Test name
Test status
Simulation time 62436671 ps
CPU time 0.71 seconds
Started Jul 01 06:33:38 PM PDT 24
Finished Jul 01 06:33:40 PM PDT 24
Peak memory 206540 kb
Host smart-fd60a491-535b-4788-8de9-74bb3fd12ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714269057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.714269057
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1572549855
Short name T260
Test name
Test status
Simulation time 22802458610 ps
CPU time 23.39 seconds
Started Jul 01 06:33:35 PM PDT 24
Finished Jul 01 06:34:00 PM PDT 24
Peak memory 233872 kb
Host smart-f7ace215-c07f-4d0d-927a-b7965acbfccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572549855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1572549855
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2569428934
Short name T590
Test name
Test status
Simulation time 98033227 ps
CPU time 0.72 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:33:43 PM PDT 24
Peak memory 206444 kb
Host smart-898af640-219b-4f6c-b627-e69c9f0f2422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569428934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2569428934
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4065734407
Short name T998
Test name
Test status
Simulation time 271430576 ps
CPU time 4.39 seconds
Started Jul 01 06:33:43 PM PDT 24
Finished Jul 01 06:33:49 PM PDT 24
Peak memory 225568 kb
Host smart-5058bf36-9b53-4cbb-8577-f1ba8e604f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065734407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4065734407
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3667010930
Short name T906
Test name
Test status
Simulation time 13992063 ps
CPU time 0.76 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:33:45 PM PDT 24
Peak memory 206480 kb
Host smart-437d906e-6560-401f-863b-fea5c7487d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667010930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3667010930
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.820102902
Short name T803
Test name
Test status
Simulation time 3572116050 ps
CPU time 32.28 seconds
Started Jul 01 06:33:44 PM PDT 24
Finished Jul 01 06:34:17 PM PDT 24
Peak memory 240920 kb
Host smart-075b9c4e-2aaa-4901-a14b-e195eec08a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820102902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.820102902
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2635036680
Short name T643
Test name
Test status
Simulation time 7519213484 ps
CPU time 38.48 seconds
Started Jul 01 06:33:41 PM PDT 24
Finished Jul 01 06:34:21 PM PDT 24
Peak memory 218928 kb
Host smart-00f26358-dd8b-4c5b-9a94-b5e73c503451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635036680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2635036680
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3841333648
Short name T682
Test name
Test status
Simulation time 24202684924 ps
CPU time 267.65 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:38:11 PM PDT 24
Peak memory 251580 kb
Host smart-d8982911-b74d-466b-a40c-1d5a24303a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841333648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3841333648
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.356596983
Short name T852
Test name
Test status
Simulation time 12028374800 ps
CPU time 25.41 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:34:08 PM PDT 24
Peak memory 242088 kb
Host smart-fb84b085-d379-48fd-bf7e-90940e80a497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356596983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.356596983
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3369572828
Short name T461
Test name
Test status
Simulation time 1010842964 ps
CPU time 24.46 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:34:08 PM PDT 24
Peak memory 235928 kb
Host smart-b28f1769-6db8-4331-896b-0bbfa2666188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369572828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3369572828
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2340083910
Short name T558
Test name
Test status
Simulation time 104922854 ps
CPU time 2.44 seconds
Started Jul 01 06:33:43 PM PDT 24
Finished Jul 01 06:33:47 PM PDT 24
Peak memory 233436 kb
Host smart-7e96a4b1-4992-46a3-83da-f52e71c9157b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340083910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2340083910
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3784758688
Short name T1003
Test name
Test status
Simulation time 2262119831 ps
CPU time 23.93 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:34:08 PM PDT 24
Peak memory 233844 kb
Host smart-0d0576bb-1b2d-4572-a033-9a41a943f85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784758688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3784758688
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3452271029
Short name T309
Test name
Test status
Simulation time 2277927647 ps
CPU time 8.2 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:33:51 PM PDT 24
Peak memory 233840 kb
Host smart-7ab4e9b8-919a-4536-9be6-cfdb68d6aa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452271029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3452271029
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1277189418
Short name T755
Test name
Test status
Simulation time 1577587529 ps
CPU time 7.95 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:33:51 PM PDT 24
Peak memory 233952 kb
Host smart-49e9ca2e-7d72-4ef4-adac-95bcd1e8a558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277189418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1277189418
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.99167542
Short name T1025
Test name
Test status
Simulation time 1161207899 ps
CPU time 7.59 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:33:50 PM PDT 24
Peak memory 223056 kb
Host smart-7ed07766-9ca2-4518-ae15-a7097b5b8cd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=99167542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direc
t.99167542
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.634142479
Short name T20
Test name
Test status
Simulation time 8349431459 ps
CPU time 70.81 seconds
Started Jul 01 06:33:43 PM PDT 24
Finished Jul 01 06:34:55 PM PDT 24
Peak memory 255000 kb
Host smart-17aa26e8-34f3-4355-a5ec-9552e82c5fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634142479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.634142479
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.247423914
Short name T1026
Test name
Test status
Simulation time 4082882626 ps
CPU time 11.47 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:33:55 PM PDT 24
Peak memory 217540 kb
Host smart-ec06c7e9-1fc7-464d-ba19-f25732183790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247423914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.247423914
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2230547196
Short name T990
Test name
Test status
Simulation time 6140359022 ps
CPU time 7.94 seconds
Started Jul 01 06:33:46 PM PDT 24
Finished Jul 01 06:33:55 PM PDT 24
Peak memory 217500 kb
Host smart-d6f05a3b-f361-4037-87bd-e91aa99d427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230547196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2230547196
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2180840436
Short name T424
Test name
Test status
Simulation time 360374633 ps
CPU time 1.1 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:33:44 PM PDT 24
Peak memory 208476 kb
Host smart-9449f347-f731-4682-9111-1b3623200813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180840436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2180840436
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.878916766
Short name T527
Test name
Test status
Simulation time 540596211 ps
CPU time 0.97 seconds
Started Jul 01 06:33:47 PM PDT 24
Finished Jul 01 06:33:48 PM PDT 24
Peak memory 208020 kb
Host smart-dfc7dd01-5f33-44d6-a9c4-ddcb4096874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878916766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.878916766
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.937590713
Short name T891
Test name
Test status
Simulation time 27923641658 ps
CPU time 14.14 seconds
Started Jul 01 06:33:43 PM PDT 24
Finished Jul 01 06:33:58 PM PDT 24
Peak memory 233848 kb
Host smart-ae891c16-aa93-4a8a-8816-05ab3aaef013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937590713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.937590713
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4290485391
Short name T443
Test name
Test status
Simulation time 15383124 ps
CPU time 0.72 seconds
Started Jul 01 06:33:50 PM PDT 24
Finished Jul 01 06:33:52 PM PDT 24
Peak memory 206344 kb
Host smart-fa45459c-6e19-456c-8af3-5dbbc9fb8b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290485391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4290485391
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1316607790
Short name T439
Test name
Test status
Simulation time 559117700 ps
CPU time 7.34 seconds
Started Jul 01 06:33:48 PM PDT 24
Finished Jul 01 06:33:56 PM PDT 24
Peak memory 233768 kb
Host smart-b32bdcfb-dfc7-45ed-997c-06b25985861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316607790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1316607790
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2732102071
Short name T579
Test name
Test status
Simulation time 21483063 ps
CPU time 0.77 seconds
Started Jul 01 06:33:43 PM PDT 24
Finished Jul 01 06:33:45 PM PDT 24
Peak memory 206484 kb
Host smart-d31cddae-29da-47ec-9a9b-dbb911a627b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732102071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2732102071
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1111126564
Short name T270
Test name
Test status
Simulation time 66581247208 ps
CPU time 176.08 seconds
Started Jul 01 06:33:49 PM PDT 24
Finished Jul 01 06:36:46 PM PDT 24
Peak memory 257288 kb
Host smart-8778400d-bd0a-4eb3-8eb3-6ea0bc5514fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111126564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1111126564
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.308156985
Short name T252
Test name
Test status
Simulation time 17264018084 ps
CPU time 65.19 seconds
Started Jul 01 06:33:48 PM PDT 24
Finished Jul 01 06:34:54 PM PDT 24
Peak memory 255136 kb
Host smart-8a82cb0f-ad06-499d-bf12-c061fe37a432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308156985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.308156985
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2976502927
Short name T245
Test name
Test status
Simulation time 273301027 ps
CPU time 3.71 seconds
Started Jul 01 06:33:49 PM PDT 24
Finished Jul 01 06:33:54 PM PDT 24
Peak memory 225524 kb
Host smart-b354bf2a-c0cf-4cc7-b3db-6ff24ceb0200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976502927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2976502927
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1157214816
Short name T888
Test name
Test status
Simulation time 3899961676 ps
CPU time 19.28 seconds
Started Jul 01 06:33:53 PM PDT 24
Finished Jul 01 06:34:13 PM PDT 24
Peak memory 250460 kb
Host smart-4c614f2e-5b02-400b-9492-bec7091fa30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157214816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1157214816
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1011657256
Short name T181
Test name
Test status
Simulation time 30425213321 ps
CPU time 22.54 seconds
Started Jul 01 06:33:52 PM PDT 24
Finished Jul 01 06:34:16 PM PDT 24
Peak memory 233956 kb
Host smart-c728e178-90d3-4948-8cb5-3b89c2cd60ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011657256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1011657256
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1560703512
Short name T843
Test name
Test status
Simulation time 392693721 ps
CPU time 7.11 seconds
Started Jul 01 06:33:49 PM PDT 24
Finished Jul 01 06:33:58 PM PDT 24
Peak memory 233800 kb
Host smart-21b34a89-a21f-47bf-8ec4-4a8872f1cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560703512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1560703512
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.237563290
Short name T508
Test name
Test status
Simulation time 1901984399 ps
CPU time 7.26 seconds
Started Jul 01 06:33:48 PM PDT 24
Finished Jul 01 06:33:57 PM PDT 24
Peak memory 233784 kb
Host smart-711442cd-2579-4b64-906f-9704745b7401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237563290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.237563290
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.44838794
Short name T847
Test name
Test status
Simulation time 19390398108 ps
CPU time 15.64 seconds
Started Jul 01 06:33:48 PM PDT 24
Finished Jul 01 06:34:05 PM PDT 24
Peak memory 225728 kb
Host smart-478ecc56-e5ba-409f-8fa8-a04905bcd003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44838794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.44838794
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1389479856
Short name T429
Test name
Test status
Simulation time 5975761302 ps
CPU time 16 seconds
Started Jul 01 06:33:48 PM PDT 24
Finished Jul 01 06:34:05 PM PDT 24
Peak memory 220536 kb
Host smart-aa72ac15-e8f2-419c-969c-694c3aebe443
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1389479856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1389479856
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1970264849
Short name T19
Test name
Test status
Simulation time 185959909 ps
CPU time 0.95 seconds
Started Jul 01 06:33:51 PM PDT 24
Finished Jul 01 06:33:54 PM PDT 24
Peak memory 207532 kb
Host smart-3dae4be0-32d3-4a27-a4af-99b8a8c3ae04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970264849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1970264849
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2737555646
Short name T478
Test name
Test status
Simulation time 48623500 ps
CPU time 0.73 seconds
Started Jul 01 06:33:43 PM PDT 24
Finished Jul 01 06:33:46 PM PDT 24
Peak memory 206648 kb
Host smart-5f6c1dff-d437-4175-8e80-3f1f976e2010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737555646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2737555646
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2419380585
Short name T623
Test name
Test status
Simulation time 20885826801 ps
CPU time 10.73 seconds
Started Jul 01 06:33:43 PM PDT 24
Finished Jul 01 06:33:55 PM PDT 24
Peak memory 217496 kb
Host smart-68fa068c-751d-45d0-ac30-311f6deb0549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419380585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2419380585
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3557510235
Short name T815
Test name
Test status
Simulation time 116590808 ps
CPU time 1.54 seconds
Started Jul 01 06:33:43 PM PDT 24
Finished Jul 01 06:33:46 PM PDT 24
Peak memory 217360 kb
Host smart-895c8e58-c514-4e79-b230-182c38db5d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557510235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3557510235
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.495835335
Short name T686
Test name
Test status
Simulation time 441479568 ps
CPU time 0.83 seconds
Started Jul 01 06:33:42 PM PDT 24
Finished Jul 01 06:33:45 PM PDT 24
Peak memory 207072 kb
Host smart-1e8b86f6-c328-4a42-8acc-88537bceef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495835335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.495835335
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.784584015
Short name T50
Test name
Test status
Simulation time 4938793919 ps
CPU time 10.49 seconds
Started Jul 01 06:33:49 PM PDT 24
Finished Jul 01 06:34:00 PM PDT 24
Peak memory 225700 kb
Host smart-40080745-72f7-41a3-8b64-bbaef0a86202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784584015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.784584015
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4090301749
Short name T630
Test name
Test status
Simulation time 20062243 ps
CPU time 0.73 seconds
Started Jul 01 06:34:01 PM PDT 24
Finished Jul 01 06:34:03 PM PDT 24
Peak memory 206380 kb
Host smart-79541538-a09b-4c07-b7b5-efd35321bced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090301749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4090301749
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1428966018
Short name T655
Test name
Test status
Simulation time 905960119 ps
CPU time 6.4 seconds
Started Jul 01 06:33:52 PM PDT 24
Finished Jul 01 06:34:00 PM PDT 24
Peak memory 225600 kb
Host smart-694eaca9-cb35-4e09-b5b9-bf86dfa5ab9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428966018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1428966018
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3106313980
Short name T375
Test name
Test status
Simulation time 148307021 ps
CPU time 0.82 seconds
Started Jul 01 06:33:50 PM PDT 24
Finished Jul 01 06:33:52 PM PDT 24
Peak memory 207540 kb
Host smart-b1dec5d0-c6c3-4b50-8771-85e81c6f00db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106313980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3106313980
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.220244088
Short name T211
Test name
Test status
Simulation time 4031146342 ps
CPU time 70.19 seconds
Started Jul 01 06:33:58 PM PDT 24
Finished Jul 01 06:35:09 PM PDT 24
Peak memory 257780 kb
Host smart-f6e7b1c9-4711-430c-b51f-5e22e5144b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220244088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.220244088
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3699774371
Short name T332
Test name
Test status
Simulation time 48906600331 ps
CPU time 101.56 seconds
Started Jul 01 06:33:59 PM PDT 24
Finished Jul 01 06:35:41 PM PDT 24
Peak memory 252088 kb
Host smart-3fbe8383-2fed-46b8-aba6-bf76225e0658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699774371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3699774371
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.783031642
Short name T335
Test name
Test status
Simulation time 2102494112 ps
CPU time 15.23 seconds
Started Jul 01 06:33:59 PM PDT 24
Finished Jul 01 06:34:15 PM PDT 24
Peak memory 218624 kb
Host smart-78db0cf3-2de7-4685-9e2d-7d535ba141b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783031642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.783031642
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.609358432
Short name T963
Test name
Test status
Simulation time 4013519469 ps
CPU time 21.24 seconds
Started Jul 01 06:33:58 PM PDT 24
Finished Jul 01 06:34:21 PM PDT 24
Peak memory 233868 kb
Host smart-5a53b431-9e10-4552-8bc6-445eb89a3545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609358432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.609358432
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1792918139
Short name T310
Test name
Test status
Simulation time 143169042289 ps
CPU time 266.32 seconds
Started Jul 01 06:33:57 PM PDT 24
Finished Jul 01 06:38:25 PM PDT 24
Peak memory 269044 kb
Host smart-066b347d-ed6a-45ee-9a1f-dc158c3b698d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792918139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1792918139
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2705416095
Short name T626
Test name
Test status
Simulation time 2934038255 ps
CPU time 27.72 seconds
Started Jul 01 06:33:53 PM PDT 24
Finished Jul 01 06:34:22 PM PDT 24
Peak memory 232048 kb
Host smart-6d8f8cd7-8d36-4e6d-9f00-ea0a00e55db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705416095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2705416095
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2480453053
Short name T635
Test name
Test status
Simulation time 141670362 ps
CPU time 2.29 seconds
Started Jul 01 06:33:51 PM PDT 24
Finished Jul 01 06:33:55 PM PDT 24
Peak memory 224692 kb
Host smart-c8824fff-b8c2-4d6f-8795-1c0a670f2458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480453053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2480453053
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1210124058
Short name T61
Test name
Test status
Simulation time 10063016057 ps
CPU time 10.12 seconds
Started Jul 01 06:33:51 PM PDT 24
Finished Jul 01 06:34:03 PM PDT 24
Peak memory 233896 kb
Host smart-6dfbb2a1-66cd-40be-b49a-b9e3ea9197a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210124058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1210124058
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.309453791
Short name T532
Test name
Test status
Simulation time 2671580426 ps
CPU time 6.39 seconds
Started Jul 01 06:33:51 PM PDT 24
Finished Jul 01 06:33:59 PM PDT 24
Peak memory 225720 kb
Host smart-599a184e-7c52-4859-aab1-99c369f28774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309453791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.309453791
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3946476697
Short name T1006
Test name
Test status
Simulation time 1097806869 ps
CPU time 4.26 seconds
Started Jul 01 06:33:58 PM PDT 24
Finished Jul 01 06:34:03 PM PDT 24
Peak memory 219860 kb
Host smart-85205ff4-0ba1-4971-bec5-cb213e75cd13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3946476697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3946476697
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4143857085
Short name T37
Test name
Test status
Simulation time 14298657618 ps
CPU time 24.48 seconds
Started Jul 01 06:34:03 PM PDT 24
Finished Jul 01 06:34:28 PM PDT 24
Peak memory 218892 kb
Host smart-abda718c-51e3-4015-8915-891b083308d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143857085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4143857085
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.478934119
Short name T811
Test name
Test status
Simulation time 2379677762 ps
CPU time 15.79 seconds
Started Jul 01 06:33:50 PM PDT 24
Finished Jul 01 06:34:07 PM PDT 24
Peak memory 217452 kb
Host smart-7d33133d-b34e-4c95-8286-c969a6530142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478934119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.478934119
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3654112170
Short name T829
Test name
Test status
Simulation time 23164571468 ps
CPU time 14.66 seconds
Started Jul 01 06:33:47 PM PDT 24
Finished Jul 01 06:34:02 PM PDT 24
Peak memory 217572 kb
Host smart-918c2a42-485a-4780-a6e7-bd915b0c6dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654112170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3654112170
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3430853354
Short name T856
Test name
Test status
Simulation time 203277085 ps
CPU time 6.98 seconds
Started Jul 01 06:33:54 PM PDT 24
Finished Jul 01 06:34:02 PM PDT 24
Peak memory 217320 kb
Host smart-ffef5d17-cc79-463f-a9a9-5ed1a693fcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430853354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3430853354
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2806223995
Short name T665
Test name
Test status
Simulation time 76776210 ps
CPU time 0.81 seconds
Started Jul 01 06:33:51 PM PDT 24
Finished Jul 01 06:33:53 PM PDT 24
Peak memory 206976 kb
Host smart-14c4227c-15ad-4ea1-9019-421e8db56e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806223995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2806223995
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2657770341
Short name T1017
Test name
Test status
Simulation time 1557228856 ps
CPU time 7.67 seconds
Started Jul 01 06:33:51 PM PDT 24
Finished Jul 01 06:34:01 PM PDT 24
Peak memory 250040 kb
Host smart-a0ff973e-2b78-4c1f-8f47-21540979d334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657770341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2657770341
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.862789575
Short name T993
Test name
Test status
Simulation time 24381272 ps
CPU time 0.71 seconds
Started Jul 01 06:34:09 PM PDT 24
Finished Jul 01 06:34:11 PM PDT 24
Peak memory 206484 kb
Host smart-53da2cc4-cf9e-4d7e-bb8b-7b4609a12074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862789575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.862789575
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3295006585
Short name T937
Test name
Test status
Simulation time 15861316016 ps
CPU time 21.74 seconds
Started Jul 01 06:34:07 PM PDT 24
Finished Jul 01 06:34:30 PM PDT 24
Peak memory 225672 kb
Host smart-dab573e4-d204-4a9d-80e9-e4516e2982b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295006585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3295006585
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3768021110
Short name T392
Test name
Test status
Simulation time 34889652 ps
CPU time 0.82 seconds
Started Jul 01 06:34:01 PM PDT 24
Finished Jul 01 06:34:03 PM PDT 24
Peak memory 207856 kb
Host smart-cefc3d81-7ffb-46cb-81b6-ea6e1b592a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768021110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3768021110
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3730654696
Short name T242
Test name
Test status
Simulation time 21761148681 ps
CPU time 219.2 seconds
Started Jul 01 06:34:07 PM PDT 24
Finished Jul 01 06:37:48 PM PDT 24
Peak memory 266036 kb
Host smart-80de6927-44b7-4ec1-bc3f-a2c1bb38e69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730654696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3730654696
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1623036258
Short name T331
Test name
Test status
Simulation time 8690562884 ps
CPU time 16.4 seconds
Started Jul 01 06:34:08 PM PDT 24
Finished Jul 01 06:34:26 PM PDT 24
Peak memory 218856 kb
Host smart-008f24c8-f2fe-4e33-9064-e4674fcae7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623036258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1623036258
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2166989285
Short name T333
Test name
Test status
Simulation time 27026265011 ps
CPU time 298.1 seconds
Started Jul 01 06:34:10 PM PDT 24
Finished Jul 01 06:39:10 PM PDT 24
Peak memory 260528 kb
Host smart-c718c90d-19d7-4702-8807-b921c0a4c39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166989285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2166989285
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4203596169
Short name T674
Test name
Test status
Simulation time 1698860188 ps
CPU time 16.02 seconds
Started Jul 01 06:34:07 PM PDT 24
Finished Jul 01 06:34:24 PM PDT 24
Peak memory 234872 kb
Host smart-6169e99c-9fce-4db6-be1b-fd4af1ef8e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203596169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4203596169
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.808415396
Short name T96
Test name
Test status
Simulation time 6879686755 ps
CPU time 50.74 seconds
Started Jul 01 06:34:09 PM PDT 24
Finished Jul 01 06:35:01 PM PDT 24
Peak memory 258348 kb
Host smart-ad18ae97-78c0-4c96-b407-bdbd9763b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808415396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.808415396
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.563812149
Short name T393
Test name
Test status
Simulation time 247180114 ps
CPU time 3.54 seconds
Started Jul 01 06:34:05 PM PDT 24
Finished Jul 01 06:34:10 PM PDT 24
Peak memory 233712 kb
Host smart-7355fc37-5f4a-42e2-96f6-ab6730ea10d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563812149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.563812149
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3097459075
Short name T615
Test name
Test status
Simulation time 1182718402 ps
CPU time 16.89 seconds
Started Jul 01 06:34:05 PM PDT 24
Finished Jul 01 06:34:23 PM PDT 24
Peak memory 225568 kb
Host smart-b36ac048-d5d1-4fbb-81af-be5da9777746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097459075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3097459075
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2386912148
Short name T472
Test name
Test status
Simulation time 387251733 ps
CPU time 6.5 seconds
Started Jul 01 06:34:07 PM PDT 24
Finished Jul 01 06:34:14 PM PDT 24
Peak memory 233820 kb
Host smart-4ceb4d95-41aa-4c30-8928-fe4510a82cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386912148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2386912148
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1281832634
Short name T258
Test name
Test status
Simulation time 6724487004 ps
CPU time 24.36 seconds
Started Jul 01 06:34:02 PM PDT 24
Finished Jul 01 06:34:27 PM PDT 24
Peak memory 225748 kb
Host smart-12a31e68-1af1-49f5-a9c5-a3682f3aeb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281832634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1281832634
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.56269717
Short name T533
Test name
Test status
Simulation time 1021287636 ps
CPU time 10.52 seconds
Started Jul 01 06:34:08 PM PDT 24
Finished Jul 01 06:34:20 PM PDT 24
Peak memory 223008 kb
Host smart-3762388a-62ff-4510-8b9f-5742ef616d2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=56269717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direc
t.56269717
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2806038460
Short name T874
Test name
Test status
Simulation time 38044228 ps
CPU time 0.93 seconds
Started Jul 01 06:34:07 PM PDT 24
Finished Jul 01 06:34:09 PM PDT 24
Peak memory 206664 kb
Host smart-deaaf31b-9e82-4c9b-a7af-45e23cc194c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806038460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2806038460
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1727529996
Short name T800
Test name
Test status
Simulation time 32917829315 ps
CPU time 42.78 seconds
Started Jul 01 06:34:02 PM PDT 24
Finished Jul 01 06:34:46 PM PDT 24
Peak memory 217576 kb
Host smart-5dc1f94b-9624-4848-a499-b06c230174fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727529996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1727529996
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2709426308
Short name T1023
Test name
Test status
Simulation time 6110682990 ps
CPU time 7.77 seconds
Started Jul 01 06:34:04 PM PDT 24
Finished Jul 01 06:34:13 PM PDT 24
Peak memory 217544 kb
Host smart-94efda10-c6f7-4382-ae17-6ae9d47af00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709426308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2709426308
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3091326986
Short name T415
Test name
Test status
Simulation time 61020584 ps
CPU time 0.82 seconds
Started Jul 01 06:34:07 PM PDT 24
Finished Jul 01 06:34:08 PM PDT 24
Peak memory 207948 kb
Host smart-83e8110f-0018-4ac2-9cf8-9291cde3b39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091326986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3091326986
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.833832621
Short name T369
Test name
Test status
Simulation time 14557837 ps
CPU time 0.78 seconds
Started Jul 01 06:34:02 PM PDT 24
Finished Jul 01 06:34:04 PM PDT 24
Peak memory 206980 kb
Host smart-7abccbe4-c3d3-40f6-997c-42a9d1724678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833832621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.833832621
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3976629750
Short name T989
Test name
Test status
Simulation time 574938346 ps
CPU time 10.74 seconds
Started Jul 01 06:34:05 PM PDT 24
Finished Jul 01 06:34:17 PM PDT 24
Peak memory 241668 kb
Host smart-4812c1eb-38cc-4905-a84a-44d3225aae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976629750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3976629750
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2153178380
Short name T360
Test name
Test status
Simulation time 37128255 ps
CPU time 0.72 seconds
Started Jul 01 06:34:20 PM PDT 24
Finished Jul 01 06:34:26 PM PDT 24
Peak memory 206740 kb
Host smart-3a2fd7c7-eb3b-481b-8dd2-fd9310894418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153178380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2153178380
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.318837849
Short name T384
Test name
Test status
Simulation time 7906622487 ps
CPU time 16.65 seconds
Started Jul 01 06:34:19 PM PDT 24
Finished Jul 01 06:34:40 PM PDT 24
Peak memory 225760 kb
Host smart-48c8d22d-063e-4158-bf61-865b08ab8ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318837849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.318837849
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2043284579
Short name T419
Test name
Test status
Simulation time 26919994 ps
CPU time 0.79 seconds
Started Jul 01 06:34:08 PM PDT 24
Finished Jul 01 06:34:10 PM PDT 24
Peak memory 207812 kb
Host smart-ab54de62-0728-4ad8-a3e1-c485d16b2e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043284579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2043284579
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3903264984
Short name T52
Test name
Test status
Simulation time 3906598383 ps
CPU time 28.51 seconds
Started Jul 01 06:34:16 PM PDT 24
Finished Jul 01 06:34:49 PM PDT 24
Peak memory 225772 kb
Host smart-3f06d558-a151-4010-9ce7-0fe37e734519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903264984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3903264984
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.200423601
Short name T286
Test name
Test status
Simulation time 17766389226 ps
CPU time 147.84 seconds
Started Jul 01 06:34:17 PM PDT 24
Finished Jul 01 06:36:50 PM PDT 24
Peak memory 258604 kb
Host smart-1e950c6a-38a7-4cea-95e2-e5be4e605322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200423601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.200423601
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3973996391
Short name T978
Test name
Test status
Simulation time 5226781864 ps
CPU time 112.62 seconds
Started Jul 01 06:34:18 PM PDT 24
Finished Jul 01 06:36:15 PM PDT 24
Peak memory 258640 kb
Host smart-ce5260d5-1ba9-440a-8aa0-4833b6fbb35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973996391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3973996391
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3697700148
Short name T1014
Test name
Test status
Simulation time 3899736799 ps
CPU time 61.55 seconds
Started Jul 01 06:34:16 PM PDT 24
Finished Jul 01 06:35:22 PM PDT 24
Peak memory 242144 kb
Host smart-e660587c-85f4-4b26-a5ae-d5aa5afc9b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697700148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3697700148
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.4258806769
Short name T943
Test name
Test status
Simulation time 7424036173 ps
CPU time 42.15 seconds
Started Jul 01 06:34:16 PM PDT 24
Finished Jul 01 06:35:03 PM PDT 24
Peak memory 240144 kb
Host smart-8186dc3c-282d-4979-9af9-ad403e3c5061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258806769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.4258806769
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.672822727
Short name T229
Test name
Test status
Simulation time 6881058165 ps
CPU time 24.64 seconds
Started Jul 01 06:34:17 PM PDT 24
Finished Jul 01 06:34:46 PM PDT 24
Peak memory 225700 kb
Host smart-33eed325-7ce3-45b7-9f6a-264cb7494d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672822727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.672822727
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3354332467
Short name T961
Test name
Test status
Simulation time 12240652596 ps
CPU time 16.43 seconds
Started Jul 01 06:34:18 PM PDT 24
Finished Jul 01 06:34:39 PM PDT 24
Peak memory 225656 kb
Host smart-3fb0dfdd-165c-4430-86dd-dd16cf5a9efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354332467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3354332467
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3878841049
Short name T231
Test name
Test status
Simulation time 2739910519 ps
CPU time 11.93 seconds
Started Jul 01 06:34:17 PM PDT 24
Finished Jul 01 06:34:34 PM PDT 24
Peak memory 233928 kb
Host smart-1f67f66e-7929-4d3d-a5e7-542ef0a051fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878841049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3878841049
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3573299095
Short name T606
Test name
Test status
Simulation time 67374536629 ps
CPU time 21.26 seconds
Started Jul 01 06:34:16 PM PDT 24
Finished Jul 01 06:34:43 PM PDT 24
Peak memory 225760 kb
Host smart-a12eaea3-c4f9-4395-9bad-e24507ce0b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573299095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3573299095
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.178999683
Short name T413
Test name
Test status
Simulation time 761745338 ps
CPU time 4.1 seconds
Started Jul 01 06:34:19 PM PDT 24
Finished Jul 01 06:34:28 PM PDT 24
Peak memory 220940 kb
Host smart-20a7865c-f1d6-4138-a420-1289f71a3748
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=178999683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.178999683
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3500732689
Short name T846
Test name
Test status
Simulation time 10405882791 ps
CPU time 15.4 seconds
Started Jul 01 06:34:07 PM PDT 24
Finished Jul 01 06:34:23 PM PDT 24
Peak memory 217680 kb
Host smart-fa8cbe14-e0e7-40e8-9bd1-fb24505b2d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500732689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3500732689
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.4277897253
Short name T459
Test name
Test status
Simulation time 1027486851 ps
CPU time 5.44 seconds
Started Jul 01 06:34:07 PM PDT 24
Finished Jul 01 06:34:14 PM PDT 24
Peak memory 217364 kb
Host smart-534aa34a-fdd3-4419-abf2-8b604dc84a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277897253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4277897253
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.63702465
Short name T909
Test name
Test status
Simulation time 204998364 ps
CPU time 1.07 seconds
Started Jul 01 06:34:16 PM PDT 24
Finished Jul 01 06:34:22 PM PDT 24
Peak memory 209072 kb
Host smart-b6a1d75c-c5ca-4392-ab5e-f1c353a0d0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63702465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.63702465
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2599676373
Short name T705
Test name
Test status
Simulation time 269347989 ps
CPU time 0.96 seconds
Started Jul 01 06:34:16 PM PDT 24
Finished Jul 01 06:34:22 PM PDT 24
Peak memory 207404 kb
Host smart-ed59ef17-3422-45a6-9c0d-22a66a420a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599676373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2599676373
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.4234179563
Short name T254
Test name
Test status
Simulation time 17130791392 ps
CPU time 15.5 seconds
Started Jul 01 06:34:17 PM PDT 24
Finished Jul 01 06:34:37 PM PDT 24
Peak memory 225672 kb
Host smart-55959030-65ed-4b7a-967b-1935f47b56e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234179563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4234179563
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2156965673
Short name T83
Test name
Test status
Simulation time 47862485 ps
CPU time 0.72 seconds
Started Jul 01 06:34:25 PM PDT 24
Finished Jul 01 06:34:32 PM PDT 24
Peak memory 206428 kb
Host smart-cd237ede-d512-4055-ad52-539b368b30c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156965673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2156965673
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.506513133
Short name T5
Test name
Test status
Simulation time 972066220 ps
CPU time 4.6 seconds
Started Jul 01 06:34:28 PM PDT 24
Finished Jul 01 06:34:37 PM PDT 24
Peak memory 233712 kb
Host smart-a9cee7fa-852d-40f0-ad80-f3c3374141c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506513133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.506513133
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4191996751
Short name T825
Test name
Test status
Simulation time 37715256 ps
CPU time 0.77 seconds
Started Jul 01 06:34:16 PM PDT 24
Finished Jul 01 06:34:21 PM PDT 24
Peak memory 207488 kb
Host smart-2c00404d-0094-44f2-a433-3d61cfc8fdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191996751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4191996751
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.893330318
Short name T212
Test name
Test status
Simulation time 5052912722 ps
CPU time 53.59 seconds
Started Jul 01 06:34:21 PM PDT 24
Finished Jul 01 06:35:20 PM PDT 24
Peak memory 258020 kb
Host smart-a9004bf6-3733-4dfe-8354-6195b2098644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893330318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.893330318
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.267384340
Short name T45
Test name
Test status
Simulation time 3898389421 ps
CPU time 41.44 seconds
Started Jul 01 06:34:24 PM PDT 24
Finished Jul 01 06:35:12 PM PDT 24
Peak memory 234204 kb
Host smart-a2770584-1397-45ba-89b4-43bcccd0bb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267384340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.267384340
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2462046004
Short name T917
Test name
Test status
Simulation time 14412908867 ps
CPU time 80.32 seconds
Started Jul 01 06:34:23 PM PDT 24
Finished Jul 01 06:35:50 PM PDT 24
Peak memory 250900 kb
Host smart-d6475990-0636-461c-b601-812da08b5fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462046004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2462046004
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3604142018
Short name T603
Test name
Test status
Simulation time 2966907243 ps
CPU time 13.7 seconds
Started Jul 01 06:34:28 PM PDT 24
Finished Jul 01 06:34:46 PM PDT 24
Peak memory 241988 kb
Host smart-2ea938a8-3648-42ce-bb63-e31710452279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604142018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3604142018
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2052977334
Short name T269
Test name
Test status
Simulation time 69352887631 ps
CPU time 140.77 seconds
Started Jul 01 06:34:23 PM PDT 24
Finished Jul 01 06:36:50 PM PDT 24
Peak memory 250300 kb
Host smart-a41f6364-cb6e-48c3-90f8-91f2d4cea482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052977334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2052977334
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2196393046
Short name T511
Test name
Test status
Simulation time 2011043089 ps
CPU time 18.46 seconds
Started Jul 01 06:34:21 PM PDT 24
Finished Jul 01 06:34:44 PM PDT 24
Peak memory 233824 kb
Host smart-17953104-8e42-4a75-abef-530003f3bbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196393046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2196393046
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2224808140
Short name T420
Test name
Test status
Simulation time 4128159955 ps
CPU time 44.67 seconds
Started Jul 01 06:34:22 PM PDT 24
Finished Jul 01 06:35:12 PM PDT 24
Peak memory 225696 kb
Host smart-15a45e84-8ca4-41cd-99e4-49c74ae5ebd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224808140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2224808140
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3776803561
Short name T653
Test name
Test status
Simulation time 126318145 ps
CPU time 2.34 seconds
Started Jul 01 06:34:22 PM PDT 24
Finished Jul 01 06:34:30 PM PDT 24
Peak memory 233596 kb
Host smart-20047e87-b0a8-4b42-8473-84e1ffd9a164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776803561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3776803561
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2934143714
Short name T699
Test name
Test status
Simulation time 1427723036 ps
CPU time 4.4 seconds
Started Jul 01 06:34:25 PM PDT 24
Finished Jul 01 06:34:35 PM PDT 24
Peak memory 225588 kb
Host smart-3fa63ce5-dfd9-4111-8978-d8d2c25f5ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934143714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2934143714
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1071450122
Short name T1004
Test name
Test status
Simulation time 7479016447 ps
CPU time 10.36 seconds
Started Jul 01 06:34:23 PM PDT 24
Finished Jul 01 06:34:38 PM PDT 24
Peak memory 220132 kb
Host smart-371cab18-4f7a-4e3b-bdf1-b023b19574e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1071450122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1071450122
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2454337344
Short name T647
Test name
Test status
Simulation time 127618272010 ps
CPU time 195.14 seconds
Started Jul 01 06:34:23 PM PDT 24
Finished Jul 01 06:37:45 PM PDT 24
Peak memory 272564 kb
Host smart-82da7b90-5dcd-42a9-a156-d8dec6bfb507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454337344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2454337344
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.552938624
Short name T710
Test name
Test status
Simulation time 1712944073 ps
CPU time 10.44 seconds
Started Jul 01 06:34:20 PM PDT 24
Finished Jul 01 06:34:35 PM PDT 24
Peak memory 217432 kb
Host smart-ad7434d4-a6fd-4881-bed0-92e95ae14474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552938624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.552938624
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3806116835
Short name T649
Test name
Test status
Simulation time 1342797385 ps
CPU time 7.19 seconds
Started Jul 01 06:34:16 PM PDT 24
Finished Jul 01 06:34:28 PM PDT 24
Peak memory 217368 kb
Host smart-05204710-e5ac-4ea8-9617-275a6fac3d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806116835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3806116835
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3408230391
Short name T967
Test name
Test status
Simulation time 643143260 ps
CPU time 7.1 seconds
Started Jul 01 06:34:22 PM PDT 24
Finished Jul 01 06:34:34 PM PDT 24
Peak memory 217380 kb
Host smart-b6521ce3-6380-4f73-ba31-ae119986ce70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408230391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3408230391
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4164876658
Short name T463
Test name
Test status
Simulation time 69869647 ps
CPU time 0.82 seconds
Started Jul 01 06:34:15 PM PDT 24
Finished Jul 01 06:34:21 PM PDT 24
Peak memory 206984 kb
Host smart-923949d8-f94a-43fd-9b9c-9fe6ae23cf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164876658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4164876658
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4032501708
Short name T767
Test name
Test status
Simulation time 4104521932 ps
CPU time 8.92 seconds
Started Jul 01 06:34:22 PM PDT 24
Finished Jul 01 06:34:36 PM PDT 24
Peak memory 233900 kb
Host smart-712d78eb-74a4-455d-a6e1-9e647f4342f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032501708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4032501708
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3628173607
Short name T372
Test name
Test status
Simulation time 22621259 ps
CPU time 0.74 seconds
Started Jul 01 06:28:17 PM PDT 24
Finished Jul 01 06:28:19 PM PDT 24
Peak memory 206724 kb
Host smart-f43f12b5-7450-4323-8600-06990237e2aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628173607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
628173607
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2157743700
Short name T553
Test name
Test status
Simulation time 29054034 ps
CPU time 2.05 seconds
Started Jul 01 06:28:12 PM PDT 24
Finished Jul 01 06:28:16 PM PDT 24
Peak memory 225268 kb
Host smart-71263375-0a96-417a-b4f6-09a412cd4974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157743700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2157743700
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3421168612
Short name T1010
Test name
Test status
Simulation time 31875862 ps
CPU time 0.73 seconds
Started Jul 01 06:28:03 PM PDT 24
Finished Jul 01 06:28:05 PM PDT 24
Peak memory 206888 kb
Host smart-b4fa237f-9a39-4abd-8b9d-a5eb8990b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421168612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3421168612
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2124774358
Short name T862
Test name
Test status
Simulation time 5502487897 ps
CPU time 26.05 seconds
Started Jul 01 06:28:13 PM PDT 24
Finished Jul 01 06:28:40 PM PDT 24
Peak memory 242156 kb
Host smart-413203d8-183d-4cfb-9c01-3fe8a2e0c7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124774358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2124774358
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3266955475
Short name T927
Test name
Test status
Simulation time 169930213587 ps
CPU time 406.56 seconds
Started Jul 01 06:28:11 PM PDT 24
Finished Jul 01 06:34:59 PM PDT 24
Peak memory 250480 kb
Host smart-4a513c6d-e598-46f8-9826-cc637d5ea20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266955475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3266955475
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.470469043
Short name T150
Test name
Test status
Simulation time 182392318 ps
CPU time 7.73 seconds
Started Jul 01 06:28:15 PM PDT 24
Finished Jul 01 06:28:24 PM PDT 24
Peak memory 235956 kb
Host smart-3cf18e66-3ba8-43eb-90e9-75a132d7fe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470469043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.470469043
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.603764991
Short name T721
Test name
Test status
Simulation time 1602868751 ps
CPU time 37.43 seconds
Started Jul 01 06:28:13 PM PDT 24
Finished Jul 01 06:28:51 PM PDT 24
Peak memory 251196 kb
Host smart-0cd1e1b0-2020-4bab-9c5c-a76421c92b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603764991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
603764991
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3178780757
Short name T964
Test name
Test status
Simulation time 4135954374 ps
CPU time 19.96 seconds
Started Jul 01 06:28:08 PM PDT 24
Finished Jul 01 06:28:29 PM PDT 24
Peak memory 234016 kb
Host smart-de1018ef-9419-47b9-9be0-e011bf4236cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178780757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3178780757
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3302833969
Short name T748
Test name
Test status
Simulation time 259560928 ps
CPU time 3.09 seconds
Started Jul 01 06:28:15 PM PDT 24
Finished Jul 01 06:28:19 PM PDT 24
Peak memory 233848 kb
Host smart-3f2aeeaf-3137-4ada-b1d9-3b883aaee740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302833969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3302833969
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1991513640
Short name T566
Test name
Test status
Simulation time 55955794 ps
CPU time 1.12 seconds
Started Jul 01 06:28:03 PM PDT 24
Finished Jul 01 06:28:05 PM PDT 24
Peak memory 218888 kb
Host smart-aa82bd9d-100c-4027-bcc5-e08b45d578bf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991513640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1991513640
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1166919020
Short name T758
Test name
Test status
Simulation time 564138249 ps
CPU time 4.98 seconds
Started Jul 01 06:28:07 PM PDT 24
Finished Jul 01 06:28:12 PM PDT 24
Peak memory 233780 kb
Host smart-c469ec1a-f777-4911-a4c3-d59ab326e234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166919020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1166919020
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2410917080
Short name T987
Test name
Test status
Simulation time 1735881837 ps
CPU time 10.91 seconds
Started Jul 01 06:28:08 PM PDT 24
Finished Jul 01 06:28:20 PM PDT 24
Peak memory 225620 kb
Host smart-057a92a3-f2bf-401a-a214-dfa080ca2a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410917080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2410917080
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3646045003
Short name T357
Test name
Test status
Simulation time 836610680 ps
CPU time 9.84 seconds
Started Jul 01 06:28:12 PM PDT 24
Finished Jul 01 06:28:23 PM PDT 24
Peak memory 223448 kb
Host smart-1a3229c5-9d8c-4089-b436-fcfaec9ef833
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3646045003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3646045003
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4291647453
Short name T648
Test name
Test status
Simulation time 43371224 ps
CPU time 1.04 seconds
Started Jul 01 06:28:20 PM PDT 24
Finished Jul 01 06:28:21 PM PDT 24
Peak memory 208556 kb
Host smart-a489b47d-3748-4e04-8619-268a20353c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291647453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4291647453
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.181082165
Short name T343
Test name
Test status
Simulation time 1900306203 ps
CPU time 24.7 seconds
Started Jul 01 06:28:07 PM PDT 24
Finished Jul 01 06:28:33 PM PDT 24
Peak memory 217796 kb
Host smart-ed39d236-30ec-40d8-819c-dffa00844649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181082165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.181082165
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2848083600
Short name T676
Test name
Test status
Simulation time 783305569 ps
CPU time 2.19 seconds
Started Jul 01 06:28:04 PM PDT 24
Finished Jul 01 06:28:07 PM PDT 24
Peak memory 217380 kb
Host smart-47f35920-f373-4de0-921a-febbc9cf9564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848083600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2848083600
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3601473387
Short name T454
Test name
Test status
Simulation time 111399888 ps
CPU time 1.25 seconds
Started Jul 01 06:28:08 PM PDT 24
Finished Jul 01 06:28:11 PM PDT 24
Peak memory 209144 kb
Host smart-154b0992-b07d-4098-916b-8696265fd524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601473387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3601473387
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.826045860
Short name T861
Test name
Test status
Simulation time 137962817 ps
CPU time 0.95 seconds
Started Jul 01 06:28:07 PM PDT 24
Finished Jul 01 06:28:09 PM PDT 24
Peak memory 208000 kb
Host smart-af4409bf-be69-46d7-bf06-63e76dfb6048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826045860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.826045860
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.33065169
Short name T4
Test name
Test status
Simulation time 42265463 ps
CPU time 2.31 seconds
Started Jul 01 06:28:11 PM PDT 24
Finished Jul 01 06:28:14 PM PDT 24
Peak memory 233800 kb
Host smart-7d119601-f372-4b53-bccd-c9404b207d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33065169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.33065169
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3496249497
Short name T711
Test name
Test status
Simulation time 33950186 ps
CPU time 0.75 seconds
Started Jul 01 06:28:28 PM PDT 24
Finished Jul 01 06:28:30 PM PDT 24
Peak memory 206408 kb
Host smart-8b5690ab-45d7-48d0-82a6-8ab8a6ed299c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496249497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
496249497
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3361889822
Short name T602
Test name
Test status
Simulation time 126838303 ps
CPU time 2.84 seconds
Started Jul 01 06:28:24 PM PDT 24
Finished Jul 01 06:28:28 PM PDT 24
Peak memory 233760 kb
Host smart-67cf07b3-884a-4e02-a42e-cec23f87b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361889822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3361889822
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2904181756
Short name T659
Test name
Test status
Simulation time 12320358 ps
CPU time 0.74 seconds
Started Jul 01 06:28:19 PM PDT 24
Finished Jul 01 06:28:20 PM PDT 24
Peak memory 206520 kb
Host smart-294edd11-3099-4553-bf5b-23d141234373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904181756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2904181756
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1443286341
Short name T911
Test name
Test status
Simulation time 16845741 ps
CPU time 0.74 seconds
Started Jul 01 06:28:29 PM PDT 24
Finished Jul 01 06:28:30 PM PDT 24
Peak memory 216892 kb
Host smart-87f29201-ba0f-42f9-8721-eed42606e4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443286341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1443286341
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2672373086
Short name T159
Test name
Test status
Simulation time 41345742365 ps
CPU time 390.83 seconds
Started Jul 01 06:28:31 PM PDT 24
Finished Jul 01 06:35:02 PM PDT 24
Peak memory 257260 kb
Host smart-33027c50-0539-40cc-aff4-53c97e9fc354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672373086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2672373086
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1353986242
Short name T1013
Test name
Test status
Simulation time 77910285099 ps
CPU time 27.29 seconds
Started Jul 01 06:28:30 PM PDT 24
Finished Jul 01 06:28:58 PM PDT 24
Peak memory 220992 kb
Host smart-643f64a5-f095-4a43-aa49-e77626fbc1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353986242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1353986242
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3058621347
Short name T1007
Test name
Test status
Simulation time 22081275091 ps
CPU time 78.62 seconds
Started Jul 01 06:28:23 PM PDT 24
Finished Jul 01 06:29:42 PM PDT 24
Peak memory 250280 kb
Host smart-730e73c1-2e2d-4207-b53a-a8f119f81e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058621347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3058621347
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3912835895
Short name T409
Test name
Test status
Simulation time 13391019867 ps
CPU time 45.47 seconds
Started Jul 01 06:28:22 PM PDT 24
Finished Jul 01 06:29:08 PM PDT 24
Peak memory 242488 kb
Host smart-6930c717-b281-45bb-b0cf-62613f47923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912835895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3912835895
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.512125566
Short name T561
Test name
Test status
Simulation time 1285096046 ps
CPU time 5.88 seconds
Started Jul 01 06:28:23 PM PDT 24
Finished Jul 01 06:28:30 PM PDT 24
Peak memory 225568 kb
Host smart-b65831bf-1a63-44fe-baf8-88276c413dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512125566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.512125566
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2141882666
Short name T531
Test name
Test status
Simulation time 6315484387 ps
CPU time 37.23 seconds
Started Jul 01 06:28:23 PM PDT 24
Finished Jul 01 06:29:02 PM PDT 24
Peak memory 233852 kb
Host smart-c052beed-5f46-485b-a55c-79354c2fce4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141882666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2141882666
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.611279175
Short name T749
Test name
Test status
Simulation time 27804202 ps
CPU time 1.1 seconds
Started Jul 01 06:28:19 PM PDT 24
Finished Jul 01 06:28:20 PM PDT 24
Peak memory 217760 kb
Host smart-614cbf4c-0b79-41d9-98c3-27c63fc20412
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611279175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.611279175
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3885514596
Short name T287
Test name
Test status
Simulation time 258055287 ps
CPU time 2.98 seconds
Started Jul 01 06:28:23 PM PDT 24
Finished Jul 01 06:28:28 PM PDT 24
Peak memory 225524 kb
Host smart-c30047ce-fdd6-4d7c-a1e3-9c3e5bd3bda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885514596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3885514596
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1261724319
Short name T276
Test name
Test status
Simulation time 651564458 ps
CPU time 7.38 seconds
Started Jul 01 06:28:24 PM PDT 24
Finished Jul 01 06:28:33 PM PDT 24
Peak memory 233796 kb
Host smart-be2aa1b9-a1d2-45e0-bba9-be22fe5845a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261724319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1261724319
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2303656485
Short name T945
Test name
Test status
Simulation time 807115078 ps
CPU time 11.17 seconds
Started Jul 01 06:28:29 PM PDT 24
Finished Jul 01 06:28:41 PM PDT 24
Peak memory 220352 kb
Host smart-aecacbc6-4bf0-486f-982d-d9cfca38095b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2303656485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2303656485
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.891868364
Short name T180
Test name
Test status
Simulation time 43205111 ps
CPU time 0.97 seconds
Started Jul 01 06:28:30 PM PDT 24
Finished Jul 01 06:28:32 PM PDT 24
Peak memory 207856 kb
Host smart-16b9419f-2d16-4948-b6c3-acf1dea2fa52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891868364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.891868364
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2480500053
Short name T567
Test name
Test status
Simulation time 6493235239 ps
CPU time 11.38 seconds
Started Jul 01 06:28:24 PM PDT 24
Finished Jul 01 06:28:37 PM PDT 24
Peak memory 217556 kb
Host smart-545bd367-2e75-4a36-95d5-c1d362b4bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480500053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2480500053
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3023157700
Short name T900
Test name
Test status
Simulation time 13135709311 ps
CPU time 9.69 seconds
Started Jul 01 06:28:23 PM PDT 24
Finished Jul 01 06:28:34 PM PDT 24
Peak memory 217676 kb
Host smart-e3f464db-ea12-41ba-8642-3fa20b86c42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023157700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3023157700
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2184587255
Short name T745
Test name
Test status
Simulation time 76582111 ps
CPU time 1.01 seconds
Started Jul 01 06:28:23 PM PDT 24
Finished Jul 01 06:28:25 PM PDT 24
Peak memory 208696 kb
Host smart-caf1d810-dd19-48c4-a505-b6a0ff37c757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184587255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2184587255
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1400270634
Short name T374
Test name
Test status
Simulation time 31635597 ps
CPU time 0.74 seconds
Started Jul 01 06:28:23 PM PDT 24
Finished Jul 01 06:28:25 PM PDT 24
Peak memory 206584 kb
Host smart-c8596172-41f2-44c6-8d4b-b5b1956900b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400270634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1400270634
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3828090728
Short name T272
Test name
Test status
Simulation time 761872837 ps
CPU time 7.33 seconds
Started Jul 01 06:28:23 PM PDT 24
Finished Jul 01 06:28:32 PM PDT 24
Peak memory 221828 kb
Host smart-e223360b-e02c-45f3-aae5-7811e4bc34ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828090728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3828090728
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2362715445
Short name T358
Test name
Test status
Simulation time 13314536 ps
CPU time 0.75 seconds
Started Jul 01 06:28:41 PM PDT 24
Finished Jul 01 06:28:43 PM PDT 24
Peak memory 205808 kb
Host smart-f586ca65-211d-4b2a-91b3-df4d51ebdf3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362715445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
362715445
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.388333604
Short name T782
Test name
Test status
Simulation time 529453976 ps
CPU time 3.57 seconds
Started Jul 01 06:28:37 PM PDT 24
Finished Jul 01 06:28:41 PM PDT 24
Peak memory 233756 kb
Host smart-4e4b3841-8e34-4112-837d-45bc530479e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388333604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.388333604
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1228172588
Short name T520
Test name
Test status
Simulation time 15211896 ps
CPU time 0.77 seconds
Started Jul 01 06:28:28 PM PDT 24
Finished Jul 01 06:28:30 PM PDT 24
Peak memory 207840 kb
Host smart-2583db93-6b11-453f-a8bd-d5515276c0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228172588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1228172588
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.993700019
Short name T430
Test name
Test status
Simulation time 528383069 ps
CPU time 10.66 seconds
Started Jul 01 06:28:41 PM PDT 24
Finished Jul 01 06:28:53 PM PDT 24
Peak memory 240828 kb
Host smart-9f4af0fa-3e84-410c-b69a-50a1875229e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993700019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.993700019
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.966360840
Short name T306
Test name
Test status
Simulation time 17354557953 ps
CPU time 190.6 seconds
Started Jul 01 06:28:39 PM PDT 24
Finished Jul 01 06:31:50 PM PDT 24
Peak memory 257552 kb
Host smart-cc6a0019-f56e-41f0-9862-0e9629857f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966360840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.966360840
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.952075157
Short name T708
Test name
Test status
Simulation time 5053491542 ps
CPU time 34.56 seconds
Started Jul 01 06:28:41 PM PDT 24
Finished Jul 01 06:29:16 PM PDT 24
Peak memory 251488 kb
Host smart-6c205fb2-c8eb-4f38-91d3-becf26f0612f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952075157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
952075157
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.296638515
Short name T719
Test name
Test status
Simulation time 1583326892 ps
CPU time 5.03 seconds
Started Jul 01 06:28:38 PM PDT 24
Finished Jul 01 06:28:43 PM PDT 24
Peak memory 225660 kb
Host smart-d4f98276-9ec7-4bbc-8b8b-795f09ea5218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296638515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.296638515
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4220191965
Short name T534
Test name
Test status
Simulation time 55702516163 ps
CPU time 101.96 seconds
Started Jul 01 06:28:35 PM PDT 24
Finished Jul 01 06:30:18 PM PDT 24
Peak memory 258532 kb
Host smart-2df37437-cd4a-4df6-8b60-94f7a0585b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220191965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4220191965
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1997889889
Short name T654
Test name
Test status
Simulation time 7549470999 ps
CPU time 16.27 seconds
Started Jul 01 06:28:36 PM PDT 24
Finished Jul 01 06:28:53 PM PDT 24
Peak memory 225680 kb
Host smart-20170716-a7c8-4445-b4fa-c357d827f1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997889889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1997889889
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.632691211
Short name T614
Test name
Test status
Simulation time 1626041008 ps
CPU time 3.71 seconds
Started Jul 01 06:28:35 PM PDT 24
Finished Jul 01 06:28:40 PM PDT 24
Peak memory 225684 kb
Host smart-f4592a76-611b-43ea-b950-c4d6b2f26cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632691211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.632691211
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2464897975
Short name T809
Test name
Test status
Simulation time 15538565 ps
CPU time 1.04 seconds
Started Jul 01 06:28:28 PM PDT 24
Finished Jul 01 06:28:30 PM PDT 24
Peak memory 217800 kb
Host smart-a9e7a75a-029b-4a61-a6db-1e908eb8f972
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464897975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2464897975
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2689285457
Short name T226
Test name
Test status
Simulation time 3021282396 ps
CPU time 8.61 seconds
Started Jul 01 06:28:36 PM PDT 24
Finished Jul 01 06:28:45 PM PDT 24
Peak memory 233916 kb
Host smart-8b120193-c984-43c0-b398-06d22f8ee2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689285457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2689285457
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2031761792
Short name T597
Test name
Test status
Simulation time 5945326603 ps
CPU time 12.19 seconds
Started Jul 01 06:28:38 PM PDT 24
Finished Jul 01 06:28:51 PM PDT 24
Peak memory 242088 kb
Host smart-7a3c625c-ce50-414b-acda-6ecea460794c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031761792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2031761792
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3669411853
Short name T432
Test name
Test status
Simulation time 9752849519 ps
CPU time 10.06 seconds
Started Jul 01 06:28:40 PM PDT 24
Finished Jul 01 06:28:52 PM PDT 24
Peak memory 219688 kb
Host smart-a1c55643-889b-4793-8841-692d8537ee37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3669411853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3669411853
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.845369362
Short name T499
Test name
Test status
Simulation time 28745154815 ps
CPU time 41.62 seconds
Started Jul 01 06:28:34 PM PDT 24
Finished Jul 01 06:29:16 PM PDT 24
Peak memory 217540 kb
Host smart-87ec18bf-c577-4838-9e58-5bfc123092ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845369362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.845369362
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.774369457
Short name T101
Test name
Test status
Simulation time 4616588985 ps
CPU time 9.5 seconds
Started Jul 01 06:28:37 PM PDT 24
Finished Jul 01 06:28:47 PM PDT 24
Peak memory 217472 kb
Host smart-09851da4-3d4c-41dd-9ed1-1b55e6a9d31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774369457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.774369457
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.247231257
Short name T6
Test name
Test status
Simulation time 92245291 ps
CPU time 1.05 seconds
Started Jul 01 06:28:36 PM PDT 24
Finished Jul 01 06:28:38 PM PDT 24
Peak memory 208948 kb
Host smart-3a8cec0a-6e56-4885-9add-2f9cfd0ecb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247231257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.247231257
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1333744502
Short name T366
Test name
Test status
Simulation time 46522665 ps
CPU time 0.93 seconds
Started Jul 01 06:28:34 PM PDT 24
Finished Jul 01 06:28:36 PM PDT 24
Peak memory 207416 kb
Host smart-968a5886-7387-4124-b1ca-ba84a1e49b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333744502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1333744502
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1999122755
Short name T836
Test name
Test status
Simulation time 384090504 ps
CPU time 2.16 seconds
Started Jul 01 06:28:35 PM PDT 24
Finished Jul 01 06:28:38 PM PDT 24
Peak memory 225364 kb
Host smart-e70f22ef-1c83-4474-ac34-f1e817c0d2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999122755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1999122755
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.345835093
Short name T8
Test name
Test status
Simulation time 36276951 ps
CPU time 0.74 seconds
Started Jul 01 06:28:56 PM PDT 24
Finished Jul 01 06:29:01 PM PDT 24
Peak memory 206760 kb
Host smart-b689f837-b987-4a09-9d70-1fbc3f0b4918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345835093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.345835093
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3095781366
Short name T714
Test name
Test status
Simulation time 56934013 ps
CPU time 1.99 seconds
Started Jul 01 06:28:53 PM PDT 24
Finished Jul 01 06:28:56 PM PDT 24
Peak memory 225516 kb
Host smart-68350a51-fd94-4175-b132-dc1487322118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095781366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3095781366
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1107155588
Short name T995
Test name
Test status
Simulation time 78087284 ps
CPU time 0.8 seconds
Started Jul 01 06:28:43 PM PDT 24
Finished Jul 01 06:28:45 PM PDT 24
Peak memory 207516 kb
Host smart-94bc8a8d-7eaf-40cb-9c29-23ce2d6511ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107155588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1107155588
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1037766459
Short name T481
Test name
Test status
Simulation time 10781344 ps
CPU time 0.74 seconds
Started Jul 01 06:28:53 PM PDT 24
Finished Jul 01 06:28:55 PM PDT 24
Peak memory 216928 kb
Host smart-f959ed86-0505-4df2-bfc3-76313b3cfab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037766459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1037766459
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.322160903
Short name T418
Test name
Test status
Simulation time 118677646138 ps
CPU time 99.28 seconds
Started Jul 01 06:28:51 PM PDT 24
Finished Jul 01 06:30:32 PM PDT 24
Peak memory 251800 kb
Host smart-cbb436fa-7d1a-4843-824f-e2d94a4cd97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322160903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.322160903
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2118944009
Short name T968
Test name
Test status
Simulation time 1989720972 ps
CPU time 28.81 seconds
Started Jul 01 06:28:51 PM PDT 24
Finished Jul 01 06:29:21 PM PDT 24
Peak memory 237728 kb
Host smart-eb8e2d41-a25d-4a8c-b4af-1f7569601cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118944009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2118944009
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2217156725
Short name T728
Test name
Test status
Simulation time 4181546184 ps
CPU time 16.12 seconds
Started Jul 01 06:28:50 PM PDT 24
Finished Jul 01 06:29:08 PM PDT 24
Peak memory 235548 kb
Host smart-a9b9f822-6450-4f09-8d06-d12baea1de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217156725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2217156725
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3667275264
Short name T920
Test name
Test status
Simulation time 113273364026 ps
CPU time 198.38 seconds
Started Jul 01 06:28:53 PM PDT 24
Finished Jul 01 06:32:12 PM PDT 24
Peak memory 264740 kb
Host smart-195af4a3-8cf7-4b05-bc5a-575d17e441df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667275264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3667275264
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2472021619
Short name T222
Test name
Test status
Simulation time 715162737 ps
CPU time 7.47 seconds
Started Jul 01 06:28:51 PM PDT 24
Finished Jul 01 06:29:00 PM PDT 24
Peak memory 233820 kb
Host smart-db521a1d-02a1-4437-b9ba-d03bc21cfd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472021619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2472021619
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1945855137
Short name T971
Test name
Test status
Simulation time 3382410307 ps
CPU time 6.16 seconds
Started Jul 01 06:28:52 PM PDT 24
Finished Jul 01 06:29:00 PM PDT 24
Peak memory 240984 kb
Host smart-f247d3a3-dd65-41a5-86ad-ea929ad3401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945855137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1945855137
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.65878273
Short name T541
Test name
Test status
Simulation time 196995145 ps
CPU time 1.04 seconds
Started Jul 01 06:28:45 PM PDT 24
Finished Jul 01 06:28:47 PM PDT 24
Peak memory 217676 kb
Host smart-3af8ccb1-49e1-4cb4-8273-c0e935d5b4b2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65878273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.65878273
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3043140301
Short name T950
Test name
Test status
Simulation time 4420223629 ps
CPU time 9.49 seconds
Started Jul 01 06:28:45 PM PDT 24
Finished Jul 01 06:28:55 PM PDT 24
Peak memory 225740 kb
Host smart-418d1a10-8110-49bb-9699-f814239d8949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043140301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3043140301
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.223295445
Short name T575
Test name
Test status
Simulation time 1409284844 ps
CPU time 7.38 seconds
Started Jul 01 06:28:43 PM PDT 24
Finished Jul 01 06:28:51 PM PDT 24
Peak memory 233748 kb
Host smart-acf82ebc-570a-4c0d-8560-ec54f6ba1560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223295445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.223295445
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1569843015
Short name T894
Test name
Test status
Simulation time 1415802129 ps
CPU time 12.27 seconds
Started Jul 01 06:28:53 PM PDT 24
Finished Jul 01 06:29:07 PM PDT 24
Peak memory 220396 kb
Host smart-ba3a3e52-54af-4858-aac0-4f5948e2acf8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1569843015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1569843015
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3803918798
Short name T498
Test name
Test status
Simulation time 45157593519 ps
CPU time 192.99 seconds
Started Jul 01 06:28:51 PM PDT 24
Finished Jul 01 06:32:06 PM PDT 24
Peak memory 252564 kb
Host smart-b47defaf-6699-49be-be28-8671c10eed5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803918798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3803918798
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.534215221
Short name T642
Test name
Test status
Simulation time 20519063483 ps
CPU time 9.35 seconds
Started Jul 01 06:28:46 PM PDT 24
Finished Jul 01 06:28:56 PM PDT 24
Peak memory 217484 kb
Host smart-2bc22fd3-6aed-440c-8047-5f3e55b1f6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534215221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.534215221
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.922169383
Short name T1029
Test name
Test status
Simulation time 1112814787 ps
CPU time 3.76 seconds
Started Jul 01 06:28:43 PM PDT 24
Finished Jul 01 06:28:48 PM PDT 24
Peak memory 217416 kb
Host smart-b84dff17-d142-49ea-a581-bc00d6880a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922169383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.922169383
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1917862052
Short name T482
Test name
Test status
Simulation time 32304589 ps
CPU time 1.67 seconds
Started Jul 01 06:28:45 PM PDT 24
Finished Jul 01 06:28:47 PM PDT 24
Peak memory 217364 kb
Host smart-f9403691-d97f-429e-9539-21d59f9f43d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917862052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1917862052
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1456832864
Short name T383
Test name
Test status
Simulation time 361129813 ps
CPU time 0.79 seconds
Started Jul 01 06:28:45 PM PDT 24
Finished Jul 01 06:28:46 PM PDT 24
Peak memory 206976 kb
Host smart-e67cea77-479b-4fbf-a041-c61dcab6653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456832864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1456832864
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1598913483
Short name T572
Test name
Test status
Simulation time 130775863 ps
CPU time 2.67 seconds
Started Jul 01 06:28:50 PM PDT 24
Finished Jul 01 06:28:54 PM PDT 24
Peak memory 225620 kb
Host smart-bca5a279-93fe-4547-9a53-6c185585f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598913483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1598913483
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.733421891
Short name T878
Test name
Test status
Simulation time 123143481 ps
CPU time 0.69 seconds
Started Jul 01 06:29:01 PM PDT 24
Finished Jul 01 06:29:04 PM PDT 24
Peak memory 206376 kb
Host smart-5a45bd41-50bf-4f07-b7b4-594c8bed2c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733421891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.733421891
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3690818270
Short name T577
Test name
Test status
Simulation time 47171500 ps
CPU time 2.58 seconds
Started Jul 01 06:28:58 PM PDT 24
Finished Jul 01 06:29:04 PM PDT 24
Peak memory 233888 kb
Host smart-32de2c2f-005d-4c84-93ba-921c3ef3a350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690818270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3690818270
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2893246730
Short name T522
Test name
Test status
Simulation time 14723279 ps
CPU time 0.86 seconds
Started Jul 01 06:28:59 PM PDT 24
Finished Jul 01 06:29:02 PM PDT 24
Peak memory 207552 kb
Host smart-c59e12b5-2025-4a34-b1ef-5b49abef5943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893246730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2893246730
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1530515111
Short name T593
Test name
Test status
Simulation time 63257488 ps
CPU time 1 seconds
Started Jul 01 06:29:01 PM PDT 24
Finished Jul 01 06:29:05 PM PDT 24
Peak memory 217188 kb
Host smart-2e34389b-a2d8-464c-80b8-f72a8bf7104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530515111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1530515111
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2647838711
Short name T320
Test name
Test status
Simulation time 85878767717 ps
CPU time 338.25 seconds
Started Jul 01 06:29:03 PM PDT 24
Finished Jul 01 06:34:44 PM PDT 24
Peak memory 266444 kb
Host smart-4ab36eaf-b9de-4496-80b7-a05d4017b669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647838711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2647838711
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2670837118
Short name T186
Test name
Test status
Simulation time 14171481929 ps
CPU time 107.61 seconds
Started Jul 01 06:29:03 PM PDT 24
Finished Jul 01 06:30:54 PM PDT 24
Peak memory 250232 kb
Host smart-f4fe6145-e559-4af2-922c-b9864f9a4cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670837118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2670837118
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1654607795
Short name T633
Test name
Test status
Simulation time 852340975 ps
CPU time 14.96 seconds
Started Jul 01 06:29:02 PM PDT 24
Finished Jul 01 06:29:20 PM PDT 24
Peak memory 234864 kb
Host smart-1dfe3c27-2e20-4232-a917-85ea22f53040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654607795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1654607795
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.701587476
Short name T919
Test name
Test status
Simulation time 3580469155 ps
CPU time 44.9 seconds
Started Jul 01 06:29:01 PM PDT 24
Finished Jul 01 06:29:49 PM PDT 24
Peak memory 238580 kb
Host smart-ea28f5e8-d53e-4367-b396-29f78489d5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701587476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
701587476
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3147359238
Short name T787
Test name
Test status
Simulation time 1010485771 ps
CPU time 11.99 seconds
Started Jul 01 06:28:55 PM PDT 24
Finished Jul 01 06:29:09 PM PDT 24
Peak memory 233816 kb
Host smart-5a7ae0d2-1e03-4ea6-8e2e-081dd2c90f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147359238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3147359238
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1972824110
Short name T290
Test name
Test status
Simulation time 2676651049 ps
CPU time 6.73 seconds
Started Jul 01 06:28:55 PM PDT 24
Finished Jul 01 06:29:04 PM PDT 24
Peak memory 233972 kb
Host smart-9acbd009-b1a5-4cf1-b771-731e2faaa6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972824110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1972824110
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.4241641976
Short name T401
Test name
Test status
Simulation time 30390332 ps
CPU time 1.05 seconds
Started Jul 01 06:28:57 PM PDT 24
Finished Jul 01 06:29:02 PM PDT 24
Peak memory 217692 kb
Host smart-11331894-bd2d-4b84-8bc7-614ab1aa81b8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241641976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4241641976
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3333122577
Short name T137
Test name
Test status
Simulation time 122854530 ps
CPU time 2.71 seconds
Started Jul 01 06:28:58 PM PDT 24
Finished Jul 01 06:29:04 PM PDT 24
Peak memory 233544 kb
Host smart-5e977a5f-aa84-40af-aeef-33cb84526949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333122577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3333122577
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3501670921
Short name T469
Test name
Test status
Simulation time 7408587043 ps
CPU time 24.83 seconds
Started Jul 01 06:28:59 PM PDT 24
Finished Jul 01 06:29:26 PM PDT 24
Peak memory 241884 kb
Host smart-97bc19b8-de84-4055-93e7-fcb9fbe48734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501670921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3501670921
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2261704801
Short name T680
Test name
Test status
Simulation time 178835941 ps
CPU time 4.39 seconds
Started Jul 01 06:29:05 PM PDT 24
Finished Jul 01 06:29:12 PM PDT 24
Peak memory 222180 kb
Host smart-8d9f48c9-9646-4aca-a871-7fdb45a55af3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2261704801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2261704801
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1974610630
Short name T201
Test name
Test status
Simulation time 154112325791 ps
CPU time 545.86 seconds
Started Jul 01 06:29:05 PM PDT 24
Finished Jul 01 06:38:14 PM PDT 24
Peak memory 258656 kb
Host smart-c2c7f860-aebd-44a5-bf5d-041a8492dfde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974610630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1974610630
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1561358521
Short name T660
Test name
Test status
Simulation time 8353727886 ps
CPU time 46.61 seconds
Started Jul 01 06:28:58 PM PDT 24
Finished Jul 01 06:29:48 PM PDT 24
Peak memory 217452 kb
Host smart-f0c0846a-2060-489a-836c-9e176381f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561358521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1561358521
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.985712966
Short name T462
Test name
Test status
Simulation time 3909306806 ps
CPU time 13.17 seconds
Started Jul 01 06:28:56 PM PDT 24
Finished Jul 01 06:29:13 PM PDT 24
Peak memory 217752 kb
Host smart-e6c7a071-5fb5-4995-bfc3-d9c0a07cd26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985712966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.985712966
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.301127140
Short name T456
Test name
Test status
Simulation time 168419922 ps
CPU time 1.45 seconds
Started Jul 01 06:28:54 PM PDT 24
Finished Jul 01 06:28:57 PM PDT 24
Peak memory 217616 kb
Host smart-67fff776-3d03-4531-9ebe-f3480d946c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301127140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.301127140
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1198828266
Short name T980
Test name
Test status
Simulation time 52816719 ps
CPU time 0.83 seconds
Started Jul 01 06:28:58 PM PDT 24
Finished Jul 01 06:29:02 PM PDT 24
Peak memory 206976 kb
Host smart-a02f5b9c-0e74-4338-8244-d18a5511fdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198828266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1198828266
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.221941488
Short name T571
Test name
Test status
Simulation time 2016589847 ps
CPU time 8.5 seconds
Started Jul 01 06:28:57 PM PDT 24
Finished Jul 01 06:29:09 PM PDT 24
Peak memory 233848 kb
Host smart-73b4d558-f328-4ff0-b48e-2b471693e850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221941488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.221941488
Directory /workspace/9.spi_device_upload/latest
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