Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2475169	1			T1	343		T3	1		T4	1
all_values[1]	2475169	1			T1	343		T3	1		T4	1
all_values[2]	2475169	1			T1	343		T3	1		T4	1
all_values[3]	2475169	1			T1	343		T3	1		T4	1
all_values[4]	2475169	1			T1	343		T3	1		T4	1
all_values[5]	2475169	1			T1	343		T3	1		T4	1
all_values[6]	2475169	1			T1	343		T3	1		T4	1
all_values[7]	2475169	1			T1	343		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18719335

1

T1

2744

T3

8

T4

8

auto[1]

1082017

1

T15

97

T17

13099

T18

1989

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19779038

1

T1

2744

T3

8

T4

8

auto[1]

22314

1

T15

67

T25

253

T26

176

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2363904	1			T1	343		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	9842	1			T15	5		T25	123		T26	104
all_values[0]	auto[1]	auto[0]	100812	1			T15	2		T17	2608		T34	2465
all_values[0]	auto[1]	auto[1]	611	1			T15	5		T17	3		T18	2
all_values[1]	auto[0]	auto[0]	2283418	1			T1	343		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	6207	1			T15	2		T25	90		T26	36
all_values[1]	auto[1]	auto[0]	184778	1			T15	10		T17	2611		T34	2
all_values[1]	auto[1]	auto[1]	766	1			T15	6		T17	4		T18	2
all_values[2]	auto[0]	auto[0]	2422689	1			T1	343		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	2435	1			T15	7		T25	40		T26	36
all_values[2]	auto[1]	auto[0]	49733	1			T15	6		T17	6		T34	2525
all_values[2]	auto[1]	auto[1]	312	1			T15	4		T17	8		T18	1
all_values[3]	auto[0]	auto[0]	2405310	1			T1	343		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	217	1			T15	5		T17	3		T18	1
all_values[3]	auto[1]	auto[0]	69397	1			T15	6		T17	8		T18	988
all_values[3]	auto[1]	auto[1]	245	1			T15	4		T17	3		T18	3
all_values[4]	auto[0]	auto[0]	2275425	1			T1	343		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	227	1			T15	5		T17	7		T18	2
all_values[4]	auto[1]	auto[0]	199319	1			T15	4		T17	2606		T34	1
all_values[4]	auto[1]	auto[1]	198	1			T15	7		T17	3		T34	2
all_values[5]	auto[0]	auto[0]	2266449	1			T1	343		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	199	1			T15	2		T17	2		T18	1
all_values[5]	auto[1]	auto[0]	208317	1			T15	9		T17	2613		T34	1
all_values[5]	auto[1]	auto[1]	204	1			T15	4		T17	3		T34	1
all_values[6]	auto[0]	auto[0]	2309344	1			T1	343		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	182	1			T15	2		T17	3		T34	4
all_values[6]	auto[1]	auto[0]	165401	1			T15	7		T17	2608		T18	1
all_values[6]	auto[1]	auto[1]	242	1			T15	6		T17	7		T34	1
all_values[7]	auto[0]	auto[0]	2373272	1			T1	343		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	215	1			T15	3		T17	6		T34	3
all_values[7]	auto[1]	auto[0]	101470	1			T15	17		T17	4		T18	989
all_values[7]	auto[1]	auto[1]	212	1			T17	4		T18	3		T34	4