Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35679	1			T1	642		T5	12		T6	581
auto[SpiFlashAddrCfg]	7156	1			T1	38		T6	44		T7	8
auto[SpiFlashAddr3b]	8652	1			T1	61		T5	8		T6	49
auto[SpiFlashAddr4b]	7285	1			T1	57		T6	40		T10	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33253

1

T1

147

T5

20

T6

286

auto[1]

25519

1

T1

651

T6

428

T13

24

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31985

1

T1

437

T5

8

T6

282

auto[1]

26787

1

T1

361

T5

12

T6

432

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40190	1			T1	682		T5	12		T6	602
values[1]	1059	1			T1	9		T6	3		T13	2
values[2]	1370	1			T1	7		T6	7		T10	2
values[3]	1324	1			T1	7		T6	13		T14	2
values[4]	1403	1			T1	19		T6	5		T7	2
values[5]	1305	1			T1	8		T6	7		T13	4
values[6]	1387	1			T1	6		T6	6		T12	6
values[7]	1386	1			T1	9		T6	12		T7	4
values[8]	9348	1			T1	51		T5	8		T6	59

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28867

1

T5

20

T6

714

T7

14

auto[1]

29905

1

T1

798

T26

92

T17

631

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55638

1

T1

778

T5

20

T6

699

write

3134

1

T1

20

T6

15

T10

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18171

1

T1

123

T6

128

T7

8

valids[0x1]

40601

1

T1

675

T5

20

T6

586

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1550	1			T1	13		T6	9		T7	2
internal_process_ops[0x5a]	1511	1			T1	11		T5	8		T6	6
internal_process_ops[0x05]	22403	1			T1	550		T5	8		T6	504
internal_process_ops[0x35]	1406	1			T1	11		T6	9		T7	2
internal_process_ops[0x15]	1512	1			T1	12		T5	4		T6	7
internal_process_ops[0x03]	981	1			T1	6		T6	5		T25	12
internal_process_ops[0x0b]	1104	1			T1	3		T6	9		T7	2
internal_process_ops[0x3b]	1011	1			T1	3		T6	10		T10	2
internal_process_ops[0x6b]	1033	1			T1	2		T6	7		T25	8
internal_process_ops[0xbb]	968	1			T1	6		T6	5		T25	7
internal_process_ops[0xeb]	965	1			T1	1		T6	13		T7	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57214

1

T1

790

T5

20

T6

709

auto[1]

1558

1

T1

8

T6

5

T13

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56550

1

T1

779

T5

20

T6

698

auto[1]

2222

1

T1

19

T6

16

T25

15

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10093

1

T5

12

T6

213

T7

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6047

1

T6

366

T13

6

T25

35

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1918

1

T6

23

T7

8

T9

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1612

1

T6

21

T13

6

T25

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2229

1

T5

8

T6

27

T7

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1948

1

T6

16

T13

10

T25

38

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1883

1

T6

15

T10

6

T14

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1683

1

T6

18

T25

15

T44

11

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

114

1

T6

1

T25

1

T177

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

91

1

T25

1

T47

1

T50

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

73

1

T25

1

T44

1

T20

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

105

1

T6

1

T25

2

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

77

1

T14

2

T25

2

T45

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

78

1

T25

1

T44

2

T34

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

103

1

T25

1

T44

1

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

113

1

T49

2

T34

3

T178

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

92

1

T6

4

T10

2

T12

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

85

1

T25

1

T46

2

T102

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

78

1

T25

1

T47

1

T179

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

92

1

T6

2

T25

1

T48

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

102

1

T6

2

T25

2

T44

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

77

1

T6

1

T25

1

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

78

1

T6

3

T102

1

T20

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

96

1

T6

1

T13

2

T20

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10654

1

T1

63

T26

26

T17

279

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8071

1

T1

579

T26

29

T17

106

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1550

1

T1

19

T26

5

T17

22

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1318

1

T1

10

T26

4

T17

27

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1893

1

T1

31

T26

3

T17

35

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1795

1

T1

24

T26

5

T17

49

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1468

1

T1

24

T26

4

T17

32

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1476

1

T1

28

T26

14

T17

40

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

117

1

T17

5

T18

5

T52

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

117

1

T17

1

T55

2

T39

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

101

1

T17

5

T55

2

T39

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

96

1

T17

1

T54

2

T39

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

107

1

T1

2

T54

1

T55

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

83

1

T1

1

T17

2

T54

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T1

4

T17

2

T40

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

102

1

T1

2

T17

1

T55

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

113

1

T1

1

T17

2

T40

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

101

1

T1

3

T17

1

T40

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

112

1

T17

1

T18

9

T54

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

114

1

T1

2

T26

1

T17

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

89

1

T1

3

T17

7

T18

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

122

1

T17

2

T18

2

T52

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

125

1

T1

2

T18

2

T52

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

86

1

T26

1

T17

8

T18

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3540	1			T6	45		T9	2		T12	2
auto[0]	values[0]	valids[0x1]	15256	1			T5	12		T6	557		T7	4
auto[0]	values[1]	valids[0x1]	529	1			T6	3		T13	2		T25	8
auto[0]	values[2]	valids[0x0]	493	1			T6	5		T25	6		T44	2
auto[0]	values[2]	valids[0x1]	235	1			T6	2		T10	2		T25	3
auto[0]	values[3]	valids[0x0]	446	1			T6	8		T14	2		T44	7
auto[0]	values[3]	valids[0x1]	261	1			T6	5		T25	2		T44	2
auto[0]	values[4]	valids[0x0]	448	1			T6	5		T13	6		T14	2
auto[0]	values[4]	valids[0x1]	261	1			T7	2		T25	2		T44	6
auto[0]	values[5]	valids[0x0]	475	1			T6	6		T13	4		T25	1
auto[0]	values[5]	valids[0x1]	258	1			T6	1		T25	2		T44	5
auto[0]	values[6]	valids[0x0]	483	1			T6	5		T25	3		T44	2
auto[0]	values[6]	valids[0x1]	285	1			T6	1		T12	6		T25	7
auto[0]	values[7]	valids[0x0]	487	1			T6	9		T7	4		T25	2
auto[0]	values[7]	valids[0x1]	302	1			T6	3		T25	4		T44	2
auto[0]	values[8]	valids[0x0]	3232	1			T6	45		T7	4		T10	4
auto[0]	values[8]	valids[0x1]	1876	1			T5	8		T6	14		T9	4
auto[1]	values[0]	valids[0x0]	3857	1			T1	59		T26	15		T17	60
auto[1]	values[0]	valids[0x1]	17537	1			T1	623		T26	43		T17	377
auto[1]	values[1]	valids[0x1]	530	1			T1	9		T26	4		T17	5
auto[1]	values[2]	valids[0x0]	397	1			T1	6		T26	2		T17	10
auto[1]	values[2]	valids[0x1]	245	1			T1	1		T17	4		T40	2
auto[1]	values[3]	valids[0x0]	359	1			T1	5		T17	8		T40	1
auto[1]	values[3]	valids[0x1]	258	1			T1	2		T17	4		T40	2
auto[1]	values[4]	valids[0x0]	400	1			T1	5		T26	1		T17	7
auto[1]	values[4]	valids[0x1]	294	1			T1	14		T26	3		T17	6
auto[1]	values[5]	valids[0x0]	346	1			T1	6		T17	8		T40	2
auto[1]	values[5]	valids[0x1]	226	1			T1	2		T26	1		T17	14
auto[1]	values[6]	valids[0x0]	395	1			T1	4		T26	1		T17	7
auto[1]	values[6]	valids[0x1]	224	1			T1	2		T26	4		T17	7
auto[1]	values[7]	valids[0x0]	363	1			T1	8		T26	1		T17	9
auto[1]	values[7]	valids[0x1]	234	1			T1	1		T17	6		T40	6
auto[1]	values[8]	valids[0x0]	2450	1			T1	30		T26	8		T17	55
auto[1]	values[8]	valids[0x1]	1790	1			T1	21		T26	9		T17	44