Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2997231

1

T1

9802

T5

36928

T6

21539

auto[1]

30601

1

T1

538

T6

494

T25

21

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

851808

1

T1

106

T5

36928

T6

69

auto[1]

2176024

1

T1

10234

T6

21964

T12

4792

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	611949	1			T1	591		T5	4602		T6	7435
auto[524288:1048575]	371276	1			T1	1671		T5	1643		T6	645
auto[1048576:1572863]	336047	1			T1	7		T5	1226		T6	3858
auto[1572864:2097151]	317674	1			T1	1577		T5	4783		T6	554
auto[2097152:2621439]	366619	1			T1	1338		T5	6731		T6	85
auto[2621440:3145727]	350795	1			T1	1068		T5	1557		T6	3086
auto[3145728:3670015]	344493	1			T1	3247		T5	7562		T6	3060
auto[3670016:4194303]	328979	1			T1	841		T5	8824		T6	3310

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2208419

1

T1

10329

T5

198

T6

22018

auto[1]

819413

1

T1

11

T5

36730

T6

15

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2623034

1

T1

9480

T5

36928

T6

14818

auto[1]

404798

1

T1

860

T6

7215

T25

669

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	190759	1			T1	9		T5	4602		T6	6
auto[0]	auto[0]	auto[0:524287]	auto[1]	350821	1			T1	514		T6	2055		T12	4792
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	107529	1			T1	16		T5	1643		T6	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	211666	1			T1	1416		T6	6		T25	2293
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	86680	1			T1	3		T5	1226		T6	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	196274	1			T1	1		T6	2997		T25	257
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	61300	1			T1	5		T5	4783		T6	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	211886	1			T1	1004		T6	257		T25	2855
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	105221	1			T1	16		T5	6731		T6	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	198369	1			T1	1276		T6	7		T25	648
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	103083	1			T1	10		T5	1557		T6	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	199448	1			T1	648		T6	2973		T25	3010
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	98788	1			T1	5		T5	7562		T6	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	190715	1			T1	3236		T6	2931		T25	2974
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	88862	1			T1	9		T5	8824		T6	6
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	195713	1			T1	774		T6	3205		T25	1648
auto[0]	auto[1]	auto[0:524287]	auto[0]	733	1			T6	1		T26	4		T18	8
auto[0]	auto[1]	auto[0:524287]	auto[1]	64354	1			T6	5373		T26	1		T18	239
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	936	1			T1	1		T6	4		T25	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	47616	1			T6	520		T17	2		T55	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	599	1			T6	2		T17	4		T18	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	48511	1			T6	771		T17	4		T18	259
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1139	1			T1	3		T6	4		T25	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	39704	1			T1	473		T6	256		T25	262
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	589	1			T1	1		T54	1		T55	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	59088	1			T6	5		T18	1		T54	2497
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	841	1			T1	4		T25	6		T17	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	43339	1			T1	372		T25	388		T17	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	559	1			T1	5		T17	2		T52	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	51133	1			T1	1		T6	128		T17	517
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	652	1			T6	2		T17	4		T18	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	40324	1			T6	2		T17	2565		T18	128
auto[1]	auto[0]	auto[0:524287]	auto[0]	503	1			T1	2		T25	1		T26	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	4228	1			T1	66		T26	1		T17	41
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	315	1			T1	7		T6	1		T25	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2577	1			T1	231		T6	33		T25	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	348	1			T1	1		T6	2		T25	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3211	1			T1	2		T6	36		T17	8
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	373	1			T1	2		T6	1		T26	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2538	1			T1	90		T6	31		T26	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	374	1			T1	2		T6	2		T25	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2553	1			T1	43		T6	67		T17	23
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	286	1			T1	2		T6	3		T25	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3209	1			T1	32		T6	103		T25	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	332	1			T25	2		T17	3		T18	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2237	1			T17	35		T18	195		T54	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	385	1			T1	3		T6	1		T26	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2451	1			T1	55		T6	67		T26	21
auto[1]	auto[1]	auto[0:524287]	auto[0]	88	1			T26	1		T18	2		T54	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	463	1			T26	1		T18	26		T56	4
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	87	1			T6	3		T39	5		T34	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	550	1			T6	72		T34	2		T32	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	78	1			T6	1		T17	1		T18	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	346	1			T6	44		T17	18		T46	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	74	1			T25	3		T18	1		T92	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	660	1			T25	4		T18	2		T92	6
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	95	1			T18	1		T39	10		T44	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	330	1			T18	6		T44	5		T239	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	65	1			T18	2		T34	1		T20	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	524	1			T18	79		T205	40		T31	20
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	69	1			T39	6		T92	1		T34	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	660	1			T39	32		T92	17		T34	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	66	1			T6	2		T55	1		T44	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	526	1			T6	25		T55	9		T44	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1779704	1			T1	8932		T5	198		T6	14463
auto[0]	auto[0]	auto[1]	817410	1			T1	10		T5	36730		T6	8
auto[0]	auto[1]	auto[0]	398702	1			T1	860		T6	7063		T25	662
auto[0]	auto[1]	auto[1]	1415	1			T6	5		T17	1		T44	1
auto[1]	auto[0]	auto[0]	25423	1			T1	537		T6	346		T25	14
auto[1]	auto[0]	auto[1]	497	1			T1	1		T6	1		T26	1
auto[1]	auto[1]	auto[0]	4590	1			T6	146		T25	6		T26	2
auto[1]	auto[1]	auto[1]	91	1			T6	1		T25	1		T39	5