Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2475169	1			T1	343		T3	1		T4	1
all_pins[1]	2475169	1			T1	343		T3	1		T4	1
all_pins[2]	2475169	1			T1	343		T3	1		T4	1
all_pins[3]	2475169	1			T1	343		T3	1		T4	1
all_pins[4]	2475169	1			T1	343		T3	1		T4	1
all_pins[5]	2475169	1			T1	343		T3	1		T4	1
all_pins[6]	2475169	1			T1	343		T3	1		T4	1
all_pins[7]	2475169	1			T1	343		T3	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19634530	1			T1	2744		T3	8		T4	8
values[0x1]	166822	1			T15	36		T17	58		T18	11
transitions[0x0=>0x1]	164934	1			T15	29		T17	36		T18	6
transitions[0x1=>0x0]	164942	1			T15	29		T17	36		T18	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2474461	1			T1	343		T3	1		T4	1
all_pins[0]	values[0x1]	708	1			T15	5		T17	15		T18	2
all_pins[0]	transitions[0x0=>0x1]	488	1			T15	5		T17	3		T34	134
all_pins[0]	transitions[0x1=>0x0]	648	1			T15	6		T17	3		T19	2
all_pins[1]	values[0x0]	2474301	1			T1	343		T3	1		T4	1
all_pins[1]	values[0x1]	868	1			T15	6		T17	15		T18	2
all_pins[1]	transitions[0x0=>0x1]	780	1			T15	4		T17	13		T18	1
all_pins[1]	transitions[0x1=>0x0]	238	1			T15	2		T17	6		T34	65
all_pins[2]	values[0x0]	2474843	1			T1	343		T3	1		T4	1
all_pins[2]	values[0x1]	326	1			T15	4		T17	8		T18	1
all_pins[2]	transitions[0x0=>0x1]	256	1			T15	3		T17	6		T18	1
all_pins[2]	transitions[0x1=>0x0]	175	1			T15	3		T17	1		T18	3
all_pins[3]	values[0x0]	2474924	1			T1	343		T3	1		T4	1
all_pins[3]	values[0x1]	245	1			T15	4		T17	3		T18	3
all_pins[3]	transitions[0x0=>0x1]	182	1			T15	1		T17	1		T18	3
all_pins[3]	transitions[0x1=>0x0]	135	1			T15	4		T17	1		T34	2
all_pins[4]	values[0x0]	2474971	1			T1	343		T3	1		T4	1
all_pins[4]	values[0x1]	198	1			T15	7		T17	3		T34	2
all_pins[4]	transitions[0x0=>0x1]	152	1			T15	7		T17	3		T34	2
all_pins[4]	transitions[0x1=>0x0]	2364	1			T15	4		T17	3		T34	1
all_pins[5]	values[0x0]	2472759	1			T1	343		T3	1		T4	1
all_pins[5]	values[0x1]	2410	1			T15	4		T17	3		T34	1
all_pins[5]	transitions[0x0=>0x1]	1126	1			T15	3		T17	1		T34	1
all_pins[5]	transitions[0x1=>0x0]	160571	1			T15	5		T17	5		T34	1
all_pins[6]	values[0x0]	2313314	1			T1	343		T3	1		T4	1
all_pins[6]	values[0x1]	161855	1			T15	6		T17	7		T34	1
all_pins[6]	transitions[0x0=>0x1]	161790	1			T15	6		T17	5		T19	2
all_pins[6]	transitions[0x1=>0x0]	147	1			T17	2		T18	3		T34	3
all_pins[7]	values[0x0]	2474957	1			T1	343		T3	1		T4	1
all_pins[7]	values[0x1]	212	1			T17	4		T18	3		T34	4
all_pins[7]	transitions[0x0=>0x1]	160	1			T17	4		T18	1		T34	3
all_pins[7]	transitions[0x1=>0x0]	664	1			T15	5		T17	15		T34	133