Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16839

1

T5

20

T6

286

T7

14

auto[1]

12028

1

T6

428

T13

24

T25

111

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3505	1			T6	108		T10	18		T132	2
values[1]	3814	1			T6	83		T25	41		T47	20
values[2]	3474	1			T5	20		T6	21		T13	24
values[3]	3296	1			T6	125		T25	40		T114	4
values[4]	3516	1			T7	14		T25	71		T46	40
values[5]	3902	1			T6	240		T12	18		T25	22
values[6]	4125	1			T9	6		T14	12		T25	22
values[7]	3235	1			T6	137		T25	45		T177	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3508	1			T10	18		T25	20		T45	12
values[1]	3980	1			T6	108		T13	24		T25	25
values[2]	3521	1			T6	21		T240	6		T46	28
values[3]	3063	1			T6	206		T9	6		T25	44
values[4]	3484	1			T5	20		T6	156		T25	22
values[5]	3256	1			T6	57		T7	14		T12	18
values[6]	3614	1			T6	63		T14	12		T25	20
values[7]	4441	1			T6	103		T25	42		T44	63

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	335	1			T10	18		T205	11		T22	7
auto[0]	values[0]	values[1]	373	1			T6	100		T31	27		T225	46
auto[0]	values[0]	values[2]	130	1			T241	9		T213	9		T85	13
auto[0]	values[0]	values[3]	245	1			T132	2		T242	2		T31	25
auto[0]	values[0]	values[4]	134	1			T243	14		T244	11		T245	14
auto[0]	values[0]	values[5]	175	1			T246	10		T22	26		T220	12
auto[0]	values[0]	values[6]	276	1			T46	31		T102	19		T196	14
auto[0]	values[0]	values[7]	392	1			T205	8		T82	37		T58	14
auto[0]	values[1]	values[0]	328	1			T20	11		T205	13		T60	12
auto[0]	values[1]	values[1]	251	1			T146	16		T205	76		T32	34
auto[0]	values[1]	values[2]	205	1			T69	2		T220	9		T247	2
auto[0]	values[1]	values[3]	204	1			T47	11		T220	14		T85	12
auto[0]	values[1]	values[4]	264	1			T20	10		T210	11		T82	5
auto[0]	values[1]	values[5]	175	1			T226	18		T34	12		T190	10
auto[0]	values[1]	values[6]	234	1			T25	9		T31	11		T220	11
auto[0]	values[1]	values[7]	396	1			T6	9		T25	14		T51	10
auto[0]	values[2]	values[0]	155	1			T45	12		T248	2		T249	13
auto[0]	values[2]	values[1]	219	1			T111	14		T31	9		T243	10
auto[0]	values[2]	values[2]	323	1			T6	17		T46	22		T20	18
auto[0]	values[2]	values[3]	199	1			T50	17		T66	10		T199	4
auto[0]	values[2]	values[4]	271	1			T5	20		T50	12		T205	9
auto[0]	values[2]	values[5]	280	1			T31	6		T199	60		T215	9
auto[0]	values[2]	values[6]	230	1			T62	10		T21	10		T241	12
auto[0]	values[2]	values[7]	326	1			T20	15		T31	11		T210	35
auto[0]	values[3]	values[0]	228	1			T25	11		T50	12		T21	11
auto[0]	values[3]	values[1]	355	1			T44	35		T199	29		T213	45
auto[0]	values[3]	values[2]	157	1			T31	7		T220	10		T85	14
auto[0]	values[3]	values[3]	153	1			T6	8		T114	4		T31	10
auto[0]	values[3]	values[4]	227	1			T46	11		T205	16		T228	16
auto[0]	values[3]	values[5]	160	1			T25	9		T44	6		T205	7
auto[0]	values[3]	values[6]	496	1			T6	32		T191	15		T60	59
auto[0]	values[3]	values[7]	237	1			T47	17		T205	56		T22	11
auto[0]	values[4]	values[0]	196	1			T46	8		T20	8		T82	10
auto[0]	values[4]	values[1]	178	1			T46	18		T179	10		T20	34
auto[0]	values[4]	values[2]	278	1			T34	14		T199	17		T241	14
auto[0]	values[4]	values[3]	104	1			T31	13		T85	8		T249	13
auto[0]	values[4]	values[4]	260	1			T25	14		T70	22		T20	14
auto[0]	values[4]	values[5]	359	1			T7	14		T25	21		T250	36
auto[0]	values[4]	values[6]	349	1			T115	10		T31	94		T32	20
auto[0]	values[4]	values[7]	238	1			T25	10		T47	10		T251	2
auto[0]	values[5]	values[0]	267	1			T21	11		T239	6		T58	16
auto[0]	values[5]	values[1]	205	1			T31	13		T32	20		T199	12
auto[0]	values[5]	values[2]	275	1			T50	14		T82	14		T98	22
auto[0]	values[5]	values[3]	232	1			T6	22		T25	9		T34	12
auto[0]	values[5]	values[4]	138	1			T6	10		T31	12		T60	14
auto[0]	values[5]	values[5]	637	1			T6	50		T12	18		T46	13
auto[0]	values[5]	values[6]	288	1			T190	8		T244	13		T252	8
auto[0]	values[5]	values[7]	356	1			T21	10		T205	12		T31	21
auto[0]	values[6]	values[0]	337	1			T44	14		T31	18		T241	17
auto[0]	values[6]	values[1]	500	1			T149	12		T22	12		T213	14
auto[0]	values[6]	values[2]	361	1			T176	7		T210	11		T85	14
auto[0]	values[6]	values[3]	291	1			T9	6		T25	9		T44	17
auto[0]	values[6]	values[4]	257	1			T199	9		T210	11		T253	6
auto[0]	values[6]	values[5]	215	1			T254	14		T60	20		T255	10
auto[0]	values[6]	values[6]	217	1			T14	12		T199	15		T190	15
auto[0]	values[6]	values[7]	298	1			T102	7		T256	6		T249	13
auto[0]	values[7]	values[0]	175	1			T47	8		T210	11		T85	8
auto[0]	values[7]	values[1]	300	1			T25	14		T21	9		T205	12
auto[0]	values[7]	values[2]	494	1			T240	6		T216	10		T85	135
auto[0]	values[7]	values[3]	98	1			T6	11		T257	16		T258	9
auto[0]	values[7]	values[4]	266	1			T145	10		T259	14		T191	20
auto[0]	values[7]	values[5]	97	1			T25	10		T177	8		T44	28
auto[0]	values[7]	values[6]	166	1			T6	14		T212	18		T31	15
auto[0]	values[7]	values[7]	274	1			T6	13		T44	12		T260	10
auto[1]	values[0]	values[0]	196	1			T205	9		T22	13		T176	8
auto[1]	values[0]	values[1]	138	1			T6	8		T31	20		T225	9
auto[1]	values[0]	values[2]	102	1			T241	18		T213	46		T85	7
auto[1]	values[0]	values[3]	177	1			T31	35		T241	19		T60	11
auto[1]	values[0]	values[4]	117	1			T243	6		T229	16		T244	9
auto[1]	values[0]	values[5]	146	1			T22	15		T217	22		T220	8
auto[1]	values[0]	values[6]	277	1			T46	29		T102	5		T31	10
auto[1]	values[0]	values[7]	292	1			T205	98		T81	20		T82	35
auto[1]	values[1]	values[0]	251	1			T20	10		T205	7		T60	8
auto[1]	values[1]	values[1]	224	1			T205	11		T32	28		T190	24
auto[1]	values[1]	values[2]	157	1			T220	20		T261	10		T244	4
auto[1]	values[1]	values[3]	201	1			T47	9		T220	30		T85	8
auto[1]	values[1]	values[4]	155	1			T20	10		T210	9		T82	15
auto[1]	values[1]	values[5]	62	1			T34	8		T190	10		T237	10
auto[1]	values[1]	values[6]	261	1			T25	11		T31	10		T220	9
auto[1]	values[1]	values[7]	446	1			T6	74		T25	7		T51	38
auto[1]	values[2]	values[0]	152	1			T249	7		T262	2		T263	29
auto[1]	values[2]	values[1]	214	1			T13	24		T31	81		T243	10
auto[1]	values[2]	values[2]	174	1			T6	4		T46	6		T20	7
auto[1]	values[2]	values[3]	260	1			T50	3		T199	144		T190	8
auto[1]	values[2]	values[4]	165	1			T50	8		T205	24		T210	9
auto[1]	values[2]	values[5]	184	1			T264	6		T31	80		T199	12
auto[1]	values[2]	values[6]	83	1			T21	10		T241	9		T265	8
auto[1]	values[2]	values[7]	239	1			T20	6		T31	9		T210	17
auto[1]	values[3]	values[0]	174	1			T25	9		T50	8		T21	10
auto[1]	values[3]	values[1]	80	1			T44	17		T199	5		T213	6
auto[1]	values[3]	values[2]	126	1			T31	21		T220	10		T85	6
auto[1]	values[3]	values[3]	138	1			T6	74		T31	10		T210	7
auto[1]	values[3]	values[4]	234	1			T46	12		T205	12		T225	89
auto[1]	values[3]	values[5]	270	1			T25	11		T44	14		T205	157
auto[1]	values[3]	values[6]	120	1			T6	11		T191	5		T60	9
auto[1]	values[3]	values[7]	141	1			T47	3		T197	16		T205	5
auto[1]	values[4]	values[0]	185	1			T46	12		T49	8		T20	36
auto[1]	values[4]	values[1]	188	1			T46	2		T179	10		T20	8
auto[1]	values[4]	values[2]	249	1			T34	12		T199	3		T241	8
auto[1]	values[4]	values[3]	143	1			T31	7		T85	49		T249	16
auto[1]	values[4]	values[4]	255	1			T25	8		T20	9		T205	68
auto[1]	values[4]	values[5]	139	1			T25	7		T190	7		T201	13
auto[1]	values[4]	values[6]	156	1			T31	24		T32	5		T266	10
auto[1]	values[4]	values[7]	239	1			T25	11		T47	10		T199	11
auto[1]	values[5]	values[0]	154	1			T21	20		T239	27		T58	8
auto[1]	values[5]	values[1]	258	1			T31	7		T32	8		T199	129
auto[1]	values[5]	values[2]	127	1			T50	6		T82	6		T171	11
auto[1]	values[5]	values[3]	156	1			T6	5		T25	13		T34	9
auto[1]	values[5]	values[4]	227	1			T6	146		T31	8		T60	6
auto[1]	values[5]	values[5]	176	1			T6	7		T46	8		T20	9
auto[1]	values[5]	values[6]	210	1			T190	12		T244	7		T206	7
auto[1]	values[5]	values[7]	196	1			T21	10		T205	18		T31	6
auto[1]	values[6]	values[0]	157	1			T44	37		T31	5		T241	6
auto[1]	values[6]	values[1]	205	1			T22	10		T213	6		T243	12
auto[1]	values[6]	values[2]	168	1			T176	13		T210	9		T85	6
auto[1]	values[6]	values[3]	328	1			T25	13		T44	44		T34	9
auto[1]	values[6]	values[4]	339	1			T178	18		T199	103		T210	10
auto[1]	values[6]	values[5]	136	1			T267	2		T254	6		T60	20
auto[1]	values[6]	values[6]	192	1			T199	5		T190	5		T225	33
auto[1]	values[6]	values[7]	124	1			T102	13		T268	2		T249	9
auto[1]	values[7]	values[0]	218	1			T47	12		T210	78		T85	87
auto[1]	values[7]	values[1]	292	1			T25	11		T21	13		T205	8
auto[1]	values[7]	values[2]	195	1			T85	9		T171	16		T262	19
auto[1]	values[7]	values[3]	134	1			T6	86		T269	10		T258	14
auto[1]	values[7]	values[4]	175	1			T270	18		T271	22		T191	20
auto[1]	values[7]	values[5]	45	1			T25	10		T44	7		T272	10
auto[1]	values[7]	values[6]	59	1			T6	6		T31	5		T245	6
auto[1]	values[7]	values[7]	247	1			T6	7		T44	51		T48	4