Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	394	1			T6	7		T25	4		T44	4
auto[ReadAddrCrossIntoMailbox]	292	1			T6	5		T25	3		T44	1
auto[ReadAddrCrossOutOfMailbox]	263	1			T6	1		T25	4		T44	2
auto[ReadAddrCrossAllMailbox]	194	1			T6	2		T25	2		T44	2
auto[ReadAddrOutsideMailbox]	3394	1			T6	34		T7	6		T9	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2213

1

T6

25

T7

3

T9

1

auto[1]

2324

1

T6

24

T7

3

T9

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	735	1			T6	5		T25	12		T44	5
read_ops[0x0b]	818	1			T6	9		T7	2		T9	2
read_ops[0x3b]	765	1			T6	10		T10	2		T14	2
read_ops[0x6b]	781	1			T6	7		T25	8		T44	5
read_ops[0xbb]	745	1			T6	5		T25	7		T132	2
read_ops[0xeb]	693	1			T6	13		T7	4		T13	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T102	2		T146	1		T66	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T146	1		T66	2		T31	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T115	1		T32	1		T213	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T44	1		T46	1		T115	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T25	1		T115	2		T205	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T6	1		T115	2		T50	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T31	1		T190	1		T60	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T199	1		T239	1		T233	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	265	1			T6	3		T25	7		T46	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	272	1			T6	1		T25	4		T44	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T6	1		T25	1		T51	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T145	1		T21	1		T82	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T227	1		T31	1		T243	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T227	1		T22	1		T243	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T25	2		T44	2		T205	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T243	2		T82	4		T85	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T6	1		T44	1		T115	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T115	1		T34	1		T243	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	323	1			T6	3		T7	1		T9	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T6	4		T7	1		T9	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T6	4		T25	1		T227	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T227	1		T146	2		T196	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T6	1		T34	1		T58	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T34	1		T20	1		T210	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T220	1		T213	1		T85	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T85	1		T190	1		T225	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T227	1		T31	1		T266	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T25	1		T227	1		T20	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T6	1		T10	1		T14	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T6	4		T10	1		T14	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T44	1		T34	1		T66	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T50	1		T66	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T205	1		T22	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T6	1		T25	2		T46	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T213	2		T243	1		T273	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T20	1		T31	1		T210	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T20	1		T199	1		T210	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T22	1		T215	1		T273	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T6	4		T25	5		T44	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T6	2		T25	1		T44	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T50	1		T85	1		T190	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T6	1		T25	1		T44	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T6	1		T210	1		T213	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T47	1		T31	2		T199	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T220	1		T85	1		T58	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T47	1		T205	1		T22	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T50	1		T34	1		T58	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T210	1		T243	2		T85	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T6	1		T25	4		T132	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T6	2		T25	2		T132	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T25	1		T227	1		T34	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T6	1		T44	1		T227	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T6	1		T25	1		T31	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T6	1		T51	1		T58	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	12	1			T25	1		T210	1		T82	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T46	1		T31	1		T243	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T190	1		T225	1		T215	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T6	1		T25	1		T44	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	250	1			T6	4		T7	2		T13	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	268	1			T6	5		T7	2		T13	3